Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device in which signal lines on each layer can be easily drawn out independently, and a method for manufacturing the same.SOLUTION: A semiconductor device includes a substrate 10 and at least one functional layer 20. The functional layer includes a first signal line 203 and a second signal line 205 that are stacked vertically on the substrate. The second signal line is located on a side of the first signal line that is farther from the substrate, and is insulated from the first signal line through insulating film layers 209 to 211. The first signal line and the second signal line each extend in a first horizontal direction and have a main body extension portion and a pull-out end portion. The pull-out end portion is located at least at one end of the main body extension portion in the first horizontal direction, and the orthogonal projections of the main body extension portion of the first signal line and the main body extension portion of the second signal line overlap each other on the substrate, and the orthogonal projections of the pull-out end portion of the first signal line and the pull-out end portion of the second signal line do not overlap each other on the substrate.SELECTED DRAWING: Figure 30

Description

[Technical field]

[0001] The present invention relates to the field of semiconductors, and more particularly to semiconductor devices and methods for manufacturing semiconductor devices. [Background technology]

[0002] With the development of the semiconductor industry, the market demand for the memory density of DRAM (Dynamic Random Access Memory) is increasing, but the existing 1T1C (T stands for transistor, C stands for capacitor) memory structure (i.e., a memory structure including one transistor and one capacitor) is difficult to realize three-dimensional stacking, and in the planar layout, the memory density is affected by the critical dimension, and the critical dimension is limited by the development of photolithography equipment, so it is difficult to increase the memory density. The 2T0C memory structure (i.e., a memory structure including two transistors and no capacitor) can increase the memory density by increasing the number of stacks without reducing the critical dimension, but the 2T0C memory structure has multiple layers of signal lines, and how to draw out the signal lines of each layer is an urgent issue that needs to be solved. Summary of the Invention

[0003] The present invention provides a semiconductor device and a method for manufacturing the same that facilitate drawing out signal lines on each layer and connecting them to other structures.

[0004] A first aspect of the present invention provides a semiconductor device including a substrate and at least one functional layer, the functional layer including a first signal line and a second signal line stacked along a vertical direction of the substrate, the second signal line being located on a side of the first signal line farther from the substrate and insulated from the first signal line via an insulating film layer, the first signal line and the second signal line both extending in a first horizontal direction, the first signal line and the second signal line each have a body extension and a pull-out end, and in the first signal line and the second signal line, the pull-out end is located at at least one end of the body extension in a first horizontal direction; The orthogonal projections of the body extension of the first signal line and the body extension of the second signal line on the substrate overlap, and the orthogonal projections of the pull-out end of the first signal line and the pull-out end of the second signal line on the substrate do not overlap.

[0005] A second aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising the steps of: Providing a substrate; forming at least one functional layer on the substrate; The step of forming the functional layer includes: forming a first signal line extending in a first horizontal direction on the substrate and a first insulating film layer covering the first signal line; forming a second signal line extending in a first horizontal direction on a side of the first insulating film layer away from the substrate; the first signal line and the second signal line each have a body extension and a pull-out end, and in the first signal line and the second signal line, the pull-out end is located at at least one end of the body extension in a first horizontal direction; an orthogonal projection of a body extension of the first signal line and a body extension of the second signal line on the substrate overlaps; The orthogonal projections of the lead-out end of the first signal line and the lead-out end of the second signal line on the substrate do not overlap.

[0006] The technical solution provided by the embodiment of the present invention has at least the following advantages: By arranging the lead-out ends of signal lines located in different layers and extending in the same direction in a staggered manner so as not to overlap, the signal lines of each layer can be led out independently without interfering with each other. [Brief description of the drawings]

[0007] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure. It should be understood that the drawings in the following description are merely some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without creative efforts. [Figure 1] 1 shows a schematic diagram of a three-dimensional structure of a semiconductor device provided by an embodiment of the present invention; [Diagram 2] 2 shows a cross-sectional view of the semiconductor device shown in FIG. 1 taken along the line AA. [Diagram 3] 2 shows a cross-sectional view of the semiconductor device shown in FIG. 1 taken along the line BB. [Figure 4] 2 shows a cross-sectional view of a memory unit of the semiconductor device shown in FIG. 1 taken along the line AA. [Diagram 5] 2 shows a cross-sectional view of a memory unit of the semiconductor device shown in FIG. 1 taken along the BB direction. [Figure 6] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 7] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 8] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 9] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 10] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 11] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 12]2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 13] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 14] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 15] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 16] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 17] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 18] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 19] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 20] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 21] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 22] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 23] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 24]2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 25] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 26] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 27] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 28] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 29] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 30] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 31] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 32] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 33] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 34] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 35] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 36]2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 37] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 38] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Figure 39] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 40] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 41] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 42] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. [Diagram 43] 2A to 2C are schematic cross-sectional views of a semiconductor device after each step is performed in a method for manufacturing the semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] Next, exemplary embodiments will be described in more detail with reference to the drawings. However, exemplary embodiments can be implemented in various forms and should not be understood to be limited to the examples described in this specification. On the contrary, these embodiments are provided to make the present application more comprehensive and complete, and to fully convey the concept of exemplary embodiments to those skilled in the art.

[0009] Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments of the present application. However, one skilled in the art will recognize that the technical solutions of the present application can be implemented or other methods, components, devices, steps, etc. can be employed without one or more of the specific details. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the present application.

[0010] The present application will be described in more detail below based on the accompanying drawings and specific examples. It should be noted that the technical features contained in the various examples of the present application described below can be combined with each other as long as they are not mutually inconsistent. The embodiments described below with reference to the accompanying drawings are examples for explaining the present application and should not be construed as limiting the present application.

[0011] An embodiment of the present invention provides a semiconductor device, which may be, but is not limited to, a DRAM, a ferroelectric random access memory (FeRAM), or other types of semiconductor devices.

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the structure of a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0013] 1, the semiconductor device includes a substrate 10 and a functional layer 20 formed on the substrate 10. In this embodiment, in order to increase the memory density of the semiconductor device, the functional layer 20 of the semiconductor device is provided in two or more layers, but is not limited thereto and may be a single layer.

[0014] Here, when two or more functional layers 20 are provided in the semiconductor device, the semiconductor device can be understood to be a three-dimensional stacked type semiconductor device.

[0015] The semiconductor device is not limited to having the functional layer 20, and may have components such as a control circuit (not shown) and a readout circuit in addition to the functional layer 20. A detailed description thereof will be omitted here.

[0016] 2 and 3, the substrate 10 may include a semiconductor substrate 101 and an insulating separation layer 102 formed on the semiconductor substrate 101. In this embodiment, the insulating separation layer 102 may have a laminated structure, which means a structure in which two or more film layers of different materials are sequentially laminated, but is not limited thereto, and the insulating separation layer 102 may have a single layer structure.

[0017] For example, the material of the semiconductor substrate 101 may be, but is not limited to, a semiconductor material of an element such as silicon (Si) or germanium (Ge), and may be a crystalline inorganic compound semiconductor material such as silicon carbide (SiC) or silicon germanium. The material of the insulating isolation layer 102 may be, but is not limited to, a semiconductor material of an element such as silicon oxide (SiO 2 The insulating material may include one or more of the following insulating materials: silicon nitride (SiN), silicon oxynitride (SiON), and may also include other materials with low K values.

[0018] As shown in Figures 2 and 3, the insulating isolation layer 102 may include a first film layer 1021 and a second film layer 1022 sequentially formed on the substrate 10, the material of the first film layer 1021 may be a silicon oxide material, and the material of the second film layer 1022 may be a silicon nitride material, but is not limited thereto, and the materials of the first film layer 1021 and the second film layer 1022 may be other insulating materials.

[0019] 2 and 3, the functional layer 20 may include a first signal line 203 and a second signal line 205 stacked on the substrate 10 along the vertical direction Z. The vertical direction Z may be a direction intersecting the substrate 10, and further, the vertical direction Z may be a direction perpendicular or nearly perpendicular to the substrate 10.

[0020] The second signal line 205 is located on the side of the first signal line 203 farther from the substrate 10 and is insulated from the first signal line 203 via an insulating film layer. The first signal line 203 and the second signal line 205 both extend in a first horizontal direction X, which may be parallel to the substrate 10.

[0021] The first signal line 203 and the second signal line 205 each have a body extension (not shown) and a pull-out end (not shown). In the first signal line 203 and the second signal line 205, the pull-out end is located at at least one end of the body extension in the first horizontal direction X, and this pull-out end is used to receive a level signal output by a control circuit via a pull-out structure and to output a level signal to a read-out circuit.

[0022] Among these, the orthogonal projections of the main body extension of the first signal line 203 and the main body extension of the second signal line 205 on the substrate 10 overlap, and the orthogonal projections of the lead-out end of the first signal line 203 and the lead-out end of the second signal line 205 on the substrate 10 do not overlap. That is, the lead-out ends of signal lines located on different layers and extending in the same direction are shifted so as not to overlap.

[0023] In this embodiment, the lead-out ends of signal lines located on different layers and extending in the same direction are staggered so as not to overlap, so that the signal lines on each layer can be led out independently without interfering with each other.

[0024] In the first signal line 203 and the second signal line 205, the lead-out end has a first surface close to the substrate 10 and a second surface far from the substrate 10, and in the first signal line 203 and the second signal line 205, the lead-out direction is the direction in which the first surface faces the second surface, but is not limited thereto, and the lead-out direction may be the direction in which the second surface faces the first surface. This makes it possible to lead out the lead-out structure connected to the first signal line 203 and the lead-out structure connected to the second signal line 205 from the same side, making manufacturing easier.

[0025] In addition, when the direction in which the first surface faces the second surface is the pull-out direction, the end of the pull-out structure far from the first surface connected to the corresponding pull-out end is the terminal in the pull-out direction, and is connected to a structure such as a control circuit or a read-out circuit. When the direction in which the second surface faces the first surface is the pull-out direction, the end of the pull-out structure far from the second surface connected to the corresponding pull-out end is the terminal in the pull-out direction, and is connected to a structure such as a control circuit or a read-out circuit. Furthermore, it should be noted that the end far from the terminal of the pull-out structure may be defined as the tip.

[0026] For example, the tip of the lead-out structure can contact the first surface or the second surface of the corresponding lead-out end to realize electrical connection. Specifically, when the direction in which the second surface faces the first surface is the lead-out direction, the lead-out structure contacts the first surface of the corresponding lead-out end, and when the direction in which the first surface faces the second surface is the lead-out direction, the lead-out structure contacts the second surface of the corresponding lead-out end. Here, the surface in contact with the tip of the lead-out structure may be defined as the lead-out surface.

[0027] In this embodiment, in order to achieve electrical connection by contacting the tip of the draw-out structure, the first surface of the draw-out ends of the first signal line 203 and the second signal line 205 may be the draw-out surface, or the second surface of the draw-out ends of the first signal line 203 and the second signal line 205 may be the draw-out surface, but is not limited to this. A groove or a through hole may be provided in the draw-out ends of the first signal line 203 and the second signal line 205, and the tip of the draw-out structure may be fitted into the groove or through hole to contact the draw-out ends of the first signal line 203 and the second signal line 205, thereby electrically connecting the two.

[0028] In this embodiment, the extension lengths of the second signal line 205 and the first signal line 203 can be designed to be different, that is, the extension lengths of the signal lines located in different layers and extending in the same direction can be designed to be different, so that among the multiple signal lines located in different layers and extending in the same direction, the longer signal line portion is not shielded by the shorter signal line. Note that, since the unshielded portion is the drawing end, the multiple signal lines located in different layers and extending in the same direction are arranged in a stepped manner, and the signal lines of each layer can be drawn out with different drawing structures.

[0029] Among these, the stacking positions of the longer signal line and the shorter signal line extending in the same direction can be determined according to the drawing direction. For example, in the first signal line 203 and the second signal line 205, when the direction in which the second surface faces the first surface is the drawing direction, the extension length of the first signal line 203 located in the same functional layer 20 is smaller than the extension length of the second signal line 205. Or, in the first signal line 203 and the second signal line 205, when the direction in which the first surface faces the second surface is the drawing direction, the extension length of the second signal line 205 located in the same functional layer 20 is smaller than the extension length of the first signal line 203.

[0030] Optionally, the first signal line 203 and the second signal line 205 are provided with lead-out ends at opposite ends of the body extension in the first horizontal direction X to facilitate connection with control circuitry.

[0031] In this embodiment, the functional layer 20 can be provided as a plurality of layers, which are sequentially stacked on the substrate 10 in the vertical direction Z.

[0032] When the functional layer 20 is provided in multiple layers, among two adjacent functional layers 20, in the first signal line 203 and the second signal line 205, if the direction in which the second surface faces the first surface is the pull-out direction, the extension length of the first signal line 203 of the functional layer 20 farther from the substrate 10 is greater than the extension length of the second signal line 205 of the functional layer 20 closer to the substrate 10, or, in the first signal line 203 and the second signal line 205, if the direction in which the first surface faces the second surface is the pull-out direction, the extension length of the first signal line 203 of the functional layer 20 farther from the substrate 10 is less than the extension length of the second signal line 205 of the functional layer 20 closer to the substrate 10.

[0033] The functional layer 20 further includes a third signal line 204 extending in the second horizontal direction Y. The third signal line 204 has a main body extension and a lead-out end, and the lead-out end of the third signal line 204 is located at at least one end of the main body extension in the second horizontal direction Y. The third signal line 204 is laminated with the first signal line 203 and the second signal line 205 along the vertical direction Z, and is insulated from adjacent signal lines via an insulating film layer. The second horizontal direction Y is parallel to the substrate 10, and the second horizontal direction Y intersects with the first horizontal direction X. Furthermore, the second horizontal direction Y may be mutually orthogonal to the first horizontal direction X.

[0034] The functional layer 20 further includes a fourth signal line 206 extending in the second horizontal direction Y. The fourth signal line 206 has a body extension and a pull-out end, and the pull-out end of the fourth signal line 206 is located at at least one end of the body extension in the second horizontal direction Y. The fourth signal line 206 is stacked with the first signal line 203, the second signal line 205, and the third signal line 204 along the vertical direction Z, and is insulated from adjacent signal lines by an insulating film layer.

[0035] Among these, the orthogonal projections of the main body extension of the fourth signal line 206 and the main body extension of the third signal line 204 overlap on the substrate 10, and the orthogonal projections of the lead-out end of the fourth signal line 206 and the lead-out end of the third signal line 204 do not overlap on the substrate 10. In other words, the lead-out end of the fourth signal line 206 and the lead-out end of the third signal line 204, which are located on different layers and extend in the same direction, are shifted so as not to overlap.

[0036] For example, in the functional layer 20, a third signal line 204 is formed between the first signal line 203 and the second signal line 205. In the functional layer 20, a fourth signal line 206 is formed between the third signal line 204 and the second signal line 205, or in the functional layer 20, the fourth signal line 206 is formed on the side of the second signal line 205 farther from the third signal line 204.

[0037] In addition, in the third signal line 204 and the fourth signal line 206, the pull-out ends have a first surface closer to the substrate 10 and a second surface farther from the substrate 10. In the third signal line 204 and the fourth signal line 206, the pull-out direction is the direction in which the first surface faces the second surface, or the direction in which the second surface faces the first surface. By setting the pull-out direction to be the direction in which the second surface faces the first surface, the pull-out structure connected to the third signal line 204 and the pull-out structure connected to the fourth signal line 206 can be pulled out from the same side, making manufacturing easier.

[0038] For example, in order to contact the tip of the pull-out structure (i.e., the starting end in the pull-out direction) to realize an electrical connection, the first surface of the pull-out ends of the third signal line 204 and the fourth signal line 206 may be the pull-out surface, or the second surface of the pull-out ends of the third signal line 204 and the fourth signal line 206 may be the pull-out surface, but is not limited to this. A groove or a through hole may be provided in the pull-out ends of the third signal line 204 and the fourth signal line 206, and the tip of the pull-out structure may be fitted into the groove or through hole to contact the pull-out ends of the third signal line 204 and the fourth signal line 206, thereby achieving an electrical connection.

[0039] In this embodiment, the third signal line 204 and the fourth signal line 206 can be designed to have different extension lengths, i.e., the extension lengths of the signal lines located in different layers and extending in the same direction can be designed to be different, so that among the multiple signal lines located in different layers and extending in the same direction, the longer signal line portion is not shielded by the shorter signal line. Note that, since the unshielded portion is the drawing end, the multiple signal lines located in different layers and extending in the same direction are arranged in a staircase shape, and the signal lines on each layer can be drawn out with different drawing structures.

[0040] Among these, the stacking positions of the longer signal line and the shorter signal line extending in the same direction can be determined according to the specific position of the drawing surface (i.e., the drawing direction). For example, in the third signal line 204 and the fourth signal line 206, when the direction in which the second surface faces the first surface is the drawing direction, the extension length of the third signal line 204 located in the same functional layer 20 is smaller than the extension length of the fourth signal line 206. Or, in the third signal line 204 and the fourth signal line 206, when the direction in which the first surface faces the second surface is the drawing direction, the extension length of the fourth signal line 206 located in the same functional layer 20 is smaller than the extension length of the third signal line 204.

[0041] Optionally, the third signal line 204 and the fourth signal line 206 are provided with lead-out ends at both ends of the main body extension in the second horizontal direction Y to facilitate connection to a control circuit.

[0042] When the functional layer 20 is provided in multiple layers, if the direction in which the second surface faces the first surface of the third signal line 204 and the fourth signal line 206 of two adjacent functional layers 20 is the pull-out direction, the length of the third signal line 204 of the functional layer 20 farther from the substrate 10 is greater than the length of the fourth signal line 206 of the functional layer 20 closer to the substrate 10, or if the direction in which the first surface faces the second surface of the third signal line 204 and the fourth signal line 206 is the pull-out direction, the length of the third signal line 204 of the functional layer 20 farther from the substrate 10 is less than the length of the fourth signal line 206 of the functional layer 20 closer to the substrate 10.

[0043] The semiconductor device may further include a first draw-out structure S1, a second draw-out structure S3, a third draw-out structure S2, and a fourth draw-out structure S4 arranged at intervals from each other, and the fourth draw-out structure S1 to the fourth draw-out structure S4 all extend in the vertical direction Z and have different extension lengths.

[0044] Among these, one end of the first lead-out structure S1 (i.e., the start end in the lead-out direction, which can also be defined as the tip) is in contact with the lead-out end of the first signal line 203, the other end of the first lead-out structure S1 (i.e., the end in the lead-out direction, which can also be defined as the terminal end) extends along the lead-out direction and penetrates each insulating film layer, one end of the second lead-out structure S3 (i.e., the start end in the lead-out direction, which can also be defined as the tip) is in contact with the lead-out end of the second signal line 205, and the other end of the second lead-out structure S3 (i.e., the end in the lead-out direction, which can also be defined as the terminal end) extends along the lead-out direction and penetrates each insulating film layer. One end of the third lead-out structure S2 (i.e., the starting end in the lead-out direction, which can also be defined as the tip) is in contact with the lead-out end of the third signal line 204, the other end of the third lead-out structure S2 (i.e., the terminal end in the lead-out direction, which can also be defined as the end) extends along the lead-out direction and penetrates each insulating film layer, and one end of the fourth lead-out structure S4 (i.e., the starting end in the lead-out direction, which can also be defined as the tip) is in contact with the lead-out end of the fourth signal line 206, and the other end of the fourth lead-out structure S4 (i.e., the terminal end in the lead-out direction, which can also be defined as the end) extends along the lead-out direction and penetrates each insulating film layer.

[0045] Hereinafter, specific embodiments of the present invention will be described in detail with reference to FIGS.

[0046] As shown in Figures 2 and 3, the functional layer 20 includes a plurality of memory units 20a arranged in an array along a first horizontal direction X and a second horizontal direction Y, and the functional layer 20 has an array-type memory structure, which can increase the memory density of each functional layer 20, but is not limited thereto, and according to specific circumstances, the functional layer 20 can also include a single memory unit 20.

[0047] In this embodiment, the memory unit 20a may be a 2TOC structure, specifically, as shown with reference to Figures 4 and 5, the memory unit 20a may include at least a first transistor 201, a second transistor 202, a first signal line 203, a third signal line 204, a second signal line 205, and a fourth signal line 206.

[0048] Among these, the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 each include a main body extension portion (not shown) and a pull-out end portion (not shown), and as shown with reference to Figures 2 and 3, the pull-out ends of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are located at opposite ends of the main body extension portion in the extension direction for connection to a pull-out structure.

[0049] In addition, the first transistor 201 is connected to the body extension of the first signal line 203 and the body extension of the third signal line 204, the second transistor 202 is connected to the body extension of the second signal line 205 and the body extension of the fourth signal line 206, and one or more of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are used to receive a level signal output by the control circuit via the pull-out structure or to output a level signal to the read-out circuit, thereby selecting the memory unit 20a to be read and written in the functional layer 20, and realizing data read and write operations.

[0050] As shown in FIG. 4 and FIG. 5, the first transistor 201 and the second transistor 202 each include a channel portion SD and a gate portion G insulated from the channel portion SD. Specifically, a gate insulating portion GI is formed between the channel portion SD and the gate portion G. The channel portion SD includes a first connection region, a second connection region, and a channel region located between the first connection region and the second connection region, which are not shown, and one of the first connection region and the second connection region is a source region, and the other is a drain region. The gate portion G includes a gate region, and specifically, the entire gate portion G can be understood as the gate region.

[0051] The first connection region of the first transistor 201 is connected to the body extension of the first signal line 203. For example, the first connection region of the first transistor 201 may be in direct contact with the body extension of the first signal line 203, but is not limited thereto, and may be indirectly electrically connected using other conductive structures. The second connection region of the first transistor 201 is connected to the body extension of the third signal line 204. For example, the second connection region of the first transistor 201 may be in direct contact with the body extension of the first signal line 203, but is not limited thereto, and may be indirectly electrically connected using other conductive structures. The first connection region of the second transistor 202 is connected to the gate region of the first transistor 201. For example, the first connection region of the second transistor 202 may be in direct contact with the gate region of the first transistor 201, or the first connection region of the second transistor 202 may be in contact with the gate region of the first transistor 201 via a conductive contact pad 207 to achieve the connection. The second connection region of the second transistor 202 is connected to the body extension of the second signal line 205. For example, the second connection region of the second transistor 202 may be in direct contact with the body extension of the second signal line 205, but is not limited to this, and may be indirectly electrically connected using other conductive structures. The gate region of the second transistor 202 is connected to the body extension of the fourth signal line 206. For example, the gate region of the second transistor 202 may be in direct contact with the body extension of the fourth signal line 206, but is not limited to this, and may be indirectly electrically connected using other conductive structures.

[0052] The memory unit 20a in this embodiment adopts a 2TOC structure, and compared to a 1T1C memory structure, it is possible to reduce the area occupied by one memory unit 20a while ensuring the memory performance of one memory unit 20a, and by appropriately increasing the number of memory units 20a in each layer of the functional layer 20, it is possible to improve the memory density of each layer of the functional layer 20, and ultimately improve the memory density of the entire semiconductor device.

[0053] For example, in the same functional layer 20, the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are stacked on each other, and two adjacent signal lines are insulated from each other by an insulating film layer, thereby reducing signal crosstalk between the first transistor 201 and the second transistor 202 and reducing the area occupied by the memory unit 20.

[0054] In this embodiment, "stacked" refers to each structure being located in a different film layer and each film layer being stacked in one direction, and "insulated from each other" refers to an insulating film layer being provided between two adjacent structures.

[0055] For example, the materials of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 may include one or more of conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver), and the insulating material may include SiO 2 (silicon dioxide), A12O3 (alumina), HfO2 (hafnium dioxide), TiO 2 (titanium dioxide) and SiN (silicon nitride).

[0056] Among these, in the same functional layer 20, the first signal line 203 and the second signal line 205 can both extend in the first horizontal direction X, and the third signal line 204 and the fourth signal line 206 can both extend in the second horizontal direction Y. By making the extending directions of the first signal line 203 and the third signal line 204 different and the extending directions of the second signal line 205 and the fourth signal line 206 different, it is possible to reduce the difficulty of designing and controlling the functional layer 20 while realizing the control of the transistor, and also to reduce the parasitic capacitance generated between the two signal lines to which the transistor is connected. By making the extending directions of the first signal line 203 and the second signal line 205 the same and the extending directions of the third signal line 204 and the fourth signal line 206 the same, it is possible to further reduce the difficulty of designing the memory unit 20a and reduce the occupied area.

[0057] Moreover, the first horizontal direction X and the second horizontal direction Y are orthogonal to each other to reduce the occupation area of ​​the storage unit 20 .

[0058] In addition, when the functional layer 20 includes a plurality of storage units 20a arranged in an array in the first horizontal direction X and the second horizontal direction Y, in order to reduce the difficulty of controlling the functional layer 20, as shown in FIG. 2, the plurality of storage units 20a arranged in the first horizontal direction X share a first signal line 203 and a second signal line 205 extending in the first horizontal direction X. The plurality of storage units 20a arranged in the second horizontal direction Y share a third signal line 204 and a fourth signal line 206 extending in the second horizontal direction Y. This reduces costs.

[0059] The first signal line 203 and the second signal line 205 in the functional layer 20 are stacked and extend in the same direction, and the third signal line 204 and the fourth signal line 206 are stacked and extend in the same direction, so that in the functional layer 20, in order to make it easier to independently extract signal lines located in different layers and extending in the same direction, in this embodiment, the lengths of the signal lines located in different layers and extending in the same direction can be designed to be different. That is, the extension lengths of the second signal line 205 and the first signal line 203 are different, and the extension lengths of the fourth signal line 206 and the third signal line 204 are different, so that among the multiple signal lines located in different layers and extending in the same direction, the longer signal line is not shielded by the shorter signal line, and the multiple signal lines located in different layers and extending in the same direction are arranged in a stepped manner, making it easier to extract the signal lines of each layer.

[0060] As shown in Figures 1 to 3, each functional layer 20 corresponds to a first draw-out structure S1, a third draw-out structure S2, a second draw-out structure S3, and a fourth draw-out structure S4 arranged at intervals, with the draw-out end of the first signal line 203 contacting the first draw-out structure S1, the draw-out end of the third signal line 204 contacting the third draw-out structure S2, the draw-out end of the second signal line 205 contacting the second draw-out structure S3, and the draw-out end of the fourth signal line 206 contacting the fourth draw-out structure S4, and each signal line can be connected to a control circuit or a read-out circuit by the draw-out structure it contacts, thereby realizing independent draw-out of the signal lines in the memory unit 20a.

[0061] In addition, the position where the pull-out end of the signal line contacts the pull-out structure may be the pull-out surface (i.e., the first surface or the second surface described above), and in this case, the insulating film layer formed on the side where the pull-out surface of the signal line is located may be penetrated by the corresponding pull-out structure.

[0062] 2 and 3, in the same functional layer 20, a first signal line 203, a third signal line 204, a second signal line 205 and a fourth signal line 206 are stacked in the vertical direction Z.

[0063] In this embodiment, the first horizontal direction X and the second horizontal direction Y are parallel to the substrate 10, and the vertical direction Z is perpendicular or nearly perpendicular to the substrate 10. That is, the extension directions of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are parallel to the substrate 10, and the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are stacked in a direction perpendicular to the substrate 10, thereby reducing the difficulty of manufacturing and the design cost.

[0064] Furthermore, as shown in Figures 2 to 5, when the first signal line 203, the third signal line 204, the second signal line 205 and the fourth signal line 206 are stacked in the vertical direction Z, the first transistor 201 and the second transistor 202 are also stacked on the substrate 10 in the vertical direction Z, thereby reducing the area occupied by the memory unit 20a and thereby increasing the memory density of the entire functional layer 20.

[0065] Among these, when the direction in which the first surface faces the second surface of each signal line is the drawing direction, that is, when the second signal line 205 is formed on the drawing side of the first signal line 203 and the fourth signal line 206 is formed on the drawing side of the third signal line 204, the extension length of the second signal line 205 is smaller than that of the first signal line 203 as shown in Fig. 2, and the extension length of the fourth signal line 206 is smaller than that of the third signal line 204 as shown in Fig. 3. This makes it easy to draw out each signal line by an independent drawing structure.

[0066] In the embodiment of the present invention, the orthogonal projection refers to a projection in a direction perpendicular to the substrate 10.

[0067] Optionally, in the same functional layer 20, the orthogonal projections of opposing ends of the second signal line 205 on the substrate 10 in the first horizontal direction X are both located within the orthogonal projections of the first signal line 203 on the substrate 10, and the orthogonal projections of opposing ends of the fourth signal line 206 on the substrate 10 in the second horizontal direction Y are both located within the orthogonal projections of the third signal line 204 on the substrate 10.

[0068] Furthermore, in the same functional layer 20, as shown in Fig. 2, the two opposing edges of the first signal line 203 in the first horizontal direction X do not overlap with the orthogonal projection of the second signal line 205 on the substrate 10. That is, the two opposing edges of the first signal line 203 in the first horizontal direction X on the far side from the substrate 10 are not shielded by the second signal line 205, and both of the opposing edges of the first signal line 203 in the first horizontal direction X are drawn out by the first drawing structure S1. As shown in Fig. 3, the two opposing edges of the third signal line 204 in the second horizontal direction Y do not overlap with the orthogonal projection of the fourth signal line 206 on the substrate 10. That is, neither of the two opposing edges of the third signal line 204 in the second horizontal direction Y that are far from the substrate 10 is shielded by the fourth signal line 206, and both of the two opposing edges of the third signal line 204 in the second horizontal direction Y are pulled out by the third pull-out structure S2, which facilitates the connection between the memory unit 20a and its surrounding circuits.

[0069] Continuing, as shown in FIG. 2, two opposing edges of the second signal line 205 in the first horizontal direction X are both pulled out by the second pull-out structure S3, and continuing, as shown in FIG. 3, two opposing edges of the fourth signal line 206 in the second horizontal direction Y are both pulled out by the fourth pull-out structure S4.

[0070] The two opposing edges herein refer to lead-out ends located at both opposing ends of the main body extension of each signal line in the extension direction.

[0071] As shown in FIG. 3, the number of first signal lines 203 may be the same as the number of second signal lines 205, and may correspond one-to-one in the vertical direction Z, and as shown in FIG. 2, the number of third signal lines 204 may be the same as the number of fourth signal lines 206, and may correspond one-to-one in the vertical direction Z, but this is not limited to this and the numbers do not have to be the same depending on specific circumstances.

[0072] Furthermore, the widths and / or thicknesses of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 can be designed to be equal, but are not limited to this. The widths and / or thicknesses of the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 can be designed to be slightly different depending on the actual situation, and can be designed according to the performance and processing conditions required for the actual semiconductor device.

[0073] In this embodiment, the direction in which the lead-out end of the signal line moves away from the substrate 10 can be defined as the lead-out direction. When the lead-out direction of the signal line is the direction in which the lead-out end moves away from the substrate 10, as shown in Figures 2 and 3, the second signal line 205 is formed on the side of the first signal line 203 farther from the substrate 10, and the fourth signal line 206 is formed on the side of the third signal line 204 farther from the substrate 10. By setting the lead-out direction of the signal line to the direction in which the lead-out end moves away from the substrate 10, after the formation of each film layer in the functional layer 20, the first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3, and the fourth lead-out structure S4 can be formed in a unified manner, realizing independent lead-out of each signal line, reducing the difficulty of production, and improving production efficiency.

[0074] It should be understood that if the direction of the lead-out end of the signal line is away from the substrate 10, the end of the lead-out structure farther from the substrate 10 may be connected to a control circuit or other circuit.

[0075] When the direction in which the lead-out ends of the signal lines are drawn away from the substrate 10 is the lead-out direction, the first signal line 203 and the third signal line 204 are arranged closer to the substrate 10 than the second signal line 205 and the fourth signal line 206, and the first transistor 201 is arranged closer to the substrate 10 than the second transistor 202. This makes it easier for the first signal line 203 and the third signal line 204 to be connected to the first transistor 201, and for the second signal line 205 and the fourth signal line 206 to be connected to the second transistor 202.

[0076] As shown in Figures 2 to 5, when the direction in which the pull-out end of the signal line moves away from the substrate 10 is the pull-out direction, the first signal line 203, the third signal line 204, the second signal line 205, and the fourth signal line 206 are stacked in sequence on the substrate 10 so that the extension directions of adjacent signal lines in the vertical direction Z in the functional layer 20 are different from each other, thereby reducing the parasitic capacitance generated between adjacent signal lines.

[0077] In addition, the present technical solution is not limited to designing the direction in which the lead-out end of the signal line moves away from the substrate 10 as the lead-out direction, but may also design the direction in which the lead-out end of the signal line approaches the substrate 10 as the lead-out direction. For example, when the lead-out direction of the signal line is the direction in which the lead-out end of the signal line approaches the substrate 10, the extension length of the second signal line 205 may be longer than the extension length of the first signal line 203, and the extension length of the fourth signal line 206 may be longer than the extension length of the third signal line 204. In this case, after each film layer of the functional layer 20 is formed in sequence, a lead-out structure can be uniformly formed on the substrate 10 side.

[0078] In addition, in the case where the direction in which the lead-out end of the signal line moves away from the substrate 10 is the lead-out direction, when the functional layers 20 of the semiconductor device are provided in multiple layers and stacked on the substrate 10 in the vertical direction Z, as shown in FIG. 2, the extension length of the first signal line 203 in the functional layer 20 farther from the substrate 10 is shorter than the extension length of the second signal line 205 in the functional layer 20 closer to the substrate 10 between two adjacent functional layers 20. As shown in FIG. 3, the extension length of the third signal line 204 in the functional layer 20 farther from the substrate 10 is shorter than the extension length of the fourth signal line 206 in the functional layer 20 closer to the substrate 10. This makes it easy to independently lead out signal lines located in different layers and extending in the same direction throughout the semiconductor device.

[0079] In other words, when the direction in which the drawn-out end of a signal line moves away from substrate 10 is the drawn-out direction, the extension length of signal lines located on different layers and extending in the same direction throughout the semiconductor device gradually decreases in the direction away from substrate 10.

[0080] In order to protect the structure of each memory unit 20 in the functional layer 20 , the functional layer 20 also includes an insulating film layer covering the memory unit 20 .

[0081] As shown in Figures 2 and 3, in the functional layer 20, the first lead-out structure S1 penetrates each insulating film layer on the lead-out direction side, the third lead-out structure S2 penetrates each insulating film layer on the lead-out direction side, the second lead-out structure S3 penetrates each insulating film layer on the lead-out direction side, and the fourth lead-out structure S3 penetrates each insulating film layer on the lead-out direction side.

[0082] Among these, the first lead-out structure S1, the third lead-out structure S2, the second lead-out structure S3, and the fourth lead-out structure S4 all extend in the vertical direction Z and have different extension lengths. Naturally, it can be seen that the closer the signal line is to the substrate 10, the greater the extension length of the connected lead-out structure.

[0083] After multiple functional layers 20 are sequentially stacked on the substrate 10, the first lead structure S1, the third lead structure S2, the second lead structure S3, and the fourth lead structure S4 corresponding to each functional layer 20 are uniformly formed, thereby simplifying the processing process and reducing costs.

[0084] In this embodiment, the second connection region of the channel portion SD in the transistor may be located on the far side of the channel region from the first connection region, i.e., the channel region of the channel portion SD may extend in the vertical direction Z. In this way, the length of the channel region can be increased without increasing the horizontal area of ​​the memory unit 20a, thereby increasing the memory density and reducing the leakage current. As shown in Figures 2 to 5, the gate portion G and the channel portion SD are arranged opposite to each other at least in a direction parallel to the substrate 10.

[0085] Optionally, the materials of the channel portion SD and the gate portion G are both semiconducting materials, and the gate portion G is made of a semiconducting material, which makes it easier to control the threshold voltage of the transistor and reduces defects in the interface.

[0086] Of these, the semiconductor material is either IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), or ITO (indium tin oxide), which is advantageous for reducing the leakage current of the transistor and reducing the power consumption of the transistor, but is not limited to these, and other semiconductor materials such as silicon can also be used.

[0087] It should be understood that the semiconductor materials of the channel portion SD and the gate portion G may be the same or different, for example, the semiconductor material of the channel portion SD may include IGZO and the semiconductor material of the gate portion G may include IGZO.

[0088] For example, the first connection region of the channel portion SD of the first transistor 201 is formed between the gate portion G and the first signal line 203, and both the channel region and the second connection region of the channel portion SD of the first transistor 201 are arranged surrounding the gate portion G. It should be understood that the channel region and the second connection region of the channel portion SD of the first transistor 201 are not limited to being arranged surrounding the gate portion G, and may be arranged on both opposing sides of the gate portion G. The first connection region of the channel portion SD of the second transistor 202 is formed between the gate portion G and the gate portion G of the first transistor 201, and both the channel region and the second connection region of the second transistor 202 are arranged surrounding the gate portion G. In other words, it can be seen that the cross sections of the channel portions SD of the first transistor 201 and the second transistor 202 in the vertical direction Z are U-shaped. Such a design allows the channel regions of the first transistor 201 and the second transistor 202 to have longer lengths without changing the horizontal area compared to flat vertical transistors, thereby increasing storage density.

[0089] Optionally, to increase the integration density of the semiconductor structure, as shown in Figures 2 to 5, the third signal line 204 is arranged around the second connection region of the first transistor 201, and the second signal line 205 is arranged around the second connection region of the second transistor 202.

[0090] In this embodiment, a conductive contact pad 207 is formed between the first connection region of the channel portion SD of the second transistor 202 and the gate portion G of the first transistor 201, and the orthogonal projections of the gate portions G of the first transistor 201 and the second transistor 202 on the substrate 10 overlap with the orthogonal projections of the conductive contact pad 207 on the substrate 10. Furthermore, the orthogonal projections of the gate portions G of the first transistor 201 and the second transistor 202 on the substrate 10 can be located within the orthogonal projections of the conductive contact pad 207 on the substrate 10. By providing the conductive contact pad 207, it is possible to ensure an electrical conduction area between the gate portion G of the first transistor 201 and the first connection region of the second transistor 202, and to ensure the operating performance of the memory unit 20a.

[0091] The embodiment of the present invention also provides a method for manufacturing a semiconductor device used to manufacture the semiconductor device described in any of the above-mentioned embodiments. The method for manufacturing a semiconductor device includes providing a substrate 10 and forming at least one functional layer 20 on the substrate 10. The layout relationship, configuration shape, length relationship, and drawing direction between each component in the functional layer 20 can be referred to the contents shown in Figures 1 to 5 and the contents described in any of the above-mentioned embodiments, and the description thereof will be omitted here.

[0092] In this embodiment, the step of forming the functional layer 20 may include:

[0093] In step S1, a first signal line 203 extending in a first horizontal direction X and a first insulating film layer 209 covering the first signal line 203 are formed on a substrate 10.

[0094] In step S2, the second signal line 205 extending in the first horizontal direction X is formed on the side of the first insulating film layer 209 remote from the substrate 10.

[0095] In this embodiment, the step of forming the functional layer 20 may further include:

[0096] Before forming the second signal line 205, the third signal line 204, the second insulating film layer 210, the fourth signal line 206, and the third insulating film layer 212 are sequentially formed on the side of the first insulating film layer 209 farther from the substrate 10, and the third signal line 204 and the fourth signal line 206 all extend in the second horizontal direction Y, the third signal line 204 and the fourth signal line 206 are insulated from each other via the second insulating film layer 210, and the fourth signal line 206 and the second signal line 205 are insulated from each other via the third insulating film layer 212, or Before forming the second signal line 205, the third signal line 204 and the second insulating film layer 210 are sequentially formed on the side of the first insulating film layer 209 farther from the substrate 10. After forming the second signal line 205, the third insulating film layer 212 and the fourth signal line 206 are sequentially formed. The third signal line 204 and the fourth signal line 206 both extend in the second horizontal direction Y. The third signal line 204 and the second signal line 205 are insulated from each other via the second insulating film layer 210, and the second signal line 205 and the fourth signal line 206 are insulated from each other via the third insulating film layer 212.

[0097] Hereinafter, a manufacturing method according to an embodiment of the present invention will be described in detail with reference to FIGS.

[0098] The steps of forming the functional layer 20 on the substrate 10 may specifically include steps S100, S102, S104, S106, S108, S110, S112, S114, S116, and the like.

[0099] In step S100, the first signal line 203 and the first insulating film layer 209 covering the first signal line 203 are formed in this order on the substrate 10.

[0100] For example, if substrate 10 includes a semiconductor substrate 101 and an insulating isolation layer 102 formed on semiconductor substrate 101, forming a first signal line 203 on substrate 10 can be understood to mean forming the first signal line 203 on the side of insulating isolation layer 102 away from semiconductor substrate 101.

[0101] As an example, the step of forming the first signal line 203 may specifically include step S1001, step S1002, and step S1003.

[0102] In step S1001, as shown in FIG. 6, a plurality of first signal lines 203 are formed at intervals in the second horizontal direction Y on the substrate 10.

[0103] In step S1002, as shown in FIG. 7, a first isolating material film 213a is formed to cover each of the first signal lines 203 and fill the spaces between adjacent first signal lines 203.

[0104] 8, a portion of the first isolation material film 213a that is higher than the first signal line 203 is removed to form a first isolation pattern layer 213, and a surface of the first isolation pattern layer 213 that is farther from the substrate 10 is flush with a surface of the first signal line 203 that is farther from the substrate 10. That is, the surface of the first signal line 203 that is farther from the substrate 10 is exposed, and the first isolation pattern layer 213 includes at least a first isolation portion 2131 that is filled between adjacent first signal lines 203.

[0105] After step S1003 is performed, a first insulating film layer 209 that covers the first signal line 203 is formed.

[0106] In step S102, a third signal line 204 and a second insulating film layer 210 covering the third signal line 204 are sequentially formed on the side of the first insulating film layer 209 away from the substrate 10, and the main body extension portion of the third signal line 204 overlaps with the main body extension portion of the first signal line 203 on the substrate 10.

[0107] As an example, the step of forming the third signal line 204 may specifically include step S1021, step S1022, and step S1023.

[0108] In step S1021, as shown in FIG. 9, a plurality of third signal lines 204 are formed at intervals in the first horizontal direction X on the side of the first insulating film layer 209 remote from the substrate 10.

[0109] In step S1022, as shown in FIG. 10, a second isolating material film 214a is formed to cover each of the third signal lines 204 and to fill spaces between adjacent third signal lines 204.

[0110] 11, a portion of the second isolation material film 214a that is higher than the third signal line 204 is removed to form a second isolation pattern layer 214, and a surface of the second isolation pattern layer 214 that is farther from the substrate 10 is flush with a surface of the third signal line 204 that is farther from the substrate 10. That is, the surface of the third signal line 204 that is farther from the substrate 10 is exposed, and the second isolation pattern layer 214 includes at least a second isolation portion 2141 that is filled between adjacent third signal lines 204.

[0111] After step S1023 is performed, the second insulating film layer 210 that covers the third signal line 204 is formed.

[0112] In step S104, as shown in FIGS. 12 and 13, a first through hole H1 is formed which penetrates in order through the second insulating film layer 210, the main body extension of the third signal line 204, and the first insulating film layer 209, and the first through hole H1 exposes the surface of the main body extension of the first signal line 203 that is farther from the substrate 10.

[0113] 12 and 13, in the orthogonal projection on the substrate 10, the first through-hole H1 is located within the intersection of the body extension of the first signal line 203 and the body extension of the third signal line 204. This reduces the difficulty in connecting the subsequent first transistor 201 to the first signal line 203 and the third signal line 204.

[0114] In step S106, as shown in Figures 14 and 15, a first transistor 201 is formed in the first through hole H1, and a first connection region of the first transistor 201 is contacted to a body extension portion of the first signal line 203, and a second connection region of the first transistor 201 is contacted to a body extension portion of the third signal line 204.

[0115] In step S108, an interlayer insulating film layer 211 that covers the first transistor 201 and the second insulating film layer 210 is formed.

[0116] In step S110, the second signal line 205 and the third insulating film layer 212 covering the second signal line 205 are formed in sequence on the side of the interlayer insulating film layer 211 farther from the substrate 10.

[0117] As an example, the step of forming the second signal line 205 may specifically include step S1101, step S1102, and step S1103.

[0118] In step S1101, as shown in FIG. 16, a plurality of second signal lines 205 are formed at intervals in the second horizontal direction Y on the side of the interlayer insulating film layer 211 remote from the substrate 10.

[0119] In step S1102, as shown in FIG. 17, a third isolating material film 215a is formed to cover each second signal line 205 and fill spaces between adjacent second signal lines 205.

[0120] 18, a portion of the third isolation material film 215a that is higher than the second signal line 205 is removed to form a third isolation pattern layer 215, and a surface of the third isolation pattern layer 215 that is farther from the substrate 10 is flush with a surface of the second signal line 205 that is farther from the substrate 10. That is, the surface of the second signal line 205 that is farther from the substrate 10 is exposed, and the third isolation pattern layer 215 includes at least a third isolation portion 2151 that is filled between adjacent second signal lines 205.

[0121] After step S1103 is performed, a third insulating film layer 212 that covers the second signal line 205 is formed.

[0122] In step S112, as shown in Figures 19 and 20, a second through hole H2 is formed which penetrates the third insulating film layer 212, the second signal line 205, and the interlayer insulating film layer 211 in that order, and the orthogonal projections of the second through hole H2 and the first through hole H1 on the substrate 10 overlap.

[0123] In step S114, as shown in Figures 21 and 22, a second transistor 202 is formed in the second through hole H2, and a first connection region of the second transistor 202 is connected to the gate region (i.e., gate portion G) of the first transistor 201, and a second connection region of the second transistor 202 is contacted to the body extension portion of the second signal line 205.

[0124] For example, in the orthogonal projection on the substrate 10, the second through-hole H2 is located within the intersection of the body extension of the second signal line 205 and the body extension of the fourth signal line 206. This reduces the difficulty in connecting the subsequent second transistor 202 to the second signal line 205 and the fourth signal line 206.

[0125] As an example, a conductive contact pad 207 may be formed prior to forming the second transistor 202 to realize a connection between the first connection region of the second transistor 202 and the gate region of the first transistor 201.

[0126] Specifically, after forming the first transistor 201 and before forming the interlayer insulating film layer 211, the manufacturing method further includes a step S107 of forming a conductive contact pad 207, the side of the conductive contact pad 207 closer to the substrate 10 being contacted with the gate region of the first transistor 201, and the side of the conductive contact pad 207 farther from the substrate 10 being contacted with the first connection region of the second transistor 202.

[0127] In order to prevent a short circuit between the channel portion SD and the gate portion G of the first transistor 201, the conductive contact pad 207 and the channel portion SD of the first transistor 201 are insulated from each other. For example, the side of the channel portion SD farther from the substrate 10 is covered with a gate insulating portion GI, and the conductive contact pad 207 is insulated from the channel portion SD of the first transistor 201 via the gate insulating portion GI, but other insulating film layers may be provided.

[0128] Among these, step S107 may specifically include step S1071, step S1072, step S1073, step S1074, step S1075, step S1076, and step S1077.

[0129] In step S1071, a first conductive material film 301 and a first sacrificial material film 311 are formed in this order, and the first conductive material film 301 and the first sacrificial material film 311 cover the second insulating film layer 210 and the first transistor 201.

[0130] For example, the first sacrificial material film 311 may include, but is not limited to, a laminate of multiple film layers, such as a SOC (spin-on carbon) film layer and a SiN (silicon nitride) film layer, which are stacked in sequence, and the first sacrificial material film 311 may have a single-layer structure, and the material may include one or more insulating materials, such as silicon oxynitride and silicon oxide.

[0131] In step S1072, as shown in FIG. 23 , a first photoresist mask pattern layer 321 is formed on the side of the first sacrificial material film 311 farther from the first conductive material film 301, and the first photoresist mask pattern layer 321 includes a plurality of first photolithography via holes 3210 arranged in an array in a first horizontal direction X and a second horizontal direction Y, and the first photolithography via holes 3210 correspond one-to-one to the first transistors 201.

[0132] In step S1073, as shown in FIG. 24, the first sacrificial material film 311 is patterned using a first photoresist mask pattern layer 321 to form a first sacrificial pattern layer 3110, which includes a plurality of spaced apart first sacrificial via holes 31101, which correspond one-to-one to the first photolithographic via holes 3210, and which expose the surface of the first conductive material film 301 away from the substrate 10.

[0133] In step S1074, the first photoresist mask pattern layer 321 is removed, and then a first intermediate mask material film is formed, which covers the surface of the first sacrificial pattern layer 3110 away from the substrate 10 and fills the first sacrificial via hole 31101.

[0134] In step S1075, as shown in FIG. 25, a portion of the first intermediate mask material film that is higher than the first sacrificial pattern layer 3110 is removed to form a first intermediate mask pattern layer, the first intermediate mask pattern layer including a plurality of spaced apart first intermediate mask blocks 331, the first intermediate mask blocks 331 being disposed within the first sacrificial via holes 31101, and the surface of the first intermediate mask blocks 331 facing away from the substrate 10 being flush with the surface of the first sacrificial pattern layer 3110 facing away from the substrate 10.

[0135] In other embodiments, the first sacrificial material film 311 may be multiple sub-layers stacked in sequence. For example, when the first sacrificial material film 311 is a SOC film layer and a SiN film layer stacked in sequence, the material of the first intermediate mask material film may be SiN, and reverse silicon nitride deposition can be achieved by removing the SiN higher than the top surface of the SOC film layer, the removal process may be a planarization process, the removal process may be the SOC film layer as a stop layer, and the planarization process may be chemical mechanical polishing (CMP). However, the material of the first intermediate mask material film may be, but is not limited to, SiON or SiO 2or the like, and the removal process may select other process methods such as etching, and the endpoint of the removal process may be the entire first sacrificial material film 311 or the top surface of any sub-layer therein.

[0136] In step S1076, the first sacrificial pattern layer 3110 is removed, leaving the first intermediate mask block 331, as shown in FIG.

[0137] In step S1077, as shown in FIG. 27, the first conductive material film 301 is patterned using a first intermediate mask block 331 to form a plurality of spaced apart conductive contact pads 207 in one-to-one correspondence with the first transistors 201.

[0138] Here, after forming the conductive contact pads 207 and before forming the interlayer insulating film layer 211, the manufacturing method further includes the steps of: As shown in FIG. 28, forming a fourth isolation material film 216a on the side of the second insulating film layer 210 away from the substrate, the fourth isolation material film 216a covering each conductive contact pad 207 and filling between adjacent conductive contact pads 207; 29, a portion of the fourth isolation material film 216a that is higher than the conductive contact pads 207 is removed to form a fourth isolation pattern layer 216, and the surface of the fourth isolation pattern layer 216 that is farther from the substrate 10 is flush with the surface of the conductive contact pads 207 that is farther from the substrate 10. That is, the surface of the conductive contact pads 207 that is farther from the substrate 10 is exposed, and the fourth isolation pattern layer 216 includes at least a fourth isolation portion 2161 that is filled between adjacent conductive contact pads 207.

[0139] In step S116, a fourth signal line 206 and a fourth insulating film layer 208 covering the fourth signal line 206 are formed on the side of the second transistor 202 away from the substrate 10, and the body extension of the fourth signal line 206 is in contact with the gate region (i.e., gate portion G) of the second transistor 202.

[0140] In order to prevent a short circuit between the channel portion SD and the gate portion G of the second transistor 202, the body extension of the fourth signal line 206 is insulated from the channel portion SD of the second transistor 202. For example, the side of the channel portion SD farther from the substrate 10 is covered with a gate insulating portion GI, and the body extension of the fourth signal line 206 is insulated from the channel portion SD of the second transistor 202 via the gate insulating portion GI, but other insulating film layers may be provided.

[0141] From the above, it can be seen that in this embodiment, the manufacturing method of the first signal line 203 to the fourth signal line 206 may be the same. Specifically, the step of forming the first signal line 203 to the fourth signal line 206 includes first forming a plurality of signal lines arranged at intervals (i.e., first forming a conductive pattern layer), then forming a separation material film that covers each signal line and fills between adjacent signal lines, and then removing parts of the separation material film that are higher than the signal lines to expose the upper surfaces of the signal lines to form a separation pattern layer, the surface of the separation pattern layer farther from the substrate is flush with the surface of the signal lines farther from the substrate, and the separation pattern layer includes at least a separation part that fills between adjacent signal lines.

[0142] After forming the plurality of fourth signal lines 206 arranged at intervals, it is not necessary to remove the portion of the fourth insulating film layer 208 that is higher than the fourth signal line 206, but this is not limited to the above. Similar to the method of forming the other first signal lines 203 to third signal lines 204, after removing the portion of the fourth insulating film layer 208 that is higher than the fourth signal line 206, subsequent manufacturing may be performed depending on specific circumstances, such as covering other insulating film layers or conductive layers.

[0143] In this embodiment, the fabrication of the conductive contact pads 207 and the fourth isolation pattern layer 216 can also be omitted.

[0144] In an embodiment, the methods for forming the plurality of spaced apart first signal lines 203, third signal lines 204, second signal lines 205, and fourth signal lines 206 may be the same. Specifically, the steps of forming the plurality of spaced apart signal lines (i.e., conductive pattern layers) may include step S10, step S11, step S12, step S13, step S14, step S15, step S16, step S17, step S18, and step S19.

[0145] In step S10, the second conductive material film 401, the hard mask material film 501, and the second sacrificial material film 411 are formed on the substrate 10 in this order.

[0146] To ensure better collimation for etching downwards, the hardness of the hard mask material film 501 may be greater than the hardness of the second sacrificial material film 411 .

[0147] For example, the hard mask material film 501 may be an amorphous carbon (AC) film, but is not limited thereto, and other materials may be used. The second sacrificial material film 411 may include a plurality of film layers, such as a SiON film layer, a SOC film layer, and a SiON film layer, which are stacked in order, but is not limited thereto, and other insulating materials may be used. It may also be a single-layer film, but this will not be described in detail here.

[0148] In this embodiment, depending on the circumstances, the formation of the hard mask material film 501 may be omitted.

[0149] In step S11, as shown in FIG. 31, a second photoresist mask pattern layer is formed on the side of the second sacrificial material film 411 away from the substrate 10, and the second photoresist mask pattern layer includes a plurality of photoresist mask strips 421 spaced apart in the P direction.

[0150] In step S12, as shown in FIG. 32, the second sacrificial material film 411 is patterned using a second photoresist mask pattern layer to form a second sacrificial pattern layer, the second sacrificial pattern layer includes a plurality of sacrificial mask strips 4111 spaced apart in the P direction, and the sacrificial mask strips 4111 and the photoresist mask strips 421 have a one-to-one correspondence.

[0151] In step S13, the second photoresist mask pattern layer is removed, and then an intermediate mask material film 502 is formed covering each sacrificial mask strip 4111, as shown in FIG.

[0152] For example, the material of the intermediate mask material film 502 is SiO 2 However, the present invention is not limited to this and may be made of an insulating material such as SiON or SiN.

[0153] In step S14, as shown in FIG. 33, a trimming mask layer 503 is formed on the side of the intermediate mask material film 502 away from the substrate 10, and the sacrificial mask strip 4111 has at least one edge region in its extension direction (e.g., direction Q in FIG. 33) that is not covered by the trimming mask layer 503.

[0154] For example, the trimming mask layer 503 may be a photoresist processed by a photolithography process, but is not limited thereto, and may be other materials, which will not be described in detail here.

[0155] 34, in step S15, the trimming mask layer 503 is utilized to remove the portion of the intermediate mask material film 502 that is not covered by the trimming mask layer 503. At this time, the portion of the sacrificial mask strip 4111 that is not covered by the trimming mask layer 503 is exposed, but this is not limiting, and in this step, in addition to the portion of the intermediate mask material film 502 that is not covered by the trimming mask layer 503, the portion of the sacrificial mask strip 4111 that is not covered by the trimming mask layer 503 can also be removed.

[0156] 35, in step S16, the trimming mask layer 503 is removed, and the intermediate mask material film 502 is patterned to form an intermediate mask pattern layer, which is composed of a plurality of intermediate mask strips 5021 separated from each other in the P direction, and the intermediate mask strips 5021 are formed on two opposing side surfaces of each sacrificial mask strip 4111, and the intermediate mask strips 5021 formed on the adjacent side surfaces of two adjacent sacrificial mask strips 4111 are separated from each other. That is, two intermediate mask strips separated from each other are provided between two adjacent sacrificial mask strips 4111, and are formed on the side walls of one sacrificial mask strip 4111, respectively.

[0157] It should be noted that when the intermediate mask material film 502 is patterned, only the intermediate mask material formed on the sidewalls of the sacrificial mask strips 4111 is retained to form the intermediate mask strips 5021, and the intermediate mask material at the remaining positions (e.g., the side of the sacrificial mask strips 4111 away from the substrate 10 and the hard mask material film 501) is removed so that the sacrificial mask strips 4111 are separated from each other.

[0158] In step S17, as shown in FIG. 36 , the sacrificial pattern layer is removed, and the intermediate mask pattern layer is used to pattern the hard mask material film 501 to form a hard mask pattern layer, where the hard mask pattern layer includes a plurality of hard mask strips 5011 spaced apart in the P direction, and the hard mask strips 5011 have a one-to-one correspondence with the intermediate mask strips 5021.

[0159] In step S18, as shown in FIG. 37, the intermediate mask strips 5021 are removed, and the second conductive material film 401 is patterned using a hard mask pattern layer to form a conductive pattern layer, which includes a plurality of spaced apart signal lines 4011, and the signal lines 4011 have a one-to-one correspondence with the hard mask strips 5011.

[0160] In step S19, as shown in FIG. 38, the hard mask pattern layer is removed.

[0161] When the signal line 4011 formed by sequentially applying steps S10, S11, S12, S13, S14, S15, S16, S17, S18, and S19 is the first signal line 203 or the second signal line 203 described above, the P direction can be understood as the second horizontal direction Y described above, and the Q direction can be understood as the first horizontal direction X described above. However, when the signal line 4011 formed by sequentially applying steps S10, S11, S12, S13, S14, S15, S16, S17, S18, and S19 is the third signal line 204 or the fourth signal line 206 described above, the P direction can be understood as the first horizontal direction X described above, and the Q direction can be understood as the second horizontal direction Y described above.

[0162] The length in the first horizontal direction X of the trimming mask layer 503 used in the step of forming the first signal line 203 is a first length, the length in the first horizontal direction X of the trimming mask layer 503 used in the step of forming the second signal line 205 is a second length, the length in the second horizontal direction Y of the trimming mask layer 503 used in the step of forming the third signal line 204 is a third length, and the length in the second horizontal direction Y of the trimming mask layer 503 used in the step of forming the fourth signal line 206 is a fourth length.

[0163] Here, in the same functional layer 20, when the first surface is the extraction surface, the second length is greater than the first length such that the extension length of the second signal line 205 is greater than the extension length of the first signal line 203, and the fourth length is greater than the third length such that the extension length of the fourth signal line 206 is greater than the extension length of the third signal line 204; or, when the second surface is the extraction surface, the second length is smaller than the first length such that the extension length of the second signal line 205 is smaller than the extension length of the first signal line 203, and the fourth length is smaller than the third length such that the extension length of the fourth signal line 206 is smaller than the extension length of the third signal line 204.

[0164] Specifically, assuming that the second surface is the extraction surface, the steps of forming the first signal line 203 and the second signal line 205 are similar to each other except that the extension lengths of the trimming mask layer 503 in the Q direction in step S14 are different. For example, the extension length of the trimming mask layer 503 corresponding to the second signal line 205 in the Q direction is smaller than the extension length of the trimming mask layer 503 corresponding to the first signal line 203 in the Q direction so that the extension length of the second signal line 205 finally formed is smaller than the extension length of the first signal line 203. Similarly, the steps of forming the third signal line 204 and the fourth signal line 206 are similar to each other except that the extension lengths of the trimming mask layer 503 in the P direction in step S14 are different. For example, the extension length in the P direction of the trimming mask layer 503 corresponding to the fourth signal line 206 is smaller than the extension length in the P direction of the trimming mask layer 503 corresponding to the third signal line 204 so that the extension length of the fourth signal line 206 that is finally formed is smaller than the extension length of the third signal line 204.

[0165] For example, the above-mentioned conductive material film, hard mask material film 501 and second sacrificial material film 411 can be formed using a deposition process such as, but not limited to, CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), etc., and a coating process or the like may also be used depending on the specific situation.

[0166] For example, the material of the conductive material film may be one or more of conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), and the insulating material may be SiO 2 (silicon dioxide), A12O3 (aluminum oxide), HfO2 (hafnium dioxide), TiO 2(titanium dioxide), SiN (silicon nitride), and the like.

[0167] In addition, if the production of the hard mask material film 501 in step S10 is omitted, after removing the sacrificial pattern layer, the second conductive material film 401 can be directly patterned using the intermediate mask pattern layer to form a conductive pattern layer.

[0168] In a specific embodiment, the steps of forming the first through hole H1 and the second through hole H2 may include step S20, step S21, step S22, step S23, step S24, step S25, and step S26, respectively.

[0169] In step S20, a third sacrificial material film 601 is formed on the side of the laminate structure including a lower insulating film layer 602, an intermediate signal line 603, and an upper insulating film layer 604, which are laminated in this order on the substrate 10, farther from the substrate 10.

[0170] For example, the third sacrificial material film 601 may include multiple film layers, such as a SiON film layer, a SOC film layer, and a SiON film layer, which are stacked in sequence, but is not limited thereto, and other insulating materials may be used. It may also be a single layer film, but this will not be described in detail here.

[0171] In step S21, as shown in FIG. 39, a third photoresist mask pattern layer 605 is formed on a side of the third sacrificial material film 601 away from the substrate 10, and the third photoresist mask pattern layer 605 includes a plurality of third photolithographic via holes 6051 arranged in an array along the first horizontal direction X and the second horizontal direction Y.

[0172] In step S22, as shown in FIG. 40, the third sacrificial material film 601 is patterned using a third photoresist mask pattern layer 605 to form a third sacrificial pattern layer 6011, which includes a plurality of spaced apart third sacrificial via holes 60111, which correspond one-to-one to the third photolithography via holes 6051, and which expose the surface of the upper insulating film layer 604 away from the substrate 10.

[0173] In step S23, as shown in FIG. 41, the third photoresist mask pattern layer 605 is removed, and then an insulating material film 606 is formed, which covers the surface of the third sacrificial pattern layer 6011 farther from the substrate 10 and fills in the third sacrificial via hole 60111, and the portion of the insulating material film 606 located in the third sacrificial via hole 60111 is a blind groove structure 6061.

[0174] For example, the insulating material film 606 may be, but is not limited to, silicon oxide, or other insulating material, which may be formed using, but is not limited to, an ALD deposition process, or may be formed using CVD or other deposition processes.

[0175] In step S24, as shown in FIG. 42, a portion of the insulating material film 606 that is higher than the third sacrificial pattern layer 6011 and the bottom wall of the blind groove structure 6061 are removed, leaving the side walls of the blind groove structure 6061 to form a target etching hole 60611, the opening of which is smaller than the opening of the third sacrificial via hole 60111.

[0176] In step S25, as shown in FIG. 43, the stacked structure is patterned using the target etching holes 60611 to form through holes H penetrating the stacked structure.

[0177] In step S26, the third sacrificial pattern layer 6011 of the laminate structure and the sidewalls of the blind groove structures 6061 are removed, as shown in FIG.

[0178] Among these, in the step of forming the through hole H as the first through hole H1, the lower insulating film layer 602 is the first insulating film layer 209, the intermediate signal line 603 is the third signal line 204, and the upper insulating film layer 604 is the second insulating film layer 210. In the step of forming the through hole H as the second through hole H2, the lower insulating film layer 602 is the interlayer insulating film layer 211, the intermediate signal line 603 is the second signal line 205 or the fourth signal line 206, and the upper insulating film layer 604 is the third insulating film layer 212.

[0179] In this embodiment, the material of the interlayer insulating film is SiO 2 (silicon dioxide), Al 2 O 3 (aluminum oxide), HfO2 (hafnium dioxide), TiO 2 (titanium dioxide), SiN (silicon nitride), and the like.

[0180] In one embodiment, the steps of forming the first transistor 201 and the second transistor 202 each include: forming a channel film that covers a surface of the laminated structure that is far from the substrate 10 and fills through holes in the laminated structure; The channel film is patterned to form a groove-shaped channel portion SD located in the through hole, and a surface of a side wall of the groove in the channel portion SD farther from the substrate 10 is lower than a surface of the laminated structure farther from the substrate 10; a gate insulating film and a gate film are formed in this order, the gate insulating film and the gate film cover the surface of the laminated structure remote from the substrate 10 and the surface of the sidewall of the groove in the channel portion SD remote from the substrate 10, and are filled in the groove of the channel portion SD, a portion of the gate insulating film located in the through hole is a gate insulating portion GI, a portion of the gate insulating portion GI is located in the groove of the channel portion SD and a portion of the gate insulating portion GI covers the surface of the sidewall of the groove in the channel portion SD remote from the substrate 10, a portion of the gate insulating portion GI located in the groove of the channel portion SD is groove-shaped, a portion of the gate film located in the groove of the gate insulating portion GI is a gate portion G, and the groove of the gate insulating portion GI is filled with the gate portion G; The method includes removing portions of the gate insulating film and the gate film that are higher than the stacked structure so that the surfaces of the stacked structure, the gate insulating portion GI, and the gate portion G that are farther from the substrate 10 are exposed and are flush with each other, thereby forming a transistor located in the through hole.

[0181] In the step of forming the first transistor 201, the stacked structure includes a first insulating film layer 209, a third signal line 204 and a second insulating film layer 210 stacked in this order, and the through hole is a first through hole H1, and in the step of forming the second transistor 202, the stacked structure includes an interlayer insulating film layer 211, a second signal line 205 and a third insulating film layer 212 stacked in this order, and the through hole is a second through hole H2.

[0182] For example, the channel film and the gate film may be one of IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), and ITO (indium tin oxide), which are beneficial for reducing the leakage current and reducing the power consumption of the transistor, but are not limited thereto, and may be other semiconductor materials such as silicon. The material of the gate insulating film is SiO 2 (Silicon dioxide), Al 2 O 3 (aluminum oxide), HfO2 (hafnium dioxide), TiO 2 (titanium dioxide), SiN (silicon nitride), and the like.

[0183] In this embodiment, the step of forming at least one functional layer 20 on the substrate 10 may specifically include the step of sequentially forming a plurality of functional layers 20 on the substrate 10, as shown in FIGS. 1 to 3.

[0184] As shown in Figures 2 and 3, of two adjacent functional layers 20, the functional layer 20 farther from the substrate 10 is defined as the upper functional layer, and the functional layer 20 closer to the substrate 10 is defined as the lower functional layer 20. When the second surface is an extraction surface, the length in the first horizontal direction X of the trimming mask layer 503 used in the step of forming the first signal line 203 of the upper functional layer is smaller than the length in the first horizontal direction X of the trimming mask layer 503 used in the step of forming the second signal line 205 of the lower functional layer so that the extension length of the first signal line 203 of the upper functional layer is smaller than the extension length of the second signal line 205 of the lower functional layer, and the length in the second horizontal direction Y of the trimming mask layer 503 used in the step of forming the third signal line 204 of the upper functional layer is smaller than the length in the second horizontal direction Y of the trimming mask layer 503 used in the step of forming the fourth signal line 206 of the lower functional layer so that the extension length of the third signal line 204 of the upper functional layer is smaller than the extension length of the fourth signal line 206 of the lower functional layer.

[0185] However, this is not limited to the above. When the first surface is an extraction surface, the length in the first horizontal direction X of the trimming mask layer 503 used in the step of forming the first signal line 203 of the upper functional layer is greater than the length in the first horizontal direction X of the trimming mask layer 503 used in the step of forming the second signal line 205 of the lower functional layer so that the extension length of the first signal line 203 of the upper functional layer is greater than the extension length of the second signal line 205 of the lower functional layer, and the length in the second horizontal direction Y of the trimming mask layer 503 used in the step of forming the third signal line 204 of the upper functional layer is greater than the length in the second horizontal direction Y of the trimming mask layer 503 used in the step of forming the fourth signal line 206 of the lower functional layer so that the extension length of the third signal line 204 of the upper functional layer is greater than the extension length of the fourth signal line 206 of the lower functional layer.

[0186] After one functional layer 20 is formed on the substrate 10, and before other functional layers 20 are stacked, an insulating separation layer 102 is first formed on the side of the lower functional layer (functional layer 20 closer to the substrate 10) away from the substrate 10, and then an upper functional layer (functional layer 20 away from the substrate 10) is formed to provide electrical insulation between the upper functional layer 20.

[0187] In this embodiment, after the step of forming at least one functional layer 20 on the substrate 10, the manufacturing method further includes: As shown in Figures 2 and 3, a first drawer structure S1, a third drawer structure S2, a second drawer structure S3, and a fourth drawer structure S4 are formed extending in the vertical direction Z and spaced apart from each other, and the first drawer structure S1, the third drawer structure S2, the second drawer structure S3, and the fourth drawer structure S4 correspond to each functional layer 20.

[0188] For example, with the second surface as the lead-out surface, the first lead-out structure S1 penetrates at least the fourth insulating film layer 208, the third insulating film layer 212, the interlayer insulating film layer 211, the second insulating film layer 210 and the first insulating film layer 209 of the corresponding functional layer 20 to contact the lead-out surface of the lead-out end of the first signal line 203 of the corresponding functional layer 20. The third lead-out structure S2 penetrates at least the fourth insulating film layer 208, the third insulating film layer 212, the interlayer insulating film layer 211 and the second insulating film layer 210 of the corresponding functional layer 20 to contact the lead-out surface of the lead-out end of the third signal line 204 of the corresponding functional layer 20. The second lead-out structure S3 penetrates at least the fourth insulating film layer 208 and the third insulating film layer 212 of the corresponding functional layer 20 to contact the lead-out surface of the lead-out end of the second signal line 205 of the corresponding functional layer 20. The fourth lead-out structure S 4 penetrates at least the fourth insulating film layer 208 of the corresponding functional layer 20 in order to contact the lead-out surface of the lead-out end of the fourth signal line 206 of the corresponding functional layer 20 .

[0189] For example, the materials of the first pull-out structure S1, the third pull-out structure S2, the second pull-out structure S3, and the fourth pull-out structure S4 may be one or more of conductive materials such as TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), ITO (indium tin oxide), A1 (aluminum), Cu (copper), Ru (ruthenium), Ag (silver), etc.

[0190] Although the embodiments of the present disclosure have been illustrated and described above, the above-described embodiments are illustrative and should not be construed as limiting the present disclosure. A person skilled in the art may change, modify, replace, and change the above-described embodiments within the scope of the present disclosure, and therefore, any changes or modifications made in accordance with the claims and specifications of the present disclosure should be included in the scope of the patent of the present disclosure.

Claims

1. A semiconductor device including a substrate and at least one functional layer, the functional layer includes a first signal line and a second signal line stacked along a direction perpendicular to the substrate, the second signal line being located on a side of the first signal line farther from the substrate and insulated from the first signal line via an insulating film layer, the first signal line and the second signal line both extending in a first horizontal direction, the first signal line and the second signal line each have a body extension and a pull-out end, and in the first signal line and the second signal line, the pull-out end is located at at least one end of the body extension in a first horizontal direction; an orthogonal projection of a body extension of the first signal line and a body extension of the second signal line on the substrate overlaps; The orthogonal projections of the lead-out end of the first signal line and the lead-out end of the second signal line on the substrate do not overlap. A semiconductor device comprising:

2. In the first signal line and the second signal line, the lead-out end has a first surface close to the substrate and a second surface remote from the substrate; In the first signal line and the second signal line, a direction in which the first surface faces the second surface or a direction in which the second surface faces the first surface is an extraction direction.

2. The semiconductor device according to claim 1,

3. When the direction in which the second surface faces the first surface is the drawing direction, the extension length of the first signal line located in the same functional layer is shorter than the extension length of the second signal line; or When the direction in which the first surface faces the second surface is the drawing direction, the extension length of the second signal line located in the same functional layer is shorter than the extension length of the first signal line.

3. The semiconductor device according to claim 2.

4. The functional layer further includes a third signal line extending in a second horizontal direction; the third signal line is stacked with the first signal line and the second signal line along the vertical direction, and is insulated from adjacent signal lines via an insulating film layer; the second horizontal direction intersects with the first horizontal direction; The third signal line has a body extension and a lead-out end, and the lead-out end of the third signal line is located at least at one end of the body extension of the third signal line in the second horizontal direction.

4. The semiconductor device according to claim 2, wherein the first insulating layer is a conductive layer.

5. the functional layer further includes a fourth signal line extending in a second horizontal direction; the fourth signal line is stacked along a direction perpendicular to the first signal line, the second signal line, and the third signal line, and is insulated from adjacent signal lines via an insulating film layer; the fourth signal line has a body extension and a pull-out end, the pull-out end of the fourth signal line being located at at least one end of the body extension of the fourth signal line in a second horizontal direction; an orthogonal projection of a body extension of the fourth signal line and a body extension of the third signal line on the substrate overlaps with each other; The orthogonal projections of the lead-out end of the fourth signal line and the lead-out end of the third signal line on the substrate do not overlap.

5. The semiconductor device according to claim 4.

6. In the functional layer, the third signal line is formed between the first signal line and the second signal line, In the functional layer, the fourth signal line is formed between the third signal line and the second signal line; or In the functional layer, the fourth signal line is formed on a side of the second signal line farther from the third signal line.

6. The semiconductor device according to claim 5,

7. In the third signal line and the fourth signal line, the lead-out end has a first surface close to the substrate and a second surface remote from the substrate; In the third signal line and the fourth signal line, a direction in which the first surface faces the second surface or a direction in which the second surface faces the first surface is an extraction direction.

7. The semiconductor device according to claim 6.

8. When the direction in which the second surface faces the first surface is the lead-out direction, the extension length of the third signal line located in the same functional layer is shorter than the extension length of the fourth signal line; or When the direction in which the first surface faces the second surface is the drawing direction, the extension length of the fourth signal line located in the same functional layer is shorter than the extension length of the third signal line.

8. The semiconductor device according to claim 7,

9. further comprising a first drawer structure, a second drawer structure, a third drawer structure, and a fourth drawer structure spaced apart from one another; the first to fourth lead-out structures all extend in a vertical direction and have different extension lengths; one end of the first lead-out structure contacts the lead-out end of the first signal line, and the other end extends along a lead-out direction and penetrates each insulating film layer; one end of the second lead-out structure contacts the lead-out end of the second signal line, and the other end extends along a lead-out direction and penetrates each insulating film layer; one end of the third lead-out structure contacts the lead-out end of the third signal line, and the other end extends along a lead-out direction and penetrates each insulating film layer; one end of the fourth lead-out structure contacts the lead-out end of the fourth signal line, and the other end extends along a lead-out direction and penetrates each insulating film layer; The first drawer structure, the second drawer structure, the third drawer structure, and the fourth drawer structure correspond to each of the functional layers.

8. The semiconductor device according to claim 7,

10. When the second surface faces the first surface in a withdrawal direction, the withdrawal structure contacts the first surface of the corresponding withdrawal end; or When the first surface faces the second surface in a withdrawal direction, the withdrawal structure contacts the second surface of the corresponding withdrawal end.

10. The semiconductor device according to claim 9.

11. The functional layer is provided with a plurality of layers, which are stacked in sequence along a direction perpendicular to the substrate, Among the two adjacent functional layers, When the direction in which the second surface faces the first surface is the drawing direction, an extension length of a first signal line in the functional layer farther from the substrate is greater than an extension length of a second signal line in the functional layer closer to the substrate, and a length of a third signal line in the functional layer farther from the substrate is greater than a length of a fourth signal line in the functional layer closer to the substrate; or When the direction in which the first surface faces the second surface is the drawing direction, the extension length of the first signal line in the functional layer farther from the substrate is shorter than the extension length of the second signal line in the functional layer closer to the substrate, and the length of the third signal line in the functional layer farther from the substrate is shorter than the length of the fourth signal line in the functional layer closer to the substrate.

8. The semiconductor device according to claim 7,

12. the functional layer further includes a first transistor and a second transistor sequentially stacked along a vertical direction, the first transistor and the second transistor each including a gate region, a first connection region, and a second connection region; A first connection region of the first transistor is connected to a body extension of the first signal line, a second connection region of the first transistor is connected to a body extension of the third signal line, a first connection region of the second transistor is connected to a gate region of the first transistor, a second connection region of the second transistor is connected to a body extension of the second signal line, and a gate region of the second transistor is connected to a body extension of the fourth signal line.

7. The semiconductor device according to claim 6.

13. In the functional layer, the fourth signal line is formed on a side of the second signal line farther from the third signal line, each of the first transistor and the second transistor includes a channel portion and a gate portion; the channel portion includes the first connection region, the second connection region, and a channel region located between the first connection region and the second connection region, the second connection region being located on a side of the channel region farther from the first connection region; The gate portion is insulated from the channel portion via a gate insulating portion, the gate portion and the channel portion are provided to face each other at least in a horizontal direction, and the gate portion includes the gate region.

13. The semiconductor device according to claim 12.

14. a first connection region of the first transistor is formed between its gate portion and a body extension of the first signal line, and both the channel region and the second connection region of the first transistor are disposed around its gate portion; A first connection region of the second transistor is formed between the gate portion thereof and the gate portion of the first transistor, and both the channel region and the second connection region of the second transistor are disposed around the gate portion thereof.

14. The semiconductor device according to claim 13.

15. a body extension of the third signal line disposed surrounding a second connection region of the first transistor; The body extension of the second signal line is disposed surrounding a second connection region of the second transistor.

15. The semiconductor device according to claim 14.

16. a conductive contact pad is formed between a first connection region of the second transistor and a gate portion of the first transistor; The orthogonal projections of the gate portions of the first transistor and the second transistor on the substrate both overlap with the orthogonal projections of the conductive contact pad on the substrate.

15. The semiconductor device according to claim 14.

17. A method for manufacturing a semiconductor device, comprising: Providing a substrate; forming at least one functional layer on the substrate; The step of forming the functional layer includes: forming a first signal line extending in a first horizontal direction on the substrate and a first insulating film layer covering the first signal line; forming a second signal line extending in a first horizontal direction on a side of the first insulating film layer away from the substrate; the first signal line and the second signal line each have a body extension and a pull-out end, and in the first signal line and the second signal line, the pull-out end is located at at least one end of the body extension in a first horizontal direction; an orthogonal projection of a body extension of the first signal line and a body extension of the second signal line on the substrate overlaps; The orthogonal projections of the lead-out end of the first signal line and the lead-out end of the second signal line on the substrate do not overlap.

4. A method for manufacturing a semiconductor device comprising the steps of:

18. The step of forming the functional layer further includes: a third signal line, a second insulating film layer, a fourth signal line, and a third insulating film layer are sequentially formed on a side of the first insulating film layer farther from the substrate before forming the second signal line, the third signal line and the fourth signal line both extending in a second horizontal direction, the third signal line and the fourth signal line being insulated from each other via the second insulating film layer, and the fourth signal line and the second signal line being insulated from each other via the third insulating film layer; or forming a third signal line and a second insulating film layer in sequence on a side of the first insulating film layer farther from the substrate before forming the second signal line, and forming a third insulating film layer and a fourth signal line in sequence after forming the second signal line, the third signal line and the fourth signal line both extending in a second horizontal direction, the third signal line and the second signal line being insulated from each other via the second insulating film layer, and the second signal line and the fourth signal line being insulated from each other via the third insulating film layer; the third signal line and the fourth signal line each have a body extension and a pull-out end, and in the third signal line and the fourth signal line, the pull-out end is located at least at one end of the body extension in a first horizontal direction; an orthogonal projection of a body extension of the third signal line and a body extension of the fourth signal line on the substrate overlaps with each other; The orthogonal projections of the lead-out end of the third signal line and the lead-out end of the fourth signal line on the substrate do not overlap. The method according to claim 17 .

19. In the first signal line, the second signal line, the third signal line, and the fourth signal line, the lead-out end has a first surface close to the substrate and a second surface far from the substrate, and a lead-out direction is a direction in which the first surface faces the second surface or a direction in which the second surface faces the first surface. The method of claim 18.

20. The steps of forming the first signal line, the second signal line, the third signal line, and the fourth signal line each include: sequentially forming a laminated conductive material film, a sacrificial material film and a photoresist mask pattern layer on a substrate, the photoresist mask pattern layer including a plurality of spaced apart photoresist mask strips; patterning the sacrificial material film with the photoresist mask pattern layer to form a sacrificial pattern layer, the sacrificial pattern layer including a plurality of spaced apart sacrificial mask strips, the sacrificial mask strips and the photoresist mask strips in one-to-one correspondence; removing the photoresist mask pattern layer and then forming an intermediate mask material film covering each of the sacrificial mask strips; forming a trimming mask layer on the intermediate mask material film on a side remote from the substrate, the sacrificial mask strip having at least one edge region in an extension direction thereof not covered by the trimming mask layer; removing a portion of the intermediate mask material film that is not covered by the trimming mask layer using the trimming mask layer; removing the trimming mask layer, and then patterning the intermediate mask material film to form an intermediate mask pattern layer, the intermediate mask pattern layer being composed of a plurality of intermediate mask strips separated from each other, the intermediate mask strips being formed on two opposing sides of each of the sacrificial mask strips, and the intermediate mask strips formed on the adjacent sides of two adjacent sacrificial mask strips being separated from each other; removing the sacrificial pattern layer and patterning the conductive material film with the intermediate mask pattern layer to form a conductive pattern layer including a plurality of spaced apart signal lines, the signal lines corresponding one-to-one to the intermediate mask strips; and removing the intermediate mask pattern layer. The method of claim 19 .

21. The step of forming the first signal line, the second signal line, the third signal line, and the fourth signal line further includes: forming a hard mask material film on the substrate after forming the conductive material film and before forming the sacrificial material film; the hardness of the hard mask material film is greater than the hardness of the sacrificial material film; patterning the conductive material film using the intermediate mask pattern layer to form a conductive pattern layer, patterning the hardmask material film with the intermediate mask pattern layer to form a hardmask pattern layer, the hardmask pattern layer including a plurality of spaced apart hardmask strips, the hardmask strips corresponding one-to-one to the intermediate mask strips; removing the intermediate mask strip and patterning the conductive material film with the hard mask pattern layer to form a conductive pattern layer. The method of claim 20.

22. After forming the conductive pattern layer, the manufacturing method further comprises: forming an isolation material layer covering each of the signal lines and filling between adjacent signal lines; removing a portion of the isolation material film that is higher than the signal lines to form an isolation pattern layer, a surface of the isolation pattern layer farther from the substrate being flush with a surface of the signal lines farther from the substrate, and the isolation pattern layer including at least an isolation portion that is filled between adjacent signal lines. The method of claim 20.

23. a length in a first horizontal direction of the trimming mask layer used in the step of forming the first signal line is a first length, a length in the first horizontal direction of the trimming mask layer used in the step of forming the second signal line is a second length, a length in a second horizontal direction of the trimming mask layer used in the step of forming the third signal line is a third length, and a length in the second horizontal direction of the trimming mask layer used in the step of forming the fourth signal line is a fourth length; In the same functional layer, When the first surface is the lead-out surface, the second length is greater than the first length such that the extension length of the second signal line is greater than the extension length of the first signal line, and the fourth length is greater than the third length such that the extension length of the fourth signal line is greater than the extension length of the third signal line, or When the second surface is the lead-out surface, the second length is smaller than the first length such that the extension length of the second signal line is smaller than the extension length of the first signal line, and the fourth length is smaller than the third length such that the extension length of the fourth signal line is smaller than the extension length of the third signal line. The method of claim 20.

24. The step of forming at least one functional layer on the substrate includes: forming a plurality of functional layers, which are stacked in sequence on the substrate; Of the two adjacent functional layers, the functional layer farther from the substrate is defined as an upper functional layer, and the functional layer closer to the substrate is defined as a lower functional layer; When the first surface is the lead-out surface, a length in a first horizontal direction of a trimming mask layer used in the step of forming a first signal line of the upper functional layer is greater than a length in a first horizontal direction of a trimming mask layer used in the step of forming a second signal line of the lower functional layer such that an extension length of a first signal line of the upper functional layer is greater than an extension length of a second signal line of the lower functional layer, and a length in a second horizontal direction of a trimming mask layer used in the step of forming a third signal line of the upper functional layer is greater than a length in a second horizontal direction of a trimming mask layer used in the step of forming a fourth signal line of the lower functional layer such that an extension length of a third signal line of the upper functional layer is greater than an extension length of a fourth signal line of the lower functional layer, or When the second surface is the lead-out surface, a length in a first horizontal direction of a trimming mask layer used in the step of forming a first signal line of the upper functional layer is smaller than a length in the first horizontal direction of a trimming mask layer used in the step of forming a second signal line of the lower functional layer such that an extension length of a first signal line of the upper functional layer is smaller than an extension length of a second signal line of the lower functional layer, and a length in a second horizontal direction of a trimming mask layer used in the step of forming a third signal line of the upper functional layer is smaller than a length in the second horizontal direction of a trimming mask layer used in the step of forming a fourth signal line of the lower functional layer such that an extension length of a third signal line of the upper functional layer is smaller than an extension length of a fourth signal line of the lower functional layer. The method of claim 20.

25. After the step of forming at least one functional layer on the substrate, the manufacturing method further comprises: forming a first drawer structure, a second drawer structure, a third drawer structure, and a fourth drawer structure extending vertically and spaced apart from one another; The first drawer structure, the second drawer structure, the third drawer structure, and the fourth drawer structure correspond to each of the functional layers; one end of the first lead-out structure contacts the lead-out end of the first signal line, and the other end extends along a lead-out direction and penetrates each insulating film layer; one end of the second lead-out structure contacts the lead-out end of the second signal line, and the other end extends along a lead-out direction and penetrates each insulating film layer; one end of the third lead-out structure contacts the lead-out end of the third signal line, and the other end extends along a lead-out direction and penetrates each insulating film layer; The fourth lead-out structure has one end that contacts the lead-out end of the fourth signal line and the other end that extends along the lead-out direction and penetrates each insulating film layer. The method of claim 19 .

26. the fourth signal line is formed on a side of the second signal line farther from the substrate, The step of forming the functional layer after forming the second insulating film layer and before forming the second signal line further includes: forming a first through hole penetrating the second insulating film layer, the body extension of the third signal line, and the first insulating film layer in this order, the first through hole exposing a surface of the body extension of the first signal line farther from the substrate; forming a first transistor in the first through hole, a first connection region of the first transistor being contacted to a body extension of the first signal line and a second connection region of the first transistor being contacted to a body extension of the third signal line; forming an interlayer insulating film layer, the interlayer insulating film layer covering the first transistor and the second insulating film layer and being located on a side of the second signal line closer to the substrate; The step of forming the functional layer after forming the third insulating film layer and before forming the fourth signal line further includes: forming a second through hole penetrating the third insulating film layer, the second signal line, and the interlayer insulating film layer in this order, and orthogonal projections of the second through hole and the first through hole on the substrate overlap; forming a second transistor in the second through hole, a first connection region of the second transistor connected to a gate region of the first transistor, a second connection region of the second transistor contacted to a body extension of the second signal line, and a body extension of the subsequently formed fourth signal line contacted to the gate region of the second transistor; After forming the fourth signal line, the step of forming the functional layer further includes: forming a fourth insulating film layer covering the fourth signal line. The method of claim 18.

27. The steps of forming the first through hole and the second through hole each include: forming a sacrificial material film on a side of a laminate structure including a lower insulating film layer, an intermediate signal line, and an upper insulating film layer, which are laminated in order on the substrate, away from the substrate; forming a photoresist mask pattern layer on a side of the sacrificial material film remote from the substrate, the photoresist mask pattern layer including a plurality of photolithographic via holes arrayed in a first horizontal direction and a second horizontal direction; patterning the sacrificial material film with the photoresist mask pattern layer to form a sacrificial pattern layer, the sacrificial pattern layer including a plurality of spaced apart sacrificial via holes in one-to-one correspondence with the photolithographic via holes, the sacrificial via holes exposing a surface of the upper insulating film layer away from the substrate; removing the photoresist mask pattern layer, and then forming an insulating material film, the insulating material film covering a surface of the sacrificial pattern layer farther from the substrate and filling the sacrificial via hole, and a portion of the insulating material film located in the sacrificial via hole has a blind groove structure; removing a portion of the insulating material film that is higher than the sacrificial pattern layer and a bottom wall of the blind groove structure, and leaving a side wall of the blind groove structure to form a target etching hole, the opening of the target etching hole being smaller than the opening of the sacrificial via hole; patterning the laminated structure using the target etching holes to form through-holes that penetrate the laminated structure; removing the sacrificial pattern layer and sidewalls of the blind groove structure of the laminate structure; In the step of forming the first through hole, the lower insulating film layer is the first insulating film layer, the intermediate signal line is the third signal line, and the upper insulating film layer is the second insulating film layer; In the step of forming the second through hole, the lower insulating film layer is the interlayer insulating film layer, the intermediate signal line is the second signal line or the fourth signal line, and the upper insulating film layer is the third insulating film layer.

27. The method of claim 26.

28. The steps of forming the first transistor and the second transistor each include: forming a channel film covering a surface of the laminate structure remote from the substrate and filling a through hole of the laminate structure; the channel film is patterned to form a groove-shaped channel portion located in the through hole, a surface of a sidewall of the groove in the channel portion farther from the substrate is lower than a surface of the laminated structure farther from the substrate, the channel portion includes the first connection region, the second connection region, and a channel region located between the first connection region and the second connection region, the second connection region being located on a side of the channel region farther from the first connection region; a gate insulating film and a gate film are formed in this order, the gate insulating film and the gate film cover a surface of the laminated structure farther from the substrate and a surface of a sidewall of the groove in the channel portion farther from the substrate, and are filled in the groove of the channel portion, a portion of the gate insulating film located in the through hole is a gate insulating portion, a portion of the gate insulating portion is located in the groove of the channel portion and covers a surface of the sidewall of the groove of the channel portion farther from the substrate, a portion of the gate insulating portion located in the groove of the channel portion is groove-shaped, a portion of the gate film located in the groove of the gate insulating portion is a gate portion, the gate portion includes the gate region, and the groove of the gate insulating portion is filled with the gate portion; removing portions of the gate insulating film and the gate film that are higher than the stacked structure so that surfaces of the stacked structure, the gate insulating portion, and the gate portion farther from the substrate are exposed and flush with each other, thereby forming a transistor located in the through hole; in the step of forming the first transistor, the laminated structure includes the first insulating film layer, the third signal line, and the second insulating film layer, which are laminated in order, and the through hole is a first through hole; In the step of forming the second transistor, the laminated structure includes the interlayer insulating film layer, the second signal line, and the third insulating film layer, which are laminated in this order, and the through hole is a second through hole.

27. The method of claim 26.

29. After forming the first transistor and before forming the interlayer insulating film layer, the manufacturing method further includes: forming a conductive contact pad, a side of the conductive contact pad proximal to the substrate being contacted to a gate region of the first transistor and a side of the conductive contact pad distal to the substrate being contacted to a first connection region of the second transistor.

27. The method of claim 26.

30. The step of forming the conductive contact pads comprises: forming a conductive material film and a sacrificial material film in sequence, the conductive material film and the sacrificial material film covering the second insulating film layer and the first transistor; forming a photoresist mask pattern layer on a side of the sacrificial material film away from the conductive material film, the photolithographic via holes being arranged in an array in a first horizontal direction and a second horizontal direction, the photolithographic via holes being in one-to-one correspondence with the first transistors; patterning the sacrificial material film with the photoresist mask pattern layer to form a sacrificial pattern layer, the sacrificial pattern layer including a plurality of spaced apart sacrificial via holes in one-to-one correspondence with the photolithographic via holes, the sacrificial via holes exposing a surface of the conductive material film remote from the substrate; removing the photoresist mask pattern, and then forming an intermediate mask material film covering a surface of the sacrificial pattern layer away from the substrate and filling the sacrificial via hole; removing a portion of the intermediate mask material film that is higher than the sacrificial pattern layer to form an intermediate mask pattern layer, the intermediate mask pattern layer including a plurality of spaced apart intermediate mask blocks, the intermediate mask blocks being disposed within the sacrificial via holes, and a surface of the intermediate mask blocks that is farther from the substrate being flush with a surface of the sacrificial pattern layer that is farther from the substrate; removing the sacrificial pattern layer to leave the intermediate mask block; patterning the conductive material film with the intermediate mask block to form a plurality of spaced apart conductive contact pads, the conductive contact pads having a one-to-one correspondence with the first transistors.

30. The method of claim 29.

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