METHOD FOR MANUFACTURING IMPROVED SiC SUBSTRATE AND SiC EPILAYER

Abstract

To provide a method, a SiC substrate, and a semiconductor device that improve the quality and performance of SiC epilayers by reducing the concentration of TM incorporated into the SiC epilayer during processing.SOLUTION: A method for manufacturing a silicon carbide (SiC) substrate includes at least the steps of a) providing a SiC substrate 1 suitable for growing a SiC epilayer, and b) implanting a group Va element into the SiC substrate by irradiating at least a portion of the SiC substrate with group Va ions, wherein the irradiation is performed at an energy between 100 keV and 200 keV and at an irradiation dose between 105 cm-2 and 1010 cm-2.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] Technical Field The present invention relates to methods for producing silicon carbide (SiC) substrates and SiC epilayers on such substrates, where the substrates are modified to capture transition metals (TM). Additionally, the present invention relates to the modified SiC substrates themselves, and to semiconductor devices comprising these SiC substrates. [Background technology]

[0002] Background technology With regard to the functionality and lifetime of state-of-the-art electronics, the quality of semiconductor devices is of paramount importance. Especially in the field of epitaxially grown SiC layers, impurities must be avoided, since such impurities can impair the structural and electronic properties of the semiconductor layer. Such defects are particularly detrimental in semiconductor layers processed for high voltage (HV) applications. One source of undesired impurities introduced into the process and layers is TM. TM are usually present in the crucible material and can be incorporated into the SiC boule or SiC substrate during bulk growth. After the creation of the substrate, such impurities can diffuse into the final epilayer during homoepitaxy of the epilayer. Transition metal impurities are known to form deep levels in the band gap of SiC that can impair the functionality of devices. As a function of the crucible material and the overall processing conditions, the TM concentration in the epilayer can range from 10 13 cm -3 From 10 14 cm -3 For HV applications, the epilayer doping is low (<10 14 cm -3 ), the presence of such TM in the epilayer poses serious problems for the fabrication of HV devices. Therefore, it is important to reduce the TM concentration in the epilayer or to pre-passivate the TM.

[0003] Patent documents also disclose suitable means for the treatment of impurities in SiC semiconductor devices. For example, US Pat. No. 9 508 802 discloses a process for manufacturing a semiconductor device. The process comprises forming a SiC epitaxial layer on a SiC substrate, implanting ions into the epitaxial layer, forming a gettering layer with a higher defect density than that of the SiC substrate, and subjecting the epitaxial layer to a heat treatment. The semiconductor device comprises a SiC substrate, a SiC epitaxial layer formed on the SiC substrate, and a gettering layer with a higher defect density than that of the SiC substrate. The method is based on the implantation of He into the epilayer. After high temperature treatment, the He implanted area serves as a gettering layer for the diffusing TM. A drawback of this method is that the implantation of the epilayer creates more electrically active defects, which affect the electronic properties of the finished HV device in terms of leakage current, minority carrier lifetime, and on-resistance. Summary of the Invention [Problem to be solved by the invention]

[0004] Summary of the Invention It is therefore an object of the present invention to provide a solution for improving the quality and performance of SiC epilayers, in particular by reducing the concentration of TMs incorporated into the SiC epilayer during processing, and in particular to avoid or mitigate the disadvantages of known solutions. [Means for solving the problem]

[0005] The object of the invention is solved by the features of the independent claims. Preferred embodiments are detailed in the dependent claims.

[0006] The object is therefore to provide a method for producing a silicon carbide (SiC) substrate, comprising: a) providing a SiC substrate suitable for growing a SiC epilayer; b) implanting a group Va element into the SiC substrate by irradiating at least a portion of the SiC substrate with group Va ions; At least The irradiation is performed with an energy of 100 keV or more and 200 keV or less, and 10 5 cm -2 Over 10 10 cm -2 This is addressed by a method which is carried out at the following irradiation doses:

[0007] In other words, in particular, the invention proposes a method for producing silicon carbide (SiC) substrates. SiC substrates are generally used as a basis for growing structurally defined SiC epilayers. The materials and structures are used as semiconductors for high voltage and / or high temperature applications. The substrates can be in the form of boules or wafers. If boules are used, wafers can be cut from the boules in a later step to produce wafers. If the substrates are in the form of wafers, the dimensions of the wafers can be adjusted according to special needs. Standard wafer thicknesses and diameters can be used in the process of the invention. Substrate thicknesses can be in the range of, for example, 10 to 400 μm. Suitable substrate diameters can be in the range of 1 cm to 10 cm. Typical boule dimensions are in the range of 10 to 20 cm.

[0008] The method comprises a step a). In this step, a SiC substrate suitable for the growth of a SiC epilayer is provided. This means that the substrate is suitable to provide the necessary features for depositing a structurally coherent and defined SiC epilayer in a later step. The defined SiC epilayer may be, for example, a 2H-, 4H- or 6H-SiC epilayer. 4H- and 6H-SiC epilayers are preferred. The substrate may be, for example, a seed substrate, which includes a special seed layer on top of the substrate. It is also possible for the seed layer to be deposited after the formation of the substrate of the invention. The substrate is particularly suitable for growth if a suitable epilayer can be formed by using high temperature chemical vapor deposition techniques or any other technique that achieves a structurally well-defined epilayer.

[0009] Furthermore, the method includes a step b) of implanting a group Va element into the SiC substrate by irradiating at least a portion of the SiC substrate with group Va ions. The SiC substrate is modified by incorporating a group Va element into the substrate. Group Va elements are elements of the fifth main group of the periodic system of elements, namely N, P, As, Sb, Bi. The elements N, P, and As are preferred. The implantation or incorporation can be performed, for example, by accelerating the element in the form of particles and bombarding the accelerated particles with the substrate. The element can be kinetically incorporated into the substrate, for example, by irradiation. A suitable implantation of a group Va element can be based on the incorporation of the respective ions, where Va ions are accelerated by an electric accelerator and directed towards the substrate surface.

[0010] The irradiation in step b) has an energy of 100 keV to 200 keV and 10 5 cm -2 Over 10 10 cm -2The following irradiation doses are performed: 1) Va implantation at 1000 nm and 1000 nm. The overall irradiation conditions in the form of energy and dose are selected to achieve a certain Va implantation level in the substrate. The selection of the irradiation parameters makes it possible in particular to generate carbon vacancies (VC) in the substrate without changing the electrical properties of the substrate. It is therefore not the intention of the irradiation or implantation process to specifically affect the resistivity or conductivity of the substrate. Such changes are not achieved at the specified dose and energy levels. Higher doses and / or higher energy levels may result in undesired changes in the electrical substrate properties, in particular the resistivity of the substrate may be affected.

[0011] The present invention and the embodiments described herein provide an improved SiC substrate, which can capture TM metals at VC sites by forming transition metal-VC (TM-VC) complexes. Transition metals are known to act as acceptors, especially in n-type 4H-SiC. For this reason, it is proposed to use carbon vacancies that can effectively bond with transition metals. VC-TM complexes are easily formed and energetically stable. By this method, a TM gettering / passivation layer is formed in or by the substrate prior to epilayer growth. In this way, the final device is not subject to further ion beam processing. Although the implantation results in the formation of VC, the resistivity of the substrate is not affected due to the presence of the implanted Va group elements. The proposed implantation characteristics are suitable to achieve an appropriate VC concentration in the substrate. The VC concentration achievable by these ranges does not affect the resistivity of the substrate. Also, no high temperature post-implantation processing is required, since the dose is below the amorphization level of the crystal.

[0012] TM gettering is performed in the substrate without compromising the crystalline structure of the deposited epilayer. This leaves the epilayer structurally intact, resulting in better physical properties. The TM-VC complex is energetically extremely stable and effectively prevents the diffusion of TM from the substrate into the epilayer during homoepitaxial growth.

[0013] Such a solution is preferable compared to the use of an additional buffer layer, since the latter has to be grown in a separate step, whereas the trapping proposed in the present invention is performed by implantation. In contrast to a highly doped buffer layer, the doping of this implanted layer is much lower, leaving the electrical properties of the substrate unchanged. A high doping of the buffer layer also leads to a faster diffusion of TMs, since the Fermi level of the buffer layer is close to the conduction band. This means that the formation energy of TMs in such a buffer layer is lower, which also affects their migration and diffusion energies.

[0014] As a result, the proposed solution includes several advantages compared to buffer layers known in the art.

[0015] The object is to provide a method for producing a silicon carbide (SiC) epilayer on a SiC substrate, comprising the steps of: a) providing a SiC substrate suitable for growing a SiC epilayer; b) implanting a group Va element into the SiC substrate by irradiating at least a portion of the SiC substrate with group Va ions, the irradiation having an energy of 100 keV to 200 keV and a fluence of 10 5 cm -2 Over 10 10 cm -2 performed at a dose of radiation of c) epitaxially growing a SiC epilayer on the SiC substrate obtained in method step b), the growth being carried out at a temperature between 1200° C. and 1500° C. The problem is further solved by a method comprising at least

[0016] This method can be considered as a method for producing a final product, whereas the previous method can be considered as a method for producing an intermediate product. The difference can be seen in the last method step c), where the epitaxial layer is produced.

[0017] Surprisingly, it has been found that when the epitaxial layer is grown under the above-defined conditions, there is very little diffusion of TM from the substrate, resulting in an improved epitaxial layer. In particular, the structural and electrical properties of the epitaxial layer are better than standard, resulting in a long-lived SiC epitaxial layer. For further advantages of the method for producing a SiC epitaxial layer, see in particular the method for producing a SiC substrate. A high temperature in method step b) can be disadvantageous, since in this case TM can diffuse into the epilayer. A low temperature can be disadvantageous, since it prevents the growth of the epilayer.

[0018] The object is to provide a method for producing a carbon vacancy (VC) and a transition metal VC complex, the sum of the concentrations of the VC and the transition metal VC complex being 10 12 cm -3 Over 10 16 cm -3The problem is further solved by the SiC substrate, which is: The sum of VC and TM-VC complexes in the substrate can be assessed by electron spin resonance (ESR) experiments. Both species have a clear and unique ESR signature, allowing the measurement to be quantitative. The concentrations of VC and transition metal VC complexes can be assessed separately, and adding up both concentrations gives the sum. The substrate can be in the form of a boule of regular or irregular shape, or the substrate can be in the form of a flat disk, plate, or wafer. Plate-like means that the shape is flat and / or extends at least substantially towards two of the three dimensions. The plate may be flat in one direction but substantially long in two directions, all three directions being perpendicular to each other. In particular, the width and length of the plate are each at least 2, 5, 10, 50, or 100 times greater than the thickness in order to be considered plate-like. The advantages of the SiC substrate according to the invention are described above in connection with the method for producing the SiC substrate of the invention.

[0019] Moreover, the object is further solved by a semiconductor device comprising a SiC substrate and an epitaxial layer on the SiC substrate, the SiC substrate being a SiC substrate according to the invention. In particular, the semiconductor device can benefit from the improved SiC substrate. The device can have better electronic properties and exhibit better lifetime. Such advantages are achieved by controlling and reducing the TM content in the epilayer of the device. The semiconductor device can be, for example, a thyristor, a diode, a gate turn-off thyristor, a power metal-insulator-semiconductor field effect transistor, a power metal-oxide-semiconductor field effect transistor, a junction field effect transistor, a bipolar junction transistor, an insulated gate bipolar transistor, or an integral gate commutated thyristor. The advantages of the semiconductor device according to the invention have been described above in relation to the method for producing a SiC substrate according to the invention and the SiC substrate.

[0020] In a first preferred embodiment of the method for manufacturing a SiC substrate, in an additional method step b'), the SiC substrate obtained in method step b) is heat treated at a temperature between 1000° C. and 1700° C. for a time period between 5 and 24 h. The heat treatment of the substrate under the above mentioned conditions makes it possible to equilibrate the substrate and to promote the formation of TM-VC complexes in the substrate if TMs are already present therein. This step makes it possible to reduce the number of diffusible TMs in the substrate. Preferably, this heat treatment step may be carried out at a temperature between 1100° C. and 1600° C. for a time period between 8 and 20 h, and even more preferably at a temperature between 1200° C. and 1400° C. for a time period between 10 and 18 h. By this heat treatment, a preferably homogeneous distribution of Va ions and VC is generated throughout the substrate. A concentration difference of 10 mol% / cm 3 If less than 1000 nm, the distribution is uniform across the substrate. The concentration can be quantitatively determined as a function of position on the substrate by EPR.

[0021] In a second preferred embodiment of the method for producing a SiC substrate, in step b) carbon vacancies (VC) are generated in the substrate, and the concentration of VC in the substrate is 10 13 cm -3 Over 10 17 cm -3 This VC concentration has been found to be useful for capturing sufficient TM in the substrate and largely avoiding the possibility of TM diffusion into the epilayer during epitaxial growth. Lower concentrations can be disadvantageous since the formation of complexes with TM is not fully achieved. Higher concentrations can be disadvantageous since they have a large effect on the electrical properties of the substrate. Furthermore, the VC concentration in the substrate should be less than 10 14 cm -3 Over 10 16 cm -3 It may be the following:

[0022] In a third preferred embodiment of the method for producing a SiC substrate, the Va group ions are selected from the group consisting of nitrogen ions, phosphorus ions, or mixtures thereof. The implantation of N and P ions into the substrate has been found to be useful for reliably producing the required VC concentration in various substrates without changing the electronic properties of the substrate.

[0023] In a fourth preferred embodiment of the method for producing a SiC substrate, the resistivity of the SiC substrate after step b) changes by less than 10% compared to the resistivity of the SiC substrate in step a). One of the main advantages of the method is that the resistivity of the substrate is essentially unchanged by the implantation of Va ions and the generation of VC. In a preferred embodiment, the resistivity of the SiC substrate after step b) changes by less than 8% compared to the resistivity of the SiC substrate in step a), and even more preferably, the resistivity of the SiC substrate after step b) changes by less than 5% compared to the resistivity of the SiC substrate in step a). The resistivity of the substrate is evaluated at 20° C. according to methods known to those skilled in the art, such as, for example, the four-probe method with removable graphite contacts.

[0024] In a fifth preferred embodiment of the method for producing a SiC substrate, the implantation density of Va group ions in the SiC substrate is 10 10 cm -3 Over 10 16 cm -3 Such implantation of group Va ions into SiC substrates has been shown to be useful for producing optimal VC concentrations in the substrate. The overall electrical and structural properties of the substrate remain largely unchanged. Moreover, the density of group Va ions in the SiC substrate is 10 11 cm -3 Over 10 15 cm -3 More preferably, the density of Va group ions in the SiC substrate is 10 12 cm -3 Over 10 14 cm -3It may be: It is further preferred that the implantation is uniform throughout the substrate.

[0025] In a sixth preferred embodiment of the method for producing a SiC substrate, the SiC substrate in method step a) and method step b) has n-type conductivity. Particularly in the case of a substrate with n-type conductivity, the method according to the invention can provide a very effective VC generation and TM complex formation. Furthermore, the formed TM-VC complex is very stable and epitaxial layers can be grown on TM-free substrates.

[0026] In a seventh preferred embodiment of the method for producing a SiC substrate, step b) is carried out at a temperature between 20° C. and 800° C. This temperature range for the Va implantation and VC generation steps can result in a reasonably uniform VC distribution in the substrate.

[0027] In a first preferred embodiment of the method for producing a SiC epilayer, after method step b) and before method step c), the SiC substrate is heat treated at a temperature between 1000° C. and 1900° C. for a time between 0.5 h and 24 h. It has been found that for a safe and reproducible formation of TM complexes in the substrate prior to epitaxial growth, a heat treatment of the substrate under the above given conditions is useful. The structure of the substrate is not changed, but TMs are trapped, probably based on a diffusion process. Non-diffusive complexes are produced. These complexes are fairly stable and do not interact with the epilayer growing in step c). As a result, a TM-free or reduced TM epilayer is achieved, which shows better electronic properties and a longer lifetime.

[0028] In a second preferred embodiment of the method for producing a SiC epilayer, the thickness of the SiC epilayer is 50 μm to 250 μm. The method for producing a SiC epilayer is particularly suitable for producing epilayers of the above thickness. The epilayer is particularly suitable for high voltage applications, and based on the fact that the TM is reliably captured in the substrate, the epilayer exhibits outstanding life and uniform electrical properties. Furthermore, the thickness of the SiC epilayer may be 60 μm to 200 μm, and more preferably, the thickness of the SiC epilayer may be 80 μm to 50 μm.

[0029] In a first preferred embodiment of the semiconductor device, the epitaxial layer is an n-type 4H-SiC epitaxial layer. In particular, an n-type 4H SiC epitaxial layer can benefit from a reduced TM concentration in the epitaxial layer.

[0030] In a second preferred embodiment of the semiconductor device, the thickness of the epitaxial layer is 50 μm to 200 μm. The advantages of a semiconductor device comprising an epitaxial layer in such a thickness range have already been described in the context of the epilayer.

[0031] BRIEF DESCRIPTION OF THE DRAWINGS These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter. [Brief description of the drawings]

[0032] [Figure 1] 1 shows a preferred embodiment of a method according to the invention for producing a silicon carbide (SiC) substrate. [Diagram 2] 1 shows a preferred embodiment of a method according to the invention for producing a silicon carbide epilayer on a SiC substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] Description of the Preferred Embodiments The description includes aspects related to procedures or methods when describing structural features of the claimed invention; in such a way, the structural features can be fully understood. It is emphasized to the reader that such structural features can be taken out of the described context without hesitation or intermediate generalization issues to form aspects of the present invention. It is also emphasized to the reader that any structural feature described below can be understood as an individual aspect of the present invention for distinction from known solutions, regardless of the possibility of being taken out of the context.

[0034] In FIG. 1, a process for the manufacture of a SiC substrate 1 is shown. The provided substrate 1 may be in the form of a boule, a wafer or a plate. In this figure, a plate-like shape is shown. The SiC substrate 1 comprises a transition metal 2. TM2 is distributed in the SiC substrate 1. In the next process step, i.e. method step b), the SiC substrate 1 is irradiated with a group Va element. The group Va element may be in the form of particles or ions. Preferably, the group Va element is provided in the form of ions, which are accelerated and kinetically implanted in the SiC substrate 1. The implantation of Va ions in the SiC substrate 1 forms carbon vacancies VC3. The SiC substrate 1 can be heat treated at a higher temperature in a further method step. The heat treatment leads to the diffusion of VC3 and TM2, forming positionally stable TM-VC complexes 4. The TM-VC complexes 4 remain trapped at the formation site and can no longer diffuse throughout the SiC substrate 1. By using this method step, a SiC substrate 1 is produced that does not contain much mobile TM2. The SiC substrate 1 can be stored for further processing. In addition, it is possible to immediately use the SiC substrate 1 for epitaxially growing an epitaxial layer 5 on the substrate 1. The epitaxial growth of the epitaxial layer 5 can be performed according to methods known to those skilled in the art. By including this separate method step, a SiC epilayer 5 is produced on the SiC substrate 1, which does not contain TM2. In general, the overall concentration of diffusible TM2 is significantly lower. This method can be used to produce an epilayer 5 for high voltage applications. The epilayer 5 can be, for example, a 4-H SiC epilayer.

[0035] In FIG. 2 a process for the manufacture of a SiC epilayer 5 on a SiC substrate 1 is shown. The provided substrate 1 may be in the form of a boule or a wafer or a plate. In this figure a plate-like shape is used. The SiC substrate 1 comprises a transition metal 2. TM2 is distributed in the SiC substrate 1. In the next process step, i.e. method step b), the SiC substrate 1 is irradiated with a Va element. The Va element may be in the form of particles or ions. Preferably, the Va element is provided in the form of ions, which are accelerated and kinetically implanted in the SiC substrate 1. The implantation of Va ions in the SiC substrate 1 results in the formation of carbon vacancies 3. Such a SiC substrate 1 can be used in the next method step of growing an epilayer 5 on the surface of the SiC substrate 1. In the course of the growth of the epilayer 5, TM2 diffuses through the SiC substrate 1 and is captured in VC3. In the figure it is shown that there is still one diffusive TM2 that is not bonded to VC3. The remaining TM2 is transformed into thermodynamically and spatially stable TM-VC complexes 4. The TM-VC complexes 4 remain in the SiC substrate 1 and do not diffuse into the epilayer 5 during epitaxial growth. This reduces the amount of TM2 incorporated in the epilayer 5 and improves the electronic and structural properties of the epilayer 5. The epitaxial growth of the epilayer 5 can be performed according to methods known to those skilled in the art. This method can be used to produce epilayers 5 for high voltage applications. The epilayer 5 can be, for example, a 4-H SiC epilayer.

[0036] A possible method sequence may include providing a SiC substrate 1, the SiC substrate 1 having a thickness of 350 μm. The SiC substrate 1 may be 10 18 cm -3 The N-doped GaN is approximately 10 14 cm -3 The implantation of Va group elements is carried out in process step b). The implantation is carried out by application of N ions at RT. 7 cm -2A dose of 100 keV was used, and the implant energy was 100 keV. Using these parameters, a dose of approximately 3 × 10 14 cm -3 of VC was generated, and the concentration of injected N was about 10 12 cm -3 An additional heat treatment step is performed at 1200° C. for 10 hours. In this step, the Vc-TM complex 4 is formed. In the next step, a 100 μm 4H—SiC epilayer 5 is grown (N is about 10 14 cm -3 ). No TM2 is found in the epitaxially grown layer 5 and the resistivity of the epitaxial layer 5 is intact. Devices can now be fabricated. The anode is formed by implantation of Al followed by a 30 minute heat treatment at 1700°C. A mesa is formed by RIE and ohmic metal is deposited to produce a 10 kV pin diode. [Explanation of symbols]

[0037] List of reference numbers 1. SiC substrate 2 Transition metals (TM) 3 Carbon Vacancy (VC) 4 Transition metal-carbon vacancy (TM-VC) composite 5 Epilayer

Claims

1. A method for manufacturing a silicon carbide (SiC) substrate (1), comprising the steps of: a) providing a SiC substrate (1) suitable for growing a SiC epilayer (5); b) implanting group Va elements into the SiC substrate (1) by irradiating at least a portion of the SiC substrate (1) with group Va ions; At least The irradiation has an energy of 100 keV to 200 keV and a ５ cm －２ More than 10 １０ cm －２ The method is carried out at the following doses:

2. 10. The method according to the preceding claim, wherein in an additional method step b') the SiC substrate (1) obtained in method step b) is heat treated at a temperature between 1000 ° C and 1700 ° C for a time between 5 h and 24 h.

3. In step b), carbon vacancies (VC) (3) are generated in the substrate (1), and the concentration of VC (3) in the substrate (1) is 10 １３ cm －３ More than 10 １７ cm －３ 2. A method according to any one of the preceding claims, wherein:

4. 2. The method of any one of the preceding claims, wherein the Group Va ions are selected from the group consisting of nitrogen ions, phosphorus ions, or mixtures thereof.

5. 10. The method according to any one of the preceding claims, wherein the resistivity of the SiC substrate (1) after step b) changes by less than 10% compared to the resistivity of the SiC substrate (1) in step a).

6. The implantation density of the Va group ions in the SiC substrate (1) is 10 １０ cm －３ More than 10 １６ cm －３ 2. A method according to any one of the preceding claims, wherein:

7. 10. The method according to any one of the preceding claims, wherein the SiC substrate (1) in method steps a) and b) has n-type conductivity.

8. 10. The method of any one of the preceding claims, wherein step b) is carried out at a temperature of ≧20° C. and ≦800° C.

9. A method for producing a silicon carbide (SiC) epilayer (5) on a SiC substrate (1), comprising the steps of: a) providing a SiC substrate (1) suitable for growing a SiC epilayer (5); b) implanting a group Va element into the SiC substrate (1) by irradiating at least a portion of the SiC substrate (1) with group Va ions, the irradiation having an energy of 100 keV to 200 keV and a molecular weight of 10 ５ cm －２ More than 10 １０ cm －２ performed at a dose of radiation of c) epitaxial growth of a SiC epilayer (5) on the SiC substrate (1) obtained in method step b), said growth being carried out at a temperature between 1200° C. and 1500° C. The method includes at least the following steps.

10. 10. The method according to claim 9, wherein after method step b) and before method step c), the SiC substrate (1) is heat treated at a temperature between 1000° C. and 1900° C. for a time period between 0.5 h and 24 h.

11. 11. The method according to claim 9 or 10, wherein the thickness of the SiC epilayer (5) is 50 μm to 250 μm.

12. Carbon vacancy (V C ) and transition metal V C The V C (3) and the transition metal V C The total concentration of the complex (4) is 10 １２ cm －３ More than 10 １６ cm －３ Below is the SiC substrate (1).

13. 13. A semiconductor device comprising a SiC substrate (1) and an epitaxial layer (5) on the SiC substrate (1), the SiC substrate (1) being the SiC substrate (1) according to claim 12.

14. The semiconductor device of claim 13, wherein the epitaxial layer (5) is an n-type 4H-SiC epitaxial layer.

15. 15. The semiconductor device according to claim 13 or 14, wherein the epitaxial layer (5) has a thickness of 50 μm to 200 μm.

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