Manufacturing method for semiconductor device

Abstract

To provide a semiconductor device whose operation speed is high.SOLUTION: In a semiconductor device, a transistor 200 includes an insulator 222, an oxide semiconductor 230 thereon, conductors 242a and 242b on the oxide semiconductor and the insulator 222, an insulator 250 on the oxide semiconductor, and a conductor 260 thereon. On the conductors 242a and 242b, an insulator 275 is provided and an insulator 280 is provided thereon. The insulator 250 and the conductor 260 are disposed inside an opening provided in an insulator 280 and an insulator 275, the opening reaches the oxide semiconductor, and the insulator 250 is in contact with the oxide semiconductor in the opening. The oxide semiconductor has a shape with a high aspect ratio. An upper part thereof, and side surfaces on A1 side and A2 side function as channel formation regions. The channel width of the transistor 200 increases and the on-state current, mutual conductance, frequency characteristic, and the like can be made excellent.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, a memory device, and an electronic device each including an oxide semiconductor layer. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input / output device (e.g., a touch panel), a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) that are chipped by processing a semiconductor wafer and on which electrodes that serve as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as components in a variety of electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface is attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.

[0007] It is also known that a transistor using an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a CPU with low power consumption that utilizes the property of a transistor using an oxide semiconductor that the leakage current is small. Furthermore, for example, Patent Document 2 discloses a memory device that can retain stored data for a long period of time by utilizing the property of a transistor using an oxide semiconductor that the leakage current is small. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A Summary of the Invention [Problem to be solved by the invention]

[0009] An object of one embodiment of the present invention is to provide a semiconductor device with high operating speed. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device in which variation in electrical characteristics of transistors is small. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device. Another object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another object of one embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device.

[0010] Another object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a memory device with a large storage capacity. Another object of one embodiment of the present invention is to provide a memory device with high operation speed. Another object of one embodiment of the present invention is to provide a memory device with low power consumption. Another object of one embodiment of the present invention is to provide a novel memory device.

[0011] Note that the description of these problems does not preclude the existence of other problems. One embodiment of the present invention does not necessarily have to solve all of these problems. Problems other than these can be extracted from the description of the specification, drawings, and claims. [Means for solving the problem]

[0012] One embodiment of the present invention includes forming a columnar second insulator over a first insulator, forming a first oxide semiconductor covering a top surface of the first insulator, a side surface of the second insulator, and a top surface of the second insulator, removing a region of the first oxide semiconductor covering the top surface of the second insulator and a region covering the top surface of the first insulator by anisotropic etching to form a second oxide semiconductor, removing the second insulator, forming a first conductor covering the second oxide semiconductor and the first insulator, forming a third insulator over the first conductor, providing a first opening in the third insulator that reaches the first conductor, providing a second opening in the third insulator that reaches the first conductor, and forming a third insulator over the first conductor. a fourth insulator covering the second oxide semiconductor, the second conductor, the third conductor, and the third insulator is formed; the fourth conductor is formed on the fourth insulator; a fifth conductor located in the first opening and a sixth conductor located in the second opening are formed by removing part of the fourth conductor; and a fifth insulator located in the first opening and a sixth insulator located in the second opening are formed by removing part of the fourth insulator, and the fifth insulator located in the first opening and the sixth insulator located in the second opening are formed by removing part of the fourth insulator, wherein the third conductor is provided to overlap with the first opening.

[0013] In the above embodiment, the first opening is preferably provided so as to overlap the second oxide semiconductor.

[0014] In the above embodiment, it is preferable that the first opening and the second opening do not overlap.

[0015] In the above aspect, it is preferable that the fifth conductor and the sixth conductor are formed by a first process that removes a region of the fourth conductor that covers an upper surface of the third insulator, and the fifth insulator and the sixth insulator are formed by a second process that removes a region of the fourth insulator that covers an upper surface of the third insulator, and the first process and the second process are planarization processes.

[0016] In the above embodiment, the planarization process is preferably performed by using a chemical mechanical polishing method.

[0017] Alternatively, one embodiment of the present invention includes forming a columnar second insulator over a first insulator, forming a first oxide semiconductor to cover a top surface of the first insulator, side surfaces of the second insulator, and a top surface of the second insulator, and removing a region of the first oxide semiconductor that covers the top surface of the second insulator and a region that covers the top surface of the first insulator by anisotropic etching to form a second oxide semiconductor, removing the second insulator, forming a first conductor and a second conductor over the first conductor as a conductor having a stacked structure to cover the second oxide semiconductor and the first insulator, forming a third insulator on the second conductor, providing a first opening that reaches the second conductor and a second opening that reaches the second conductor in the third insulator, and removing regions in the second conductor that overlap with the first opening and the second opening, respectively, to form a third conductor and a fourth conductor, and the first opening and the second opening are formed. a first mask is formed over the third insulator and the first conductor; a portion of a region of the first conductor that overlaps with the second opening is removed using the first mask to expose the second oxide semiconductor; a fifth conductor overlapping with the third conductor and a sixth conductor overlapping with the fourth conductor are formed; a fourth insulator is formed covering the second oxide semiconductor, the fifth conductor, the sixth conductor, and the third insulator; a seventh conductor is formed on the fourth insulator; an eighth conductor located in the first opening and a ninth conductor located in the second opening are formed by removing part of the seventh conductor; and a fifth insulator located in the first opening and a sixth insulator located in the second opening are formed by removing part of the fourth insulator,

[0018] In the above embodiment, the first opening is preferably provided so as to overlap the second oxide semiconductor.

[0019] In the above embodiment, it is preferable that the first conductor is tantalum nitride and the second conductor is tungsten.

[0020] In the above embodiment, the first conductor is preferably formed by using a sputtering method.

[0021] In the above aspect, it is preferable that the fifth conductor and the sixth conductor each have a region where an end protrudes to the inside of the second opening.

[0022] In the above embodiment, it is preferable that the end of the fifth conductor protruding inwardly into the second opening extends further inward than the end of the third conductor, and that the end of the sixth conductor protruding inwardly into the second opening extends further inward than the end of the fourth conductor.

[0023] In the above aspect, it is preferable that the first oxide semiconductor is formed by a step of forming a first semiconductor layer, a step of forming a second semiconductor layer on the first semiconductor layer, and a step of forming a third semiconductor layer on the second semiconductor layer, and that the first semiconductor layer and the third semiconductor layer are formed by an ALD method using a precursor containing indium and an oxidizing agent, and the second semiconductor layer is formed by a sputtering method using a sputtering target containing zinc. Effect of the Invention

[0024] According to one embodiment of the present invention, a semiconductor device with high operating speed can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with less variation in electrical characteristics of transistors can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to one embodiment of the present invention, a novel semiconductor device can be provided. According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided.

[0025] According to one embodiment of the present invention, a memory device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a memory device with a large storage capacity can be provided. According to one embodiment of the present invention, a memory device with a high operating speed can be provided. According to one embodiment of the present invention, a memory device with low power consumption can be provided. According to one embodiment of the present invention, a novel memory device can be provided.

[0026] Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all of these effects. Effects other than these can be extracted from the description in the specification, drawings, and claims. [Brief description of the drawings]

[0027] [Figure 1] Fig. 1A is a plan view showing an example of a semiconductor device, and Figs. 1B to 1D are cross-sectional views showing an example of the semiconductor device. [Diagram 2] 2A and 2B are cross-sectional views showing an example of a semiconductor device. [Diagram 3] 3A and 3B are cross-sectional views showing an example of a semiconductor device. [Figure 4]4(A) and 4(B) are cross-sectional views showing an example of a portion of a semiconductor device. [Diagram 5] 5(A) and 5(B) are plan views showing an example of a part of a semiconductor device. [Figure 6] Fig. 6A is a plan view showing an example of a semiconductor device, and Figs. 6B to 6D are cross-sectional views showing an example of the semiconductor device. [Figure 7] FIG. 7 is a cross-sectional view showing an example of a semiconductor device. [Figure 8] Fig. 8A is a plan view showing an example of a semiconductor device, and Figs. 8B to 8D are cross-sectional views showing an example of the semiconductor device. [Figure 9] Fig. 9A is a plan view showing an example of a semiconductor device, and Figs. 9B to 9D are cross-sectional views showing an example of the semiconductor device. [Figure 10] 10(A) and 10(B) are cross-sectional views showing an example of a semiconductor device. [Figure 11] Fig. 11A is a plan view showing an example of a semiconductor device, and Figs. 11B to 11D are cross-sectional views showing an example of the semiconductor device. [Figure 12] 12A to 12D are cross-sectional views illustrating an example of a method for manufacturing an oxide semiconductor. [Figure 13] 13A to 13D are cross-sectional views illustrating examples of oxide semiconductors. [Figure 14] Fig. 14A is a plan view showing an example of a semiconductor device, and Figs. 14B to 14D are cross-sectional views showing an example of the semiconductor device. [Figure 15] 15A to 15D are cross-sectional views showing an example of a semiconductor device. [Figure 16] Fig. 16A is a plan view showing an example of a semiconductor device, and Figs. 16B to 16D are cross-sectional views showing an example of the semiconductor device. [Figure 17] 17(A) and 17(B) are cross-sectional views showing an example of a semiconductor device. [Figure 18]Fig. 18A is a plan view showing an example of a semiconductor device, and Figs. 18B to 18D are cross-sectional views showing an example of the semiconductor device. [Figure 19] 19(A) and 19(B) are cross-sectional views showing an example of a semiconductor device. [Figure 20] 20(A) and 20(B) are perspective views showing an example of a semiconductor device. [Figure 21] 21(A) and 21(B) are perspective views showing an example of a semiconductor device. [Figure 22] 22A to 22E are cross-sectional views showing an example of a semiconductor device. [Figure 23] 23A to 23C are plan views showing an example of a semiconductor device. [Figure 24] 24A to 24C are cross-sectional views showing an example of a semiconductor device. [Diagram 25] FIG. 25 is a cross-sectional view showing an example of a semiconductor device. [Figure 26] FIG. 26 is a cross-sectional view showing an example of a semiconductor device. [Figure 27] Fig. 27A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 27B to Fig. 27D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 28] Fig. 28A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 28B to Fig. 28D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 29] Fig. 29A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 29B to Fig. 29D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 30] Fig. 30A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 30B to Fig. 30D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 31] Fig. 31A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 31B to Fig. 31D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 32] Fig. 32A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 32B to Fig. 32D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 33] Fig. 33A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 33B to Fig. 33D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 34] Fig. 34A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 34B to Fig. 34D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 35] Fig. 35A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 35B to Fig. 35D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 36] Fig. 36A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 36B to Fig. 36D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 37] Fig. 37A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 37B to Fig. 37D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 38] Fig. 38A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 38B to Fig. 38D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Figure 39] Fig. 39A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 39B to Fig. 39D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 40] Fig. 40A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 40B to Fig. 40D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 41] Fig. 41A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 41B to Fig. 41D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 42]Fig. 42A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 42B to Fig. 42D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 43] Fig. 43A is a plan view illustrating an example of a method for manufacturing a semiconductor device, and Fig. 43B to Fig. 43D are cross-sectional views illustrating an example of a method for manufacturing a semiconductor device. [Diagram 44] 44A to 44D are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Diagram 45] 45A and 45B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Diagram 46] 46A and 46B are cross-sectional views showing an example of a method for manufacturing a semiconductor device. [Figure 47] FIG. 47 is a block diagram illustrating a configuration example of a semiconductor device. [Figure 48] 48A to 48H are diagrams illustrating examples of circuit configurations of memory cells. [Figure 49] 49A and 49B are perspective views illustrating a configuration example of a semiconductor device. [Figure 50] 50(A) and 50(B) are a schematic diagram and a circuit diagram showing an example of a semiconductor device. [Figure 51] 51(A) and 51(B) are schematic diagrams showing an example of a semiconductor device. [Figure 52] FIG. 52 is a circuit diagram showing an example of a semiconductor device. [Diagram 53] FIG. 53 is a cross-sectional view showing an example of a semiconductor device. [Figure 54] 54A and 54B are a top view and a cross-sectional view illustrating an example of a semiconductor device. [Figure 55] FIG. 55 is a block diagram illustrating the CPU. [Figure 56] FIG. 56 is a block diagram illustrating the CPU. [Figure 57] 57(A) and 57(B) are perspective views of a semiconductor device. [Figure 58] 58(A) and 58(B) are perspective views of a semiconductor device. [Figure 59] 59(A) and 59(B) are diagrams for explaining the hierarchy of memory devices in a semiconductor device. [Figure 60] 60(A) and 60(B) are diagrams showing an example of electronic equipment, and FIGS. 60(C) to 60(E) are diagrams showing an example of a mainframe computer. [Figure 61] FIG. 61 is a diagram showing an example of space equipment. [Figure 62] FIG. 62 is a diagram illustrating an example of a storage system applicable to a data center. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and the repeated explanations are omitted. In addition, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be used.

[0030] In addition, for ease of understanding, the position, size, range, etc. of each component shown in the drawings may not represent the actual position, size, range, etc. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings.

[0031] In order to facilitate understanding of the invention, particularly in plan views (also called "top views") and perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0032] In this specification, the ordinal numbers "first" and "second" are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking). In addition, an ordinal number attached to a component in one part of this specification may not match an ordinal number attached to the same component in another part of this specification or in the claims.

[0033] The words "film" and "layer" can be interchanged depending on the circumstances. For example, the term "conductive layer" can be interchanged with the term "conductive film". Or, for example, the term "insulating film" can be interchanged with the term "insulating layer". Furthermore, the term "conductor" can be interchanged with the term "conductive layer" or the term "conductive film" depending on the circumstances. Furthermore, the term "insulating body" can be interchanged with the term "insulating layer" or the term "insulating film" depending on the circumstances.

[0034] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -20 degrees or more and 20 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 70 degrees or more and 110 degrees or less.

[0035] In this specification, "connection" includes, as an example, "electrical connection." Note that the term "electrical connection" may be used to define the connection relationship between circuit elements as an object. Furthermore, "electrical connection" includes "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without a circuit element (e.g., a transistor, a switch, etc. Note that wiring is not a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected via one or more circuit elements.

[0036] For example, assuming that a circuit including A and B is in operation, if there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B, it can be defined as "A and B being indirectly connected" as objects. Even if there is a time during the operation of the circuit when no electrical signal is exchanged or an electrical potential interaction occurs between A and B, it can be defined as "A and B being indirectly connected" as long as there is a time during the operation of the circuit when an electrical signal is exchanged or an electrical potential interaction occurs between A and B.

[0037] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where it cannot be said that "A and B are indirectly connected" is when an insulator is present in the path from A to B. Specifically, there are cases where a capacitive element is connected between A and B, and cases where a transistor's gate insulating film is present between A and B. Therefore, it cannot be said that "the transistor's gate (A) and the transistor's source or drain (B) are indirectly connected."

[0038] Another example of a case in which it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via their sources and drains in the path from A to B, and a constant potential V is supplied to a node between one transistor and another transistor from a power supply, GND, etc.

[0039] The openings include, for example, grooves, slits, etc. Furthermore, a region in which an opening is formed may be referred to as an opening portion.

[0040] Although the drawings used in this embodiment mode show the case where the sidewall of the insulator in the opening portion is perpendicular or approximately perpendicular to the substrate surface or the surface on which the insulator is formed, the sidewall may have a tapered shape.

[0041] In this specification, the term "tapered shape" refers to a shape in which at least a part of the side of the structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle between the inclined side and the substrate surface or the surface to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°. The side of the structure and the substrate surface do not necessarily need to be completely flat, and may be approximately planar with a fine curvature or approximately planar with fine irregularities.

[0042] In this specification, the term "having the same or approximately the same height" refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view. For example, in a manufacturing process of a memory device, a planarization process (typically a CMP process) may be performed to expose the surface of a single layer or multiple layers. In this case, the surfaces to be processed in the CMP process have a configuration in which the heights from the reference surface are equal. However, the heights of multiple layers may differ depending on the processing device, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "having the same or approximately the same height". For example, when there are two layers (here, a first layer and a second layer) having different heights with respect to the reference surface, the difference between the height of the top surface of the first layer and the height of the top surface of the second layer is 20 nm or less, this is also referred to as "having the same or approximately the same height".

[0043] In this specification, the phrase "side edges that match or approximately match" refers to at least a portion of the contours of the stacked layers overlapping in a plan view. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer. In these cases, the phrase "side edges that match or approximately match" is also used.

[0044] (Embodiment 1) In this embodiment, a semiconductor device including an oxide semiconductor layer and a method for manufacturing the semiconductor device will be described with reference to FIGS.

[0045] <Configuration Example 1 of Semiconductor Device> A configuration example of the semiconductor device will be described with reference to Fig. 1 to Fig. 11. Fig. 1A to Fig. 1D are plan views and cross-sectional views of a semiconductor device including a transistor 200 over a substrate (not shown).

[0046] FIG. 1A is a plan view of the semiconductor device. FIG. 1B to FIG. 1D are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. FIG. 1D is a cross-sectional view of a portion indicated by a dashed line A5-A6 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Here, the dashed line A5-A6 is perpendicular to the dashed line A1-A2 and the dashed line A3-A4, and the dashed line A1-A2 and the dashed line A3-A4 are parallel to each other. In the plan view of Fig. 1A, some elements are omitted for clarity, and some elements are shown in a see-through state. Fig. 3A shows an enlarged view of the vicinity of the conductor 260 in Fig. 1D. Fig. 2A shows an enlarged view of the vicinity of the oxide semiconductor 230 in Fig. 1B. Fig. 2B shows an enlarged view of the vicinity of the oxide semiconductor 230 in Fig. 1C.

[0047] 2A shows an example in which the oxide semiconductor 230 includes an oxide semiconductor 230a, an oxide semiconductor 230b, and an oxide semiconductor 230c. The details of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c will be described later. FIG 2A also shows an example in which the insulator 250 includes an insulator 250a, an insulator 250b, an insulator 250c, and an insulator 250d.

[0048] 2B shows an example in which the oxide semiconductor 230 includes an oxide semiconductor 230a, an oxide semiconductor 230b, and an oxide semiconductor 230c. FIG. 2B also shows an example in which the conductor 240a includes a conductor 240a1 and a conductor 240a2. It is preferable that the conductors such as the conductor 260, the conductor 240a, the conductor 240b, the conductor 242a, and the conductor 242b have a layered structure. The layered structure of the conductors will be described in detail later.

[0049] 3A shows an example in which the insulator 250 includes an insulator 250a, an insulator 250b, an insulator 250c, and an insulator 250d. Details of the insulators 250a, 250b, 250c, and 250d will be described later.

[0050] The semiconductor device according to this embodiment includes an insulator 216 on a substrate (not shown), an insulator 221 on the insulator 216, an insulator 222 on the insulator 221, an oxide semiconductor 230 on the insulator 222, a conductor 242a and a conductor 242b on the oxide semiconductor 230 and the insulator 222, an insulator 250 on the oxide semiconductor 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250. Note that hereinafter, the conductor 242a and the conductor 242b may be collectively referred to as the conductor 242.

[0051] An insulator 275 is provided on the conductor 242, and an insulator 280 is provided on the insulator 275. The insulator 250 and the conductor 260 are disposed inside openings provided in the insulator 280 and the insulator 275. The openings reach the oxide semiconductor 230, and the insulator 250 is in contact with the oxide semiconductor 230 in the openings. An insulator 282 is provided on the insulator 280 and the conductor 260. An insulator 283 is provided on the insulator 282. An insulator 215 is provided under the insulator 216.

[0052] An insulator 241a is provided in contact with the inner wall of an opening of the insulator 280 or the like, and a conductor 240a is provided in contact with the side surface of the insulator 241a. The lower surface of the conductor 240a is provided in contact with the upper surface of the conductor 242a. An insulator 241b is provided in contact with the inner wall of an opening of the insulator 280 or the like, and a conductor 240b is provided in contact with the side surface of the insulator 241b. The lower surface of the conductor 240b is provided in contact with the upper surface of the conductor 242b. In the following, the conductors 240a and 240b may be collectively referred to as the conductor 240. In addition, the insulators 241a and 241b may be collectively referred to as the insulator 241.

[0053] The oxide semiconductor 230 has a region functioning as a channel formation region of the transistor 200. The conductor 260 has a region functioning as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region functioning as a first gate insulator of the transistor 200.

[0054] The conductor 242a has a region that functions as one of a source electrode or a drain electrode of the transistor 200. The conductor 240a functions as a plug that connects to the conductor 242a. The conductor 242b has a region that functions as the other of a source electrode or a drain electrode of the transistor 200. The conductor 240b functions as a plug that connects to the conductor 242b.

[0055] The oxide semiconductor 230 is formed on and in contact with the insulator 222. The oxide semiconductor 230 has a shape with a high aspect ratio in a cross-sectional view in the channel width direction as shown in Figures 2A and 2B. Therefore, the oxide semiconductor 230 can also be said to have a fin-like shape.

[0056] Here, the aspect ratio of the oxide semiconductor 230 in the cross section in the channel width direction refers to the ratio of the length L of the oxide semiconductor 230 in the A1-A2 direction (which can also be referred to as the width L of the oxide semiconductor 230) to the length H of the oxide semiconductor 230 in a direction perpendicular to the surface on which the oxide semiconductor 230 is formed (for example, the insulator 222) (which can also be referred to as the height H of the oxide semiconductor 230). The aspect ratio of the oxide semiconductor 230 is preferably as large as possible within a range in which the oxide semiconductor 230 does not fall during the manufacturing process of the transistor 200. In the oxide semiconductor 230, the height H of the oxide semiconductor 230 is at least longer than the width L of the oxide semiconductor 230. The height H of the oxide semiconductor 230 may be greater than 1 time and less than 400 times, preferably 2 times or more and 100 times or less, more preferably 5 times or more and 40 times or less, and further preferably 10 times or more and 20 times or less, of the width L of the oxide semiconductor 230. For example, the height H may be greater than 2 times and less than 10 times the width L. For example, the width L may be 5 nm to 100 nm, preferably 5 nm to 50 nm, more preferably 10 nm to 30 nm. For example, the height H may be 50 nm to 2000 nm, preferably 100 nm to 1000 nm. For example, the height H may be 50 nm to 100 nm.

[0057] 2A, in a cross-sectional view in the channel width direction, the side surface of the oxide semiconductor 230 and the top surface of the insulator 222 are preferably perpendicular or approximately perpendicular to each other. The angle between the side surface of the oxide semiconductor 230 and the top surface of the insulator 222 is defined as an angle θ. For example, the angle θ is preferably 80° to 100°, preferably 85° to 95°.

[0058] The insulator 250, the conductor 260, and the conductor 242 are provided to cover the oxide semiconductor 230 having such a high aspect ratio. In the transistor 200, as shown in FIG. 1B and FIG. 2A, a part of the insulator 250 and the conductor 260 are provided so as to sandwich the oxide semiconductor 230 in two. As a result, in a cross-sectional view in the channel width direction, the oxide semiconductor 230 and the conductor 260 are provided to face each other with the insulator 250 sandwiched between the upper part, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. That is, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 function as a channel formation region. Therefore, the channel width of the transistor 200 is larger by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230 than when the oxide semiconductor 230 is formed in a planar shape.

[0059] By increasing the channel width as described above, the on-state current, transconductance, frequency characteristics, and the like of the transistor 200 can be improved. As a result, a semiconductor device with high operating speed can be provided. Furthermore, the operating speed of a storage device using the semiconductor device can be increased. In addition, in the above structure, by providing the oxide semiconductor 230, the channel width can be increased without increasing the area occupied by the transistor 200. As a result, miniaturization or high integration of the semiconductor device can be achieved. Furthermore, the storage capacity of a storage device using the semiconductor device can be increased. Furthermore, with the above structure, the area where the side surfaces of the conductor 260 and the oxide semiconductor 230 face each other is increased, so that the transistor 200 can be normally-off by controlling the threshold voltage.

[0060] As shown in FIG. 2A and other drawings, the upper portion of the oxide semiconductor 230 may have a curved shape. Such a curved shape can prevent defects such as voids from being formed in the insulator 250 and the conductor 242 near the upper portion of the oxide semiconductor 230. Note that in FIG. 2A and FIG. 2B and other drawings, a symmetrical structure is formed in which curved shapes are provided on both the A1 side (A3 side) and the A2 side (A4 side) of the upper portion of the oxide semiconductor 230, but the present invention is not limited to this. For example, an asymmetrical structure may be formed in which a curved shape is provided on either the A1 side (A3 side) or the A2 side (A4 side) of the upper portion of the oxide semiconductor 230.

[0061] Since the oxide semiconductor 230 has a shape with a high aspect ratio, it is preferable to form the oxide semiconductor 230 in a sidewall shape on the side surface of the pillar (the insulator 223 described later). Therefore, it is preferable to form the oxide semiconductor 230 by using the ALD method, which has good coverage. In addition, when the oxide semiconductor 230 has a stacked structure, it is preferable to form at least one layer, preferably a layer in contact with the pillar, by the ALD method.

[0062] By forming the oxide semiconductor 230 in a sidewall shape in contact with the side surfaces of the pillars, a plurality of fin-shaped regions can be simultaneously formed in the oxide semiconductor 230 as shown in FIG 1A. By forming a plurality of fin-shaped regions in this manner, the distance between the fin-shaped regions can be set in accordance with the size and shape of the pillars. Therefore, the distance between the fin-shaped regions can be reduced, the area occupied by the transistor 200 can be reduced, and the semiconductor device can be highly integrated.

[0063] Since the oxide semiconductor 230 is formed in a sidewall shape in contact with the pillar, the top surface shape of the oxide semiconductor 230 has a circumferential shape (which can also be referred to as a frame shape, annular shape, doughnut shape, or closed curve shape) with both ends coinciding, as shown in FIG. 1A. The oxide semiconductor 230 can also be referred to as having an opening in the center. Note that in FIG. 1A, the top surface shape of the oxide semiconductor 230 is line symmetric about A1-A2, but the present invention is not limited to this. For example, the top surface shape of the oxide semiconductor 230 may be asymmetric.

[0064] In the structure shown in FIG. 1A, two pillars are arranged in the A1-A2 direction, and a circumferential oxide semiconductor 230 is formed in contact with a side surface of each pillar. As shown in FIG. 1A, the oxide semiconductor 230 preferably overlaps with the conductor 260 at two or more locations in a top view. That is, the oxide semiconductor 230 has two or more regions where the oxide semiconductor 230 and the conductor 260 overlap. With this structure, as shown in FIG. 1B, a plurality of fin-shaped regions are formed in the oxide semiconductor 230 in a cross-sectional view in the channel width direction. Each of the plurality of fin-shaped regions functions as a channel formation region. That is, the transistor 200 functions as a multi-channel transistor. Thus, the channel width of the transistor 200 can be further increased.

[0065] In the above, the configuration in which two circumferential oxide semiconductors 230 are provided has been described, but the present invention is not limited thereto. For example, one or three or more circumferential oxide semiconductors 230 may be provided. In addition, the circumferential oxide semiconductors 230 may be combined to form an oxide semiconductor 230 having a shape with a plurality of openings. For example, as shown in FIG. 5(A), the oxide semiconductor 230 may be formed in a shape in which three openings are arranged in the A1-A2 direction in a top view. In this case, three pillars may be formed adjacent to each other at a short distance, and the oxide semiconductor 230 may be formed between the pillars. In addition, as shown in FIG. 5(B), the oxide semiconductor 230 may be formed in a lattice shape in a top view. In this case, a lattice-shaped trench may be formed in the pillar, and the oxide semiconductor 230 may be formed so as to fill the trench. In addition, the number of oxide semiconductors 230 is not limited to two, and one or three or more may be provided. In this way, it is preferable that the oxide semiconductor 230 has a structure having a plurality of portions extending in the channel width direction (A1-A2 direction) and a plurality of portions extending in the channel length direction (A5-A6 direction). This makes it possible to prevent the oxide semiconductor 230 from collapsing during the manufacturing process of the transistor when the oxide semiconductor 230 has a high aspect ratio.

[0066] A channel formation region and a source region and a drain region sandwiching the channel formation region are formed in the oxide semiconductor 230. At least part of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.

[0067] The channel formation region is a high-resistance region with a low carrier concentration because it has fewer oxygen vacancies or a lower impurity concentration than the source and drain regions. Therefore, the channel formation region can be said to be i-type (intrinsic) or substantially i-type.

[0068] In addition, the source and drain regions are low-resistance regions with high carrier concentrations due to a large number of oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements. In other words, the source and drain regions are n-type regions (low-resistance regions) with a high carrier concentration compared to the channel formation region.

[0069] The carrier concentration in the channel formation region is 1×10 18 cm -3 Below, 1×10 17 cm -3 Less than 1×10 16 cm -3 Less than 1×10 15 cm -3 Less than 1×10 14 cm -3 Less than 1×10 13 cm -3 Less than 1×10 12 cm -3 Less than 1×10 11 cm -3 Less than or equal to 1×10 10 cm -3 The lower limit of the carrier concentration in the channel formation region is not particularly limited, but is preferably less than 1×10 -9 cm -3 It can be said that:

[0070] Note that when the carrier concentration of the oxide semiconductor 230 is reduced, the impurity concentration in the oxide semiconductor 230 is reduced to reduce the density of defect states. In this specification and the like, a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that an oxide semiconductor (or metal oxide) with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0071] In order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the channel formation region in the oxide semiconductor 230. In order to reduce the impurity concentration in the oxide semiconductor 230, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like. Note that the impurities in the oxide semiconductor 230 refer to, for example, any element other than the main component constituting the oxide semiconductor 230. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0072] In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide semiconductor 230. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may change continuously within each region without being limited to a stepwise change from region to region. That is, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.

[0073] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region in which a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. O H) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists even when no voltage is applied to the gate electrode, and a current flows through the transistor). Therefore, in the channel formation region of the oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H be reduced as much as possible. In other words, it is preferable that the channel formation region in the oxide semiconductor has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0074] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor and heat treatment is performed. In this way, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies within the substrate surface, the characteristics of a semiconductor device having the transistor may vary. Furthermore, if oxygen supplied from the insulator to the oxide semiconductor diffuses into a conductor such as a gate electrode, a source electrode, or a drain electrode, the conductor may be oxidized and its conductivity may be impaired, which may adversely affect the electrical characteristics and reliability of the transistor.

[0075] Therefore, in the oxide semiconductor, the channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, and the source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H in the source and drain regions. Also, it is preferable to prevent an excessive amount of oxygen from being supplied to the source and drain regions. O It is preferable to prevent the amount of H from being excessively reduced. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor is V O H can be formed, so V O To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0076] Therefore, in this embodiment, a semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress the oxidation of the conductor 242a, the conductor 242b, and the conductor 260, and suppress the reduction in the hydrogen concentration in the source and drain regions.

[0077] It is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 242a, the conductor 242b, and the conductor 260, respectively. Examples of the conductive material include a conductive material containing nitrogen and a conductive material containing oxygen. This can suppress a decrease in the conductivity of the conductor 242a, the conductor 242b, and the conductor 260. When a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors that have at least a metal and nitrogen.

[0078] The conductor 242a and the conductor 242b are disposed apart from each other and are provided in contact with the oxide semiconductor 230. As shown in FIG. 2B and the like, the conductor 242 is provided so as to cover the oxide semiconductor 230, which has a high aspect ratio. In addition, the conductor 242a (the conductor 242b) preferably has a structure in which it is in contact with two or more fin-shaped regions of the oxide semiconductor 230 in a cross-sectional view as shown in FIG. 1C.

[0079] Here, in the vicinity of the source or drain of the transistor 200, as shown in FIG. 2B, the conductor 242a is provided so as to be folded in half with the oxide semiconductor 230 sandwiched therebetween. As a result, in a cross-sectional view in the channel width direction, the conductor 242a is in contact with the oxide semiconductor 230 at the top, the side surface on the A3 side, and the side surface on the A4 side of the oxide semiconductor 230. Thus, compared to the case where the oxide semiconductor 230 is formed in a planar shape, the contact area between the conductor 242a and the oxide semiconductor 230 is increased by the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, by using a structure in which the conductor 242a is in contact with a plurality of fin-shaped regions of the oxide semiconductor 230 as shown in FIG. 1C, the contact area can be further increased. Note that although the vicinity of the conductor 242a is shown in FIG. 2B and FIG. 1C, the same applies to the conductor 242b. That is, similar to the above-described conductor 242a and oxide semiconductor 230, the contact area between the conductor 242b and the oxide semiconductor 230 is large.

[0080] By increasing the contact area between the conductor 242 and the oxide semiconductor 230 as described above, the on-state current, frequency characteristics, and the like of the transistor 200 can be improved without increasing the area occupied by the transistor 200. As a result, a semiconductor device with high operating speed can be provided. In addition, the operating speed of a memory device using the semiconductor device can be increased. As a result, the semiconductor device can be miniaturized or highly integrated. In addition, the storage capacity of a memory device using the semiconductor device can be increased.

[0081] The conductor 242a and the conductor 242b are preferably made of a conductive material that is not easily oxidized or a conductive material that has a function of suppressing diffusion of oxygen because they are in contact with the oxide semiconductor 230. This can suppress a decrease in the conductivity of the conductor 242a and the conductor 242b. In addition, it can suppress the extraction of oxygen from the oxide semiconductor 230 and the formation of an excessive amount of oxygen vacancy. In addition, it is preferable to use a material that easily absorbs (extracts) hydrogen as the conductor 242a and the conductor 242b because the hydrogen concentration in the oxide semiconductor 230 can be reduced.

[0082] As the conductor 242, it is preferable to use a metal nitride, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0083] Note that hydrogen contained in the oxide semiconductor 230 or the like may diffuse into the conductor 242a or the conductor 242b. In particular, when a nitride containing tantalum is used for the conductor 242a and the conductor 242b, hydrogen contained in the oxide semiconductor 230 or the like is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide semiconductor 230 or the like may be absorbed by the conductor 242a or the conductor 242b.

[0084] In order to suppress a decrease in the electrical conductivity of the conductor 242a and the conductor 242b, a crystalline oxide such as CAAC-OS can be used as the oxide semiconductor 230. In particular, it is preferable to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. The use of CAAC-OS can suppress the extraction of oxygen from the oxide semiconductor 230 by the conductor 242a or the conductor 242b. In addition, a decrease in the electrical conductivity of the conductor 242a and the conductor 242b can be suppressed.

[0085] It is preferable that the conductor 242a and the conductor 242b have a two-layer structure. The conductor 242a can be a laminated film of the conductor 242a1 and the conductor 242a2 on the conductor 242a1, and the conductor 242b can be a laminated film of the conductor 242b1 and the conductor 242b2 on the conductor 242b1. In this case, it is preferable to use the above-mentioned conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the layer in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1). This can suppress a decrease in the conductivity of the conductor 242a and the conductor 242b. In addition, it is possible to suppress the extraction of oxygen from the oxide semiconductor 230 and the formation of an excessive amount of oxygen vacancy. Furthermore, when a material that easily absorbs (removes) hydrogen is used for the layers in contact with the oxide semiconductor 230 (the conductor 242a1 and the conductor 242b1), the hydrogen concentration in the oxide semiconductor 230 can be reduced, which is preferable.

[0086] Moreover, it is preferable that the conductor 242a2 and the conductor 242b2 have higher conductivity than the conductor 242a1 and the conductor 242b1. For example, it is preferable that the film thickness of the conductor 242a2 and the conductor 242b2 is larger than the film thickness of the conductor 242a1 and the conductor 242b1. As the conductor 242a2 and the conductor 242b2, a conductor that can be used for the conductor 260b described later may be used. By using the above structure, it is possible to reduce the resistance of the conductor 242a2 and the conductor 242b2. As a result, it is possible to increase the on-current of the transistor 200 and improve the operating speed of the semiconductor device according to this embodiment.

[0087] For example, tantalum nitride or titanium nitride can be used as the conductor 242a1 and the conductor 242b1, and tungsten can be used as the conductor 242a2 and the conductor 242b2.

[0088] The semiconductor device shown in Figures 8A to 8D shows an example in which the conductor 242a and the conductor 242b each have a two-layer structure in the configuration shown in Figures 1A to 1D. Also, Figure 10A shows an enlarged view of the vicinity of the conductor 260 in Figure 8D.

[0089] 1B and 1D, the conductor 260 is disposed in openings formed in the insulator 280 and the insulator 275. The conductor 260 is provided in the opening so as to cover the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230 via the insulator 250. The top surface of the conductor 260 is disposed so as to be flush or approximately flush with the top of the insulator 250 and the top surface of the insulator 280.

[0090] In the opening in which the conductor 260 and the insulator 250 are disposed, the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the insulator 250 and the like provided in the opening of the insulator 280 is improved, and defects such as voids can be reduced.

[0091] The conductor 260 functions as a first gate electrode of the transistor 200. Here, the conductor 260 is preferably provided to extend in the channel width direction as shown in Figures 1A and 1B. With this structure, when a plurality of transistors are provided, the conductor 260 functions as a wiring.

[0092] A part of the conductor 260 is provided so as to be folded in half with the fin-shaped oxide semiconductor 230 sandwiched therebetween. As a result, in a cross-sectional view in the channel width direction as shown in FIG. 2A, the oxide semiconductor 230 and the conductor 260 are provided to face each other with the insulator 250 sandwiched therebetween at the upper part, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230. That is, the upper part, the side surface on the A1 side, and the side surface on the A2 side of the oxide semiconductor 230 each function as a channel formation region. Thus, the channel width of the transistor 200 is larger by the side surface on the A1 side and the side surface on the A2 side of the oxide semiconductor 230 than when the oxide semiconductor 230 has a planar shape.

[0093] In FIG. 1(D) and the like, the conductor 260 is shown to have a two-layer structure. Here, the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a. For example, the conductor 260a is preferably arranged so as to surround the bottom and side surfaces of the conductor 260b. In this case, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 260a.

[0094] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0095] Furthermore, since the conductor 260a has a function of suppressing the diffusion of oxygen, it is possible to suppress the conductor 260b from being oxidized by oxygen contained in the insulator 280 and the like, and thus to suppress a decrease in conductivity. As a conductive material having a function of suppressing the diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and the like are preferably used. Furthermore, since ruthenium has conductivity even when oxidized, it is possible to suppress a decrease in conductivity even when oxygen is taken into ruthenium. Therefore, ruthenium and ruthenium oxide can maintain low conductivity even when provided in contact with an insulator that releases oxygen.

[0096] Moreover, it is preferable that the conductor 260b is a conductor having high conductivity. For example, the conductor 260b may be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above-mentioned conductive material.

[0097] In the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. Here, the side surface of the insulator 280 in the above-mentioned opening coincides or substantially coincides with the side surface of the conductor 242a and the side surface of the conductor 242b. Therefore, the conductor 260 can be arranged so as to overlap the region between the conductor 242a and the conductor 242b without alignment.

[0098] The insulators 216 and 280 each preferably have a dielectric constant lower than that of the insulator 222. By using a material with a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced.

[0099] For example, insulator 216 and insulator 280 each preferably comprise one or more of silicon oxide, silicon oxynitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, and silicon oxide with vacancies.

[0100] In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferred because they can easily form a region containing oxygen that is desorbed by heating.

[0101] Additionally, the top surfaces of the insulators 216 and 280 may each be flattened.

[0102] It is preferable that the concentration of impurities such as water and hydrogen is reduced in the insulator 280. For example, it is preferable that the insulator 280 has an oxide containing silicon, such as silicon oxide or silicon oxynitride.

[0103] Conductor 240a and conductor 240b are formed in openings of insulator 275, insulator 280, insulator 282, and insulator 283, respectively. The lower surface of conductor 240a contacts the upper surface of conductor 242a, and the lower surface of conductor 240b contacts the upper surface of conductor 242b. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 283 are approximately the same.

[0104] The conductor 240 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240 may have a layered structure in which a first conductor is provided in contact with a side surface of the insulator 241 and a second conductor is provided further inside. In this case, the above-mentioned conductive material can be used as the second conductor. Here, the first conductor corresponds to the conductor 240a1 and the conductive layer 240b1 shown in FIG. 2(B), and the second conductor corresponds to the conductor 240a2 and the conductive layer 240b2 shown in FIG. 2(B).

[0105] In addition, when the conductor 240 has a layered structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the first conductor arranged near the insulator 283, the insulator 282, the insulator 280, and the insulator 275. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. In addition, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. With such a structure, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide semiconductor 230 through the conductor 240a and the conductor 240b.

[0106] The insulators 241a and 241b are formed in contact with the inner walls of the openings of the insulators 275, 280, 282, and 283, respectively. The inner side surface of the insulator 241a contacts the conductor 240a, and the inner side surface of the insulator 241b contacts the conductor 240b.

[0107] The insulator 241 may be a barrier insulating film that can be used for the insulator 275 or the like. For example, the insulator 241 may be an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. Providing the insulator 241 can prevent impurities such as water and hydrogen contained in the insulator 280 or the like from being mixed into the oxide semiconductor 230 through the conductor 240a and the conductor 240b. Silicon nitride is particularly suitable because it has high blocking properties against hydrogen. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

[0108] When the insulator 241 has a layered structure as shown in Figure 1(D), it is preferable that a first insulator in contact with the inner wall of an opening, such as the insulator 280, and a second insulator on the inside thereof use a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0109] For example, the first insulator may be aluminum oxide formed by thermal ALD, and the second insulator may be silicon nitride formed by PEALD. This configuration can suppress oxidation of the conductor 240 and reduce hydrogen contamination of the conductor 240.

[0110] In the above, the insulator 241 has a two-layer laminated structure, but the present invention is not limited to this. For example, the insulator 241 may be provided as a single layer or a laminated structure of three or more layers. In the above, the conductor 240 has a two-layer laminated structure, but the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a laminated structure of three or more layers.

[0111] For example, as shown in FIG. 2B, a structure may be used in which the conductor 240a covers the oxide semiconductor 230 and the conductor 242a that is folded in half with the oxide semiconductor 230 sandwiched therebetween. As a result, in a cross-sectional view in the channel width direction, the conductor 240a is in contact with the conductor 242a at the top, the side surface on the A3 side, and the side surface on the A4 side of the oxide semiconductor 230. Thus, compared to a case in which the oxide semiconductor 230 is formed in a planar shape, the contact area between the conductor 240a and the conductor 242a is increased by the side surface on the A3 side and the side surface on the A4 side of the oxide semiconductor 230. Furthermore, by using a structure in which the conductor 240a covers multiple fin-shaped regions of the oxide semiconductor 230 as shown in FIG. 1C, the contact area between the conductor 240a and the conductor 242a can be further increased. 2B and 1C show the vicinity of the conductor 240a and the conductor 242a, the same applies to the conductor 240b and the conductor 242b. That is, like the conductor 240a and the conductor 242a described above, the contact area between the conductor 240b and the conductor 242b is large.

[0112] By increasing the contact area between the conductor 240 and the conductor 242 as described above, the contact resistance between the conductor 240 and the conductor 242 can be reduced. This makes it possible to improve the on-current, frequency characteristics, and the like of the transistor 200 without significantly increasing the occupation area of ​​the transistor 200. This makes it possible to provide a semiconductor device with a high operating speed. In addition, the operating speed of a storage device using the semiconductor device can be increased. This also makes it possible to miniaturize or highly integrate the semiconductor device. In addition, the storage capacity of a storage device using the semiconductor device can be increased.

[0113] 1A, the shape of the opening in which the conductor 240 and the insulator 241 are provided is rectangular in top view, but is not limited to this. For example, the opening may be circular, approximately circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.

[0114] 6A to 6D, the semiconductor device of this embodiment may have a structure in which an insulator 224 is provided under the oxide semiconductor 230. The top surface of the insulator 224 has a shape similar to that of the oxide semiconductor 230, and the insulator 224 overlaps with the oxide semiconductor 230 when viewed from above. The bottom surface of the insulator 224 is in contact with the insulator 222, the side surface of the insulator 224 is in contact with the insulator 250 and the conductor 242a, and the top surface of the insulator 224 is in contact with the bottom surface of the oxide semiconductor 230. The insulator 224 may be formed using an insulating material that can be used for the insulator 250b. For example, silicon oxide can be used as the insulator 224. Since FIGS. 6A to 6D correspond to FIGS. 1A to 1D, the above description can be referred to for a detailed configuration.

[0115] 7, it is preferable that the thickness t2 of the insulator 250 in the openings of the insulator 280 and the insulator 275 is thinner than the thickness t1 of the insulator 224. With this configuration, the bottom surface of the conductor 260 (conductor 260a) located in the opening can be positioned lower than the bottom surface of the oxide semiconductor 230 by the difference (t1-t2) between the thickness t1 and the thickness t2.

[0116] By disposing the lower surface of the conductor 260 below the lower surface of the oxide semiconductor 230, a gate electric field can be applied sufficiently from the upper end to the lower end of the oxide semiconductor 230. In other words, in the opening of the insulator 280 or the like, the entire oxide semiconductor 230 can be electrically surrounded by the electric field of the conductor 260 and can function as a channel formation region. With this configuration, the lower end of the oxide semiconductor 230 can be prevented from functioning as a parasitic channel, and the leakage current between the source electrode and the drain electrode can be reduced. In addition, it is possible to suppress characteristic defects such as normally-on of the transistor caused by the parasitic channel. In other words, it is possible to improve the electrical characteristics of the transistor 200.

[0117] As described above, the oxide semiconductor 230 functions as a channel formation region from its upper end to its lower end, whereby the channel width can be increased, and thus the on-state current, transconductance, frequency characteristics, and the like of the transistor 200 can be improved.

[0118] In this specification and the like, the structure of a transistor in which the electric field of the gate electrode electrically surrounds the channel formation region as described above is called a surrounded channel (S-channel) structure. In the S-channel structure, the gate electrode is disposed so as to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.). By adopting the S-channel structure, it is possible to obtain a transistor that is more resistant to the short channel effect, in other words, in which the short channel effect is less likely to occur.

[0119] Note that the S-channel structure electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a GAA (gate all around) structure or a LGAA (lateral gate all around) structure. By forming the transistor 200 with the S-channel structure, the GAA structure, or the LGAA structure, the channel formation region formed at or near the interface between the oxide semiconductor 230 and the gate insulator can be the entire bulk of the oxide semiconductor 230. Therefore, it is possible to improve the current density flowing through the transistor, and thus it is expected that the on-state current of the transistor or the field-effect mobility of the transistor can be improved. In addition, in one embodiment of the present invention, the oxide semiconductor 230 has a CAAC structure and a fin-like shape. With this structure, a current path flowing between the source and drain of the transistor can be parallel to the ab plane of the crystal axis. In other words, an oxide semiconductor having a CAAC structure and a fin-like shape has a conduction path equivalent to that of a two-dimensional semiconductor material. Furthermore, by using such an oxide semiconductor, a device having two-dimensional conduction can be manufactured.

[0120] <Modification 1-1 of the semiconductor device> 9(A) to 9(D) are different from those shown in Figures 8(A) to 8(D) mainly in that the conductor 242a1 and the conductor 242b1 protrude more than the conductor 242a2 and the conductor 242b2, respectively, in a cross-sectional view in the channel length direction of the transistor 200. In addition, Figure 10(B) shows an enlarged view of the vicinity of the conductor 260 in Figure 9(D).

[0121] The protruding portions of the conductor 242a1 and the conductor 242b1 are covered with the insulator 250. Here, the distance between the conductor 242a1 and the conductor 242b1 is smaller than the distance between the conductor 242a2 and the conductor 242b2. With this configuration, it is possible to shorten the distance between the source and the drain, and accordingly shorten the channel length. Thus, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, it is possible to provide a semiconductor device with improved operating speed.

[0122] <Modification 1-2 of the semiconductor device> 11(A) to 11(D), the semiconductor device of this embodiment may have a structure in which a conductor 205 is provided under an insulator 221. The conductor 205 has a region that functions as a second gate electrode (lower gate electrode) of the transistor 200. The insulator 222 and the insulator 221 each have a region that functions as a second gate insulator of the transistor 200. Here, FIGS. 11(A) to 11(D) correspond to FIGS. 1(A) to 1(D), and therefore the above description can be referred to for the detailed structure.

[0123] In the transistor 200, the conductor 205 is arranged to overlap with the oxide semiconductor 230 and the conductor 260. Here, the conductor 205 is preferably provided to be embedded in an opening formed in the insulator 216. The conductor 205 is preferably provided to extend in the channel width direction as shown in Figures 11(A) and 11(B). With such a structure, the conductor 205 functions as a wiring when a plurality of transistors are provided.

[0124] As shown in Figures 11(B) and 11(D), it is preferable that the conductor 205 has a conductor 205a and a conductor 205b. The conductor 205a is provided in contact with the bottom surface and the side wall of the opening. The conductor 205b is provided so as to fill the recess of the conductor 205a formed along the opening. Here, the height of the upper surface of the conductor 205 coincides or approximately coincides with the height of the upper surface of the insulator 216.

[0125] Here, the conductor 205a preferably has a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it preferably has a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.).

[0126] By using a conductive material having a function of reducing hydrogen diffusion for the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing into the oxide semiconductor 230 through the insulator 216 or the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion for the conductor 205a, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 205b. Examples of conductive materials having a function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, and ruthenium. Furthermore, since ruthenium has conductivity even when oxidized, it is possible to suppress a decrease in conductivity even when oxygen is taken into ruthenium. Ruthenium and ruthenium oxide can maintain low conductivity even when provided in contact with an insulator that releases oxygen. The conductor 205a can have a single-layer structure or a multilayer structure of the above conductive materials. For example, the conductor 205a preferably has titanium nitride.

[0127] The conductor 205b is preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. For example, the conductor 205b preferably contains tungsten.

[0128] The conductor 205 can function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be increased and the off-current can be reduced. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0129] The electrical resistivity of the conductor 205 is designed taking into consideration the potential applied to the conductor 205, and the film thickness of the conductor 205 is set to match the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within a range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and thus diffusion of the impurities into the oxide semiconductor 230 can be suppressed.

[0130] In the above, a laminated structure of the conductor 205a and the conductor 205b is shown, but the present invention is not limited to this, and the conductor 205 may have a single layer structure or a laminated structure of three or more layers. For example, when the conductor 205 has a three-layer laminated structure, the laminated structure of the conductor 205a and the conductor 205b may further include a conductor having the same material as the conductor 205a on the conductor 205b. In this case, the conductor may be formed so that the upper surface of the conductor 205b is lower than the top of the conductor 205a, and the recess formed by the conductor 205a and the conductor 205b is filled.

[0131] <Configuration Example 2 of Semiconductor Device> A configuration example of a semiconductor device will be described with reference to FIG. 14 and FIG.

[0132] 14A to 15B show a 1T (transistor) 1C (capacitor) type memory cell using the above-described transistor 200 and a capacitor 460. When a semiconductor device has a memory cell, the semiconductor device can function as a memory device. In addition, a memory array (also referred to as a memory cell array) can be formed by arranging a plurality of memory cells in a matrix. As an example, the memory device includes a memory array and a driver circuit that drives the memory array.

[0133] FIG. 14(A) shows a plan view of a memory cell. FIG. 14(B) is a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in FIG. 14(A), and includes a cross-sectional view of the transistor 200 in the channel length direction. FIG. 14(C) is a cross-sectional view corresponding to the portion indicated by the dashed line B3-B4 in FIG. 14(A), and includes a cross-sectional view of the transistor 200 in the channel width direction. FIG. 14(D) is a cross-sectional view corresponding to the portion indicated by the dashed line B5-B6 in FIG. 14(A), and also includes a cross-sectional view of the capacitance element 460. FIG. 15(A) is a cross-sectional view corresponding to the portion indicated by the dashed line B7-B8 in FIG. 14(A), and includes a cross-sectional view of the transistor 200 in the channel width direction. FIG. 15(B) is a cross-sectional view corresponding to the portion indicated by the dashed line B9-B10 in FIG. 14(A), and includes a cross-sectional view of the transistor 200 in the channel width direction. In the plan view of FIG. 14(A), some elements are omitted for clarity.

[0134] The transistor 200 may be the transistor 200 shown in FIG. 1A to FIG. 1D or FIG. 8A to FIG. 8D. The structure of the transistor 200 shown in FIG. 14A and the like is similar to the structure shown in FIG. 1A to FIG. 1D or FIG. 8A to FIG. 8D, and may be indicated by similar hatching patterns and symbols. For the detailed structure, the above description may be referred to. Note that in FIG. 14A and FIG. 14B, the stacked structure of the conductor 260 (conductor 260a, conductor 260b), the stacked structure of the conductor 242a and the conductor 242b (conductor 242a1, conductor 242a2, conductor 242b1, conductor 242b2), and the like may be omitted. Further, an insulator 285 is formed over the insulator 283, and a conductor 413 connected to the conductor 240a is formed over the insulator 285. The insulator 285 can be formed using an insulating material that can be used for the insulator 216. The conductor 413 can be formed using a conductive material that can be used for the conductor 242.

[0135] The capacitor 460 includes an oxide semiconductor 230, a conductor 242b over the oxide semiconductor 230, an insulator 454 over the conductor 242b, and a conductor 456 over the insulator 454. The oxide semiconductor 230 and the conductor 242b are used in common with the transistor 200. The insulator 454 has a similar structure to the insulator 250 and can be formed in the same process. The conductor 456 has a similar structure to the conductor 260 and can be formed in the same process. By using a structure in which the oxide semiconductor 230 is shared by the transistor 200 and the capacitor 460, it is not necessary to separate the oxide semiconductor 230 into the transistor 200 and the capacitor and form a pattern; therefore, the area occupied by the transistor 200 and the capacitor 460 can be reduced. Furthermore, the cost required for the manufacturing process can be reduced.

[0136] The capacitor 460 and the transistor 200 can be formed in the same layer. As shown in FIG. 14B, the capacitor 460 and the transistor 200 can be formed in a region sandwiched between the insulator 215 and the insulator 282. The insulator 454 of the capacitor 460 and the insulator 250 of the transistor 200 can be formed from the same insulating film, and the conductor 456 and the conductor 260 can be formed from the same conductive film. Therefore, the formation of the capacitor 460 does not require any additional film formation steps for an insulating film, a conductive film, a semiconductor film, or the like. When the insulator 454 and the insulator 250 are processed in the same process, no additional processing steps are required. Similarly, when the conductor 456 and the conductor 260 are processed in the same process, no additional processing steps are required. Compared to the case where only the transistor 200 is provided, the thickness of the layer does not change when both the transistor 200 and the capacitor 460 are provided in the same layer.

[0137] 14A to 14D and the like, a capacitor can be manufactured without significant changes from the manufacturing process of a transistor, and the thickness of a layer in which a memory cell is provided does not need to be significantly changed, so that the semiconductor device of one embodiment of the present invention is suitable as a memory cell having a three-dimensional structure.

[0138] Here, the capacitor 460 has a conductor 242b functioning as a first electrode, a conductor 456 functioning as a second electrode, and an insulator 454 functioning as a dielectric. That is, the capacitor 460 configures a metal-insulator-metal (MIM) capacitor.

[0139] The capacitor 460 shares the oxide semiconductor 230 with the transistor 200. The insulator 454 and the conductor 456 are provided in openings formed in the insulator 280 and the insulator 275. The insulator 454 can be formed from the same insulator as the insulator 250, and the conductor 456 can be formed from the same conductor as the conductor 260. The conductor 242b has an opening in the transistor 200, whereas the conductor 242b overlaps with the conductor 456 and the insulator 454 in the capacitor 460. The openings provided in the insulator 275 and the insulator 280 in the region where the capacitor 460 is disposed reach the conductor 242b, and the insulator 454 is in contact with a top surface of the conductor 242b through the opening.

[0140] 14D and the like, in the capacitor 460, similarly to the transistor 200, the height of the oxide semiconductor 230 is larger than the width of the oxide semiconductor 230 in a cross-sectional view in the channel width direction. In addition, the oxide semiconductor 230 and the conductor 456 overlap with each other in two or more regions when viewed from above. Thus, the area in which the conductor 242b, the insulator 454, and the conductor 456 provided along the top surface and side surface of the oxide semiconductor 230 face each other can be increased. As a result, the capacitance can be increased without significantly increasing the area occupied by the capacitor 460.

[0141] 14A to 15B show an example in which there are two or more regions where the oxide semiconductor 230 and the conductor 260 overlap (regions where the oxide semiconductor 230 and the conductor 456 overlap); however, there may be only one region where the oxide semiconductor 230 and the conductor 260 overlap (regions where the oxide semiconductor 230 and the conductor 456 overlap). FIG. 15C is a modification of FIG. 14C and is mainly different in that there is only one region where the oxide semiconductor 230 and the conductor 260 overlap. FIG. 15D is a modification of FIG. 14D and is mainly different in that there is only one region where the oxide semiconductor 230 and the conductor 456 overlap.

[0142] The semiconductor device illustrated in FIGS. 16A to 17B differs from the semiconductor device illustrated in FIGS. 14A to 15B in that the capacitor 460 includes an insulator 454b instead of the insulator 454 and a conductor 456b instead of the conductor 456.

[0143] 16A to 17B, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 have openings that reach the conductor 242b. The insulator 454b is provided so as to cover the sidewall of the opening and the top surface of the conductor 242b. The insulator 454b is preferably provided in contact with the top surface of the conductor 242b. The conductor 456b is provided so as to fill the opening. A region of the insulator 454b that is sandwiched between the conductor 242b and the conductor 456b functions as a dielectric of the capacitor 460.

[0144] The insulator 454b and the conductor 456b can be formed after the insulator 250 and the conductor 260 of the transistor 200 are formed and then the insulator 282 and the insulator 283 are formed. In the manufacturing process of the insulator 454b and the conductor 456b, the surface of the oxide semiconductor 230 of the transistor 200 is not exposed; therefore, for example, damage such as etching during the formation of a capacitor is unlikely to occur.

[0145] The insulator 454b may be made of a material different from that of the insulator 250. For example, the insulator 454b may be made of a material with a high dielectric constant. Alternatively, the insulator 454b may be made of a material that may have ferroelectric properties.

[0146] The conductor 456b may be formed using a material different from that of the conductor 260. For example, the conductor 456b can be formed using a material having even lower resistance than the conductor 260.

[0147] A material that can have ferroelectricity can be used as an insulator included in the semiconductor device of one embodiment of the present invention. In particular, a material that can have ferroelectricity is preferably used as the insulator 454b. Examples of the material that can have ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. X (X is a real number greater than 0). Examples of materials that can have ferroelectricity include materials in which an element J1 (here, element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide. Here, the ratio of the number of hafnium atoms to the number of element J1 can be set appropriately, for example, the ratio of the number of hafnium atoms to the number of element J1 can be set to 1:1 or close thereto. Examples of materials that can have ferroelectricity include materials in which an element J2 (here, element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide. Also, the ratio of the number of zirconium atoms to the number of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of element J2 can be set to 1:1 or close thereto. In addition, lead titanate (PbTiO X Piezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used.

[0148] In addition, examples of materials that can have ferroelectricity include metal nitrides having elements M1, M2, and nitrogen. Here, the element M1 is one or more selected from aluminum, gallium, indium, and the like. In addition, the element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, and the like. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. In addition, metal oxides having elements M1 and nitrogen may have ferroelectricity even if they do not contain element M2. In addition, examples of materials that can have ferroelectricity include materials in which element M3 is added to the above metal nitrides. In addition, element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, and the like. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.

[0149] Moreover, examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure.

[0150] In the above description, metal oxides and metal nitrides are exemplified, but the present invention is not limited thereto. For example, metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.

[0151] In addition, as a material capable of having ferroelectricity, for example, a mixture or compound made of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulator of one embodiment of the present invention can have a laminated structure made of a plurality of materials selected from the materials listed above. However, since the crystal structure (characteristics) of the materials listed above may change depending not only on the film formation conditions but also on various processes, in this specification and the like, a material that exhibits ferroelectricity is not only called a ferroelectric but also called a material capable of having ferroelectricity.

[0152] The semiconductor device shown in Figures 18(A) to 19(B) mainly differs from the semiconductor device shown in Figures 14(A) to 15(B) in that the structure shown in Figures 9(A) to 9(D), and Figure 10(B) is applied as the transistor 200 and that the lower layer of the conductor 242b (conductor 242b1) is used as one electrode of the capacitor 460.

[0153] 18A to 19B, the conductor 242b1 has an opening in the transistor 200, and in the capacitor 460, the conductor 242b1 overlaps with the conductor 456 and the insulator 454. In a region where the capacitor 460 is disposed, an opening provided in the insulator 275 and the insulator 280 reaches the conductor 242b1, and the insulator 454 is in contact with a top surface of the conductor 242b1 in the opening. In addition, the conductor 242b2 is removed in a region that overlaps with the conductor 456 of the capacitor 460. Thus, the conductor 242b1 has a region that overlaps with the conductor 242b2 and a region that protrudes from an end of the conductor 242b2 in the transistor 200, and does not overlap with the conductor 242b2 in the capacitor 460.

[0154] 18B and the like, the conductor 456 can have a layered structure of a conductor 456a and a conductor 456b over the conductor 456a. Here, the conductor 456a and the conductor 260a can be formed by processing the same conductive film, and the conductor 456b and the conductor 260b can be formed by processing the same conductive film.

[0155] 20(A) and 20(B) are perspective views showing the structure of the semiconductor device shown in FIGS. 14(A) to 15(B). Note that insulators are omitted in FIG. 20(A). Also, some conductors such as the conductor 240a are omitted. Also, FIG. 20(B) is a see-through view of the conductor 260 and the conductor 456 in FIG. 20(A).

[0156] In FIGS. 20A and 20B, there are four regions where the oxide semiconductor 230 overlaps with the conductor 260, and there are four regions where the oxide semiconductor 230 overlaps with the conductor 456.

[0157] FIG. 21A is a modification of FIG. 20B and illustrates an example in which there is one region where the oxide semiconductor 230 overlaps with the conductor 260 and one region where the oxide semiconductor 230 overlaps with the conductor 456.

[0158] Fig. 21B is a perspective view showing the structure of the semiconductor device shown in Fig. 18A to Fig. 19B. Note that insulators are omitted in Fig. 21B. Some conductors, such as the conductor 240a, are also omitted. The conductor 260 and the conductor 456 are shown in transparent view.

[0159] Fig. 22A shows an enlarged view of a portion of the structure of the capacitor 460 shown in Fig. 14D. Note that in Fig. 22A, the conductor 242b has a layered structure of conductors 242b1 and 242b2, and the conductor 456 has a layered structure of conductors 456a and 456b.

[0160] FIG. 22B shows an enlarged view of a part of the configuration of the capacitor 460 shown in FIG. 18D.

[0161] 22B, the lower electrode of the capacitor 460 is formed as a single layer of the conductor 242b1, so that even if the distance between the fins of the adjacent oxide semiconductors 230 is narrow in the cross-sectional view of FIG 22B, the lower electrode and the insulator 454 formed over the lower electrode can be well covered up to below the oxide semiconductor 230. Thus, the surface area of ​​the lower electrode of the capacitor 460 can be increased, and the capacitance value of the capacitor 460 can be increased.

[0162] 22C to 22E show how the oxide semiconductor 230 is covered with the conductor 242b1, the conductor 242b2, and the insulator 454.

[0163] FIG. 22C shows that the thickness of the conductor 242b1 is thinner on the side surface of the oxide semiconductor 230 than on the top surface of the insulator 222 and the top surface of the oxide semiconductor 230. There is a concern that the resistance of the conductor 242b1 is high in the area where the thickness is thin. Even in such a case, the resistance of the oxide semiconductor 230 can be reduced to function as an electrode, so that the circuit including the capacitor 460 can be operated suitably. When the oxide semiconductor 230 has an appropriate V O The resistance of the oxide semiconductor 230 can be reduced by containing H. Note that it may be expressed that the oxide semiconductor 230 functions as an auxiliary electrode of the conductor 242b1.

[0164] 22D shows an example in which the conductor 242b2 is provided by stacking the conductor 242b1 shown in FIG 22C. By forming the lower electrode of the capacitor 460 to have a stacked structure of the conductor 242b1 and the conductor 242b2, variation in resistance value within the plane of the lower electrode can be reduced.

[0165] Note that when a conductive film to be the conductor 242b2 is formed in a region where the transistor 200 and a region where the capacitor 460 are provided and then the conductive film is removed from the region where the capacitor 460 is provided, part of the conductive film may remain. In FIG. 22E, the remaining part of the conductive film is illustrated as the conductor 242b2R. The remaining conductor 242b2R may improve the coverage of the insulator 454.

[0166] 23A shows the top view shown in Fig. 14A with some components omitted and with the oxide semiconductor 230 shown transparently by a solid line. In addition, Fig. 23B and Fig. 23C each show a modification of Fig. 23A.

[0167] 23B, the interval between adjacent fins in the y direction in the oxide semiconductor 230 is wide in a region overlapping with the conductor 456, that is, in the region where the capacitor 460 is formed. Therefore, even if the interval between the fins is narrow in the region where the transistor 200 is provided, the conductor 456 can well cover the sidewall below the oxide semiconductor 230.

[0168] 23C, the distance between adjacent fins in the oxide semiconductor 230 in the y direction is narrowed, and the number of regions in which the oxide semiconductor 230 and the conductor 456 overlap can be increased. This can also be expressed as an increase in the number of fins of the oxide semiconductor 230 covered by the conductor 456. In the example illustrated in FIG. 23A, in the region in which the transistor 200 is provided, there are two regions in which the conductor 260 and the oxide semiconductor 230 overlap, and in the region in which the capacitor 460 is provided, there are also two regions in which the conductor 456 and the oxide semiconductor 230 overlap. In the example illustrated in FIG. 23C, in the region in which the transistor 200 is provided, there are four regions in which the conductor 260 and the oxide semiconductor 230 overlap, whereas in the region in which the capacitor 460 is provided, there are eight regions in which the conductor 456 and the oxide semiconductor 230 overlap. This allows the capacitance of the capacitor 460 to be larger.

[0169] The semiconductor device may have a structure in which the memory cell shown in FIG. 18A to FIG. 19B is provided on a layer including a transistor formed on a silicon substrate. FIG. 24A shows an example of a structure in which the memory cell shown in FIG. 18A to FIG. 19B is provided on a layer including a transistor 310 formed on a silicon substrate. FIG. 24B shows a cross-sectional view of the transistor 310 in the channel width direction. A transistor constituting a driver circuit of the memory device can be provided in the layer including the transistor 310 formed on the silicon substrate. When the memory cell has a transistor in addition to the transistor 200, the layer including the transistor 310 can also be provided with the transistor included in the memory cell.

[0170] The transistor 310 is provided over a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 including a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 310 may be either a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate can be used.

[0171] As shown in FIG. 24B, in the transistor 310, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided to cover the side and top surfaces of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 310 is also called a fin-type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI (Silicon on Insulator) substrate.

[0172] Note that the transistor 310 illustrated in FIGS. 24A and 24B is just an example, and is not limited to the structure. Any appropriate transistor can be used depending on the circuit configuration or driving method.

[0173] Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Also, in this specification, the wiring and the plug connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0174] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 310. A conductor 328 or the like is embedded in the insulator 320 and the insulator 322. A conductor 330 or the like is embedded in the insulator 324 and the insulator 326. The conductor 328 and the conductor 330 function as contact plugs or wirings.

[0175] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve the flatness.

[0176] The transistor 200 and the capacitor 460 are provided over the insulator 326 .

[0177] <Configuration Example 3 of Semiconductor Device> 24A and 24B, the transistor 310 is connected to the transistor 200 or the capacitor 460, and a 2T (transistor) 1C (capacitor) type memory cell using the transistor 200, the transistor 310, and the capacitor 460 can be formed.

[0178] 24(C), the conductor 242b of the transistor 200 is connected to the conductor 330 provided in the underlying layer through a conductor 458. As shown in Fig. 24(C), the conductor 242b functioning as one of the source and drain of the transistor 200 is connected to the conductor 316 functioning as the gate electrode of the transistor 310 through the conductor 458, the conductor 330, and the conductor 328. Note that Fig. 24(C) is a view including a cross section of the transistor 200 in the channel width direction.

[0179] <Configuration Example 4 of Semiconductor Device> The structure illustrated in FIG. 25 illustrates an example of a 2T1C memory cell including a transistor 200, a capacitor 460, and a transistor 200b. The transistor 200b has a similar structure to the transistor 200. The transistors 200 and 200b are formed in the same layer and are arranged so that their channel length directions intersect with each other. Since the transistor 200b has a similar structure to the transistor 200, the components are indicated with the same hatching patterns and symbols. For a detailed structure, refer to the above description.

[0180] In FIG. 25, the conductor 242b of the transistor 200 is connected to the conductor 260 of the transistor 200b through the conductor 240c, the conductor 413b, and the conductor 240d.

[0181] Here, the conductor 240c and the conductor 240d are formed so as to be embedded in the openings of the insulator 282, the insulator 283, and the insulator 285, and have a structure similar to that of the conductor 240a. The insulator 241c and the insulator 241d are formed so as to be embedded in the openings of the insulator 282, the insulator 283, and the insulator 285, and have a structure similar to that of the insulator 241a. The conductor 413b is preferably provided in contact with the upper surface of the conductor 240c and the upper surface of the conductor 240d. The lower surface of the conductor 240c is preferably provided in contact with the conductor 242b. The lower surface of the conductor 240d is preferably provided in contact with the upper surface of the conductor 260 of the transistor 200b. With such a structure, one of the source and drain of the transistor 200, one electrode of the capacitor 460, and the gate of the transistor 200b are connected.

[0182] 25 shows a structure in which the transistor 200 and the transistor 200b are provided in the same layer, but the present invention is not limited to this. For example, as shown in FIG 26, a layer 401a including the transistor 200 and the capacitor 460 may be stacked over a layer 401b including the transistor 200b. Note that the layer 401a and the layer 401b have a structure similar to that of the layers from the insulator 215 to the insulator 285 shown in FIG 18B and the like.

[0183] 26, the conductor 240e and the insulator 241e may be formed in openings provided in the insulator 282, the insulator 283, and the insulator 285 of the layer 401b and the insulator 215, the insulator 216, the insulator 221, and the insulator 222 of the layer 401a. With this structure, the conductor 242b of the transistor 200 and the conductor 260 of the transistor 200b can be connected.

[0184] Here, the oxide semiconductor 230 included in the transistor 200b is preferably provided so as to overlap with the oxide semiconductor 230 included in the transistor 200 and the capacitor 460. With such a structure, the area occupied by the memory cell can be reduced.

[0185] <Oxide semiconductor layer> Here, an oxide semiconductor layer that can be used for the oxide semiconductor 230 will be described. The oxide semiconductor layer contains a metal oxide.

[0186] When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, when a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects. Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as crystal grain boundaries, and volume defects such as voids.

[0187] By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Examples of the structure of the crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystal structure, and a nanocrystal (nc) structure.

[0188] The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention has a plurality of microcrystals. Moreover, no clear grain boundary is observed between the plurality of microcrystals. The metal oxide included in the oxide semiconductor layer of one embodiment of the present invention preferably has a plurality of oriented microcrystals, and preferably has a crystal structure in which the plurality of microcrystals are connected without clear grain boundaries when observed from the orientation direction.

[0189] The oxide semiconductor layer of one embodiment of the present invention preferably contains a metal oxide having a crystal structure different from a single crystal structure and a polycrystalline structure, and more preferably contains a metal oxide having a CAAC structure.

[0190] The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have a c-axis orientation and are connected in the ab plane without having clear crystal grain boundaries. When a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image, it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Thus, the oxide semiconductor layer having a CAAC structure can be said to have a structure having layered crystal parts. The metal atoms arranged in a layered manner can be observed as a row of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. The bright spots are arranged, for example, in a direction parallel to the surface on which the oxide semiconductor layer is formed.

[0191] In addition, in each of the multiple microcrystals, the metal atoms are arranged in layers parallel or approximately parallel to the surface on which the film is formed, and the layers in which the metal atoms are arranged are stacked in a direction perpendicular or approximately perpendicular to the surface on which the film is formed, and this structure is sometimes referred to as a CAAC structure. If the microcrystals have such a configuration, the crystal structure of the microcrystals is not limited to a hexagonal system. For example, some of the multiple microcrystals may have a crystal structure other than a hexagonal system (for example, a cubic system crystal structure).

[0192] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the film is formed. In the CAAC structure, metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which the film is formed. In the region of the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the film is formed.

[0193] The polycrystalline structure has crystal grain boundaries. When a heat treatment is performed after forming an oxide semiconductor layer having a polycrystalline structure, a minute gap (also referred to as a nanocrack or a microcrack) or a minute space (also referred to as a nanospace or a microspace) may be formed between the crystal parts. When a minute gap or a minute space is formed in the oxide semiconductor layer, the electric resistance of the oxide semiconductor layer increases. This is because the electric resistance of the minute gap or the minute space is very high, for example, infinite. When an oxide semiconductor layer having a minute gap or a minute space is used in a channel formation region of a transistor, the contact resistance between the oxide semiconductor layer and one or both of a source electrode and a drain electrode increases. This adversely affects the initial characteristics or reliability of the transistor. In contrast, in the CAAC structure, crystal grain boundaries are not clearly observed in the ab plane, so that a highly reliable semiconductor device can be realized. In addition, since there are few crystal grain boundaries, the energy barrier against carrier conduction in the channel of the transistor is small, and an improvement in on-current is expected. In addition, it is expected that an increase in the electrical resistance of a semiconductor layer of a transistor including an oxide semiconductor layer can be suppressed, or the initial characteristics (particularly, on-state current) of the transistor can be improved, so that the transistor can be suitable for high-speed operation.

[0194] A metal oxide that increases the on-state current of a transistor is preferably used for the channel formation region of the transistor. In order to increase the on-state current of the transistor, it is preferable to increase the mobility of the metal oxide used in the transistor. In order to increase the mobility of the metal oxide, it is necessary to improve the transmission of carriers (electrons in the case of an n-channel transistor) or reduce scattering factors that contribute to the transmission of carriers. Note that carriers flow from the source to the drain through the channel formation region. Therefore, by providing a channel formation region in which carriers can easily flow in the channel length direction, the on-state current of a transistor can be increased.

[0195] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED), or the analysis may be performed by combining a plurality of these techniques.

[0196] When an oxide semiconductor layer having a CAAC structure is subjected to electron beam diffraction, spots (bright points) indicating c-axis orientation are observed in the electron beam diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to the normal vector of the surface on which the oxide semiconductor layer is formed or the normal vector of the surface of the oxide semiconductor layer.

[0197] Furthermore, an FFT pattern obtained by subjecting a TEM image to a Fast Fourier Transform (FFT) process reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0198] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is obtained, and an FFT pattern is created by performing FFT processing for each region in the cross-sectional TEM image, and the crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that are high in brightness and are approximately equal distances from the center among the spots observed in the created FFT pattern is taken as the crystal axis direction. A region in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered as a CAAC structure.

[0199] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the ab plane, and the layer has crystallinity. In addition, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and typically, hexagonal Voronoi regions are observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0200] We will now explain how to create a Voronoi diagram. First, image analysis of a TEM image involves performing FFT processing, then filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT filtered image. Lattice points are extracted from the created FFT filtered image, and perpendicular bisectors of the lines connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal region surrounded by the lines connecting the Voronoi points is defined as the Voronoi region. In this way, a Voronoi diagram can be created.

[0201] In the creation of a Voronoi diagram, a rectangular region of 50 nm in length and 50 nm in width may be observed as an example of the observation range of the TEM, but the observation range is not limited to this.

[0202] Furthermore, when the distribution of hexagonal lattice orientations is analyzed using lattice points extracted by image analysis of planar TEM images, the difference in hexagonal lattice orientations at the boundary between two structures with different hexagonal lattice orientations is small, the boundary is observed to be blurred, and the two structures appear to be connected in a manner that seems to interpenetrate. In other words, no clear boundary is observed in the CAAC structure.

[0203] The orientation of the hexagonal lattice can be calculated by calculating the orientation of the hexagon formed by the six lattice points closest to each lattice point.

[0204] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not limited. The oxide semiconductor layer may include at least one of an amorphous semiconductor (a semiconductor having an amorphous structure), a single crystal semiconductor (a semiconductor having a single crystal structure), and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics may be suppressed.

[0205] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and more preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain element M. Also, the metal oxide preferably contains two or three selected from indium, element M, and zinc, and more preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain element M. Here, element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, tin, yttrium, and aluminum, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. In this specification, etc., metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification, etc. may include metalloid elements.

[0206] The main component in a metal oxide refers to a metal element whose proportion relative to all metal elements contained in the metal oxide is, for example, 0.1 atomic % or more, or 1 atomic % or more.

[0207] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which the oxide semiconductor layer is formed. In the TEM image, the metal atoms are observed as bright spots. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Also, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0208] Examples of the metal oxide according to one embodiment of the present invention include indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum Indium zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also referred to as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used. Indium oxide can be used as the metal oxide according to one embodiment of the present invention. Gallium oxide, zinc oxide, etc. can be used as the metal oxide according to one embodiment of the present invention.

[0209] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-current and high frequency characteristics.

[0210] In addition, by increasing the ratio of the number of zinc atoms to the total number of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing the fluctuation of the electrical characteristics of the transistor and improving its reliability.

[0211] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. In addition, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.

[0212] The metal oxide may have one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may have one or more metal elements having a higher period number in addition to indium. The greater the overlap of the orbits of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Thus, by including a metal element having a higher period number, the field effect mobility of the transistor may be increased. Examples of metal elements having a higher period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0213] The metal oxide may contain one or more nonmetallic elements. When the metal oxide contains a nonmetallic element, the field-effect mobility of the transistor may be increased. Examples of the nonmetallic element include carbon, nitrogen, phosphorus, sulfur, fluorine, chlorine, bromine, and hydrogen.

[0214] [Method for producing oxide semiconductor layer] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide using two types of film formation methods.

[0215] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a metal oxide having a CAAC structure is formed. In this case, a sputtering method can be used as a film formation method, whereby a metal oxide having high crystallinity can be formed. Alternatively, a pulsed laser deposition (PLD) method or the like may be used as a film formation method.

[0216] Here, when a metal oxide is formed using the above-mentioned film formation method (hereinafter, the first film formation method), a mixed layer may be formed at the interface between the metal oxide and the surface to be formed. There is a concern that the mixed layer may hinder the crystallization of the metal oxide. By forming a metal oxide as a first layer on the surface to be formed in advance using a film formation method (hereinafter, the second film formation method) that causes less damage compared to the sputtering method, PLD method, and the like shown as the first film formation method, and then providing a metal oxide using the first film formation method as a second layer, the formation of a mixed layer at the interface between the oxide semiconductor layer and the surface to be formed can be suppressed. In addition, impurities contained in the surface to be formed can be suppressed from being mixed into the second layer. As a result, the crystallinity of the second layer can be further improved.

[0217] Atomic layer deposition (ALD) and chemical vapor deposition (CVD) are suitable as the second film formation method because they can suppress damage to the surface to be formed compared with sputtering. Examples of the second film formation method include molecular beam epitaxy (MBE) and wet methods. Examples of CVD methods include plasma enhanced CVD (PECVD), thermal CVD, photo CVD, and metal organic CVD (MOCVD). The MBE method is a film formation method that grows a thin film with a crystal structure that reflects the crystal system of the substrate, and can be said to be one of the film formation methods that cause less damage to the surface to be formed. The wet method is one of the film formation methods that cause less damage to the surface to be formed. Examples of wet methods include spray coating.

[0218] A third layer can be further formed on the second layer. The third layer can be formed, for example, by the second film formation method.

[0219] After the oxide semiconductor layer is formed, heat treatment is preferably performed.

[0220] In the method for forming an oxide semiconductor layer according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductor layers (the first layer and the third layer) can be increased by using the second layer (i.e., CAAC) having high crystallinity as a nucleus or seed. This can increase the crystallinity of the entire oxide semiconductor layer. In other words, the second layer can be used as a nucleus or seed to cause solid-phase growth of a metal oxide in the upper and lower oxide semiconductor layers, thereby forming an oxide semiconductor layer having high crystallinity. An oxide semiconductor layer formed by such a film formation method, specifically an oxide semiconductor layer having a CAAC structure, can be referred to as an axial growth CAAC (AG CAAC).

[0221] Even if a method that easily forms a metal oxide with high crystallinity is not used as a method for forming the first layer and the third layer, the crystallinity of the first layer and the third layer can be increased by using the method for forming an oxide semiconductor layer of one embodiment of the present invention. In addition, heat treatment has an assisting effect of increasing the crystallinity of the first layer and the third layer.

[0222] An example of a method for manufacturing the oxide semiconductor 30 will be described below with reference to FIGS.

[0223] First, a layer 29 is formed. The layer 29 corresponds to an insulating film or a conductive film included in the semiconductor device. For example, an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film can be used as the layer 29. Alternatively, for example, a conductive film that functions as an electrode of the semiconductor device can be used as the layer 29. The layer 29 does not need to have crystallinity. In other words, the layer 29 may have an amorphous structure. Furthermore, when the layer 29 has crystallinity, the layer 29 may have a crystal structure that has low lattice matching with the metal oxide included in the oxide semiconductor 30.

[0224] Next, an oxide semiconductor 30a is formed on the layer 29 (FIG. 12(A)).

[0225] In a manufacturing method according to one embodiment of the present invention, the oxide semiconductor 30b is formed by a sputtering method as described later. When a metal oxide film is formed by a sputtering method, a mixed layer of a component of the metal oxide to be formed and a component contained in a layer on which the film is to be formed may be formed (also referred to as alloying) by sputtering particles emitted from a target or the like, or by energy applied to a substrate by the sputtering particles or the like. There is a concern that the alloying may inhibit crystallization of an oxide semiconductor layer thereover. In addition, when the alloying occurs, it is difficult to improve the crystallinity of the alloyed region even when a heat treatment to be described later is performed. There is a concern that the use of an oxide semiconductor layer having an alloyed region in a transistor may adversely affect the initial characteristics or reliability of the transistor.

[0226] Therefore, before forming the oxide semiconductor 30b, the oxide semiconductor 30a is formed in advance using a film formation method that causes little damage to the surface on which the oxide semiconductor 30b is to be formed. This suppresses alloying of the components contained in the oxide semiconductor 30 and the components contained in the layer 29, and makes the thickness of the alloyed region thin, or makes the alloyed region thin enough that it cannot be observed. Here, the oxide semiconductor 30a is formed using the ALD method.

[0227] Examples of the ALD method include a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma-excited reactant is used.

[0228] The ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles emitted from a target or the like are deposited. The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. By using the ALD method as a film formation method for the oxide semiconductor 30a and the oxide semiconductor 30c described later, the coverage of the oxide semiconductor layer can be improved. Thus, the oxide semiconductor layer can be well covered on steps, openings, and the like with high aspect ratios.

[0229] In addition, the PEALD method may be preferable because it uses plasma and allows film formation at a lower temperature. Note that some precursors used in the ALD method contain elements such as carbon or chlorine. For this reason, films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods.

[0230] Here, a method for forming an In-M-Zn oxide as the oxide semiconductor 30a by the ALD method will be described.

[0231] First, a source gas containing a precursor having indium is introduced into the chamber, and the precursor is adsorbed onto the surface of layer 29. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than indium while leaving indium adsorbed onto the substrate, thereby forming a layer in which indium and oxygen are combined.

[0232] Next, a source gas containing a precursor having element M is introduced into the chamber and adsorbed onto the layer of indium and oxygen. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than element M while leaving element M adsorbed on the substrate, thereby forming a layer of element M and oxygen.

[0233] Next, a source gas containing a zinc-containing precursor is introduced into the chamber and adsorbed onto the layer of combined element M and oxygen. Next, an oxidizing agent is introduced into the chamber as a reactant and reacted with the adsorbed precursor, thereby desorbing components other than zinc while leaving zinc adsorbed on the substrate, thereby forming a layer of combined zinc and oxygen.

[0234] By repeating the above-described method, an In-M-Zn oxide can be formed as the oxide semiconductor 30a on the layer 29 by the ALD method.

[0235] The substrate is heated to a temperature corresponding to the decomposition temperature of the precursor. In the case of a thermal ALD method using triethylindium as the indium-containing precursor, triethylgallium as the gallium-containing precursor, and diethylzinc as the zinc-containing precursor, the substrate is heated to a temperature of 100° C. or higher and 350° C. or lower, preferably 150° C. or higher and 300° C. or lower.

[0236] In the above, after the precursor is adsorbed, it is preferable to stop the introduction of the precursor-containing source gas, purge the chamber, and then discharge the excess precursor and reaction products, etc. from the chamber. Also, in the above, it is preferable to stop the introduction of the oxidant, purge the chamber, and then discharge the excess reactant and reaction products, etc. from the chamber after the adsorbed precursor is reacted with the oxidant.

[0237] Furthermore, unless otherwise specified in this specification and elsewhere, when ozone, oxygen, or water is used as a reactant or oxidant, these are not limited to being in a gas or molecular state, but also include those in a plasma state, radical state, and ion state.

[0238] When the oxide semiconductor 30a is formed by the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than that of the CAAC structure, may be formed.

[0239] Next, an In-M-Zn oxide is formed as an oxide semiconductor 30b on the oxide semiconductor 30a by a sputtering method (FIG. 12B). The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure.

[0240] When the oxide semiconductor 30b is formed by sputtering, the mixed layer 31 is formed on or near the surface of the oxide semiconductor 30a. In addition, minute crystal regions may be formed in the mixed layer 31 due to sputtering particles or energy given to the substrate by the sputtering particles or the like during the formation of the oxide semiconductor 30b. In a subsequent heat treatment process, the mixed layer 31 or the minute crystal regions formed in the mixed layer 31 may become nuclei, and at least a part of the oxide semiconductor 30a may be crystallized.

[0241] Sputtering methods include RF sputtering, which uses a high-frequency power source as a sputtering power source, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to an electrode in a pulsed manner. DC sputtering can be suitably used when forming a metal conductive film, and can increase productivity due to its high film formation rate. Pulsed DC sputtering can be suitably used when forming a metal conductive film and a semiconductor film. RF sputtering can be suitably used to form an insulating film. Compounds such as oxides, nitrides, and carbides can be formed by reactive sputtering using a reactive gas. The metal oxide used in the oxide semiconductor layer of one embodiment of the present invention can be formed by appropriately selecting from these methods depending on the conductivity of the target of the sputtering method and the like.

[0242] In-M-Zn oxide can be used as a target for the sputtering method. When forming a metal oxide by the sputtering method, oxygen or a mixed gas of oxygen and a noble gas can be used as the sputtering gas. In addition, by increasing the ratio of oxygen contained in the sputtering gas, the amount of excess oxygen in the oxide film to be formed can be increased.

[0243] Furthermore, there are cases where a metal oxide having higher crystallinity can be formed as the ratio of the flow rate of oxygen gas to the total deposition gas used during deposition (hereinafter also referred to as oxygen flow rate ratio) is higher.

[0244] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the ratio of oxygen contained in the sputtering gas is set to more than 30% and not more than 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the ratio of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%, when the metal oxide is formed. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0245] When a metal oxide is formed by a sputtering method, the composition of the formed metal oxide may differ from that of the sputtering target. In particular, the zinc content in the formed metal oxide may decrease to about 50% compared to that of the sputtering target.

[0246] In forming the oxide semiconductor 30b by sputtering, it is preferable to heat the substrate. In forming the metal oxide, a metal oxide with high crystallinity may be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In forming the oxide semiconductor 30b by sputtering, the substrate heating temperature is preferably 100°C or more and 400°C or less, and more preferably 200°C or more and 300°C or less.

[0247] Next, the oxide semiconductor 30c is formed on the oxide semiconductor 30b (FIG. 12C). Here, the oxide semiconductor 30c is formed by the ALD method. The formation of the oxide semiconductor 30c by the ALD method can be performed by referring to the formation method of the oxide semiconductor 30a.

[0248] When an oxide semiconductor 30c having a lower crystallinity than the CAAC structure is formed on an oxide semiconductor 30b having a CAAC structure by using an ALD method, the oxide semiconductor 30c may grow epitaxially around the oxide semiconductor 30b as a nucleus. Thus, when the oxide semiconductor 30c is formed, the oxide semiconductor 30c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 30c.

[0249] The oxide semiconductor 30c can be used, for example, as a layer in contact with a gate insulating layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating layer, carrier mobility can be increased when the transistor is in an on-state.

[0250] Furthermore, by forming the oxide semiconductor 30c using the ALD method, damage to the oxide semiconductor 30b is reduced, and the oxide semiconductor 30 as a whole can have high crystallinity.

[0251] By using the ALD method, which has high coverage, as a method for forming the oxide semiconductor 30a and the oxide semiconductor 30c, the oxide semiconductor layer as a whole can have high coverage. In addition, the oxide semiconductor 30b, which has high crystallinity, is formed by using a sputtering method, and the crystallinity of the upper and lower oxide semiconductor layers (the oxide semiconductor 30a and the oxide semiconductor 30c) is also increased by epitaxial growth from the oxide semiconductor 30b, so that the crystallinity of the oxide semiconductor 30 can be increased throughout the entire layer. Thus, the oxide semiconductor 30 can have both high coverage and high crystallinity.

[0252] A heat treatment step may then be performed.

[0253] The temperature of the heat treatment may be, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. The temperature may be typically 400° C.±25° C. (375° C. to 425° C.). The treatment time may be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When a rapid thermal annealing (RTA) device is used, the treatment time may be, for example, 1 second to 5 minutes. It is expected that the heat treatment will repair the gaps in the crystal parts at the atomic level of the CAAC structure of the oxide semiconductor 30b by the oxide semiconductor 30c.

[0254] There is no particular limitation on the heating device used for the heat treatment, and it may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. The LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high-temperature gas.

[0255] The heat treatment step may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor 30c. If the region is formed only below the oxide semiconductor 30c after the ALD process, the heat treatment step may cause the region to expand upward (FIG. 12D). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 30c.

[0256] In addition, the heat treatment process may further repair the oxide semiconductor 30b by the oxide semiconductor 30c (in other words, the crystal molecules formed by the ALD method) that fills gaps in the atomic-level crystal parts of the CAAC structure of the oxide semiconductor 30b.

[0257] It is also preferable that at least a part of the oxide semiconductor 30a is converted into a CAAC by the heat treatment process (FIG. 12(D)). It is expected that the CAAC is easily generated because the mixed layer 31 formed in the oxide semiconductor 30a during the deposition of the oxide semiconductor 30b serves as a nucleus or seed. It is preferable that the region in the oxide semiconductor 30a that is converted into a CAAC is large, and it is preferable that the CAAC is converted into the vicinity of the layer 29.

[0258] Furthermore, because the CAAC process occurs from the top to the bottom of the oxide semiconductor 30a, the CAAC process can be performed up to the vicinity of the layer 29 regardless of the material or crystallinity of the layer 29. For example, even when the layer 29 has an amorphous structure, the oxide semiconductor 30a can have high crystallinity. Thus, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is to be formed has an amorphous structure.

[0259] After the oxide semiconductor 30c is formed, a microwave treatment may be performed.

[0260] Here, the microwave treatment refers to a treatment using a device having a power source that generates high-density plasma using microwaves. In this specification, microwave refers to an electromagnetic wave having a frequency of 300 MHz or more and 300 GHz or less. Microwave treatment can also be called microwave-excited high-density plasma treatment.

[0261] It is preferable to reduce the impurity concentration in the oxide semiconductor 30 by performing the microwave treatment in an atmosphere containing oxygen. Examples of impurities include hydrogen and carbon. Note that, although the above example illustrates a configuration in which the microwave treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, the microwave treatment may be performed on an insulating film, more specifically, a silicon oxide film, located near the metal oxide in an atmosphere containing oxygen. In addition, the crystallinity of the oxide semiconductor layer may be increased by the heat of the microwave treatment.

[0262] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably from 10 Pa to 1000 Pa, and more preferably from 300 Pa to 700 Pa. The microwave treatment is preferably carried out in a heated state. The substrate temperature can be from room temperature (e.g., 25°C) to 750°C, preferably from 100°C to 500°C, more preferably from 200°C to 500°C, even more preferably from 300°C to 500°C, and even more preferably from 400°C to 500°C. For example, it can be from 400°C to 450°C.

[0263] Alternatively, after the microwave treatment, a heat treatment may be performed continuously without exposure to the outside air. The temperature of the heat treatment is, for example, preferably 100° C. to 750° C., more preferably 300° C. to 500° C., and further preferably 400° C. to 450° C.

[0264] The microwave treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave treatment in an atmosphere containing oxygen, the oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the oxide semiconductor layer. The action of the plasma, microwaves, or the like can form defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (hereinafter, referred to as V O In this way, the V in the oxide semiconductor layer is separated into oxygen vacancies and hydrogen, and the hydrogen impurities can be removed from the oxide semiconductor layer. OH can be reduced. At this time, carbon bonded to oxygen, hydrogen, or the like can also be removed in some cases. In this manner, impurities such as carbon or hydrogen can be reduced by performing microwave treatment. In addition, oxygen radicals generated by the oxygen plasma can be supplied to oxygen vacancies formed in the oxide semiconductor layer, whereby oxygen vacancies in the oxide semiconductor layer can be further reduced.

[0265] Oxygen to be injected into the oxide semiconductor layer may take various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (atoms, molecules, or ions having an unpaired electron, also referred to as O radicals). Note that oxygen to be injected into the oxide semiconductor layer may take one or more of the above forms, and is particularly preferably an oxygen radical.

[0266] In the above manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state in which the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0267] Note that one or both of the above heat treatment and microwave treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0268] In addition, an oxide semiconductor layer having a CAAC structure formed using the above-mentioned two types of film formation methods may have one or more of a higher dielectric constant, a higher film density, and a higher film hardness than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0269] By using an oxide semiconductor layer having a CAAC structure formed by using the above-described two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a transistor with high reliability, etc.) can be realized.

[0270] In the oxide semiconductor 30, it is preferable that the region having the CAAC structure is widely present throughout the entire layer including the oxide semiconductor 30a and the oxide semiconductor 30c. FIG. 13A shows the crystallization of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c. The crystals in the region having the CAAC structure in the oxide semiconductor 30a are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. The crystals in the region having the CAAC structure in the oxide semiconductor 30c are connected to the crystals in the region having the CAAC structure in the oxide semiconductor 30b. The oxide semiconductor 30 may be expressed as a single layer with no clearly observed interface. The oxide semiconductor 30 may be expressed as a single layer.

[0271] The regions having the CAAC structure in the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c can be observed as bright spots arranged parallel to the surface on which the oxide semiconductor layer is formed, for example, in cross-sectional observation using a high-resolution TEM. The c-axes of the CAAC structures in the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c are preferably approximately parallel to the normal direction of the surface on which the oxide semiconductor layer is formed.

[0272] Also, there are cases where a part of the oxide semiconductor 30a or the oxide semiconductor 30c is not crystallized. The example shown in Fig. 13(B) shows a state where the vicinity of the interface with the layer 29 in the oxide semiconductor 30a is not crystallized. Fig. 13(C) shows a state where the vicinity of the surface in the oxide semiconductor 30c is not crystallized. Fig. 13(D) shows a state where the vicinity of the interface with the layer 29 of the oxide semiconductor 30a and the vicinity of the surface of the oxide semiconductor 30c are not crystallized.

[0273] The oxide semiconductor layer of one embodiment of the present invention has high crystallinity throughout the layer. Therefore, in the oxide semiconductor 30, the boundaries between the stacked films of the oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c may not be visible. In particular, it may be difficult to confirm the boundaries between the stacked films after heat treatment. The presence or absence of the boundaries between the stacked films can be confirmed by, for example, cross-sectional TEM, cross-sectional STEM, or the like.

[0274] In addition, it is preferable that the degree of lattice mismatch between the crystals of the oxide semiconductor 30b and the crystals of the oxide semiconductor 30a or the oxide semiconductor 30c is small. This allows the oxide semiconductor 30a or the oxide semiconductor 30c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 30b. In this case, for example, in a cross-sectional observation of the oxide semiconductor 30 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are confirmed in the oxide semiconductor 30a or the oxide semiconductor 30c.

[0275] As long as the degree of lattice mismatch between the crystals of the oxide semiconductor 30b and the crystals of the oxide semiconductor 30a or the oxide semiconductor 30c is small, the crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c is not particularly limited. The crystal structure of the oxide semiconductor 30a or the oxide semiconductor 30c may be any of a cubic system, a tetragonal system, an orthorhombic system, a hexagonal system, a monoclinic system, and a trigonal system.

[0276] In addition, when one or both of a microwave treatment and a heat treatment are performed in the step of forming the oxide semiconductor 30, it may not be necessary to form the oxide semiconductor 30b. For example, as described above, by performing one or both of a microwave treatment and a heat treatment after forming the oxide semiconductor 30a, the crystallinity of the oxide semiconductor 30a can be improved, and the crystallinity of the oxide semiconductor 30c can be increased by using the oxide semiconductor 30a as a nucleus or seed. In addition, by performing one or both of a microwave treatment and a heat treatment after forming the oxide semiconductor 30c, the crystallinity of the oxide semiconductor 30 can be improved. Therefore, a CAAC structure can be formed in the oxide semiconductor 30.

[0277] Also, for example, a metal oxide layer can be provided between layer 29 and oxide semiconductor 30 .

[0278] The metal oxide layer is preferably made of a metal oxide material applicable to the oxide semiconductor 30. The metal oxide layer preferably contains, for example, one or both of gallium and zinc. For example, gallium oxide, zinc oxide, indium gallium oxide, gallium zinc oxide, aluminum zinc oxide, indium gallium zinc oxide, or the like can be used in a single layer or a stacked layer. When indium gallium zinc oxide is used, specifically, a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition therearound, or In:M:Zn=1:3:4 [atomic ratio] or a composition therearound may be used.

[0279] The metal oxide layer can be thinner than the oxide semiconductor 30, and may have a thickness of, for example, 0.1 nm to 1 nm, or 0.1 nm to 0.5 nm.

[0280] When the metal oxide layer contains gallium, it is possible to suppress the diffusion of oxygen contained in the oxide semiconductor 30 into the layer 29 and the like, and to suppress the formation of oxygen vacancies in the oxide semiconductor 30. When the metal oxide layer contains zinc, the crystallinity of the metal oxide layer is increased, and the crystallinity of the oxide semiconductor 30 provided on the metal oxide layer can be improved. When the metal oxide layer is disposed between the layer 29 and the oxide semiconductor 30, it is possible to suppress the diffusion of impurity components such as hydrogen contained in the layer 29 into the oxide semiconductor 30.

[0281] As described above, even in the configuration without the oxide semiconductor 30b, the oxide semiconductor above can be grown in a solid phase using the oxide semiconductor 30a or the metal oxide layer of the layer 29 as a nucleus or seed to form an oxide semiconductor with high crystallinity. The oxide semiconductor formed using such a film formation method can also be called an AG CAAC. That is, the AG CAAC can be formed without using the first film formation method (e.g., sputtering method, PLD method, etc.). In other words, the AG CAAC can also be formed using the above-mentioned second film formation method (e.g., ALD method, CVD method, etc.) and one or both of a microwave treatment and a heat treatment.

[0282] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0283] When the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor 30 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, further preferably 20 nm to 50 nm. In addition, in a transistor used in a finer semiconductor device, the film thickness of the oxide semiconductor 30 is preferably 1 nm to 20 nm, more preferably 3 nm to 15 nm, and further preferably 5 nm to 12 nm.

[0284] The oxide semiconductor 30b is preferably, for example, 200 nm or less. When the oxide semiconductor 30b has a layered structure, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0285] Alternatively, if the oxide semiconductor 30b can function as a crystal nucleus, the oxide semiconductor 30b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 30b exist discretely.

[0286] The oxide semiconductor 30a and the oxide semiconductor 30c each have a thickness of, for example, 1 nm to 50 nm, preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm.

[0287] The thickness of the region where the component contained in the oxide semiconductor 30 and the component contained in the layer 29 are alloyed is 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that Figures 12(A) and 12(B) show an example in which no alloy region is formed between the layer 29 and the oxide semiconductor 30a.

[0288] In addition, the thickness of the alloyed region may be calculated by performing a line analysis of the composition of the region and its surroundings using secondary ion mass spectrometry (SIMS) or energy dispersive X-ray spectroscopy (EDX).

[0289] For example, the EDX line analysis is performed on the above region and its periphery with the direction perpendicular to the surface of the oxide semiconductor 30a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by the analysis, the depth at which the quantitative value of a metal (In when the oxide semiconductor 30a contains In) that is the main component of the oxide semiconductor 30a and is not the main component of the layer that becomes the surface to be formed (here, layer 29) becomes half-value is defined as the depth (position) of the interface between the above region and the oxide semiconductor 30a. Also, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that becomes the surface to be formed and is not the main component of the oxide semiconductor 30a becomes half-value is defined as the depth (position) of the interface between the above region and the layer that becomes the surface to be formed. From the above, the thickness of the alloyed region can be calculated.

[0290] For example, when a silicon oxide layer is used as the layer 29 and an oxide semiconductor 30 formed on the layer 29 is subjected to SIMS analysis, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 29 is defined as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0 x 10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth at which the thickness decreases to the interface and the depth is defined as thickness t_s. The thickness t_s is preferably 3 nm or less, and more preferably 2 nm or less.

[0291] By reducing the alloyed region, the CAAC structure can be formed near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region from more than 0 nm to 3 nm or less, preferably more than 0 nm to 2 nm or less, more preferably 1 nm to 2 nm or less, approximately perpendicularly from the formation surface of the oxide semiconductor 30.

[0292] The oxide semiconductor 30a has a region located, for example, at a distance of 0 nm to 3 nm from the upper surface of the layer 29. The oxide semiconductor 30c is located, for example, at a distance of 0 nm to 3 nm from the upper surface of the oxide semiconductor 30. The oxide semiconductors 30a, 30b, and 30c have, for example, approximately the same thickness. Alternatively, the oxide semiconductors 30a, 30b, and 30c may have different thicknesses.

[0293] [c-axis orientation rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using crystal orientation, for example.

[0294] The CAAC structure of an oxide semiconductor layer can be evaluated from a map showing crystal orientation in some cases. In a region having the CAAC structure, for example, the crystals are observed to be c-axis oriented.

[0295] A map showing the crystal orientation can be obtained, for example, by acquiring a cross-sectional TEM image, performing a fast Fourier transform (FFT) process for each region in the cross-sectional TEM image to create an FFT pattern, and calculating the direction of the crystal axis of each region. Specifically, for example, two spots with high intensity are observed in the FFT pattern of a region having layered crystal parts. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots. The FFT pattern reflects reciprocal lattice space information similar to that of an electron beam diffraction pattern.

[0296] In a map showing the crystal orientation, the c-axis orientation rate can be calculated by calculating the ratio of the area oriented along the c-axis.

[0297] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0298] In addition, when performing analysis using a cross-sectional TEM image, the observation range of the cross-sectional TEM image may be, for example, a region having a width of 100 nm in the horizontal direction, with the direction perpendicular to the surface to be formed being the vertical direction. However, the observation range is not limited to this.

[0299] In the oxide semiconductor layer of one embodiment of the present invention, when the c-axis orientation rate is calculated as the percentage of regions whose orientation differs from the c-axis by 20° or less, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0300] The c-axis orientation rates of the region where the oxide semiconductor 30a is formed, the region where the oxide semiconductor 30b is formed, and the region where the oxide semiconductor 30c is formed are Rc1, Rc2, and Rc3, respectively. Here, the c-axis orientation rate is calculated as the percentage of the region where the difference from the c-axis is within 20°, for example. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1.

[0301] [Composition of oxide semiconductor layer] The oxide semiconductor 30a preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30c preferably has a different composition from the oxide semiconductor 30b. The oxide semiconductor 30a may have the same composition as the oxide semiconductor 30c. Alternatively, the oxide semiconductor 30a and the oxide semiconductor 30c may have different compositions.

[0302] The oxide semiconductor 30b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 30b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor 30b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 30b preferably contains, in addition to zinc, the element M. By containing the element M in the oxide semiconductor 30b, for example, it is possible to suppress the formation of oxygen vacancies in the metal oxide. Specifically, the oxide semiconductor 30b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, or In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. In addition, it is preferable to use one or more of gallium, tin, yttrium, and aluminum as the element M.

[0303] The oxide semiconductor 30b may be configured not to include the element M. For example, it may be an In-Zn oxide. Specifically, it may be configured to have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, an indium oxide may be used. It may also be configured to include a trace amount of the element M. For example, it may be configured to have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof. Also, it may be configured to have a composition of In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0304] The oxide semiconductor 30a and the oxide semiconductor 30c can be a metal oxide having a high ratio of In. It is particularly preferable that the oxide semiconductor 30a and the oxide semiconductor 30c are a metal oxide having a high ratio of In compared to the oxide semiconductor 30b. For example, the ALD method can be used to form the oxide semiconductor 30a and the oxide semiconductor 30c. It is particularly preferable to use a metal oxide having a higher ratio of In than the element M. By using a metal oxide having a high ratio of In, it is possible to increase the on-current and improve the frequency characteristics when the oxide semiconductor layer is applied to a transistor.

[0305] An oxide semiconductor with a high In content tends to be polycrystallized. Use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. In the oxide semiconductor layer of one embodiment of the present invention, the crystal orientation of the oxide semiconductor 30b can be reflected in the oxide semiconductor 30a and the oxide semiconductor 30c with a high In content. Thus, even when a metal oxide with a high In content is used for the oxide semiconductor 30a and the oxide semiconductor 30c, polycrystallization can be suppressed.

[0306] Alternatively, the oxide semiconductor 30a and the oxide semiconductor 30c may be configured to not include the element M. For example, they may be In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 [atomic ratio] or a composition in the vicinity thereof, In:Zn=2:1 [atomic ratio] or a composition in the vicinity thereof, or In:Zn=4:1 [atomic ratio] or a composition in the vicinity thereof. Alternatively, indium oxide may be used. Also, the oxide semiconductor 30a and the oxide semiconductor 30c may be configured to include a trace amount of the element M. Specifically, they may have a composition of In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof, In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition in the vicinity thereof, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition in the vicinity thereof.

[0307] Metal oxides having a high Ga ratio can also be used as the oxide semiconductors 30a and 30c. For example, metal oxides having a high Ga ratio compared to the oxide semiconductor 30b can be used as the oxide semiconductors 30a and 30c. For example, it is preferable to use metal oxides having a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a composition close thereto, metal oxides having a composition of In:Ga:Zn=1:3:2 [atomic ratio] or a composition close thereto, or metal oxides having a composition of In:Ga:Zn=1:3:4 [atomic ratio] or a composition close thereto, for the oxide semiconductors 30a and 30c, respectively. Increasing the ratio of Ga may allow the band gaps of the oxide semiconductors 30a and 30c to be larger than that of the oxide semiconductor 30b. As a result, the oxide semiconductor 30b is sandwiched between the oxide semiconductors 30a and 30c having a large band gap, and the oxide semiconductor 30b can function mainly as a current path (channel). In addition, the trap levels at the interface of the oxide semiconductor 30b and its vicinity can be reduced. This makes it possible to realize a buried channel type transistor in which the channel is far from the insulating layer interface, thereby increasing the field effect mobility. In addition, the influence of the interface state that may be formed on the back channel side is reduced, and light degradation of the transistor (e.g., negative bias light degradation) can be suppressed, thereby improving the reliability of the transistor.

[0308] Alternatively, one of the oxide semiconductors 30a and 30c may be a metal oxide having a higher proportion of In than the oxide semiconductor 30b, and the other may be a metal oxide having a higher proportion of Ga than the oxide semiconductor 30b.

[0309] The oxide semiconductor 30a, the oxide semiconductor 30b, and the oxide semiconductor 30c may each have a plurality of layers having the above-described compositions stacked together. For example, the oxide semiconductor 30c may have a structure in which a metal oxide having a high proportion of Ga is stacked on a metal oxide having a high proportion of In.

[0310] The oxide semiconductor 30a and the oxide semiconductor 30c may be made of a metal oxide having the same composition as the oxide semiconductor 30b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0311] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 30a and 30c are formed using compositions that make it difficult to form a CAAC structure when they are formed into a single layer, crystal growth occurs with the oxide semiconductor 30b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 30a and 30c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductors 30a and 30c and the oxide semiconductor 30b.

[0312] The composition of the metal oxide used in the oxide semiconductor 30 can be analyzed by, for example, EDX, X-ray photoelectron spectroscopy (XPS), inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0313] [Impurities in oxide semiconductors] Here, the influence of each impurity in an oxide semiconductor will be described. The impurities contained in an oxide semiconductor can be quantified by XPS, SIMS, EDX, ICP-MS, ICP-AES, or the like.

[0314] It is preferable that the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions. O ) and impurities may cause electrical characteristics to fluctuate and reliability to deteriorate. In addition, hydrogen near the oxygen vacancy may cause V O H, which may generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, in the channel formation region, V O It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0315] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the concentration of impurities in the oxide semiconductor. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurities in an oxide semiconductor refer to, for example, elements other than the main components constituting the oxide semiconductor. For example, an element with a concentration of less than 1 atomic % or less than 0.1 atomic % may be referred to as an impurity.

[0316] When an oxide semiconductor contains silicon or carbon, which is one of the group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm3 Less than 1×10, more preferably 18 atoms / cm 3 The silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 3×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 3×10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 The following applies.

[0317] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of an oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than or equal to 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 Less than or equal to 5×10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 The following applies.

[0318] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to metal atoms to form water, which may form oxygen vacancies. When hydrogen enters the oxygen vacancies, electrons serving as carriers may be generated. Some of the hydrogen may bond with oxygen bonded to metal atoms to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 less than 1×10 17 atoms / cm 3 Less than.

[0319] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0320] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0321] The average thickness of the oxide semiconductor 30 in the channel formation region is preferably 30 nm or less, more preferably 15 nm or less, and further preferably 10 nm or less.

[0322] The oxide semiconductor 30a is an oxide semiconductor layer formed on a surface to be formed. The thickness of the oxide semiconductor 30a is preferably 0.5 nm or more and 3 nm or less.

[0323] In addition, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide semiconductor 230 is observed, metal atoms of the metal oxide are arranged in a layered manner in a region having a CAAC structure in some cases. In this case, for example, the metal atoms are arranged perpendicular or approximately perpendicular to the substrate surface.

[0324] The metal atoms arranged in a layered manner in the region having the CAAC structure can be observed as an arrangement of bright spots in a cross section of the oxide semiconductor layer observed using a TEM image. Thus, in the semiconductor device of one embodiment of the present invention, when a cross section of the oxide semiconductor 230 is observed, it may be possible to confirm that the bright spots are arranged in a direction perpendicular or approximately perpendicular to the substrate surface.

[0325] The oxide semiconductor 30 which is an AG CAAC can be used for the oxide semiconductor 230 of the transistor 200. FIG. 2A shows an enlarged view of the vicinity of the oxide semiconductor 230 in FIG. 1B when the oxide semiconductor 230 includes an oxide semiconductor 230a, an oxide semiconductor 230b in contact with the oxide semiconductor 230a, and an oxide semiconductor 230c in contact with the oxide semiconductor 230b. Here, the oxide semiconductor 230a corresponds to the oxide semiconductor 30a, the oxide semiconductor 230b corresponds to the oxide semiconductor 30b, and the oxide semiconductor 230c corresponds to the oxide semiconductor 30c. FIG. 2B shows an enlarged view of the vicinity of the oxide semiconductor 230 in FIG. 1C when the oxide semiconductor 230 includes the oxide semiconductor 230a, the oxide semiconductor 230b in contact with the oxide semiconductor 230a, and the oxide semiconductor 230c in contact with the oxide semiconductor 230b.

[0326] Here, the pillar (the insulator 223 described later) corresponds to the layer 29. That is, the surface on which the oxide semiconductor 230 is formed is the pillar, and the pillar is removed in the transistor 200. During the manufacturing process, one side surface of the oxide semiconductor 230a is in contact with the pillar, and the other side surface of the oxide semiconductor 230b is in contact with the oxide semiconductor 230b. After the pillar is removed, one side surface of the oxide semiconductor 230a is in contact with the insulator 250. One side surface of the oxide semiconductor 230b is in contact with the oxide semiconductor 230a, and the other side surface of the oxide semiconductor 230c. One side surface of the oxide semiconductor 230c is in contact with the oxide semiconductor 230b, and the other side surface of the oxide semiconductor 230c is in contact with the insulator 250. Here, since the side surfaces of the pillars are formed perpendicular or approximately perpendicular to the substrate surface (which can also be referred to as the surface of the insulator 222), the side surfaces of the oxide semiconductors 230 (the oxide semiconductors 230a to 230c) are also perpendicular or approximately perpendicular to the substrate surface.

[0327] As described above, in the cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using the TEM image, it is confirmed that the metal atoms are arranged in layers in a direction parallel or approximately parallel to the surface on which they are formed. In other words, in the cross section of the oxide semiconductor 230 (the oxide semiconductors 230a to 230c) observed using the TEM image, it is confirmed that the metal atoms are arranged in layers in a direction perpendicular or approximately perpendicular to the substrate surface. It can also be said that the c-axis of AG CAAC is approximately parallel to the normal direction to the side surface of the oxide semiconductor 230.

[0328] In this manner, by using the oxide semiconductor 230, which is AG CAAC, for the channel formation region of the transistor 200, a transistor with favorable on-state current, field-effect mobility, S value, frequency characteristics, and reliability can be provided.

[0329] When the oxide semiconductor 230 has a three-layer structure including the oxide semiconductors 230a to 230c as described above, the oxide semiconductor 230 is formed in this order of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c around the region where the pillars were formed. Thus, as shown in FIG. 4A, in a cross section in the channel width direction, the oxide semiconductor 230c, the oxide semiconductor 230b, the oxide semiconductor 230a, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are arranged symmetrically in this order. That is, in order to make the oxide semiconductor 230 have a bilaterally symmetric structure in a cross section, it is preferable that the oxide semiconductor 230a and the oxide semiconductor 230c have approximately the same composition. It is also preferable that the oxide semiconductor 230a and the oxide semiconductor 230c have approximately the same thickness. 2A is equal to or greater than 80° and less than 90°, that is, when the side surface of the oxide semiconductor 230 is slightly inclined, the inclination of the oxide semiconductor 230 is arranged symmetrically as shown in Fig. 4B. When the oxide semiconductor 230 is formed with an inclination, the upper part of the oxide semiconductor 230 may become thinner than the lower part of the oxide semiconductor 230 as shown in Fig. 4B.

[0330] The insulator 250 in contact with the channel formation region in the oxide semiconductor 230 preferably has a function of capturing hydrogen or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. O By reducing H, the channel formation region can be made i-type or substantially i-type.

[0331] 3A, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide semiconductor 230, an insulator 250b on the insulator 250a, an insulator 250c on the insulator 250b, and an insulator 250d on the insulator 250c. In this case, the insulator 250a and the insulator 250c preferably have a function of capturing hydrogen or fixing hydrogen.

[0332] An example of an insulator having the function of capturing or fixing hydrogen is a metal oxide having an amorphous structure. For example, it is preferable to use a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium as the insulator 250a and the insulator 250c. In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. In other words, it can be said that a metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.

[0333] It is also preferable to use a high dielectric constant (high-k) material for the insulator 250a and the insulator 250c. An example of a high-k material is an oxide containing one or both of aluminum and hafnium. By using a high-k material for the insulator 250a and the insulator 250c, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0334] For the insulator 250a and the insulator 250c, it is preferable to use an oxide containing one or both of aluminum and hafnium, and it is more preferable to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium.

[0335] In this embodiment, an aluminum oxide film is used as the insulator 250a. The aluminum oxide film preferably has an amorphous structure. By providing the insulator 250a in contact with the oxide semiconductor 230, hydrogen contained in the oxide semiconductor 230 and the like can be more effectively captured and fixed.

[0336] In the present embodiment, hafnium oxide is used as the insulator 250c. Here, by providing the insulator 250c between the insulators 250b and 250d, hydrogen contained in the insulators 250b and the like can be more effectively captured and fixed.

[0337] Next, it is preferable that the insulator 250b is a thermally stable insulator such as silicon oxide or silicon oxynitride. In this specification and the like, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, when silicon oxynitride is described, it refers to a material whose composition contains more oxygen than nitrogen, and when silicon nitride oxide is described, it refers to a material whose composition contains more nitrogen than oxygen.

[0338] The silicon oxide film used as the insulator 250b is preferably formed using the PEALD method.

[0339] In order to suppress oxidation of the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to provide a barrier insulator against oxygen near each of the conductor 242a, the conductor 242b, and the conductor 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulator 250a, the insulator 250d, the insulator 250c, and the insulator 275.

[0340] In this specification, a barrier insulator refers to an insulator having barrier properties. In this specification, having barrier properties refers to having a property of preventing the permeation of a corresponding substance (also referred to as low permeability). For example, an insulator with barrier properties has a property that makes it difficult for a corresponding substance to diffuse into the insulator. In addition, for example, an insulator with barrier properties has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0341] Examples of the barrier insulator against oxygen include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, silicon nitride, and silicon oxynitride. Examples of the oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, 250d, and 275 are preferably each a single-layer structure or a multilayer structure of the barrier insulator against oxygen.

[0342] The insulator 250a preferably has a barrier property against oxygen. The insulator 250a is preferably less permeable to oxygen than at least the insulator 280. The insulator 250a has a region in contact with the side surface of the conductor 242a and the side surface of the conductor 242b. The insulator 250a having a barrier property against oxygen can suppress the side surfaces of the conductor 242a and the conductor 242b from being oxidized and the formation of an oxide film on the side surface. This can suppress a decrease in the on-current or a decrease in the field-effect mobility of the transistor 200.

[0343] The insulator 250a is provided in contact with the top surface and side surfaces of the oxide semiconductor 230 and the top surface of the insulator 222. The insulator 250a has a barrier property against oxygen, which can suppress desorption of oxygen from a channel formation region of the oxide semiconductor 230 during heat treatment or the like. Thus, oxygen vacancies can be reduced in the oxide semiconductor 230.

[0344] Furthermore, the insulator 250a can prevent an excessive amount of oxygen from being supplied from the insulator 280 to the oxide semiconductor 230, and can supply an appropriate amount of oxygen to the oxide semiconductor 230. Thus, a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 200 caused by excessive oxidation of the source and drain regions can be suppressed.

[0345] An oxide containing one or both of aluminum and hafnium has a barrier property against oxygen, and therefore can be suitably used as the insulator 250a.

[0346] The insulator 250d also preferably has a barrier property against oxygen. The insulator 250d is provided between the channel formation region of the oxide semiconductor 230 and the conductor 260, and between the insulator 280 and the conductor 260. With this structure, oxygen contained in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing to the conductor 260 and forming oxygen vacancies in the channel formation region of the oxide semiconductor 230. In addition, oxygen contained in the oxide semiconductor 230 and oxygen contained in the insulator 280 can be prevented from diffusing to the conductor 260 and from oxidizing the conductor 260. The insulator 250d is preferably at least less permeable to oxygen than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250d. In this case, the insulator 250d is an insulator containing at least nitrogen and silicon.

[0347] The insulator 250d preferably has a barrier property against hydrogen, which can prevent impurities such as hydrogen contained in the conductor 260 from diffusing into the oxide semiconductor 230.

[0348] The insulator 275 also preferably has a barrier property against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242a and between the insulator 280 and the conductor 242b. The insulator 275 is provided in contact with a side surface of the conductor 242, a side surface of the oxide semiconductor 230, and an upper surface of the insulator 222. This configuration can suppress the oxygen contained in the insulator 280 from diffusing into the conductor 242. Therefore, it is possible to suppress an increase in resistivity due to oxidation of the conductor 242 caused by the oxygen contained in the insulator 280. The insulator 275 is preferably at least less permeable to oxygen than the insulator 280. For example, silicon nitride is preferably used as the insulator 275. In this case, the insulator 275 is an insulator having at least nitrogen and silicon.

[0349] A barrier insulator against hydrogen is preferably provided near each of the source and drain regions in order to suppress a decrease in the hydrogen concentrations in the source and drain regions in the oxide semiconductor 230. In the semiconductor device described in this embodiment, the barrier insulator against hydrogen is, for example, the insulator 275.

[0350] Examples of the barrier insulator against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer structure or a multilayer structure of the above-mentioned barrier insulator against hydrogen.

[0351] By providing the insulator 275 as described above, it is possible to reduce the diffusion of hydrogen in the source and drain regions to the outside, and therefore it is possible to suppress the reduction in the hydrogen concentration in the source and drain regions. Therefore, it is possible to make the source and drain regions n-type.

[0352] With the above structure, the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, so that a semiconductor device having good electrical characteristics can be provided. Furthermore, with the above structure, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, miniaturizing the transistor 200 can improve high-frequency characteristics. Specifically, the cutoff frequency can be improved.

[0353] The insulators 250a to 250d function as part of the gate insulator. The insulators 250a to 250d are provided in an opening formed in the insulator 280 together with the conductor 260. In order to miniaturize the transistor 200, it is preferable that the thicknesses of the insulators 250a to 250d are each thin. The thicknesses of the insulators 250a to 250d are each preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and further preferably 1.0 nm to 3.0 nm. Note that it is sufficient that the insulators 250a to 250d each have a region having the above-mentioned thickness at least in a part thereof.

[0354] Moreover, the thickness of the silicon oxide film used as the insulator 250b is preferably 0.7 nm or more and 3 nm or less.

[0355] In order to make the thickness of the insulators 250a to 250d as thin as described above, it is preferable to form the insulators 250a to 250d by using an atomic layer deposition (ALD) method. Also, in order to provide the insulators 250a to 250d in openings such as the insulator 280, it is preferable to form the insulators 250a to 250d by using an ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant are reacted only by thermal energy, and a plasma enhanced ALD method in which a plasma excited reactant is used. In the PEALD method, the use of plasma allows film formation at a lower temperature, which may be preferable.

[0356] The ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed, films can be formed on structures with high aspect ratios, films can be formed with fewer defects such as pinholes, films can be formed with excellent coverage, films can be formed at low temperatures, etc. Therefore, the insulator 250 can be formed with good coverage on the side surfaces of the openings formed in the insulator 280 and the side ends of the conductors 242a and 242b, and with the above-mentioned thin film thickness.

[0357] Some precursors used in the ALD method contain carbon and the like. Therefore, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. The amount of impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0358] Although the insulator 250 has been described above as having a four-layer structure of the insulators 250a to 250d, the present invention is not limited to this. The insulator 250 can have at least one of the insulators 250a to 250d. By configuring the insulator 250 as one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0359] For example, as shown in Fig. 3(B), the insulator 250 may have a three-layer structure. In this case, it is preferable that the insulator 250 has a layered structure of an insulator 250a, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In other words, this is a structure in which the insulator 250d is removed from the structure shown in Fig. 3(A).

[0360] In forming the insulator 250, it is preferable to use the ALD process two or more times. For example, the insulator 250 preferably has a laminated structure of a plurality of insulating films, and two or more of the insulating films are preferably formed using the ALD process. By forming at least two or more insulating films by the ALD process, it is possible to improve the coverage and uniformity of the film thickness of the insulator 250. In addition, it is possible to increase productivity by continuously forming two or more different films, for example, two or more insulating films, using the ALD process.

[0361] In addition to the above structure, it is preferable to have a structure that suppresses hydrogen from being mixed into the transistor 200 and the like. For example, it is preferable to provide an insulator having a function of suppressing diffusion of hydrogen so as to cover one or both of the top and bottom of the transistor 200 and the like. In the semiconductor device described in this embodiment, the insulator is, for example, the insulator 283, the insulator 282, the insulator 222, the insulator 221, or the like. Furthermore, the insulator 215 provided under the transistor 200 may have a structure similar to either one or both of the insulators 282 and 283. In this case, the insulator 215 may have a stacked structure of the insulators 282 and 283, or may have a structure in which the insulator 282 is on the bottom and the insulator 283 is on the top, or may have a structure in which the insulator 282 is on the top and the insulator 283 is on the bottom.

[0362] It is preferable that one or more of the insulators 283, 282, 222, and 221 function as a barrier insulator that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, it is preferable that one or more of the insulators 283, 282, 222, and 221 have an insulating material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), and copper atoms (through which the above impurities are difficult to permeate). Alternatively, it is preferable that the insulators have an insulating material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (through which the above oxygen is difficult to permeate).

[0363] The insulators 283, 282, 222, and 221 each preferably have an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen, and may be, for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, silicon nitride, or silicon nitride oxide. For example, the insulators 283 and 221 are preferably made of silicon nitride or the like, which has a higher hydrogen barrier property. For example, the insulator 282 is preferably made of aluminum oxide or the like, which has a high ability to capture or fix hydrogen. For example, the insulator 222 is preferably made of hafnium oxide or the like, which is a high dielectric constant (high-k) material, and has a high ability to capture or fix hydrogen.

[0364] At least one of the insulators 221 and 222 can have a stacked structure of silicon oxide or silicon oxynitride in addition to the above-mentioned materials. For example, the insulator 221 can have a stacked structure of silicon nitride and silicon oxide. For example, the insulator 222 can have a stacked structure of hafnium oxide and silicon oxide.

[0365] With such a structure, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged above the insulator 283 to the transistor 200 and the like. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from an interlayer insulating film arranged below the insulator 221 to the transistor 200 and the like. Furthermore, hydrogen contained in the insulator 280, the insulator 250, and the like can be captured and fixed to the insulator 282 or the insulator 222. Furthermore, by providing the insulators 282 and 283, oxygen contained in the insulator 280 and the like can be prevented from diffusing upward from the transistor 200 and the like. Furthermore, by providing the insulators 222 and 221, oxygen contained in the oxide semiconductor 230 and the like can be prevented from diffusing downward from the transistor 200 and the like. In this way, by using a structure in which the transistor 200 is surrounded from above and below by insulators having a function of preventing the diffusion of impurities such as water and hydrogen and oxygen, the diffusion of excess oxygen and hydrogen to the oxide semiconductor can be reduced. This makes it possible to improve the electrical characteristics and reliability of the semiconductor device.

[0366] Furthermore, it is preferable to use silicon nitride or the like, which has a higher hydrogen barrier property, for the insulators 275 and 250d. It is also preferable to use aluminum oxide or the like, which has a higher ability to capture or fix hydrogen, for the insulator 250a. It is also preferable to use hafnium oxide or the like, which has a higher ability to capture or fix hydrogen, for the insulator 250c.

[0367] <Materials for semiconductor devices> Constituent materials that can be used in the semiconductor device will be described below. Each layer constituting the semiconductor device may have a single layer structure or a multilayer structure.

[0368] <<Substrate>> As the substrate on which the transistor is formed, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. As the insulating substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate can be mentioned. As the semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide can be mentioned. Furthermore, as the semiconductor substrate, a semiconductor substrate having an insulator region inside the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, can be mentioned. As the conductive substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be mentioned. As the substrate, for example, a substrate having a metal nitride, a substrate having a metal oxide, a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate can be mentioned. Alternatively, one or more types of elements may be provided on the substrate, such as a capacitor element, a resistor element, a switch element, a light-emitting element, and a memory element.

[0369] <<Insulators>> Examples of insulators such as insulators 215, 216, 221, 222, 241, 250, 275, 280, 282, 283, 285, 315, 320, 322, 324, 326, and 454 include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides having insulating properties.

[0370] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0371] Examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0372] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide having voids, and resin.

[0373] In addition, the transistor using a metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0374] The insulator functioning as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide semiconductor 230, oxygen vacancies in the oxide semiconductor 230 can be compensated for.

[0375] <<Conductors>> As the conductors such as conductors 240, 242, 260, 316, 328, 330, 413, 413b, 456, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements, etc. As the conductors, for example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel can be used. In addition, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferable because they are conductive materials that are not easily oxidized, or materials that maintain conductivity even when they absorb oxygen. In addition, semiconductors with high conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0376] When a conductor with a layered structure is used, for example, a layered structure combining the material containing the metal element described above and a conductive material containing oxygen, a layered structure combining the material containing the metal element described above and a conductive material containing nitrogen, or a layered structure combining the material containing the metal element described above and a conductive material containing oxygen and a conductive material containing nitrogen may be applied.

[0377] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.

[0378] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. The conductive material containing the metal element and nitrogen described above may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0379] <Example 1 of manufacturing method of semiconductor device> An example of a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to Figures 27A to 34D. Here, the case of manufacturing the semiconductor device illustrated in Figures 14A to 15B will be described as an example.

[0380] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films by appropriately using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0381] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0382] CVD methods can be classified into plasma CVD (PECVD) methods that use plasma, thermal CVD (TCVD: Thermal CVD) methods that use heat, photo CVD (Photo CVD) methods that use light, etc. They can also be further classified into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal Organic CVD) methods depending on the source gas used.

[0383] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0384] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0385] The CVD method and the ALD method are different from the sputtering method in which particles emitted from a target or the like are deposited. Therefore, they are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0386] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0387] In addition, in the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors, or by controlling the number of cycles of each precursor when multiple different precursors are introduced.

[0388] In the following, the etching process may be dry etching, wet etching, or the like.

[0389] As an etching gas for the dry etching process, for example, a gas containing a halogen can be used.

[0390] As the gas containing halogen, for example, an etching gas containing one or more of fluorine, chlorine, and bromine can be used. Fluorocarbon gas, hydrofluorocarbon gas, SF6 gas, Cl2 gas, BCl3 gas, SiCl4 gas, BBr3 gas, etc. can be used alone or in combination of two or more gases. As the fluorocarbon gas, C x F y Gases represented by (y≦2x+2) can be used. Examples of fluorocarbon gases that satisfy y=2x+2 include CF4, C2F6, C3F8, and C4F 10 , C5F 12 Examples of fluorocarbon gases that satisfy y<2x+2 include C2F4, C2F2, C3F7, C3F4, C4F8, C4F6, C4F4, C4F2, and C5F 10 Examples of the hydrofluorocarbon gas include unsaturated fluorocarbon compounds such as C5F8, C5F6, and C5F4. Examples of the hydrofluorocarbon gas include CHF3 gas, CH2F2 gas, and the like.

[0391] Furthermore, when a gas containing a halogen is used as the etching gas, oxygen (O2) gas, carbon dioxide gas, nitrogen (N2) gas, helium gas, argon gas, hydrogen gas, or a hydrocarbon gas may be added as appropriate.

[0392] Also, a gas that does not contain a halogen gas but contains a hydrocarbon gas or a hydrogen gas can be used as the etching gas.

[0393] Examples of hydrocarbon gases include methane (CH4), ethane (C2H6), propane (C3H8), and butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2), and propyne (C3H4) can be used.

[0394] When a hydrocarbon gas is used as the etching gas, nitrogen gas, helium gas, argon gas, hydrogen gas, or the like can be added appropriately.

[0395] Also, as the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes may be configured to apply a high frequency voltage to one of the parallel plate electrodes. Or, a plurality of different high frequency voltages may be applied to one of the parallel plate electrodes. Or, a high frequency voltage of the same frequency may be applied to each of the parallel plate electrodes. Or, a high frequency voltage of different frequencies may be applied to each of the parallel plate electrodes. Or, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used. The etching apparatus can be appropriately set according to the object to be etched.

[0396] In addition, a lithography method can be suitably used in the manufacturing method of the semiconductor device according to one embodiment of the present invention. In the lithography method, first, a resist is exposed through a mask. Next, the exposed region is removed or left using a developer to form a resist mask. Next, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape by etching through the resist mask. For example, a resist mask can be formed by exposing the resist to KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. In addition, a liquid immersion technique in which a liquid (e.g., water) is filled between a substrate and a projection lens and exposure is performed may be used. In addition, an electron beam or an ion beam may be used instead of the light described above. Note that when an electron beam or an ion beam is used, a mask may not be used in some cases.

[0397] In addition, the resist mask that is no longer needed after processing can be removed by performing a dry etching process such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), a wet etching process, a dry etching process followed by a wet etching process, or a wet etching process followed by a dry etching process.

[0398] Further, a hard mask made of an insulator or a conductor may be used under the resist mask. When using a hard mask, an insulating film or a conductive film that serves as a hard mask material is formed on a conductive film, an insulating film, a semiconductor film, or the like to be processed, a resist mask is formed thereon, and the hard mask material is etched to form a hard mask of a desired shape. The conductive film, insulating film, semiconductor film, or the like may be etched after removing the resist mask, or may be etched while the resist mask is left. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the conductive film, insulating film, semiconductor film, or the like. On the other hand, if the material of the hard mask does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask.

[0399] Also, a SOC (Spin On Carbon) film and a SOG (Spin On Glass) film may be formed between the workpiece and the resist mask. By using the SOC film and the SOG film as a mask, the durability of the mask pattern can be improved. For example, a SOC film, a SOG film, and a resist mask can be formed in this order on the workpiece, and then lithography can be performed.

[0400] First, a substrate (not shown) is prepared, and an insulator 215 is formed over the substrate (see FIGS. 27A to 27D).

[0401] 27(A) to 34(D), (A) of each figure shows a plan view, (B) of each figure shows a cross-sectional view corresponding to the portion shown by the dashed line B1-B2 in (A) of each figure, (C) of each figure shows a cross-sectional view corresponding to the portion shown by the dashed line B3-B4 in (A) of each figure, and (D) of each figure shows a cross-sectional view of the portion shown by the dashed line B5-B6 in (A) of each figure. Note that in the plan view of (A) of each figure, some elements are omitted for clarity.

[0402] As described above, the insulator 215 can be an insulator similar to one or more of the stacked films of the insulators 282 and 283. The insulator 215 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The sputtering method, which does not require the use of molecules containing hydrogen in the film formation gas, is preferable because it can reduce the hydrogen concentration in the insulator 215.

[0403] Next, the insulator 216 is formed over the insulator 215. The insulator 216 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0404] It is preferable that the insulators 215 and 216 are successively formed without exposure to the air. For example, a multi-chamber film formation apparatus may be used. This allows the insulators 215 and 216 to be formed with reduced hydrogen in the films, and further reduces the intrusion of hydrogen into the films and the adsorption of moisture onto the film surface between each film formation process.

[0405] Here, an opening reaching the insulator 215 is formed in the insulator 216, and the conductor 205 is formed in the opening, whereby the conductor 205 of the transistor 200 shown in Figures 11(A) to 11(D) can be formed. Specifically, for example, a conductive film that can be used for the conductor 205 is formed to fill the opening, and a part of the conductive film is removed by performing CMP processing.

[0406] Next, the insulator 221 is formed over the insulator 216 (see Figures 27(A) to 27(D)).

[0407] The insulator 221 may be any of the above insulators having barrier properties against oxygen, hydrogen, and water. The insulator 221 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon nitride is formed as the insulator 221 by a PEALD method.

[0408] Next, the insulator 222 is formed over the insulator 221 (see FIGS. 27A to 27D).

[0409] As the insulator 222, an insulator containing one or both of an oxide of aluminum and hafnium may be formed. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used. Alternatively, hafnium zirconium oxide is preferably used. An insulator containing one or both of an oxide of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, hydrogen and water contained in a structure provided around the transistor are prevented from diffusing into the inside of the transistor through the insulator 222, and thus generation of oxygen vacancies in the oxide semiconductor 230 can be suppressed.

[0410] The insulator 222 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, the insulator 222 is formed by a thermal ALD method using hafnium oxide.

[0411] In this embodiment, silicon nitride is formed as the insulator 221 by a PEALD method, and hafnium oxide is formed as the insulator 222 by a thermal ALD method. In this manner, by using silicon nitride having a function of suppressing diffusion of hydrogen as the insulator 221, diffusion of hydrogen from a lower layer of the transistor 200 can be suppressed. Furthermore, by using hafnium oxide having a function of capturing or fixing hydrogen as the insulator 222, hydrogen contained in the oxide semiconductor 230 can be captured or fixed to the insulator 222. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0412] Next, an insulating film is formed over the insulator 222 and etched to form the insulator 223 (see FIGS. 27A to 27D). The insulator 223 functions as a template for forming the oxide semiconductor 230. As the insulator 223, for example, an insulator that can be used for the insulator 216 can be used.

[0413] The insulator 223 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, a silicon oxide film is formed as the insulator 223 by a sputtering method.

[0414] The insulator 223 may be processed into an island shape by lithography. For this processing, a dry etching method or a wet etching method may be used. Processing by the dry etching method is suitable for fine processing. In this embodiment, as shown in Fig. 27(A) to Fig. 27(D), two columnar insulators 223 are formed and arranged in the B3-B4 direction.

[0415] 27B to 27D, the side surface of the insulator 223 may be perpendicular or approximately perpendicular to the top surface of the insulator 222. With such a structure, a reduction in area and high density can be achieved when a plurality of transistors are provided.

[0416] Next, an oxide semiconductor film 230f which is to become the oxide semiconductor 230 is formed to cover the insulator 223 (see FIGS. 27A to 27D). The oxide semiconductor film 230f is a metal oxide film which is to become the oxide semiconductor 230 in a later step, and any of the above-described metal oxide films can be used. The oxide semiconductor film 230f can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0417] Since the oxide semiconductor film 230f is formed along the insulator 223, it is preferable that the oxide semiconductor film 230f has good coverage. Therefore, it is preferable that the oxide semiconductor film 230f is formed by using an ALD method or the like that has good coverage. In addition, since it is preferable that the oxide semiconductor 230 has a high aspect ratio, it is preferable that the oxide semiconductor film 230f has a thin film thickness. Therefore, it is preferable that the oxide semiconductor film 230f is formed by using an ALD method that can adjust the film thickness to a thin film thickness. By forming the oxide semiconductor film 230f in this manner, the oxide semiconductor film 230f is formed in contact with the upper surface and side surface of the insulator 223.

[0418] Here, the oxide semiconductor film 230f is preferably formed by the same method as the above-described oxide semiconductor 30. By forming the oxide semiconductor film 230f by using such a method, the oxide semiconductor film 230f and the oxide semiconductor 230 are formed parallel or approximately parallel to the surface on which they are to be formed. Here, the surface on which the oxide semiconductor 230 is to be formed is, for example, the top surface of the insulator 222, the side surface of the insulator 223, and the top surface of the insulator 223.

[0419] The oxide semiconductor 230 preferably has a CAAC structure. An oxide semiconductor layer having a CAAC structure has layered crystal parts, and in the crystal parts, for example, metal atoms are arranged in layers. The metal atoms arranged in layers are arranged in a direction parallel to the surface on which they are formed. When the side surface of the insulator 223 is perpendicular or approximately perpendicular to the top surface of the insulator 222, for example, the metal atoms are arranged in the oxide semiconductor 230 in a direction perpendicular or approximately perpendicular to the top surface of the insulator 222.

[0420] As shown in FIG. 2A and the like, when the oxide semiconductor 230 has a three-layer structure including the oxide semiconductors 230a to 230c, films to be the oxide semiconductors 230a and 230c may be formed by an ALD method, and a film to be the oxide semiconductor 230b may be formed by a sputtering method. Specifically, the film to be the oxide semiconductor 230a can be formed to have a composition of In:Zn=2:1 (atomic ratio) or a composition close to that. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230a. The film to be the oxide semiconductor 230b can be formed using an oxide target having a composition of In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close to that. The film to be the oxide semiconductor 230c can be formed to have a composition of In:Zn=2:1 (atomic ratio) or a composition close to that. Alternatively, indium oxide may be used for the film to be the oxide semiconductor 230c. Note that the three-layer structure of the oxide semiconductors 230a to 230c is not limited to the above structure. For example, the oxide semiconductors 230a to 230c may be formed by an ALD method. In this structure, since a sputtering method is not used, the oxide semiconductors 230a to 230c can be successively formed in one manufacturing apparatus, which reduces manufacturing costs. Note that after the oxide semiconductors 230a, 230b, and 230c are formed, microwave treatment may be performed on each of them. The microwave treatment can improve the crystallinity of the oxide semiconductor 230.

[0421] Next, heat treatment is preferably performed. The heat treatment is preferably performed within a temperature range in which the oxide semiconductor film 230f is not polycrystallized. The heat treatment of the oxide semiconductor film 230f may be performed by the same method as the heat treatment of the oxide semiconductor 30 described above.

[0422] For example, the heat treatment can be performed at a flow rate ratio of nitrogen gas and oxygen gas of 4:1 at a temperature of 450° C. for one hour.

[0423] By forming the oxide semiconductor 230 using the above method and then performing heat treatment, the oxide semiconductor 230 can be converted into AG CAAC. As a result, the on-state current, S value, field-effect mobility, frequency characteristics, and the like of the transistor 200 can be improved, and a semiconductor device with favorable electrical characteristics can be provided. In addition, a highly reliable semiconductor device can be provided.

[0424] The heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in a nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0425] In addition, the gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, moisture and the like can be prevented from being introduced into the oxide semiconductor film 230f as much as possible. Note that a highly purified gas can also be used in the heat treatment before and after this step.

[0426] Furthermore, the above-described heat treatment including oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide semiconductor film 230f. Reducing the impurities in the film in this manner can improve the crystallinity of the oxide semiconductor film 230f, resulting in a denser and more compact structure. This can increase the crystalline regions in the oxide semiconductor film 230f, thereby reducing in-plane variations in the crystalline regions in the oxide semiconductor film 230f. As a result, in-plane variations in the electrical characteristics of the transistor can be reduced.

[0427] Furthermore, by performing the heat treatment, oxygen can be supplied to the oxide semiconductor film 230f, so that oxygen vacancies in the oxide semiconductor film 230f can be reduced, thereby improving the reliability of the transistor 200.

[0428] Furthermore, by performing heat treatment, hydrogen in the oxide semiconductor film 230f moves to the insulator 222 and is absorbed into the insulator 222. In other words, hydrogen in the oxide semiconductor film 230f diffuses into the insulator 222. Thus, the hydrogen concentration in the insulator 222 increases, but the hydrogen concentration in the oxide semiconductor film 230f decreases. Note that by providing the insulator 221 in contact with the lower surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 during the heat treatment.

[0429] In particular, the oxide semiconductor film 230f (the next oxide semiconductor 230) functions as a channel formation region of the transistor 200. The transistor 200 formed using the oxide semiconductor film 230f in which the hydrogen concentration is reduced has high reliability, which is preferable.

[0430] Next, part of the oxide semiconductor film 230f is removed by anisotropic etching (see FIGS. 28A to 28D). A portion of the oxide semiconductor film 230f that is parallel to the substrate surface is mainly etched, and a sidewall-shaped oxide semiconductor 230 is formed in contact with a side surface of the insulator 223. Then, the insulator 223 is removed (see FIGS. 29A to 29D).

[0431] 29(B) shows a structure in which curved shapes are formed on both the B1 side and the B2 side of the upper part of the oxide semiconductor 230, but is not limited thereto, and may be a structure in which a curved shape is formed only on the side of the oxide semiconductor 230 that is not in contact with the insulator 223. In addition, in FIGS. 29(C) and 29(D) show a structure in which curved shapes are formed on both the B3 side and the B4 side of the upper part of the oxide semiconductor 230, but is not limited thereto, and may be a structure in which a curved shape is formed only on the side of the oxide semiconductor 230 that is not in contact with the insulator 223.

[0432] By anisotropic etching, the oxide semiconductor 230 with a high aspect ratio can be formed. By using the oxide semiconductor 230, the channel width of the transistor 200 can be increased without increasing the occupation area, thereby improving the on-state current and frequency characteristics of the transistor 200. Furthermore, the contact area between the oxide semiconductor 230 and the conductor 242a and the conductor 242b can be increased without increasing the occupation area, thereby improving the on-state current and frequency characteristics of the transistor 200.

[0433] 29A, the oxide semiconductor 230 has a circumferential shape whose both ends are aligned in a top view. The oxide semiconductor 230 can also be said to have an opening in the center. When the oxide semiconductor 230 has a three-layer structure including the oxide semiconductors 230a to 230c as described above, the circumferential oxide semiconductor 230 is formed in the order of the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c, with the region where the insulator 223 was formed being at the center. Thus, as shown in FIG. 4A, in a cross-sectional view in the channel width direction, the oxide semiconductor 230c, the oxide semiconductor 230b, the oxide semiconductor 230a, the oxide semiconductor 230a, the oxide semiconductor 230b, and the oxide semiconductor 230c are arranged symmetrically in this order.

[0434] Although the above description has been given of a configuration in which two circumferential oxide semiconductors 230 are provided, the present invention is not limited thereto. For example, one or three or more circumferential oxide semiconductors 230 may be provided. Furthermore, the circumferential oxide semiconductors 230 may be combined to form an oxide semiconductor 230 having a shape with a plurality of openings. For example, as shown in FIG. 5A, the oxide semiconductor 230 may have a shape in which three openings are arranged in the A1-A2 direction in a top view. In this case, three insulators 223 may be formed adjacent to each other at a short distance in the steps shown in FIG. 27A to FIG. 27D. Alternatively, for example, as shown in FIG. 5B, the oxide semiconductor 230 may have a lattice shape in a top view. In this case, as shown in FIG. 27A to FIG. 27D, a lattice-shaped trench may be formed in the insulator 223.

[0435] 29A, the oxide semiconductor 230 has a circumferential structure in top view, but etching may be further performed to remove part of the oxide semiconductor 230. For example, in the structure shown in FIG. 29A, by removing a part of the oxide semiconductor 230, the oxide semiconductor 230 can have a rectangular shape extending in the B1-B2 direction in top view.

[0436] Note that the oxide semiconductor 230 may be manufactured without using the pillar (insulator 223). For example, the oxide semiconductor film 230f may be formed in a planar shape over the insulator 222, and a fin-shaped oxide semiconductor 230 may be formed using a mask. By not using the pillar, the oxide semiconductor 230 may be manufactured without using a film that has high coverage on the side surface of the pillar, which may facilitate the manufacturing process. For example, the semiconductor device illustrated in FIG. 21(A) can be manufactured by forming one fin-shaped oxide semiconductor 230 using a mask as illustrated in FIGS. 30(A) to 30(D).

[0437] When the pillars are not used, the oxide semiconductor film 230f is formed to have a thickness approximately equal to the height of the oxide semiconductor 230. If the film to be formed is thick, the cost required for film formation increases. In addition, in etching the oxide semiconductor film 230f, problems such as a long etching time or adhesion of reaction products may occur. In addition, if the film stress increases due to the thickening of the film thickness, there is a concern that the adhesion with the insulator 222 may decrease.

[0438] Furthermore, when pillars are not used, the width of the fin-shaped oxide semiconductor 230 is limited by the minimum dimensions of the mask. When a lithography method is used, the width is limited by, for example, the minimum dimensions of an exposure machine. When pillars are used to form the oxide semiconductor 230, the thickness of the oxide semiconductor film 230f formed on the sidewall of the pillar becomes the width of the oxide semiconductor 230, so that an oxide semiconductor 230 having a finer width can be formed.

[0439] The anisotropic etching of the oxide semiconductor film 230f is preferably performed by dry etching.

[0440] When the oxide semiconductor film 230f is etched by dry etching, hydrofluorocarbon, CH4, BBr3, HBr, SiCl4, BCl3, Cl2, etc. can be used as the etching gas. In addition to these gases, Ar, O2, H2, N2, etc. can be used. Specifically, for example, a mixed gas of CH4 and Ar can be used.

[0441] Note that a dry etching method or a wet etching method can be used to remove the insulator 223. For example, the insulator 223 may be removed by a wet etching method.

[0442] When the insulator 222 is made of a material that is difficult to etch, such as hafnium oxide, the insulator 222 can function as an etching stopper in etching of the oxide semiconductor film 230f and the insulator 223.

[0443] 29A to 29D, the transistor 200 is provided with two insulators 223 and two oxide semiconductors 230; however, the present invention is not limited thereto. As shown in FIG. 45A, two transistors (transistor 200_1 and transistor 200_2) may each be provided with two insulators 223 and two oxide semiconductors 230. As shown in FIG. 45B, insulators 223 having different widths may be provided, and three fin-shaped oxide semiconductors 230 may be provided in each of the transistors 200_1 and 200_2 in a cross-sectional view taken along the B3-B4 direction. In this case, part of the oxide semiconductor 230 is removed so that the top surface has a linear shape extending in the B1-B2 direction, thereby dividing the oxide semiconductor 230 of the transistor 200_1 from the oxide semiconductor 230 of the transistor 200_2.

[0444] Although the structure in which the insulator 223 is removed is shown in FIG. 29A to FIG. 29D, the present invention is not limited thereto. For example, as shown in FIG. 46A, a structure in which part of the insulator 223 is left can be used. Here, the insulator 223 is left in a region in which the conductor 240 is to be provided in a later step. For example, when removing the insulator 223 in the above step, a mask may be provided by lithography in the region in which the conductor 240 is to be provided, so that the insulator 223 in the region is left. As shown in FIG. 46A, the insulator 223 is formed so as to be embedded inside the circumferential oxide semiconductor 230. As shown in FIG. 46B, in the transistor 200, the conductor 242a and the conductor 240a are formed to cover the oxide semiconductor 230 and the insulator 223. Here, the conductor 242a is in contact with the side surface and the top surface of the oxide semiconductor 230 and the top surface of the insulator 223.

[0445] Next, a conductive film 242f is formed over the insulator 222 and the oxide semiconductor 230 (see FIGS. 31A to 31D). The conductive film 242f is to become the conductor 242 in a later step.

[0446] The conductive film 242f can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, the conductive film 242f may be a stacked film of tantalum nitride formed by a sputtering method and tungsten formed by a sputtering method on the tantalum nitride. By forming the conductive film 242f to cover the oxide semiconductor 230, the contact area between the oxide semiconductor 230 and the conductor 242 can be increased without increasing the occupation area. This can improve the on-state current and frequency characteristics of the transistor 200.

[0447] By using a sputtering method, a conductive film with excellent conductivity can be formed with high mass productivity. Thus, the conductive film 242f is preferably formed by a sputtering method. Note that the coverage of the sputtering method may be lower than that of the ALD method or the like. For example, the thickness of the conductive film 242f in a region covering the sidewall of the oxide semiconductor 230 may be thinner than that of a region covering the top surface of the oxide semiconductor 230 and the top surface of the insulator 222. In such a case, the resistance of the oxide semiconductor 230 can be reduced to function as an electrode, thereby enabling a circuit including the transistor 200 and the capacitor 460 to operate favorably. Note that the oxide semiconductor 230 may be expressed as functioning as an auxiliary electrode of the conductor 242b.

[0448] Next, the conductive film 242f is processed into an island shape by lithography to form the conductor 242P (see FIGS. 32A to 32D). At this time, the conductor 242P is preferably formed to cover the oxide semiconductor 230. Furthermore, the insulator 222 is exposed in a region that does not overlap with the conductor 242P.

[0449] For the above processing, a dry etching method or a wet etching method can be used. Processing by the dry etching method is suitable for fine processing. For the conditions of the dry etching method and the dry etching apparatus, the above description can be referred to.

[0450] The side surface of the conductor 242P may be configured to be perpendicular or approximately perpendicular to the upper surface of the insulator 222. By using such a configuration, it is possible to reduce the area and increase the density when providing a plurality of transistors.

[0451] However, the present invention is not limited to the above, and the side surfaces of the oxide semiconductor 230 and the conductor 242P may be tapered. The taper angle of the side surfaces of the oxide semiconductor 230 and the conductor 242P may be, for example, 60° or more and less than 90°. By tapering the side surfaces in this manner, the coverage of the insulator 275 and the like can be improved in the subsequent steps, and defects such as voids can be reduced.

[0452] Next, an insulator 275 is deposited to cover the conductor 242P, and an insulator 280 is deposited on the insulator 275 (see FIGS. 32A to 32D).

[0453] Insulator 275 and insulator 280 can each be deposited using, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.

[0454] Here, it is preferable that the insulator 275 contacts the upper surface of the insulator 222 .

[0455] It is preferable to use an insulator having a function of suppressing oxygen permeation for the insulator 275. For example, it is preferable to form a silicon nitride film as the insulator 275 by using a PEALD method. Alternatively, it is preferable to form an aluminum oxide film as the insulator 275 by using a sputtering method and then form a silicon nitride film thereon by using a PEALD method. By making the insulator 275 have the above structure, it is possible to improve the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0456] In this manner, the oxide semiconductor 230 and the conductor 242P can be covered with the insulator 275 having a function of suppressing the diffusion of oxygen. This makes it possible to suppress the direct diffusion of oxygen from the insulator 280 or the like to the oxide semiconductor 230 and the conductor 242P in a later process.

[0457] It is preferable to form an insulator having a flat upper surface as the insulator 280 by forming an insulating film to be the insulator 280 and performing a CMP process on the insulating film. Note that a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP process may be performed until the silicon nitride reaches the insulator 280.

[0458] The insulator 280 is preferably formed of silicon oxide by a sputtering method. The insulating film to be the insulator 280 can be formed by a sputtering method in an atmosphere containing oxygen, whereby the insulator 280 containing excess oxygen can be formed. The use of a sputtering method that does not require the use of molecules containing hydrogen in a deposition gas can reduce the hydrogen concentration in the insulator 280. Note that heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 275 and the like can be removed, and the moisture and hydrogen concentrations in the oxide semiconductor 230 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0459] Next, the insulator 275 and the insulator 280 are processed by lithography to form an opening 292 that reaches the conductor 242P and the insulator 222 (see FIGS. 32(A) to 32(D)). The upper surface of the conductor 242P that overlaps with the opening 292 is exposed.

[0460] The opening 292 is formed so as to overlap with the oxide semiconductor 230 in a region where the capacitor 460 is to be formed.

[0461] In order to finely process the openings in the insulator 280, it is preferable to use short-wavelength light such as EUV light or an electron beam in the lithography method.

[0462] The above processing is preferably carried out by dry etching, which is suitable for forming an opening with a high aspect ratio because it allows anisotropic etching.

[0463] Next, a mask 278 is formed over the insulator 280 and the oxide semiconductor 230 (see FIGS. 33A to 33D).

[0464] A resist mask can be used as the mask 278. Alternatively, a laminated structure of an SOC film, an SOG film, and a resist mask may be used.

[0465] The mask 278 preferably has an opening at a position overlapping a region that will become a channel formation region in the transistor 200 .

[0466] Next, regions of the insulator 280, the insulator 275, and the conductor 242P that are not covered by the mask 278 are removed (see FIGS. 33A to 33D). At this point, openings 291 are provided in the insulator 280 and the insulator 275. The conductor 242P is divided to form the conductor 242a and the conductor 242b. In the region from which the conductor 242P is removed, the top surface of the oxide semiconductor 230 that was covered by the conductor 242P is exposed.

[0467] After processing the conductor 242P, an ashing process using oxygen plasma may be performed. By performing such an oxygen plasma process, impurities generated in the above etching process and diffused into the oxide semiconductor 230 and the like can be removed. Examples of the impurities include those originating from components contained in the workpiece of the above etching process and components contained in the gas used in the etching process. Examples of the impurities include chlorine, fluorine, tantalum, silicon, and hafnium. In particular, when chlorine gas is used in processing the conductor 242P as shown in the above etching process, the oxide semiconductor 230 is exposed to an atmosphere containing chlorine gas, so it is preferable to remove the chlorine attached to the oxide semiconductor 230. By removing the impurities attached to the oxide semiconductor 230 in this manner, the electrical characteristics and reliability of the transistor can be improved.

[0468] A cleaning treatment may be performed to remove impurities and the like attached to the surface of the oxide semiconductor 230 in the etching process. The cleaning method may be wet cleaning using a cleaning solution or the like (which may also be called wet etching treatment), plasma treatment using plasma, cleaning by heat treatment, or the like, and the above cleaning methods may be combined as appropriate. Note that the cleaning treatment may deepen the grooves.

[0469] The wet cleaning may be performed using an aqueous solution of one or more of ammonia water, oxalic acid, phosphoric acid, and hydrofluoric acid diluted with carbonated water or pure water, pure water, carbonated water, etc. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0470] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water may be called diluted hydrofluoric acid, and an aqueous solution of ammonia water diluted with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution are appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is preferably 0.01% to 5%, more preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the diluted hydrofluoric acid is preferably 0.01 ppm to 100 ppm, more preferably 0.1 ppm to 10 ppm.

[0471] Note that the ultrasonic cleaning is preferably performed at a frequency of 200 kHz or more, more preferably at a frequency of 900 kHz or more, in order to reduce damage to the oxide semiconductor 230 and the like.

[0472] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0473] In this embodiment, wet cleaning is performed using diluted ammonia water as the cleaning treatment. By performing the cleaning treatment, impurities attached to the surface of the oxide semiconductor 230 or diffused inside the oxide semiconductor 230 can be removed. Furthermore, the crystallinity of the oxide semiconductor 230 can be improved.

[0474] It is preferable to perform a heat treatment after the etching or the cleaning. The temperature of the heat treatment is 100° C. to 650° C., preferably 250° C. to 600° C., more preferably 300° C. to 550° C., and further preferably 350° C. to 400° C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment is preferably performed in an atmosphere containing oxygen, and is preferably performed at a temperature of 350° C. for one hour with a flow rate ratio of nitrogen gas to oxygen gas of 4:1. In this way, oxygen can be supplied to the oxide semiconductor 230, thereby reducing oxygen vacancies. In addition, by performing such a heat treatment, the crystallinity of the oxide semiconductor 230 can be improved. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor 230, and the hydrogen can be removed as H2O (dehydration). As a result, hydrogen remaining in the oxide semiconductor 230 recombines with the oxygen vacancies to form V O H can be suppressed. Thus, the electrical characteristics of the transistor including the oxide semiconductor 230 can be improved, and the reliability can be improved. Furthermore, the variation in electrical characteristics of a plurality of transistors formed over the same substrate can be suppressed. Note that the heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed continuously in a nitrogen atmosphere without exposure to the air. The heat treatment can also serve as the heat treatment after the deposition of the oxide semiconductor 30c in the formation of the oxide semiconductor 30 described above. Thus, the heat treatment may cause a crystal region of the oxide semiconductor 230 to grow.

[0475] Note that when heat treatment is performed with the conductor 242a and the conductor 242b in contact with the oxide semiconductor 230, the sheet resistance of a region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b may decrease. Also, the carrier concentration may increase. Thus, the resistance of the region of the oxide semiconductor 230 overlapping with the conductor 242a and the region of the oxide semiconductor 230 overlapping with the conductor 242b can be reduced in a self-aligned manner.

[0476] Next, an insulating film 250A (not shown) is formed so as to fill the openings 291 formed in the insulator 280 and the insulator 275 (see FIGS. 34A to 34D). The insulating film 250A is provided so as to cover the upper surface of the oxide semiconductor 230 overlapping with the openings 291. The insulating film 250A is processed in a later step to form the insulator 250 and the insulator 454. Here, the insulating film 250A is in contact with the insulator 280, the insulator 275, the conductor 242a, the conductor 242b, the insulator 222, and the oxide semiconductor 230.

[0477] The insulating film 250A can be formed by sputtering, CVD, MBE, PLD, or ALD. For example, the insulating film 250A is preferably formed by ALD. As with the insulator 250 described above, the insulating film 250A is preferably formed to a thin thickness, and it is necessary to reduce the variation in thickness. In contrast, the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizing agent) are alternately introduced, and the thickness can be adjusted by the number of times this cycle is repeated, so that precise thickness adjustment is possible. In addition, the insulating film 250A needs to be formed with good coverage on the bottom and side surfaces of the opening. By using the ALD method, layers of atoms can be deposited one by one on the bottom and side surfaces of the opening, so that the insulating film 250A can be formed with good coverage on the opening.

[0478] When the insulating film 250A is formed by the ALD method, ozone (O3), oxygen (O2), water (H2O), or the like can be used as an oxidizing agent. By using ozone (O3), oxygen (O2), or the like that does not contain hydrogen as an oxidizing agent, the amount of hydrogen that diffuses into the oxide semiconductor 230 can be reduced.

[0479] The insulator 250 can have a stacked structure as shown in Figures 3(A) and 3(B), etc. For example, as shown in Figure 3(A), the insulator 250 can have a stacked structure of insulators 250a to 250d. In this case, aluminum oxide can be deposited by a thermal ALD method as the insulator 250a, silicon oxide can be deposited by a PEALD method as the insulator 250b, hafnium oxide can be deposited by a thermal ALD method as the insulator 250c, and silicon nitride can be deposited by a PEALD method as the insulator 250d.

[0480] In addition, after the insulating film 250A or any of the insulators constituting the insulating film 250A is formed, it is preferable to perform a microwave treatment in an atmosphere containing oxygen. Here, the microwave treatment refers to a treatment using a device having a power source that generates high-density plasma using microwaves, for example. In addition, in this specification and the like, the microwave refers to an electromagnetic wave having a frequency of 300 MHz or more and 300 GHz or less.

[0481] In the microwave treatment, it is preferable to use a microwave treatment device having a power source that generates high-density plasma using microwaves. Here, the frequency of the microwave treatment device is preferably 300 MHz to 300 GHz, more preferably 2.4 GHz to 2.5 GHz, and can be, for example, 2.45 GHz. By using high-density plasma, high-density oxygen radicals can be generated. In addition, the power of the power source that applies microwaves of the microwave treatment device is preferably 1000 W to 10000 W, more preferably 2000 W to 5000 W. In addition, the microwave treatment device may have a power source that applies RF to the substrate side. In addition, by applying RF to the substrate side, oxygen ions generated by high-density plasma can be efficiently guided into the oxide semiconductor 230.

[0482] The microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10 Pa to 1000 Pa, and more preferably 300 Pa to 700 Pa. The treatment temperature can be room temperature (e.g., 25° C.) or higher, and is preferably 100° C. to 750° C., and more preferably 200° C. to 500° C. For example, the microwave treatment is preferably carried out at a treatment temperature of about 250° C. Alternatively, the microwave treatment is preferably carried out at a treatment temperature of about 400° C. After the oxygen plasma treatment, a heat treatment may be carried out continuously without exposure to the outside air. The heat treatment temperature is preferably, for example, 100° C. to 750° C., and more preferably 300° C. to 500° C.

[0483] Also, for example, the microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Still more preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%. In this way, by performing the microwave treatment in an atmosphere containing oxygen, the carrier concentration in the oxide semiconductor 230 can be reduced. Also, by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave treatment, the carrier concentration in the oxide semiconductor 230 can be prevented from being excessively reduced.

[0484] By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductor 242a and the conductor 242b of the oxide semiconductor 230. The action of the plasma, microwaves, etc. can reduce the V OH can be split into oxygen vacancies and hydrogen, and the hydrogen can be removed from the region. When the structure shown in FIG. 3(A) is used, it is preferable to use an insulating film (such as aluminum oxide) that has the function of capturing or fixing hydrogen as the insulator 250a. With this structure, hydrogen generated by microwave treatment can be captured or fixed by the insulating film 250A. In this way, V included in the channel formation region can be removed. O As a result, oxygen vacancies in the channel formation region and V O By supplying oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, and the carrier concentration can be reduced.

[0485] The oxygen injected into the channel formation region can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions, and oxygen radicals (also called O radicals, which are atoms, molecules, or ions with an unpaired electron). The oxygen injected into the channel formation region may be in one or more of the above forms, and is particularly preferably in the form of oxygen radicals. In addition, the film quality of the insulator 250 can be improved, thereby improving the reliability of the transistor.

[0486] Furthermore, the microwave treatment can also remove impurities such as carbon in the oxide semiconductor 230. Removal of carbon, which is an impurity in the oxide semiconductor 230, can improve the crystallinity of the oxide semiconductor 230. As a result, the oxide semiconductor 230 can become a CAAC-OS. In particular, when the oxide semiconductor 230 is formed by an ALD method, carbon contained in a precursor may be taken into the oxide semiconductor 230, so it is preferable to remove carbon by the microwave treatment.

[0487] Meanwhile, the oxide semiconductor 230 has a region overlapping with either the conductor 242a or the conductor 242b. The region can function as a source region or a drain region. Here, the conductor 242a and the conductor 242b preferably function as a shielding film against the action of microwaves, high frequency waves such as RF, oxygen plasma, and the like when performing microwave treatment in an atmosphere containing oxygen. For this reason, the conductor 242a and the conductor 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0488] The conductors 242a and 242b shield against the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like, and therefore these effects do not extend to regions of the oxide semiconductor 230 that overlap with either the conductor 242a or the conductor 242b. As a result, the microwave treatment can reduce the V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0489] In this manner, oxygen vacancies and V O By removing H, the channel formation region can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the region that functions as the source region or drain region can be suppressed, and the conductivity (state of being a low resistance region) before the microwave treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor, and suppresses variations in the electrical characteristics of the transistor within the substrate surface.

[0490] Furthermore, by modifying the film quality of the insulator 250 through microwave treatment, diffusion of hydrogen, water, impurities, and the like can be suppressed. Therefore, a post-process such as deposition of a conductive film to be the conductor 260 or a post-treatment such as heat treatment can suppress diffusion of hydrogen, water, impurities, and the like through the insulator 250 into the oxide semiconductor 230 and the like. In this manner, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0491] When the insulator 250 has a stacked structure of the insulators 250a to 250d, it is preferable to perform microwave treatment after the formation of the insulator 250b. Furthermore, another microwave treatment may be performed after the formation of the insulator 250c. In this manner, the microwave treatment in an atmosphere containing oxygen may be performed multiple times (at least two or more times). The microwave treatment may also serve as a heat treatment after the formation of the oxide semiconductor 230. Thus, the microwave treatment may cause a crystalline region of the oxide semiconductor 230 to grow.

[0492] Moreover, heat treatment may be performed while the reduced pressure state is maintained after the microwave treatment. By performing such treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be efficiently removed. Alternatively, the step of performing heat treatment may be repeated multiple times while the reduced pressure state is maintained after the microwave treatment. By repeatedly performing the heat treatment, hydrogen in the insulating film and the oxide semiconductor 230 can be more efficiently removed. Note that the heat treatment temperature is preferably 300° C. or higher and 500° C. or lower. The heat treatment can also serve as heat treatment after the formation of the oxide semiconductor 230. Thus, the heat treatment may cause a crystal region of the oxide semiconductor 230 to grow.

[0493] Next, a conductive film 260A (not shown) is formed over the insulating film 250A (see FIGS. 34A to 34D). The conductive film 260A can be processed in a later step to form the conductor 260 and the conductor 456.

[0494] The conductive film 260A can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, a plating method, or an ALD method. In this embodiment, the conductive film 260A is formed by sequentially depositing titanium nitride by a CVD method and tungsten by a CVD method on the titanium nitride. The conductive film 260A may be formed while heating the substrate. The substrate heating can also serve as a heat treatment after the oxide semiconductor 230 is deposited. Thus, the substrate heating may cause the crystal region of the oxide semiconductor 230 to grow.

[0495] Next, the insulating film 250A and the conductive film 260A are polished by CMP processing until the insulator 280 is exposed. As a result, the insulator 250, the insulator 454, the conductor 260, and the conductor 456 are formed (see FIGS. 34A to 34D).

[0496] The insulator 250 is provided in contact with the insulator 280, the insulator 275, the conductor 242a, the conductor 242b, the oxide semiconductor 230, and the insulator 222 in the opening 291. The conductor 260 is arranged to fill the opening 291 with the insulator 250 interposed therebetween. In this manner, the transistor 200 is formed.

[0497] The insulator 454 is provided in contact with the insulator 280, the insulator 275, the conductor 242b, and the insulator 222 in the opening 292. The conductor 456 is arranged to fill the opening 292 with the insulator 454 interposed therebetween. In this manner, the capacitor 460 is formed.

[0498] Next, the insulator 282 is formed over the insulator 250, the conductor 260, and the insulator 280 (see Figures 14(A) to 15(B)). The insulator 282 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably formed by a sputtering method. The insulator 282 may also be formed by forming a first layer by an ALD method and then forming a second layer thereon by a sputtering method.

[0499] Furthermore, by forming the insulator 282 in an atmosphere containing oxygen by a sputtering method, oxygen can be added to the insulator 280 during the film formation. This allows the insulator 280 to contain excess oxygen. At this time, it is preferable to form the insulator 282 while heating the substrate. By forming the insulator 282 in this manner, a suitable amount of oxygen can be supplied from the insulator 280 to the oxide semiconductor 230 through the insulator 250. Furthermore, by providing the insulator 250a in the insulator 250, an excess amount of oxygen can be supplied into the insulator 250, which can prevent the conductor 242a and the conductor 242b from being excessively oxidized in the vicinity of the insulator 250.

[0500] The aluminum oxide film is formed using an aluminum target in an atmosphere containing oxygen gas. The amount of oxygen injected into the insulator 280 can be controlled by the magnitude of the bias power applied to the substrate by the sputtering method. For example, the smaller the bias power, the smaller the amount of oxygen injected into the insulator 280, and the amount of oxygen is likely to be saturated even if the film thickness of the insulator 282 is thin. Also, the larger the bias power, the larger the amount of oxygen injected into the insulator 280. The amount of oxygen injected into the insulator 280 can be suppressed by reducing the RF bias power. When the substrate bias is applied by an RF power source, the RF frequency is preferably 10 MHz or more. Typically, it is 13.56 MHz. The higher the RF frequency, the smaller the damage to the substrate can be.

[0501] Furthermore, by forming a second layer by sputtering on the first layer formed by the ALD method, the upper end of the insulator 250 and the upper surface of the conductor 260 can be protected from the impact of ion collisions caused by the sputtering deposition.

[0502] Furthermore, heat treatment may be performed before the formation of the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be formed successively without exposure to air. By performing such treatment, moisture and hydrogen adsorbed on the surface of the insulator 280 can be removed and the moisture and hydrogen concentrations in the insulator 280 can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is 250° C.

[0503] Next, the insulator 283 is formed over the insulator 282 (see Figures 14A to 15B). The insulator 283 can be formed by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen in the deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, a silicon nitride film is formed as the insulator 283 by a sputtering method.

[0504] Here, it is preferable to successively form the insulators 282 and 283 without exposing them to the air environment. By forming the films without exposing them to the air, impurities or moisture from the air environment can be prevented from adhering to the insulators 282 and 283, and the interface or the vicinity of the interface between the insulators 282 and 283 can be kept clean.

[0505] In this embodiment, a silicon nitride film is formed as the insulator 283, and an aluminum oxide film is formed as the insulator 282. In this manner, by using silicon nitride having a function of suppressing diffusion of hydrogen for the insulator 283, diffusion of hydrogen from the upper layer of the transistor 200 can be suppressed. Furthermore, by using aluminum oxide having a function of capturing or fixing hydrogen for the insulator 282, hydrogen contained in the insulator 280 or the like can be captured or fixed to the insulator 282. As a result, the hydrogen concentration in the oxide semiconductor 230 and its vicinity can be reduced.

[0506] Next, the insulator 285 is formed over the insulator 283 (see FIGS. 14A to 15B). The insulator 285 can be any of the insulators described above as appropriate. For example, the insulator that can be used for the insulator 280 can be used as the insulator 285.

[0507] Next, openings reaching the conductor 242a are formed in the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 (see FIGS. 14A to 15B). The openings may be formed by lithography. In forming the openings, it is preferable to process the workpiece by dry etching. Since dry etching is capable of anisotropic etching, it is suitable for forming openings with a high aspect ratio. When performing anisotropic etching, for example, reactive ion etching is preferably performed. Note that the above description can be referred to for the conditions of the dry etching method and the dry etching apparatus. Note that although the shape of the openings in FIG. 14A is a square shape in a top view, the shape is not limited thereto. For example, the openings may be a circle, an approximately circle such as an ellipse, a polygon such as a square, or a polygon such as a square with rounded corners in a top view.

[0508] Next, after the openings are formed, heat treatment may be performed. The temperature of the heat treatment may be 100° C. or higher and 600° C. or lower, preferably 250° C. or higher and 550° C. or lower, more preferably 350° C. or higher and 450° C. or lower. Note that the heat treatment is preferably performed in a nitrogen gas or inert gas atmosphere. The heat treatment is preferably performed in an atmosphere not containing an oxidizing gas or an oxygen gas because the conductor 242a and the conductor 242b are exposed. For example, the heat treatment is preferably performed in a nitrogen gas atmosphere at a temperature of 400° C. for one hour. Note that the heat treatment may be performed under reduced pressure. By the heat treatment, oxygen contained in the insulator 280 can be supplied to the oxide semiconductor 230 through the insulator 250. As a result, oxygen vacancies in the channel formation region of the oxide semiconductor 230 can be reduced. The heat treatment can also serve as a heat treatment after the formation of the oxide semiconductor 230. Therefore, the heat treatment may cause a crystal region of the oxide semiconductor 230 to grow.

[0509] Here, since the side surface of the insulator 280 is exposed at the opening, the heat treatment causes oxygen contained in the insulator 280 to diffuse outward, thereby controlling the amount of oxygen contained in the insulator 280. Meanwhile, since the insulators 282 and 283 having a barrier property against oxygen are provided on the insulator 280, oxygen does not diffuse outward from the upper surface of the insulator 280. This can prevent excessive oxygen from diffusing outward from the insulator 280, which would cause oxygen vacancies in the insulator 280. In addition, the oxide semiconductor 230, the conductor 242a, and the conductor 242b are covered with the insulator 275. This can prevent an excessive amount of oxygen from diffusing directly from the insulator 280 to the oxide semiconductor 230, the conductor 242a, and the conductor 242b during the heat treatment.

[0510] In this manner, the amount of oxygen in the insulator 280 can be more suitably adjusted and a suitable amount of oxygen can be supplied to the oxide semiconductor 230. This can reduce oxygen vacancies in the oxide semiconductor 230 and prevent an excessive amount of oxygen from being supplied to the oxide semiconductor 230. Thus, the electrical characteristics and reliability of the transistor 200 can be improved. Furthermore, the step of exposing the side surface of the insulator 280 can also serve as a step of forming an opening into which the conductor 240a is to be embedded, thereby simplifying the manufacturing process of the semiconductor device.

[0511] Next, an insulating film to be the insulator 241a is formed and anisotropically etched to form the insulator 241a in the opening that reaches the conductor 242a (see Figures 14(A) to 15(B)). The insulating film to be the insulator 241a can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 241a, it is preferable to use an insulating film that has a function of suppressing oxygen permeation. For example, it is preferable to form a silicon nitride film by a PEALD method. Silicon nitride is preferable because it has high blocking properties against hydrogen.

[0512] Moreover, the anisotropic etching of the insulating film that becomes the insulator 241a may be performed by, for example, dry etching. By providing the insulator 241a on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 240a to be formed next. It is also possible to prevent impurities such as water and hydrogen contained in the insulator 280 from diffusing into the conductor 240a. Note that the anisotropic etching may form recesses in parts of the upper surfaces of the conductors 242a and 242b.

[0513] Next, a conductive film that becomes the conductor 240a is formed. The conductive film that becomes the conductor 240a is preferably a laminated structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminated structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that becomes the conductor 240a can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0514] Next, a planarization process is performed to remove a part of the conductive film that becomes the conductor 240a and expose the top surface of the insulator 285. As a result, the conductive film remains only in the opening, and the conductor 240a having a flat top surface can be formed (see Figures 14(A) to 15(B)). Note that the planarization process may remove a part of the top surface of the insulator 285. It is preferable to use a CMP method for the planarization process.

[0515] By providing the conductor 240a in contact with the conductor 242a as described above, the conductor 240a which functions as one of the source and drain of the transistor 200 can be connected to a wiring.

[0516] Next, the conductor 413 is formed over the conductor 240a.

[0517] In this manner, the semiconductor device shown in FIGS. 14A to 15B can be manufactured.

[0518] <Example 2 of manufacturing method of semiconductor device> 27A to 34D. Note that the conditions of the manufacturing process and various treatments (heat treatment, plasma treatment, microwave treatment, and the like) common to those in FIGS. 27A to 34D can be referred to as appropriate for the manufacturing process conditions and various treatments (heat treatment, plasma treatment, microwave treatment, and the like) between the processes.

[0519] First, the insulator 215, the insulator 216, the insulator 221, the insulator 222, the oxide semiconductor 230, and the conductive film 242f are formed in this order by the manufacturing method shown in FIGS.

[0520] Next, referring to FIG. 32(A) to FIG. 32(D), a part of the conductive film 242f is removed to form a conductor, an insulator 275 is formed to cover the conductor, and an insulator 280 is further formed over the insulator 275. After that, a mask having an opening is formed in a region that will become a channel formation region in the transistor 200 by using a lithography method. Parts of the insulator 280, the insulator 275, and the conductor are removed using the mask (see FIG. 35(A) to FIG. 35(D)). As a result, an opening 291b is formed in the insulator 280 and the insulator 275. The conductor is also divided to form the conductor 242a and the conductor 242b. Note that no opening is provided in a region of the insulator 280 and the insulator 275 that overlaps with a region in which the capacitor 460 is formed.

[0521] Fig. 35(A) shows a plan view, Fig. 35(B) is a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in Fig. 35(A), Fig. 35(C) is a cross-sectional view corresponding to the portion indicated by the dashed line B3-B4 in Fig. 35(A), and Fig. 35(D) is a cross-sectional view of the portion indicated by the dashed line B5-B6 in Fig. 35(A). Note that in the plan view of Fig. 35(A), some elements have been omitted for clarity.

[0522] Next, an insulating film to become the insulator 250 is formed so as to fill the openings formed in the insulator 280 etc., and then a conductive film to become the conductor 260 is formed. After that, the insulating film to become the insulator 250 and the conductive film to become the conductor 260 are polished by CMP processing until the insulator 280 is exposed. In this way, the insulator 250 and the conductor 260 are formed (see FIGS. 36(A) to 36(D)).

[0523] Fig. 36(A) shows a plan view, Fig. 36(B) is a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in Fig. 36(A), Fig. 36(C) is a cross-sectional view corresponding to the portion indicated by the dashed line B3-B4 in Fig. 36(A), and Fig. 36(D) is a cross-sectional view of the portion indicated by the dashed line B5-B6 in Fig. 36(A). Note that in the plan view of Fig. 36(A), some elements have been omitted for clarity.

[0524] Next, the insulator 282, the insulator 283, and the insulator 285 are deposited in this order. Then, openings reaching the conductor 242b are provided in the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 (see FIGS. 37(A) to 37(D)). In FIGS. 37(A) to 37(D), an opening 294 is provided in a region overlapping with a region in which the capacitor 460 is formed.

[0525] Fig. 37(A) shows a plan view, Fig. 37(B) is a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in Fig. 37(A), Fig. 37(C) is a cross-sectional view corresponding to the portion indicated by the dashed line B3-B4 in Fig. 37(A), and Fig. 37(D) is a cross-sectional view of the portion indicated by the dashed line B5-B6 in Fig. 37(A). Note that in the plan view of Fig. 37(A), some elements have been omitted for clarity.

[0526] Next, an insulating film 454f is formed (see FIGS. 38A to 38D).

[0527] Fig. 38(A) shows a plan view, Fig. 38(B) is a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in Fig. 38(A), Fig. 38(C) is a cross-sectional view corresponding to the portion indicated by the dashed line B3-B4 in Fig. 38(A), and Fig. 38(D) is a cross-sectional view of the portion indicated by the dashed line B5-B6 in Fig. 38(A). Note that in the plan view of Fig. 38(A), some elements have been omitted for clarity.

[0528] Next, a conductive film to be the conductor 456b is formed, and then part of the conductive film and part of the insulating film 454f are removed by CMP processing to expose the top surface of the insulator 285, thereby forming the conductor 456 and the insulator 454 (see Figures 39(A) to 39(D)).

[0529] Next, openings reaching the conductor 242a are provided in the insulators 275, 280, 282, 283, and 285. Then, an insulating film that becomes the insulator 241a is formed, and the insulating film is anisotropically etched to form the insulator 241a in the opening that reaches the conductor 242a.

[0530] Next, a conductive film that becomes the conductor 240a is formed, and then a CMP process is performed to remove a portion of the conductive film that becomes the conductor 240a and expose the upper surface of the insulator 285. As a result, the conductive film remains only in the openings, and the conductor 240a has a flat upper surface (see FIGS. 39(A) to 39(D)).

[0531] 37A to 37D, when the opening 294 is formed, an opening may also be provided at the location where the conductor 240a and the insulator 241a are to be provided. After that, the insulating film 454f may also be provided in the opening, and the insulating film 454f at the bottom of the opening may be removed to form the insulator 241a. In this case, a conductive film to be the conductor 456b may also be provided in the opening, and CMP processing may be performed.

[0532] Next, the conductor 413 is formed over the conductor 240a.

[0533] In this manner, the semiconductor device shown in FIGS. 16A to 17B can be manufactured.

[0534] <Example 3 of manufacturing method of semiconductor device> A manufacturing method of the semiconductor device shown in Figures 18A to 19B will be described below. In the semiconductor device shown in Figures 18A to 19B, the conductor 242a and the conductor 242b have a layered structure, and the shapes of the stacked conductors are different from each other.

[0535] 27(A) to 31(D), the insulator 215, the insulator 216, the insulator 221, the insulator 222, the oxide semiconductor 230, and the conductive film 242f are formed in this order. Here, the conductive film 242f has a stacked structure of a conductive film to be the conductor 242a1 and the conductor 242b1, and a conductive film to be the conductor 242a2 and the conductor 242b2.

[0536] Next, in the conductive film 242f, portions of the conductive film that will become the conductor 242a2 and the conductor 242b2 are removed to form the conductor 242P2, and portions of the conductive film that will become the conductor 242a1 and the conductor 242b1 are removed to form the conductor 242P1 (see Figures 40(A) to 40(D)).

[0537] Next, an insulator 275 is deposited to cover the conductor 242P2, and an insulator 280 is deposited over the insulator 275 (see FIGS. 41A to 41D).

[0538] Next, the conductor 242P2, the insulator 275, and the insulator 280 are processed using lithography to form openings in the insulator 275 and the insulator 280 that reach the conductor 242P1 and the insulator 222, and the conductor 242P2 that overlaps with the openings is removed (see Figures 41(A) to 41(D)). Here, the conductor 242P2 is divided to form the conductor 242a2 and the conductor 242b2. Also, the upper surface of the portion of the conductor 242P1 that overlaps with the openings is exposed.

[0539] The openings are formed so as to overlap with the oxide semiconductor 230 in the region where the transistor 200 is formed and the region where the capacitor 460 is formed. For example, in FIGS. 41B to 41D, an opening 291c is formed in the region where the transistor 200 is formed, and an opening 292c is formed in the region where the capacitor 460 is formed.

[0540] Next, a mask 277 is formed over the insulator 280 and the conductor 242P1 (see FIGS. 42(A) to 42(D), 44(A), and 44(B)).

[0541] Fig. 42(A) shows a plan view, Fig. 42(B) is a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in Fig. 42(A), Fig. 42(C) is a cross-sectional view corresponding to the portion indicated by the dashed line B3-B4 in Fig. 42(A), Fig. 42(D) is a cross-sectional view of the portion indicated by the dashed line B5-B6 in Fig. 42(A), Fig. 44(A) is a cross-sectional view of the portion indicated by the dashed line B7-B8 in Fig. 42(A), and Fig. 44(B) is a cross-sectional view of the portion indicated by the dashed line B9-B10 in Fig. 42(A). Note that in the plan view of Fig. 42(A), some elements are omitted for clarity.

[0542] A resist mask can be used as the mask 277. Alternatively, a laminated structure of an SOC film, an SOG film, and a resist mask may be used.

[0543] The mask 277 preferably has an opening at a position overlapping with a region that will become a channel formation region in the transistor 200. For example, as shown in Figures 42(B) and 42(C), the mask 277 has an opening in a region that overlaps with the opening 291c, that is, in a region where the conductor 242P2 has been removed. Also, as shown in Figure 42(B), the opening is preferably provided on the inner side of the opening 291c in the channel length direction.

[0544] In addition, the mask 277 preferably covers a region that will become the capacitor 460. For example, as shown in FIGS.

[0545] Next, a region of the conductor 242P1 that is not covered by the mask 277 and the insulator 280 is removed (see FIGS. 43(A) to 43(D), 44(C), and 44(D)). Here, the conductor 242P1 is divided to form the conductor 242a1 and the conductor 242b1. In addition, in the region where the conductor 242P1 is removed, the top surface of the oxide semiconductor 230 that was covered by the conductor 242P1 is exposed.

[0546] By performing processing using the mask 277, in the region where the transistor 200 is formed, the ends of the conductor 242a1 a...

Claims

1. forming a columnar second insulator on the first insulator; forming a first oxide semiconductor covering a top surface of the first insulator, a side surface of the second insulator, and a top surface of the second insulator; removing a region of the first oxide semiconductor that covers an upper surface of the second insulator and a region of the first oxide semiconductor that covers an upper surface of the first insulator by anisotropic etching to form a second oxide semiconductor; removing the second insulator; forming a first conductor covering the second oxide semiconductor and the first insulator; forming a third insulator on the first conductor; providing a first opening in the third insulator, the first opening reaching the first conductor; providing a second opening in the third insulator, the second opening reaching the first conductor, and removing a region of the first conductor overlapping with the second opening to expose the second oxide semiconductor; and forming a second conductor and a third conductor; forming a fourth insulator covering the second oxide semiconductor, the second conductor, the third conductor, and the third insulator; forming a fourth conductor on the fourth insulator; removing a portion of the fourth conductor to form a fifth conductor located in the first opening and a sixth conductor located in the second opening; removing a portion of the fourth insulator to form a fifth insulator located in the first opening and a sixth insulator located in the second opening; A method for manufacturing a semiconductor device, wherein the third conductor is provided so as to overlap with the first opening.

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the first opening is provided so as to overlap with the second oxide semiconductor.

3. In claim 1, The method for manufacturing a semiconductor device, wherein the first opening and the second opening do not overlap.

4. In claim 1, the fifth conductor and the sixth conductor are formed by a first process for removing a region of the fourth conductor that covers an upper surface of the third insulator; the fifth insulator and the sixth insulator are formed by a second process of removing a region of the fourth insulator that covers an upper surface of the third insulator; The method for manufacturing a semiconductor device, wherein the first treatment and the second treatment are planarization treatments.

5. In claim 4, The method for manufacturing a semiconductor device, wherein the planarization treatment is performed using a chemical mechanical polishing method.

6. forming a columnar second insulator on the first insulator; forming a first oxide semiconductor covering a top surface of the first insulator, a side surface of the second insulator, and a top surface of the second insulator; removing a region of the first oxide semiconductor that covers an upper surface of the second insulator and a region of the first oxide semiconductor that covers an upper surface of the first insulator by anisotropic etching to form a second oxide semiconductor; removing the second insulator; forming a first conductor and a second conductor on the first conductor as a conductor having a stacked structure to cover the second oxide semiconductor and the first insulator; forming a third insulator on the second conductor; providing a first opening in the third insulator, the first opening reaching the second conductor, and a second opening reaching the second conductor; forming a third conductor and a fourth conductor by removing regions of the second conductor overlapping with the first opening and the second opening, respectively; forming a first mask on the third insulator and on the first conductor; removing a portion of a region of the first conductor that overlaps with the second opening by using the first mask to expose the second oxide semiconductor, thereby forming a fifth conductor overlapping with the third conductor and a sixth conductor overlapping with the fourth conductor; forming a fourth insulator covering the second oxide semiconductor, the fifth conductor, the sixth conductor, and the third insulator; forming a seventh conductor on the fourth insulator; removing a portion of the seventh conductor to form an eighth conductor located in the first opening and a ninth conductor located in the second opening; removing a portion of the fourth insulator to form a fifth insulator located in the first opening and a sixth insulator located in the second opening; The fifth conductor is provided so as to overlap with the first opening.

7. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the first opening is provided so as to overlap with the second oxide semiconductor.

8. In claim 6, 4. A method for manufacturing a semiconductor device, wherein the first conductor is tantalum nitride and the second conductor is tungsten.

9. In claim 6 or claim 8, A method for manufacturing a semiconductor device, wherein the first conductor is formed by a sputtering method.

10. In claim 6, a fifth conductor and a sixth conductor each having a region where an end of the fifth conductor protrudes to an inside of the second opening;

11. In claim 10, an end of the fifth conductor protruding inwardly from the second opening extends inwardly beyond an end of the third conductor; a sixth conductor having an end protruding inwardly from the second opening, the end extending inwardly beyond an end of the fourth conductor;

12. In claim 1 or claim 6, the first oxide semiconductor is formed by a step of forming a first semiconductor layer, a step of forming a second semiconductor layer on the first semiconductor layer, and a step of forming a third semiconductor layer on the second semiconductor layer; the first semiconductor layer and the third semiconductor layer are formed by an ALD method using a precursor containing indium and an oxidizing agent; The method for manufacturing a semiconductor device, wherein the second semiconductor layer is formed by a sputtering method using a sputtering target containing zinc.

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