Semiconductor device and display device

Abstract

To improve the reliability of a semiconductor device including an oxide semiconductor.SOLUTION: A semiconductor device includes a first insulating layer, an oxide semiconductor layer with a polycrystalline structure on the first insulating layer, a gate insulating layer on the oxide semiconductor layer, a buffer layer on the gate insulating layer, a gate wire on the buffer layer, and a second insulating layer on the gate wire. The oxide semiconductor layer includes a first region, a second region, and a third region arranged in a first direction. The electric resistivity of the second region is higher than that of the first region and lower than that of the third region. The third region has a sheet resistance of 1000 Ω / sq. or less.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a semiconductor device, particularly to a semiconductor device including an oxide semiconductor. [Background technology]

[0002] In recent years, oxide semiconductors have been attracting attention as materials constituting semiconductor devices, replacing amorphous silicon, polysilicon, and single crystal silicon. In particular, thin film transistors using oxide semiconductors as channels have been developed as semiconductor devices including oxide semiconductors (for example, Patent Documents 1 to 6). Thin film transistors using oxide semiconductors as channels can be formed with a simple structure and low-temperature process, similar to semiconductor devices using amorphous silicon as channels. Thin film transistors using oxide semiconductors as channels are known to have higher field-effect mobility than thin film transistors using amorphous silicon as channels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] A thin film transistor using a conventional oxide semiconductor may be deteriorated due to application of a high voltage between the source and drain, similar to a thin film transistor using a silicon semiconductor. Such deterioration may lead to a decrease in reliability, such as a shift in threshold voltage.

[0005] An object of the present invention is to improve the reliability of a semiconductor device including an oxide semiconductor. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present invention includes a first insulating layer, an oxide semiconductor layer having a polycrystalline structure on the first insulating layer, a gate insulating layer on the oxide semiconductor layer, a buffer layer on the gate insulating layer, a gate wiring on the buffer layer, and a second insulating layer on the gate wiring, wherein the oxide semiconductor layer has a first region, a second region, and a third region aligned in a first direction, the second region having an electrical resistivity higher than that of the first region and lower than that of the third region, and the third region having a sheet resistance of 1000 Ω / sq. or less.

[0007] A semiconductor device according to one embodiment of the present invention includes a first insulating layer, an oxide semiconductor layer having a polycrystalline structure on the first insulating layer, a gate insulating layer on the oxide semiconductor layer, a buffer layer on the gate insulating layer, a gate wiring on the buffer layer, and a second insulating layer on the gate wiring, wherein the oxide semiconductor layer has a first region, a second region, and a third region aligned in a first direction, the second region having a higher electrical resistivity than the first region and a lower electrical resistivity than the third region, and an etching rate of less than 3 nm / min when the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic plan view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1 is a schematic enlarged cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 4] 4 is a sequence diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 5] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 6] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 7] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 8] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 9] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 10] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 11] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 12] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 13] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 14] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 15] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 16] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 17]1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 18] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 19] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 20] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 21] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 22] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 23] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Figure 24] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device in one embodiment of the present invention. [Diagram 25] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Figure 26] 1 is a schematic plan view showing an overall configuration of a display device according to an embodiment of the present invention; [Figure 27] 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 28] 1 is a circuit diagram showing a configuration of a pixel circuit of a display device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual form. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, elements similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "down". In this way, for convenience of explanation, the terms "up" or "down" are used in the explanation, but for example, the substrate and the oxide semiconductor layer may be arranged so that their vertical relationship is reversed from that shown in the figure. In the following explanation, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. "Up" or "down" means the order of stacking in a structure in which multiple layers are stacked, and when it is expressed as "a pixel electrode above a transistor", it may be a positional relationship in which the transistor and the pixel electrode do not overlap in a planar view. On the other hand, when it is expressed as "a pixel electrode vertically above a transistor", it means a positional relationship in which the transistor and the pixel electrode overlap in a planar view.

[0011] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, the embodiments described below will be described by taking a liquid crystal display device including a liquid crystal layer and an organic EL display device including an organic EL layer as examples of display devices, but the structure in this embodiment can be applied to display devices including other electro-optical layers as described above.

[0012] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] In this specification, "the same" includes not only completely the same, but also substantially the same. "Substantially the same" refers to a case where the difference is not completely the same but is within a slight range that can be considered to be the same, for example, within an error range of ±5% (preferably ±3%).

[0014] First Embodiment A semiconductor device according to an embodiment of the present invention will be described below by taking a thin film transistor as an example. The semiconductor device according to the embodiment described below may be a thin film transistor used in a display device, or may be a thin film transistor used in an integrated circuit (IC) such as a microprocessor (MPU) or a memory circuit.

[0015] [Configuration of semiconductor device] The configuration of a semiconductor device 10 according to one embodiment of the present invention will be described. FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. FIG. 2 is a schematic plan view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. FIG. 3 is a schematic enlarged cross-sectional view showing the configuration of the semiconductor device 10 according to one embodiment of the present invention. Specifically, FIG. 1 corresponds to a cross-sectional view taken along the dashed dotted line indicated by A-A' in FIG. 2. FIG. 3 corresponds to a cross-sectional view showing an enlarged view of the vicinity of an end of the gate wiring 160 shown in FIG. 1.

[0016] First, the cross-sectional structure of a semiconductor device 10 will be described with reference to Fig. 1. As shown in Fig. 1, the semiconductor device 10 is provided above a substrate 100. The semiconductor device 10 includes a conductive layer 105, insulating layers 110 and 120, an oxide semiconductor layer 130, a gate insulating layer 140, a buffer layer 150, a gate wiring 160, insulating layers 170 to 190, a source wiring 201, and a drain wiring 203. When the source wiring 201 and the drain wiring 203 are not particularly distinguished from each other, they may be collectively referred to as a source-drain wiring 200.

[0017] In this specification, the term "wiring" refers to a conductive layer that electrically connects elements, circuits, or an element and a circuit. A wiring can also function as an electrode. For example, a portion of the gate wiring 160 that overlaps with the oxide semiconductor layer 130 functions as a gate electrode. Furthermore, portions of the source wiring 201 and the drain wiring that are connected to the oxide semiconductor layer 130 function as a source electrode and a drain electrode, respectively.

[0018] The conductive layer 105 is provided over the substrate 100. The conductive layer 105 functions as a light-shielding film for the oxide semiconductor layer .

[0019] The insulating layers 110 and 120 are provided on the substrate 100 and the conductive layer 105. The insulating layer 110 functions as a barrier film that blocks impurities diffusing from the substrate 100 toward the oxide semiconductor layer 130. The insulating layer 120 functions as a base for the oxide semiconductor layer 130 disposed above.

[0020] The oxide semiconductor layer 130 is provided on the insulating layer 120. The oxide semiconductor layer 130 has a channel region 130a, an LDD region 130b, and a conductive region 130c aligned in a first direction. The channel region 130a is a region of the oxide semiconductor layer 130 that overlaps with the gate wiring 160, and functions as a channel of a transistor. The LDD region 130b is a region having a lower resistance than the channel region, and functions as a resistance component against carrier movement. The conductive region 130c is a region called a source region or a drain region, and functions as a conductive layer connected to the source wiring 201 or the drain wiring 203. The conductive region 130c is a region having a lower resistance than the LDD region 130b. The LDD region 130b acts as a resistance component against carrier movement, as will be described in detail later.

[0021] The gate insulating layer 140 is provided on the oxide semiconductor layer 130. The gate insulating layer 140 is a dielectric layer disposed between the oxide semiconductor layer 130 and the gate wiring 160. In this embodiment, a silicon oxide layer is used as the gate insulating layer 140, but the present invention is not limited to this example.

[0022] The buffer layer 150 is provided on the gate insulating layer 140. As described later, the buffer layer 150 is used as a layer having a function of mitigating impurity injection into the oxide semiconductor layer 130 or a function of mitigating hydrogen diffusion into the oxide semiconductor layer 130. The buffer layer 150 is removed by etching, leaving a part around the gate wiring 160. Therefore, a part of the gate insulating layer 140 is not covered by the buffer layer 150 and is exposed from the buffer layer 150. In addition, a metal material such as titanium can be used as the metal. As described later, the buffer layer 150 preferably functions as an etching stopper when etching the gate wiring 160. That is, it is desirable that the selection ratio between the buffer layer 150 and the gate wiring 160 is large. In this embodiment, a silicon oxide layer is used as the buffer layer 150, but is not limited thereto.

[0023] The buffer layer 150 has a region overlapping with the gate wiring 160 (overlapping region 150a in FIG. 3) and a region not overlapping with the gate wiring 160 (non-overlapping region 150b in FIG. 3). That is, the width of the buffer layer 150 in the first direction (D1 direction) is wider than the width of the gate wiring 160. This will be described later with reference to FIG. 3. The LDD region 130b in the oxide semiconductor layer 130 is a region located vertically below the non-overlapping region 150b of the buffer layer 150 described above. In the example shown in FIG. 1, the length (width) of the LDD region 130b in the first direction is denoted as ΔL.

[0024] The gate wiring 160 faces the oxide semiconductor layer 130 via the gate insulating layer 140 and the buffer layer 150. That is, the gate insulating layer 140 and the buffer layer 150 are provided between the oxide semiconductor layer 130 and the gate wiring 160. The gate insulating layer 140 is in contact with the oxide semiconductor layer 130. The buffer layer 150 is in contact with the gate wiring 160. The gate wiring 160 functions as a light shielding film for the top gate of the semiconductor device 10 and the oxide semiconductor layer 130.

[0025] In this embodiment, the side surface of the gate wiring 160 is inclined, but the present invention is not limited to this example. However, by inclining the side surface of the gate wiring 160 to form a tapered shape, it is possible to reduce the occurrence of cracks in the insulating layer 170 formed on the gate wiring 160 and the coverage failure of the insulating layer 170.

[0026] The insulating layers 170-190 are provided on the gate insulating layer 140, the buffer layer 150, and the gate wiring 160. In this embodiment, the laminated structure formed by the insulating layers 170-190 may be called a passivation layer. The insulating layers 170-190 insulate the gate wiring 160 from the source-drain wiring 200. By providing the insulating layers 170-190, the parasitic capacitance between the gate wiring 160 and the source-drain wiring 200 can be reduced.

[0027] In this embodiment, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are used as the insulating layers 170, 180, and 190, respectively. The materials constituting the insulating layers 170 to 190 are not limited to this example, but it is preferable to have at least one insulating layer containing hydrogen, as described later. In this embodiment, a silicon oxide layer is used as the insulating layer 190, which functions as an etching stopper when patterning the source wiring 201 and the drain wiring 203.

[0028] 1, the insulating layer 170 constituting a part of the passivation layer contacts the gate wiring 160, the buffer layer 150 (specifically, a region of the buffer layer 150 that does not overlap with the gate wiring 160), and the gate insulating layer 140. The insulating layers 170 to 190 and the gate insulating layer 140 are provided with openings 171 and 173 that reach the oxide semiconductor layer 130.

[0029] The source wiring 201 is provided inside an opening 171 provided in the insulating layers 170-190 and the gate insulating layer 140. The source wiring 201 contacts the oxide semiconductor layer 130 (specifically, the conductive region 130c) at the bottom of the opening 171. The drain wiring 203 is provided inside an opening 173 provided in the insulating layers 170-190 and the gate insulating layer 140. The drain wiring 203 contacts the oxide semiconductor layer 130 (specifically, the conductive region 130c) at the bottom of the opening 173.

[0030] The operation of the semiconductor device 10 is mainly controlled by a gate voltage supplied to the gate wiring 160. An auxiliary voltage may be supplied to the conductive layer 105. That is, the conductive layer 105 may function as a gate wiring by supplying an auxiliary voltage. However, this is not the only example, and the conductive layer 105 may be used simply as a light-shielding film. When the conductive layer 105 is used simply as a light-shielding film, the conductive layer 105 may be in a floating state without being supplied with a specific voltage.

[0031] In this embodiment, a top-gate transistor in which a gate wiring 160 is provided above the oxide semiconductor layer 130 is exemplified as the semiconductor device 10, but the present invention is not limited to this configuration. For example, a dual-gate transistor in which the conductive layer 105 is used as a gate wiring in addition to the gate wiring 160 can also be used as the semiconductor device 10. When the conductive layer 105 is used as the gate wiring, the insulating layers 110 and 120 function as gate insulating layers. However, the above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0032] Next, the planar structure of the semiconductor device 10 will be described with reference to FIG. 2. As shown in FIG. 2, the first direction (D1 direction) is a direction connecting the source wiring 201 and the drain wiring 203, and corresponds to the direction in which carriers move. The length of the channel region 130a of the oxide semiconductor layer 130 in the first direction is the channel length (L), and the length of the channel region 130a in the second direction (D2 direction) is the channel width (W). The second direction is a direction intersecting the first direction. In this embodiment, the second direction indicates a direction perpendicular to the first direction, but depending on the layout of the oxide semiconductor layer 130, the first direction and the second direction may not be perpendicular to each other.

[0033] In this embodiment, the width of the conductive layer 105 in the first direction is wider than the width of the gate wiring 160. The reason for this configuration is to effectively prevent external light from entering the channel region 130a. However, this is not limited to this example, and the width of the conductive layer 105 may be the same as the width of the gate wiring 160.

[0034] 2 illustrates a configuration in which the source-drain wiring 200 does not overlap the conductive layer 105 and the gate wiring 160 in a plan view, but the present invention is not limited to this configuration. For example, the source-drain wiring 200 may overlap at least one of the conductive layer 105 and the gate wiring 160 in a plan view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration.

[0035] [Materials of each layer of semiconductor device] The substrate 100 can support each layer constituting the semiconductor device 10. For example, a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate, can be used as the substrate 100. A rigid substrate having no light-transmitting properties, such as a silicon substrate, can also be used as the substrate. Furthermore, a flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate, can also be used as the substrate. In order to improve the heat resistance of the substrate 100, impurities may be introduced into the above-mentioned resin substrate. Note that a substrate in which a silicon oxide film or a silicon nitride film is formed on the above-mentioned rigid substrate or flexible substrate can also be used as the substrate 100.

[0036] The conductive layer 105 can reflect or absorb external light. As described above, the conductive layer 105 has an area larger than the channel region 130a of the oxide semiconductor layer 130, and therefore can block external light incident on the channel region 130a. For example, aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), tungsten (W), or an alloy or compound thereof can be used as the conductive layer 105. In addition, when conductivity is not required, a resin layer made of black resin or the like can be used instead of the conductive layer 105. The conductive layer 105 may have a single-layer structure or a multilayer structure.

[0037] The insulating layers 110, 120, 170 to 190 have a role of preventing diffusion of impurities into the oxide semiconductor layer 130. The insulating layers 110, 120, 170 to 190 may have a single-layer structure or a multilayer structure. For example, silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), aluminum nitride (AlNx), etc. can be used as the insulating layers 110, 120, 170 to 190. Here, silicon oxynitride (SiOxNy) and aluminum oxynitride (AlOxNy) are silicon compounds and aluminum compounds, respectively, containing nitrogen (N) at a ratio (x>y) smaller than that of oxygen (O). Silicon nitride oxide (SiNxOy) and aluminum nitride oxide (AlNxOy) are silicon compounds and aluminum compounds that contain oxygen at a ratio (x>y) smaller than that of nitrogen. In this embodiment, silicon nitride (SiNx) is used for the insulating layers 110 and 180, and silicon oxide (SiOx) is used for the insulating layers 120, 170, and 190.

[0038] In this embodiment, the oxide semiconductor layer 130 has a polycrystalline structure. That is, the oxide semiconductor layer 130 in this embodiment is composed of an oxide semiconductor formed by using the Poly-OS technique. The Poly-OS technique refers to a technique for forming an oxide semiconductor layer having a polycrystalline structure. A metal oxide having semiconductor properties can be used as the oxide semiconductor layer 130. For example, an oxide semiconductor containing two or more metals including indium (In) is used as the oxide semiconductor layer 130. An element other than the above may be used as the oxide semiconductor layer 130. For example, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanoid may be used as the oxide semiconductor layer 130.

[0039] The ratio of indium to the entire oxide semiconductor layer 130 is preferably 50% or more. When the ratio of indium is large, the oxide semiconductor layer 130 is more likely to crystallize. In addition, it is preferable that the oxide semiconductor layer 130 contains gallium as a metal element other than indium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 130 is hardly inhibited by gallium.

[0040] In the oxide semiconductor layer 130 of this embodiment, the ratio of indium is 50% or more, and therefore oxygen vacancies are easily formed. On the other hand, oxygen vacancies are less likely to form in a crystalline oxide semiconductor than in an amorphous oxide semiconductor. Therefore, the oxide semiconductor layer 130 has the advantage that oxygen vacancies are less likely to form, even though the ratio of indium is 50% or more.

[0041] The gate insulating layer 140 includes an oxide having insulating properties. Specifically, silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), or the like can be used as the gate insulating layer 140. The gate insulating layer 140 preferably has a composition close to a stoichiometric ratio. In addition, the gate insulating layer 140 preferably has few defects. For example, the gate insulating layer 140 may be made of an oxide in which no defects are observed when evaluated by electron spin resonance (ESR). In this embodiment, a silicon oxide layer having a thickness of 100 nm to 200 nm is used as the gate insulating layer 140.

[0042] The buffer layer 150 may be made of an oxide having insulating or conductive properties, or a metal. The buffer layer 150 may be any layer having a function of mitigating impurity injection into the oxide semiconductor layer 130 or a function of mitigating hydrogen diffusion into the oxide semiconductor layer 130. For example, the thickness of the buffer layer 150 may be in the range of 5 nm to 100 nm. In other words, the thickness of the buffer layer 150 may be thinner than the thickness of the gate insulating layer 140.

[0043] When the buffer layer 150 is an insulating layer, the buffer layer 150 functions as a part of the gate insulating layer because it is located between the oxide semiconductor layer 130 and the gate wiring 160. Therefore, when determining the device parameters of the semiconductor device 10, it is necessary to take into consideration the film thickness and dielectric constant of each of the gate insulating layer 140 and the buffer layer 150.

[0044] The buffer layer 150 may be made of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), silicon nitride oxide (SiOxNy), an oxide semiconductor (OS), or a metal. The oxide semiconductor may be a metal oxide such as IGZO. The metal may be a metal material such as titanium.

[0045] The gate wiring 160, the source wiring 201, and the drain wiring 203 are conductive. For example, copper (Cu), silver (Ag), aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), or bismuth (Bi), or an alloy or compound thereof, can be used for each of the gate wiring 160, the source wiring 201, and the drain wiring 203. Each of the gate wiring 160, the source wiring 201, and the drain wiring 203 may have a single-layer structure or a multilayer structure.

[0046] (Configuration near the end of the gate wiring) The configuration of the vicinity of the end of the gate wiring 160 will be described with reference to FIG. 3. As shown in FIG. 3, the oxide semiconductor layer 130 is divided into a channel region 130a, an LDD region 130b, and a conductive region 130c. The channel region 130a is a region of the oxide semiconductor layer 130 located vertically below the gate wiring 160, that is, a region overlapping with the gate wiring 160. The conductive region 130c is a region of the oxide semiconductor layer 130 that does not overlap with the buffer layer 150. The LDD region 130b is a region located between the channel region 130a and the conductive region 130c. Specifically, the LDD region 130b is a region that does not overlap with the gate wiring 160 and overlaps with the buffer layer 150.

[0047] As described above, the buffer layer 150 is divided into an overlapping region 150a that overlaps with the gate wiring 160 and a non-overlapping region 150b that does not overlap with the gate wiring 160. In other words, the channel region 130a can be said to be a region located vertically below the overlapping region 150a. The LDD region 130b can be said to be a region located vertically below the non-overlapping region 150b.

[0048] Thus, the oxide semiconductor layer 130 excluding the channel region 130a has a region (LDD region 130b) overlapping both the gate insulating layer 140 and the buffer layer 150, and a region (conductive region 130c) overlapping the gate insulating layer 140 but not the buffer layer 150. From another perspective, as shown in FIG. 3, a distance H1 from the upper surface of the LDD region 130b to the upper surface of the insulating layer 170 is longer than a distance H2 from the upper surface of the conductive region 130c to the upper surface of the insulating layer 170. Here, "distance H1" and "distance H2" refer to the distance in the normal direction to the upper surface of the oxide semiconductor layer 130.

[0049] 3, above the LDD region 130b, the gate insulating layer 140, the buffer layer 150 (specifically, the non-overlapping region 150b), and the insulating layer 170 are stacked. Therefore, in a process of reducing the resistance of the oxide semiconductor layer 130 using ion implantation (a process of forming the conductive region 130c) described later, the implantation of impurities into the oxide semiconductor layer 130 is suppressed. By suppressing the implantation of impurities, the LDD region 130b is formed between the channel region 130a and the conductive region 130c.

[0050] 3, the length (width) of the non-overlapping region 150b in the first direction corresponds to the length (width) of the LDD region 130b in the first direction. In FIG. 3, the length of the LDD region 130b in the first direction is represented as ΔL. The length of the non-overlapping region 150b in the first direction can be appropriately set during the patterning process of the buffer layer 150, which will be described later.

[0051] In this embodiment, the length of the non-overlapping region 150b in the first direction, i.e., the length of the LDD region 130b in the first direction, is not particularly limited. However, as described above, the LDD region 130b functions as a resistance component against the movement of carriers, and if it is too long, it may cause a deterioration in the electrical characteristics of the semiconductor device 10. Therefore, it is preferable that the length of the LDD region 130b is 1.5 μm or less (preferably 1.0 μm or less). In addition, the shorter the length of the LDD region 130b, the lower the drain breakdown voltage of the semiconductor device 10. Therefore, from the viewpoint of improving reliability, it is preferable that the length of the LDD region 130b is 0.1 μm or more (preferably 0.3 μm or more, more preferably 0.5 μm or more).

[0052] According to this embodiment, during the process of forming the conductive region 130c in the oxide semiconductor layer 130 (process of reducing the resistance of the oxide semiconductor layer 130), the LDD region 130b having a lower resistance than the channel region 130a and a higher resistance than the conductive region 130c can be formed between the channel region 130a and the conductive region 130c. The LDD region 130b acts as a resistance component against the movement of carriers, and therefore the drain breakdown voltage of the semiconductor device 10 can be improved. That is, according to this embodiment, the reliability of the semiconductor device 10 including the oxide semiconductor layer 130 can be improved.

[0053] [Method of manufacturing semiconductor device] Next, a method for manufacturing the semiconductor device 10 in one embodiment of the present invention will be described. Fig. 4 is a sequence diagram showing the method for manufacturing the semiconductor device 10 in one embodiment of the present invention. Figs. 5 to 15 are schematic cross-sectional views showing the method for manufacturing the semiconductor device 10 in one embodiment of the present invention.

[0054] As shown in Figures 4 and 5, a conductive layer 105 is formed on a substrate 100 as a light-shielding layer, and insulating layers 110 and 120 are formed on the conductive layer 105 (step S1001 in Figure 4). As the insulating layer 110, for example, a silicon nitride layer is formed. As the insulating layer 120, for example, a silicon oxide layer is formed. The insulating layers 110 and 120 are formed by a CVD (Chemical Vapor Deposition) method. In this specification, forming a film on a substrate by a method such as a sputtering method or a CVD method is expressed as "forming a thin film", but is used in the same sense as the expression "forming a thin film".

[0055] By using a silicon nitride layer as the insulating layer 110, the insulating layer 110 can block impurities diffusing from, for example, the substrate 100 side toward the oxide semiconductor layer 130. The silicon oxide layer used as the insulating layer 120 may contain silicon oxide having the physical property of releasing oxygen by heat treatment.

[0056] In this embodiment, the film formation temperature is set to 350° C. when forming the insulating layers 110 and 120. In particular, the amount of oxygen contained in the insulating layer 120 (i.e., the silicon oxide layer) can be increased by setting the film formation temperature relatively low. As will be described later, the amount of hydrogen diffusing into the oxide semiconductor layer 130 can be reduced by increasing the amount of oxygen contained in the insulating layer 120. The film formation temperature for the insulating layers 110 and 120 may be set to 250° C. or higher and 500° C. or lower (preferably 300° C. or higher and 450° C. or lower, and more preferably 325° C. or higher and 400° C. or lower).

[0057] Next, as shown in FIGS. 4 and 6, a patterned oxide semiconductor layer 130 is formed on the insulating layer 120 (step S1002 in FIG. 4). In this embodiment, the process of forming the oxide semiconductor layer 130 is called "OS patterning." That is, the oxide semiconductor layer 130 is formed by performing a patterning process on the oxide semiconductor layer formed on the insulating layer 120. In the description of this embodiment, when "oxide semiconductor layer" is written without a reference symbol, it refers to the oxide semiconductor layer in a formed state (i.e., in an unprocessed state).

[0058] The oxide semiconductor layer may be etched by wet etching or dry etching, for example, using an acidic etchant (oxalic acid or hydrofluoric acid).

[0059] In this embodiment, the oxide semiconductor layer is formed by sputtering. In particular, the oxide semiconductor layer is formed by sputtering using a target formed of an oxide semiconductor having crystallinity. As described above, the oxide semiconductor layer is composed of a metal oxide having an indium ratio of 50% or more. The thickness of the oxide semiconductor layer to be formed is, for example, 10 nm to 100 nm, 15 nm to 70 nm, or 15 nm to 40 nm. The oxide semiconductor layer of this embodiment is amorphous when formed. That is, the oxide semiconductor layer 130 before the heat treatment (OS annealing) described later (that is, the oxide semiconductor layer 130 immediately after patterning) is amorphous.

[0060] When the oxide semiconductor layer 130 is crystallized by OS annealing, which will be described later, the oxide semiconductor layer 130 is preferably amorphous (a state in which the oxide semiconductor has few crystalline components) after being formed by a sputtering method and before performing OS annealing. In other words, the deposition conditions of the oxide semiconductor layer are preferably such that the oxide semiconductor layer immediately after deposition is not crystallized as much as possible. For example, when the oxide semiconductor layer is formed by a sputtering method, it is desirable to form the oxide semiconductor layer while controlling the temperature of the object to be formed (including the substrate 100 and the structure formed thereon). Note that, although the object to be formed is actually the object to be temperature-controlled, the structure formed on the substrate 100 is very thin, and therefore it may be considered that the temperature of the substrate 100 is substantially controlled. Therefore, in the following description, the object to be formed may be simply called a "substrate".

[0061] When a thin film is formed on a substrate by sputtering, ions generated in plasma and atoms recoiled from the sputtering target collide with an object to be formed (specifically, a structure formed on the substrate 100), causing the temperature of the substrate to rise during the thin film formation process. If the temperature of the substrate rises during the thin film formation process, the oxide semiconductor layer contains microcrystals immediately after formation, which inhibits crystallization by subsequent OS annealing.

[0062] In order to control the temperature of the substrate (i.e., the film formation temperature) when the oxide semiconductor layer is formed, for example, the thin film may be formed while cooling the substrate. For example, the substrate can be cooled from the surface opposite to the surface to be formed so that the film formation temperature becomes 100° C. or less, 70° C. or less, 50° C. or less, or 30° C. or less. In particular, the film formation temperature of the oxide semiconductor layer of this embodiment is preferably 50° C. or less. In this embodiment, the oxide semiconductor layer is formed at a film formation temperature of 50° C. or less, and the OS annealing described later is performed at a heating temperature of 400° C. or more. Thus, in this embodiment, the difference between the temperature when the oxide semiconductor layer is formed and the temperature when the OS annealing is performed on the oxide semiconductor layer 130 is preferably 350° C. or more. By forming the oxide semiconductor layer while cooling the substrate, an oxide semiconductor layer having a small amount of crystalline components immediately after the formation can be obtained.

[0063] In addition, the oxygen partial pressure in the chamber during film formation is preferably 1% to 10%, more preferably 1% to 5%, and further preferably 2% to 4%. When the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor layer due to excess oxygen contained in the oxide semiconductor. On the other hand, when the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor layer becomes nonuniform, and there is a risk that an oxide semiconductor layer containing many microcrystals or an oxide semiconductor layer that does not crystallize even after heat treatment is formed.

[0064] Next, after the oxide semiconductor layer 130 is formed by patterning, a heat treatment (OS annealing) is performed on the oxide semiconductor layer 130 (step S1003 in FIG. 4). In the OS annealing, the oxide semiconductor layer 130 is heat-treated in an air atmosphere at a temperature of 250° C. to 500° C. (preferably 300° C. to 500° C., more preferably 350° C. to 450° C.), thereby crystallizing the amorphous oxide semiconductor layer 130. The heating atmosphere is not limited to the air atmosphere, but is preferably an oxidizing atmosphere (an atmosphere containing oxygen). In addition, the oxidizing atmosphere is more preferably a moist atmosphere (specifically, a moist air atmosphere). In addition, the processing time of the heat treatment is 15 minutes to 120 minutes, or 30 minutes to 60 minutes, after the predetermined temperature is reached. In this embodiment, the temperature of the OS annealing is set to 350° C.

[0065] In this embodiment, the substrate on which the oxide semiconductor layer 130 is formed is placed in a heating furnace having a heating medium (e.g., a support plate) maintained at a preset temperature (250° C. or more and 500° C. or less, 350° C. in this embodiment). The support plate as a heating medium has a role of supporting the substrate and a role of heating the substrate and the coating (including the oxide semiconductor layer 130) formed on the substrate. When the substrate on which the oxide semiconductor layer 130 is formed is placed on the support plate, the oxide semiconductor layer 130 is rapidly heated. When the substrate is placed in the heating furnace, it is desirable to suppress the temperature drop of the support plate to within 15%, 10%, or 5% of the set temperature. In other words, it is desirable to control the temperature of the support plate so that the oxide semiconductor layer 130 reaches the set temperature in as short a time as possible.

[0066] As described above, in this embodiment, after the oxide semiconductor layer 130 is formed by performing a patterning process on the oxide semiconductor layer, the oxide semiconductor layer 130 is subjected to a crystallization process. This is because the etching resistance of the oxide semiconductor layer used in this embodiment is significantly increased by crystallization. That is, in this embodiment, since the oxide semiconductor layer 130 after OS annealing exhibits very high etching resistance against an etchant (etching solution or etching gas), the oxide semiconductor layer is patterned in advance before OS annealing. The etching resistance of the oxide semiconductor layer used in this embodiment will be described later.

[0067] Next, as shown in FIG. 4 and FIG. 7, the gate insulating layer 140 and the metal oxide layer 145 are formed (step S1004 in FIG. 4). For example, a silicon oxide layer is formed as the gate insulating layer 140. The gate insulating layer 140 is formed by a CVD method. It is desirable to form an insulating layer with as few defects as possible as the gate insulating layer 140. In this embodiment, the deposition temperature of the gate insulating layer 140 is 350° C. The thickness of the gate insulating layer 140 is, for example, 50 nm to 300 nm, 60 nm to 200 nm, or 70 nm to 150 nm. In this embodiment, the thickness of the gate insulating layer 140 is 100 nm.

[0068] The metal oxide layer 145 is formed by a sputtering method. By using a sputtering method to form the metal oxide layer 145, oxygen is implanted into the gate insulating layer 140 when the metal oxide layer 145 is formed. Therefore, the gate insulating layer 140 after the metal oxide layer 145 is formed contains a large amount of oxygen. The thickness of the metal oxide layer 145 is, for example, 5 nm to 100 nm, 5 nm to 50 nm, 5 nm to 30 nm, or 7 nm to 15 nm. In this embodiment, aluminum oxide is used as the metal oxide layer 145. As described above, aluminum oxide has a high barrier property against gas, so that it is possible to suppress the oxygen implanted into the gate insulating layer 140 from diffusing upward during the heat treatment described later.

[0069] When the metal oxide layer 145 is formed by a sputtering method, the process gas used in the sputtering remains in the film of the metal oxide layer 145. For example, when Ar is used as the process gas for the sputtering, Ar may remain in the film of the metal oxide layer 145. The remaining Ar can be detected by SIMS (Secondary Ion Mass Spectrometry) analysis of the metal oxide layer 145 or the like.

[0070] Next, in a state where the metal oxide layer 145 is formed on the gate insulating layer 140, a heat treatment (oxidation annealing) is performed to supply oxygen to the oxide semiconductor layer 130 (step S1005 in FIG. 4). In the process between the formation of the oxide semiconductor layer 130 and the formation of the gate insulating layer 140 on the oxide semiconductor layer 130, oxygen vacancies may occur on the upper surface and side surfaces of the oxide semiconductor layer 130. By the oxidation annealing, oxygen released from the insulating layer 120 and the gate insulating layer 140 is supplied to the oxide semiconductor layer 130, and the oxygen vacancies are repaired. The oxidation annealing may be performed at a temperature of 250° C. or higher and 500° C. or lower (preferably 300° C. or higher and 500° C. or lower, more preferably 350° C. or higher and 450° C. or lower). In this embodiment, the oxidation annealing is performed at a temperature of 350° C.

[0071] By the oxidation annealing, oxygen released from the insulating layer 120 and the gate insulating layer 140 is supplied to the oxide semiconductor layer 130. Although hydrogen may be released from the insulating layer 110 by the above-mentioned oxidation annealing, most of the released hydrogen is captured by oxygen contained in the insulating layer 120 before reaching the oxide semiconductor layer 130.

[0072] As described above, oxygen can be supplied to the oxide semiconductor layer 130 by the oxidation annealing. During the oxidation annealing, the upward diffusion of oxygen implanted into the gate insulating layer 140 is blocked by the metal oxide layer 145, and thus the oxygen is prevented from being released into the atmosphere. Therefore, oxygen can be efficiently supplied to the oxide semiconductor layer 130 during the oxidation annealing.

[0073] 4 and 8, after the oxidation annealing, the metal oxide layer 145 is etched and removed (step S1006 in FIG. 4). The etching of the metal oxide layer 145 may be wet etching or dry etching. In the wet etching, for example, diluted hydrofluoric acid (DHF) is used.

[0074] Next, a buffer layer 150 and a conductive layer 162 are formed on the gate insulating layer 140 (step S1007 in FIG. 4). The buffer layer 150 is formed by a CVD method or a sputtering method. In this embodiment, a silicon oxide layer having a thickness of 50 nm is formed as the buffer layer 150. The conductive layer 162 is formed by a sputtering method. In this embodiment, an alloy composed of molybdenum and tungsten is used as the conductive layer 162, but the present invention is not limited to this example. The conductive layer 162 is a conductive layer for forming the above-mentioned gate wiring 160.

[0075] 4 and 9, the buffer layer 150 and the conductive layer 162 are patterned (step S1008 in FIG. 4). Specifically, a resist mask 165 is formed on the conductive layer 162, and the buffer layer 150 and the conductive layer 162 are etched together using the resist mask 165 as a mask. The patterning process shown in step S1008 forms a patterned buffer layer 150 and conductive layer 161. The etching of the buffer layer 150 and the conductive layer 162 may be wet etching or dry etching.

[0076] In this embodiment, since both the gate insulating layer 140 and the buffer layer 150 are made of silicon oxide, if etching is continued after the buffer layer 150 is etched and patterned, the gate insulating layer 140 will also be etched. Therefore, in this embodiment, the etching time is controlled to prevent the gate insulating layer 140 from being etched excessively. If a material having a high selectivity with respect to the gate insulating layer 140 is used as the buffer layer 150, it is not necessary to control the etching time as described above.

[0077] 4 and 10, an ashing process is performed on the resist mask 165 (step S1009 in FIG. 4). By performing an ashing process (heating process in an oxygen atmosphere) on the resist mask 165, the volume of the resist mask 165 is reduced overall. Therefore, as shown in FIG. 10, when viewed in cross section, the end of the resist mask 165 recedes and a part of the conductive layer 161 is exposed. As will be described later, the amount of receding of the resist mask 165 corresponds to the length (ΔL) of the LDD region 130b shown in FIG. 1.

[0078] 4 and 11, the conductive layer 161 is etched using the resist mask 165 as a mask to form the gate wiring 160 (step S1010 in FIG. 4). The etching of the conductive layer 161 may be wet etching or dry etching. As shown in FIG. 11, a part of the buffer layer 150 is exposed by forming the gate wiring 160. The exposed region corresponds to the non-overlapping region 150b shown in FIG. 3.

[0079] When etching the conductive layer 161, it is preferable that the selection ratio between the buffer layer 150 and the conductive layer 161 is as large as possible. In this embodiment, the buffer layer 150 is thin, and if the selection ratio between the buffer layer 150 and the conductive layer 161 is small, there is a risk that the buffer layer 150 will disappear due to overetching after the gate wiring 160 is formed. Therefore, it is preferable to ensure a large selection ratio by combining the materials of the conductive layer 161 and the buffer layer 150.

[0080] 4 and 12, ion implantation is performed from above the gate wiring 160 and the buffer layer 150 to add impurities to the oxide semiconductor layer 130 (step S1011 in FIG. 4). As the impurities, phosphorus, boron, argon, or the like can be used. The purpose of adding the impurities is to create oxygen vacancies in a partial region of the oxide semiconductor layer 130 to increase the conductivity, so that it is preferable to use an element with a large atomic radius as the impurity.

[0081] In this embodiment, an example of adding impurities by ion implantation is shown, but ion doping may also be used. In this embodiment, boron is added by ion implantation. The conditions for ion implantation in this embodiment are an acceleration voltage of 30 keV and a dose of 1×10 15 / cm 2 In the present embodiment, the ion implantation is performed while the resist mask 165 is left, but the ion implantation may be performed using the gate wiring 160 as a mask after removing the resist mask 165.

[0082] As shown in FIG. 12, when the impurity ions are implanted into the oxide semiconductor layer 130, the LDD region 130b and the conductive region 130c are formed in the oxide semiconductor layer 130. At this time, the region in which the impurity is not implanted and the original state is maintained functions as the channel region 130a. The impurity is added to the conductive region 130c through the gate insulating layer 140. On the other hand, the impurity is added to the LDD region 130b through the buffer layer 150 and the gate insulating layer 140. Therefore, the concentration of the impurity added to the LDD region 130b is relatively lower than the concentration of the impurity added to the conductive region 130c. For example, by appropriately controlling the film thickness of the buffer layer 150, the concentration of the impurity added to the LDD region 130b can be lower by one order of magnitude or more than the concentration of the impurity added to the conductive region 130c. As a result, the conductivity of the LDD region 130b is lower than the conductivity of the conductive region 130c. In other words, the electrical resistivity of the LDD region 130b is higher than the electrical resistivity of the conductive region 130c, or in further terms, the sheet resistance of the LDD region 130b is higher than the sheet resistance of the conductive region 130c.

[0083] 12 functions as the source region and drain region of the semiconductor device 10, as described above. When the oxide semiconductor layer 130 of this embodiment is made to have a low resistance by introducing oxygen vacancies, the resistance value is significantly lower than that of a conventional oxide semiconductor layer. Specifically, the resistance value (sheet resistance) of the conductive region 130c in the oxide semiconductor layer 130 of this embodiment is 1000 Ω / sq. or less (preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less).

[0084] Next, as shown in FIG. 4 and FIG. 13, the insulating layers 170 to 190 are formed as passivation layers on the gate insulating layer 140, the buffer layer 150, and the gate wiring 160 (step S1012 in FIG. 4). The insulating layers 170 to 190 are formed by a CVD method. In this embodiment, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are formed as the insulating layers 170 to 190, respectively. The deposition temperature of the insulating layers 170 to 190 is preferably set to 250° C. or more and 500° C. or less (preferably 300° C. or more and 450° C. or less, more preferably 325° C. or more and 400° C. or less). In this embodiment, the deposition temperature of the insulating layers 170 to 190 is set to 350° C. The thickness of the insulating layers 170 to 190 may be set to 30 nm or more and 500 nm or less. In this embodiment, the thickness of the insulating layers 170 to 190 is set to 100 nm, 300 nm, and 30 nm, respectively. However, the configuration of the passivation layer is not limited to the above example. For example, the passivation layer may have a single layer structure, a two-layer structure, or a laminated structure of four or more layers. The insulating layer used in the passivation layer may be any insulating layer selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or silicon nitride oxide (SiOxNy).

[0085] The insulating layers 170-190 function as passivation layers (protective layers) to prevent the intrusion of gas and moisture from the outside. As described above, they also serve to insulate and separate the gate wiring 160 from the source-drain wiring 200. Furthermore, in this embodiment, a silicon nitride layer is used as the insulating layer 180, which can promote the reduction in resistance of the conductive region 130c of the oxide semiconductor layer 130.

[0086] When the silicon nitride layer is formed by the CVD method, ammonia is used as a raw material gas, so that the insulating layer 180 contains a large amount of hydrogen. Therefore, when the insulating layer 180 is formed or after the insulating layer 180 is formed, the insulating layer 180 is heated, so that hydrogen diffuses from the insulating layer 180. The diffused hydrogen reaches the oxide semiconductor layer 130 via the gate insulating layer 140 and the insulating layer 170. At this time, hydrogen is trapped in the oxygen vacancies in the conductive region 130c formed by the above-mentioned ion implantation, forming a donor level. This promotes the reduction in resistance of the conductive region 130c.

[0087] 4 and 14, openings 171 and 173 are formed in the gate insulating layer 140 and the insulating layers 170 to 190 (Step S1013 in FIG. 4). The openings 171 and 173 expose a part of the conductive region 130c.

[0088] 4 and 15, source / drain wiring 200 is formed on conductive region 130c exposed by openings 171 and 173 and on insulating layer 180 (step S1014 in FIG. 4). Through the process described above, the semiconductor device 10 shown in FIG. 1 is completed.

[0089] In the semiconductor device 10 manufactured by the manufacturing method of this embodiment, when the channel length L of the channel region 130a is in the range of 1 μm to 4 μm and the channel width of the channel region 130a is in the range of 2 μm to 25 μm, the field effect mobility is 20 cm 2 / Vs or more, 25cm 2 / Vs or more, or 30cm 2 In this embodiment, the "field effect mobility" refers to the field effect mobility in the saturation region of the semiconductor device 10, and means the maximum value of the field effect mobility in a region where the potential difference (Vd) between the source wiring 201 and the drain wiring 203 is greater than the voltage (Vg) supplied to the gate wiring 160 minus the threshold voltage (Vth) of the semiconductor device 10 (Vg-Vth).

[0090] (Etching resistance of oxide semiconductor layer) As described above, the oxide semiconductor layer used in the semiconductor device 10 of the present embodiment has excellent etching resistance. Specifically, the oxide semiconductor layer of the present embodiment is hardly etched by an etchant (etching solution) for wet etching, and has a very small etching rate.

[0091] Specifically, when the oxide semiconductor layer of this embodiment is etched using an etching solution containing phosphoric acid as a main component (e.g., a mixed acid etching solution) in a temperature range of 35° C. to 45° C. (e.g., a range including an error of ±5° C. at a set temperature of 40° C.), the etching rate is less than 3 nm / min, less than 2 nm / min, or less than 1 nm / min. The ratio of phosphoric acid in the etching solution is 50% or more, 60% or more, or 70% or more. The etching solution may contain nitric acid and acetic acid in addition to phosphoric acid. In contrast, the oxide semiconductor layer having an amorphous structure of this embodiment (the oxide semiconductor layer before OS annealing) has an etching rate of 100 nm / min or more when etched using the above-mentioned etching solution in a temperature range of 35° C. to 45° C.

[0092] Furthermore, when the oxide semiconductor layer of this embodiment is etched at room temperature (which means "25°C±5°C" here) using an etching solution containing hydrogen fluoride (e.g., a hydrofluoric acid solution), the etching rate is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. The proportion of hydrogen fluoride in the etching solution is 0.5%. In contrast, the oxide semiconductor layer having an amorphous structure of this embodiment has an etching rate of 15 nm / min or more when etched at room temperature using the above-mentioned etching solution.

[0093] Here, the etching rates of various oxide semiconductor layers are shown in Table 1. Table 1 shows the etching rates of the prepared samples with respect to the mixed acid etching solution and 0.5% hydrofluoric acid solution. As the mixed acid etching solution, "Mixed Acid AT-2F (product name)" from Rasa Kogyo Co., Ltd. was used. The ratio of phosphoric acid in the mixed acid etching solution was about 65%. In addition, the temperature of the mixed acid etching solution when etching each sample was set to 40°C, and the temperature of the 0.5% hydrofluoric acid solution was set to 22°C. In Table 1, Sample 1 is an oxide semiconductor layer having a polycrystalline structure according to the present embodiment, Sample 2 is an oxide semiconductor layer having an amorphous structure according to the present embodiment, and Sample 3 is an oxide semiconductor layer containing indium gallium zinc oxide (IGZO) with an indium ratio of less than 50%.

[0094] [Table 1]

[0095] As shown in Table 1, Sample 1 was hardly etched even when using a mixed acid etching solution, and was etched at most about 2 nm / min even when using a 0.5% hydrofluoric acid solution. The etching rate of Sample 1 was 1 / 100 or less with the mixed acid etching solution and about 1 / 10 or less with the 0.5% hydrofluoric acid solution compared to the etching rate of Sample 2. Furthermore, the etching rate of Sample 1 was 1 / 100 or less with the mixed acid etching solution compared to the etching rate of Sample 3. Thus, it was found that Sample 1 has significantly better etching resistance than Samples 2 and 3.

[0096] Such excellent etching resistance of the oxide semiconductor layer of this embodiment is a property that cannot be obtained in an oxide semiconductor layer having a conventional polycrystalline structure that is produced by a process at or below 500° C. Although the detailed mechanism is unclear, such excellent etching resistance can be said to be evidence that the oxide semiconductor layer of this embodiment has a polycrystalline structure different from the conventional one.

[0097] (Modification of the first embodiment) In the above-described method for manufacturing the semiconductor device 10, an example has been shown in which the volume change of the resist mask 165 is utilized when forming the gate wiring 160, but the present invention is not limited to this example, and the resist mask may be formed in two separate steps. A modified example of the first embodiment will be described below.

[0098] 16 and 17 are schematic cross-sectional views showing a manufacturing method of semiconductor device 10 in a modified example of one embodiment of the present invention. The manufacturing method of semiconductor device 10 in this modified example is the same as the processes shown in the above-mentioned Figures 5 to 8 and Figures 12 to 15. In other words, the manufacturing method of this modified example corresponds to the manufacturing method described in the first embodiment, except for the processes shown in Figures 9 to 11.

[0099] 5 to 8 (steps S1001 to S1007 in FIG. 4), the conductive layer 162 is patterned as shown in FIG. 16. Specifically, a resist mask 165 is formed on the conductive layer 162, and the conductive layer 162 is etched to form the gate wiring 160. As described above, by increasing the selection ratio between the buffer layer 150 and the gate wiring 160, the buffer layer 150 can be used as an etching stopper when the gate wiring 160 is formed.

[0100] 17, the resist mask 165 is removed and a new resist mask 166 is formed, and then the buffer layer 150 is patterned. Specifically, the resist mask 166 is formed on the buffer layer 150 and the gate wiring 160, and the buffer layer 150 is etched to form a pattern constituted by the buffer layer 150.

[0101] 17, in a cross-sectional view along the first direction (see FIG. 1), the width of the resist mask 166 is larger than the width of the gate wiring 160. Therefore, in the pattern formed by the buffer layer 150, a region that does not overlap with the gate wiring 160, that is, the non-overlapping region 150b shown in FIG. 3, is formed. Therefore, the distance from the side surface of the gate wiring 160 to the side surface of the resist mask 166 determines the length of the LDD region 130b.

[0102] When the process shown in FIG. 17 is completed, the semiconductor device 10 of the first embodiment is completed through processes similar to those shown in the above-mentioned FIGS.

[0103] As described above, the method for manufacturing the semiconductor device 10 of the first embodiment can also perform the patterning process of the buffer layer 150 and the gate wiring 160 separately. In this case, the length of the LDD region 130b (i.e., the length of the non-overlapping region 150b of the buffer layer 150) can be controlled by the resolution of photolithography, which is suitable for miniaturization of the semiconductor device 10.

[0104] Second Embodiment In this embodiment, an example in which the configuration of the gate insulating layer 140 is different from that of the first embodiment will be described. Specifically, the semiconductor device 10a of this embodiment is configured such that a part of the gate insulating layer 140 is removed and the conductive region 130c of the oxide semiconductor layer 130 is not covered with the gate insulating layer 140. In the description of this embodiment, parts common to the first embodiment are indicated by the same reference numerals in the drawings, and the description will focus on parts different from the first embodiment.

[0105] [Configuration of semiconductor device] The configuration of the semiconductor device 10a according to one embodiment of the present invention will be described. FIG. 18 is a schematic cross-sectional view showing the configuration of the semiconductor device 10a according to one embodiment of the present invention. The semiconductor device 10a differs from the semiconductor device 10 shown in FIG. 1 in that a part of the gate insulating layer 140, specifically, a part of the gate insulating layer 140 that does not overlap with the buffer layer 150, is removed. Therefore, the conductive region 130c is exposed from the gate insulating layer 140. In other words, the conductive region 130c does not overlap with the gate insulating layer 140 and is in contact with the insulating layer 170. The insulating layer 170 is in contact with not only the conductive region 130c but also the side surface of the gate insulating layer 140 and the insulating layer 120.

[0106] Since the gate insulating layer 140 exists only vertically below the buffer layer 150, the side of the gate insulating layer 140 and the side of the buffer layer 150 in the first direction coincide with each other. However, "the side faces coincide" includes not only the case where they coincide completely, but also the case where they do not coincide within a range that can be considered as substantially coinciding (for example, the amount of deviation between the side faces is within a range of 3 nm to 15 nm). As shown in FIG. 18, the difference between the side faces of the gate wiring 160 and the buffer layer 150 in the first direction (i.e., the difference between the side faces of the gate wiring 160 and the gate insulating layer 140) corresponds to the length (ΔL) of the LDD region 130b.

[0107] [Method of manufacturing semiconductor device] Next, a method for manufacturing the semiconductor device 10a according to one embodiment of the present invention will be described. Figures 19 to 22 are schematic cross-sectional views showing a method for manufacturing the semiconductor device 10a according to one embodiment of the present invention.

[0108] The manufacturing method of the semiconductor device 10a of this embodiment is the same as the first embodiment in the processes shown in Figures 5 to 8 and Figures 14 and 15 (however, the device structure to be processed is different in the processes shown in Figures 14 and 15). In other words, the manufacturing method of this embodiment corresponds to the manufacturing method described in the first embodiment, except for the processes shown in Figures 9 to 13.

[0109] After the conductive layer 162 is formed by the process of FIG. 5 to FIG. 8 (steps S1001 to S1007 in FIG. 4) of the first embodiment, the conductive layer 162, the buffer layer 150, and the gate insulating layer 140 are patterned as shown in FIG. 19. Specifically, a resist mask 165 is formed on the conductive layer 162, and etching is performed all at once from the conductive layer 162 to the gate insulating layer 140 to expose a part of the oxide semiconductor layer 130. As described above, the etching resistance of the oxide semiconductor layer 130 is very high, and therefore the selectivity with respect to the gate insulating layer 140 is large. However, in this embodiment, since both the gate insulating layer 140 and the insulating layer 120 are formed of silicon oxide layers, it is preferable to perform time control so as not to etch the insulating layer 120 excessively.

[0110] Next, as shown in Fig. 20, an ashing process is performed on the resist mask 165. The process shown in Fig. 20 corresponds to step S1009 in Fig. 4 of the first embodiment. By performing the ashing process on the resist mask 165, the volume of the resist mask 165 is reduced overall. The amount of recession of the resist mask 165 corresponds to the length (ΔL) of the LDD region 130b shown in Fig. 1.

[0111] 21, the conductive layer 161 is etched using the resist mask 165 as a mask to form the gate wiring 160. The process shown in FIG. 21 corresponds to step S1010 in FIG. 4 of the first embodiment. By forming the gate wiring 160, a part of the buffer layer 150 is exposed. The exposed region corresponds to the non-overlapping region 150b shown in FIG. 3.

[0112] 22, insulating layers 170-190 are formed as passivation layers on the oxide semiconductor layer 130, the gate insulating layer 140, the buffer layer 150, and the gate wiring 160. The process shown in FIG. 22 corresponds to step S1012 in FIG. 4 of the first embodiment. In this embodiment, as in the first embodiment, a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer are formed as the insulating layers 170-190, respectively.

[0113] Here, unlike the first embodiment, the present embodiment does not perform a process of adding impurities to the oxide semiconductor layer 130 before forming the insulating layers 170-190 (a process corresponding to step S1011 in FIG. 4 of the first embodiment). Instead, in the present embodiment, the process of forming the insulating layers 170-190 can reduce the resistance of a part of the oxide semiconductor layer 130.

[0114] As shown in FIG. 22, when the insulating layers 170-190 are formed, the LDD region 130b and the conductive region 130c are formed in the oxide semiconductor layer 130. As described in the first embodiment, the insulating layer 180 contains a large amount of hydrogen, and hydrogen diffuses from the insulating layer 180 when the insulating layer 180 is heated during film formation. At this time, in this embodiment, the gate insulating layer 140 does not exist on a part of the oxide semiconductor layer 130 (a part that becomes the conductive region 130c), so that the oxide semiconductor layer 130 and the insulating layer 170 are in contact with each other. That is, hydrogen diffused from the insulating layer 180 easily reaches the oxide semiconductor layer 130 through the insulating layer 170. Therefore, the conductive region 130c is formed in the region of the oxide semiconductor layer 130 that is in contact with the insulating layer 170.

[0115] In the region of the oxide semiconductor layer 130 that does not overlap with the gate wiring 160 and overlaps with the gate insulating layer 140 and the buffer layer 150 (i.e., the region that overlaps with the non-overlapping region 150b shown in FIG. 3), hydrogen diffuses at a concentration relatively lower than that of the conductive region 130c. Therefore, in the region of the oxide semiconductor layer 130 that does not overlap with the gate wiring 160 and overlaps with the gate insulating layer 140 and the buffer layer 150, an LDD region 130b having a higher resistance value than the conductive region 130c is formed. Note that, in the region of the oxide semiconductor layer 130 that is positioned vertically below the gate wiring 160, hydrogen hardly diffuses, so the original state is maintained and the region functions as a channel region.

[0116] In the semiconductor device 10a of this embodiment, similarly to the semiconductor device 10 of the first embodiment, the conductivity of the LDD region 130b is smaller than that of the conductive region 130c. In other words, the resistance value (e.g., sheet resistance) of the LDD region 130b is larger than the resistance value of the conductive region 130c. Specifically, the resistance value (sheet resistance) of the conductive region 130c in the oxide semiconductor layer 130 of this embodiment is 1000Ω / sq. or less (preferably 500Ω / sq. or less, more preferably 250Ω / sq. or less).

[0117] After the process shown in FIG. 22 is completed, the semiconductor device 10a of the second embodiment is completed through processes similar to those of the first embodiment shown in FIGS.

[0118] In the manufacturing method of the semiconductor device 10a of the second embodiment, the impurity doping process shown in Fig. 12 of the first embodiment can be omitted by simply adding a process of etching the gate insulating layer 140 consecutively to the process shown in Fig. 19. Therefore, according to this embodiment, the manufacturing process of the semiconductor device can be simplified compared to the first embodiment.

[0119] (Modification of the second embodiment) In the above-described method for manufacturing the semiconductor device 10a, an example has been shown in which the volume change of the resist mask 165 is utilized when forming the gate wiring 160, but the present invention is not limited to this example, and the resist mask may be formed in two separate steps. A modified example of the second embodiment will be described below.

[0120] 23 and 24 are schematic cross-sectional views showing a method for manufacturing a semiconductor device 10a according to a modified example of the embodiment of the present invention. The method for manufacturing the semiconductor device 10a according to this modified example corresponds to the manufacturing method described in the second embodiment, except for the processes shown in FIGS. 19 to 21.

[0121] First, after the conductive layer 162 is formed by the process of the first embodiment shown in FIGS. 5 to 8 (steps S1001 to S1007 in FIG. 4), the conductive layer 162 is patterned as shown in FIG. 23. Specifically, a resist mask 165 is formed on the conductive layer 162, and the conductive layer 162 is etched to form the gate wiring 160. As described above, by increasing the selection ratio between the buffer layer 150 and the gate wiring 160, the buffer layer 150 can be used as an etching stopper when the gate wiring 160 is formed.

[0122] 24, the resist mask 165 is removed and a new resist mask 166 is formed, and then the buffer layer 150 and the gate insulating layer 140 are patterned. Specifically, the resist mask 166 is formed on the buffer layer 150 and the gate wiring 160, and the buffer layer 150 and the gate insulating layer 140 are etched to form a pattern constituted by the buffer layer 150 and the gate insulating layer 140. By the process shown in FIG. 24, a part of the oxide semiconductor layer 130 (a region that will later become the conductive region 130c) is exposed.

[0123] 24, in a cross-sectional view along the first direction (see FIG. 1), the width of the resist mask 166 is larger than the width of the gate wiring 160. Therefore, in the pattern formed by the buffer layer 150, a region that does not overlap with the gate wiring 160, that is, the non-overlapping region 150b shown in FIG. 3, is formed. Therefore, the distance from the side surface of the gate wiring 160 to the side surface of the resist mask 166 determines the length of the LDD region 130b.

[0124] 24 is completed, the resist mask 166 is removed, and then, similarly to the process shown in Fig. 22, insulating layers 170-190 are formed, and a channel region 130a, an LDD region 130b, and a conductive region 130c are formed in the oxide semiconductor layer 130. Thereafter, the semiconductor device 10a of the second embodiment is completed through processes similar to those of the first embodiment shown in Figs. 14 and 15.

[0125] As described above, the method for manufacturing the semiconductor device 10a of the second embodiment can also perform the patterning process of the buffer layer 150 and the gate wiring 160 separately. In this case, the length of the LDD region 130b (i.e., the length of the non-overlapping region 150b of the buffer layer 150) can be controlled by the resolution of photolithography, which is suitable for miniaturizing the semiconductor device 10a.

[0126] Third embodiment In the first and second embodiments, an example in which the oxide semiconductor layer 130 is provided so as to be in contact with the insulating layer 120 has been shown, but it is also possible to provide a metal oxide layer between the insulating layer 120 and the oxide semiconductor layer 130. In the description of this embodiment, parts common to the first embodiment are indicated by the same reference numerals in the drawings, and the description will focus on parts different from the first embodiment.

[0127] Fig. 25 is a schematic cross-sectional view showing the configuration of a semiconductor device 10b according to one embodiment of the present invention. The basic structure is similar to that of the semiconductor device 10 shown in Fig. 1, but the semiconductor device 10b according to this embodiment has a metal oxide layer 125 disposed between the insulating layer 120 and the oxide semiconductor layer 130. In this embodiment, the metal oxide layer 125 uses a metal oxide containing aluminum as a main component (specifically, an aluminum oxide (AlOx) layer). The metal oxide layer 125 can be formed by, for example, a sputtering method.

[0128] 25, in this embodiment, the metal oxide layer 125 has the same pattern shape as the oxide semiconductor layer 130. In this embodiment, after the metal oxide layer 125 and the oxide semiconductor layer 130 are continuously laminated, the processes of steps S1002 and S1003 in FIG. 4 are performed to obtain the oxide semiconductor layer 130 having a polycrystalline structure. Thereafter, the metal oxide layer 125 is etched using the oxide semiconductor layer 130 as a mask, whereby the metal oxide layer 125 having the same pattern shape as the oxide semiconductor layer 130 can be formed.

[0129] The thickness of the metal oxide layer 125 is, for example, 1 nm to 10 nm, 1 nm to 4 nm, or 1 nm to 3 nm. In this embodiment, the thickness of the metal oxide layer 125 is 3 nm. In this embodiment, the aluminum oxide layer used as the metal oxide layer 125 has high barrier properties against gas even when it has a thickness of 1 nm to 10 nm. Therefore, the metal oxide layer 125 of this embodiment blocks hydrogen and oxygen released from the insulating layer 120 and prevents hydrogen and oxygen released from below from reaching the oxide semiconductor layer 130.

[0130] As described above, the oxide semiconductor layer 130 of the present embodiment has an indium ratio of 50% or more, and therefore can realize a semiconductor device with high mobility, but oxygen is easily reduced and oxygen vacancies are easily formed in the layer. Therefore, blocking hydrogen released from the insulating layer 120 by the metal oxide layer 125 is preferable in terms of suppressing the reduction reaction of the oxide semiconductor layer 130.

[0131] In addition, after the oxide semiconductor layer 130 is formed, in the course of various manufacturing processes (such as a patterning process), more oxygen vacancies are formed on the upper side of the oxide semiconductor layer 130 than on the lower side. That is, the oxygen vacancies in the oxide semiconductor layer 130 are distributed unevenly in the thickness direction. In this case, if a sufficient amount of oxygen is supplied to repair the oxygen vacancies formed on the upper side of the oxide semiconductor layer 130, excessive oxygen is supplied to the lower side of the oxide semiconductor layer 130. As a result, the excessive supply of oxygen may form a defect level different from the oxygen vacancies, which may lead to phenomena such as characteristic fluctuations in reliability tests or a decrease in field effect mobility. Therefore, it can be said that blocking oxygen released from the insulating layer 120 by the metal oxide layer 125 is also preferable in terms of suppressing the excessive supply of oxygen to the lower side of the oxide semiconductor layer 130.

[0132] 1, oxygen can be supplied to the upper and side surfaces of the oxide semiconductor layer 130, which have a relatively large amount of oxygen vacancies, while suppressing the supply of oxygen to the lower surface of the oxide semiconductor layer 130, which has a small amount of oxygen vacancies. Therefore, oxygen can be efficiently supplied to the oxide semiconductor layer 130 during the oxidation annealing, and the reliability of the semiconductor device 10 can be improved.

[0133] In this embodiment, an example in which the present invention is applied to the semiconductor device 10 shown in FIG. 1 of the first embodiment has been described, but the present invention can also be applied to the semiconductor device 10a shown in FIG. 18 of the second embodiment.

[0134] Fourth embodiment In the fourth embodiment, a display device 20 using the semiconductor device according to one embodiment of the present invention will be described. In the following embodiment, a case will be described in which the semiconductor device 10 described in the first embodiment is used as an element constituting the circuit of a liquid crystal display device. However, the present invention is not limited to this example, and the semiconductor device described in the second or third embodiment may be used as an element constituting the circuit of a liquid crystal display device.

[0135] [Display device overview] FIG. 26 is a schematic plan view showing the overall configuration of a display device 20 according to an embodiment of the present invention. As shown in FIG. 26, the display device 20 has an array substrate 300, a seal part 310, a counter substrate 320, a flexible printed circuit (FPC) substrate 330, and an IC chip 340. The array substrate 300 and the counter substrate 320 are bonded together by the seal part 310. In a liquid crystal region 22 surrounded by the seal part 310, a plurality of pixels 21 are arranged in a matrix. The liquid crystal region 22 is an area that overlaps with a liquid crystal element 311, which will be described later, in a plan view. Note that, with respect to the pixels 21, the letters "R", "G", and "B" indicate that they correspond to pixels for displaying red, green, and blue, respectively.

[0136] The seal area 24 in which the seal portion 310 is provided is the area surrounding the liquid crystal area 22. The flexible printed circuit board 330 is provided in the terminal area 26. The terminal area 26 is an area of ​​the array substrate 300 exposed from the counter substrate 320, and is provided outside the seal area 24. The outside of the seal area 24 means the outside of the area in which the seal portion 310 is provided and the area surrounded by the seal portion 310. The IC chip 340 is provided on the flexible printed circuit board 330. The IC chip 340 supplies signals for driving each pixel circuit 301 (see FIG. 27) arranged in each pixel 21.

[0137] [Circuit configuration of display device] Fig. 27 is a block diagram showing a circuit configuration of a display device 20 according to an embodiment of the present invention. As shown in Fig. 27, a plurality of pixel circuits 301 are arranged in a matrix corresponding to the pixels 21 shown in Fig. 26. A source driver circuit 302 is provided at a position adjacent to the liquid crystal region 22 in the Y direction (column direction) in which the pixel circuits 301 are arranged. A gate driver circuit 303 is provided at a position adjacent to the liquid crystal region 22 in the X direction (row direction). The source driver circuit 302 and the gate driver circuit 303 are provided in the above-mentioned sealing region 24. However, the region in which the source driver circuit 302 and the gate driver circuit 303 are provided is not limited to the sealing region 24, and may be any region outside the region in which the pixel circuits 301 are provided.

[0138] Data signal lines 304 extend in the Y direction from the source driver circuit 302 and are connected to a plurality of pixel circuits 301 arranged in the Y direction. Scanning signal lines 305 extend in the X direction from the gate driver circuit 303 and are connected to a plurality of pixel circuits 301 arranged in the X direction.

[0139] A terminal section 306 is provided in the terminal region 26. The terminal section 306 and the source driver circuit 302 are connected by a connection wiring 307. Similarly, the terminal section 306 and the gate driver circuit 303 are connected by a connection wiring 308. The flexible printed circuit board 330 is connected to the terminal section 306, thereby connecting the external device and the display device 20 via the flexible printed circuit board 330. Each pixel circuit 301 provided in the display device 20 is driven by a signal from the external device input via the flexible printed circuit board 330.

[0140] The semiconductor device 10 shown in the first embodiment is used as a switching element or a current control element included in a pixel circuit 301, a source driver circuit 302, and a gate driver circuit 303.

[0141] [Pixel circuit of display device] 28 is a circuit diagram showing a configuration of a pixel circuit 301 of a display device 20 according to one embodiment of the present invention. As shown in FIG. 28, the pixel circuit 301 includes elements such as a semiconductor device 10, a storage capacitor 350, and a liquid crystal element 311.

[0142] The semiconductor device 10 has a gate wiring 160, a source wiring 201, and a drain wiring 203. The gate wiring 160 is connected to a scanning signal line 305. However, the gate wiring 160 and the scanning signal line 305 may be formed of an integrated conductive layer. The source wiring 201 is connected to a data signal line 304. However, the source wiring 201 and the data signal line 304 may be formed of an integrated conductive layer.

[0143] The drain wiring 203 is connected to the storage capacitor 350 and the liquid crystal element 311. The roles of the source wiring 201 and the drain wiring 203 may be interchanged depending on the relationship between the voltage supplied to the data signal line 304 and the voltage stored in the storage capacitor 350. That is, the source wiring 201 may function as the drain wiring, and the drain wiring 203 may function as the source wiring.

[0144] Fifth embodiment In the fourth embodiment, it has been described that each of the semiconductor devices described in the first to third embodiments can be applied to a liquid crystal display device. However, the semiconductor device of each embodiment can also be applied to display devices other than a liquid crystal display device. For example, the semiconductor device of each embodiment may be applied to a self-luminous display device such as an organic EL display device, an electronic paper display device, or the like.

[0145] The above-mentioned embodiments of the present invention (including the modified examples of each embodiment) can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or deletes components or modifies designs, or adds or omits steps or modifies conditions based on each embodiment are also included in the scope of the present invention as long as they include the gist of the present invention.

[0146] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0147] 10, 10a, 10b...semiconductor device, 20...display device, 21...pixel, 22...liquid crystal region, 24...sealing region, 26...terminal region, 100...substrate, 105...conductive layer, 110, 120...insulating layer, 125...metal oxide layer, 130...oxide semiconductor layer, 130a...channel region, 130b...LDD region, 130c...conductive region, 140...gate insulating layer, 145...metal oxide layer, 150...buffer layer, 150a...overlapping region, 150b...non-overlapping region, 160...gate wiring, 161, 162...conductive layer, 165, 166...resist matrix 170: insulating layer, 171, 173: openings, 180, 190: insulating layer, 200: source-drain wiring, 201: source wiring, 203: drain wiring, 300: array substrate, 301: pixel circuit, 302: source driver circuit, 303: gate driver circuit, 304: data signal line, 305: scanning signal line, 306: terminal section, 307, 308: connection wiring, 310: seal section, 311: liquid crystal element, 320: opposing substrate, 330: flexible printed circuit (FPC) substrate, 340: IC chip, 350: storage capacitor

Claims

1. A first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the oxide semiconductor layer; a buffer layer on the gate insulating layer; a gate wiring on the buffer layer; a second insulating layer on the gate wiring; Including, the oxide semiconductor layer has a first region, a second region, and a third region aligned in a first direction; the electrical resistivity of the second region is higher than the electrical resistivity of the first region and lower than the electrical resistivity of the third region; The semiconductor device, wherein the sheet resistance of the third region is 1000 Ω / sq. or less.

2. A first insulating layer; an oxide semiconductor layer having a polycrystalline structure on the first insulating layer; a gate insulating layer on the oxide semiconductor layer; a buffer layer on the gate insulating layer; a gate wiring on the buffer layer; a second insulating layer on the gate wiring; Including, the oxide semiconductor layer has a first region, a second region, and a third region aligned in a first direction; the electrical resistivity of the second region is higher than the electrical resistivity of the first region and lower than the electrical resistivity of the third region; The semiconductor device, wherein an etching rate when the oxide semiconductor layer is etched at 40° C. using an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

3. 3. The semiconductor device according to claim 1, wherein the buffer layer has a thickness smaller than a thickness of the gate insulating layer.

4. 3. The semiconductor device according to claim 1, wherein the buffer layer has a thickness of 5 nm to 100 nm.

5. the first region overlaps with the gate line, the second region overlaps the buffer layer but does not overlap the gate line; The semiconductor device according to claim 1 , wherein the third region does not overlap with the buffer layer.

6. The semiconductor device according to claim 1 , wherein the third region is in contact with the gate insulating layer.

7. The semiconductor device according to claim 1 , wherein the third region is in contact with the second insulating layer.

8. 3 . The semiconductor device according to claim 1 , wherein a distance from an upper surface of the second region to an upper surface of the second insulating layer is longer than a distance from an upper surface of the third region to an upper surface of the second insulating layer.

9. The semiconductor device according to claim 1 , wherein the second region is in contact with the gate insulating layer.

10. 3. The semiconductor device according to claim 1, wherein a length of said second region in said first direction is not less than 0.1 [mu]m and not more than 1.5 [mu]m.

11. The semiconductor device according to claim 1 , wherein the second insulating layer includes a silicon oxide layer.

12. the first region is a channel region, the second region is an LDD region, 3. The semiconductor device according to claim 1, wherein the third region is a source region or a drain region.

13. The semiconductor device according to claim 1 , further comprising a metal oxide layer between the first insulating layer and the oxide semiconductor layer.

14. The semiconductor device according to claim 13 , wherein the metal oxide layer is an oxide layer containing aluminum as a main component.

15. The semiconductor device according to claim 13 , wherein the metal oxide layer and the oxide semiconductor layer have the same pattern shape.

16. 3 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer contains two or more metals including indium, and a ratio of indium in the two or more metals is 50% or more.

17. A display device comprising the semiconductor device according to claim 1 or 2 in each pixel.

Images