Semiconductor device

Abstract

To provide a semiconductor device with high reliability.SOLUTION: A semiconductor device includes an oxide semiconductor layer with a polycrystalline structure including an impurity region containing an impurity element, a gate electrode on the oxide semiconductor layer, an insulating layer between the oxide semiconductor layer and the gate electrode, a first contact hole penetrating the insulating layer and exposing the impurity region, a second contact hole penetrating at least the insulating layer and having a larger depth than the depth of the first contact hole, and a connection wire electrically connecting the impurity region and a layer exposed by the second contact hole through the first contact hole and the second contact hole. The connection wire includes a first conductive layer and a second conductive layer on the first conductive layer. A part of the first conductive layer that is exposed from the second conductive layer contains the impurity element.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a semiconductor device using an oxide semiconductor having a polycrystalline structure. [Background technology]

[0002] In recent years, development of semiconductor devices including oxide semiconductor films has been progressing in place of silicon semiconductor films using amorphous silicon, low-temperature polysilicon, single crystal silicon, etc. (see, for example, Patent Documents 1 to 6). A semiconductor device including such an oxide semiconductor film can be formed with a simple structure and a low-temperature process, similar to a semiconductor device including an amorphous silicon film. In addition, a semiconductor device including an oxide semiconductor film is known to have a higher field-effect mobility than a semiconductor device including an amorphous silicon film. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2021-141338 A [Patent Document 2] JP 2014-099601 A [Patent Document 3] Patent Publication No. 2021-153196 [Patent Document 4] JP 2018-006730 A [Patent Document 5] JP 2016-184771 A [Patent Document 6] Patent Publication No. 2021-108405 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device is required to have not only high field effect mobility but also high reliability. One object of an embodiment of the present invention is to provide a semiconductor device having high reliability. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment of the present invention includes an oxide semiconductor layer having a polycrystalline structure including an impurity region containing an impurity element, a gate electrode on the oxide semiconductor layer, an insulating layer between the oxide semiconductor layer and the gate electrode, a first contact hole penetrating the insulating layer and exposing the impurity region, a second contact hole penetrating at least the insulating layer and having a depth greater than a depth of the first contact hole, and a connection wiring electrically connecting the impurity region and a layer exposed by the second contact hole via the first contact hole and the second contact hole, wherein the connection wiring includes a first conductive layer and a second conductive layer on the first conductive layer, and a portion of the first conductive layer exposed from the second conductive layer contains the impurity element. [Brief description of the drawings]

[0006] [Figure 1] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 1 is a schematic enlarged cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 3] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 4] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Diagram 5] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 6] 1A to 1C are schematic cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Figure 7] 11 is a result of a simulation showing a concentration profile of boron implanted into an oxide semiconductor layer. [Figure 8] FIG. 11 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a modified example of an embodiment of the present invention. [Figure 9] FIG. 11 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a modified example of an embodiment of the present invention. [Figure 10] FIG. 11 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a modified example of an embodiment of the present invention. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a configuration of a semiconductor device according to a modified example of an embodiment of the present invention. [Figure 12] 1 is a schematic cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0007] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily come up with by appropriately modifying the configuration of the embodiment while maintaining the gist of the invention is naturally included in the scope of the present invention. In order to make the explanation clearer, the drawings may be schematic in terms of the width, film thickness, shape, etc. of the components compared to the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each figure, components similar to those described above with respect to the previous figures may be given the same reference numerals, and detailed explanations may be omitted as appropriate.

[0008] In this specification, the direction from the substrate toward the oxide semiconductor layer is referred to as "upper" or "upper". Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "lower" or "lower". Thus, for convenience of explanation, the terms "upper" and "lower" are used in the explanation, but the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in the opposite direction to that shown in the figure. In addition, the expression "oxide semiconductor layer on the substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer, and other members may be arranged between the substrate and the oxide semiconductor layer. "Upper" and "lower" refer to the order of stacking in a structure in which multiple layers are stacked, and when a pixel electrode is expressed as being above a semiconductor device, the semiconductor device and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is expressed as being vertically above a semiconductor device, the semiconductor device and the pixel electrode may overlap in a planar view. Note that the planar view refers to a view from a direction perpendicular to the surface of the substrate.

[0009] In this specification and the like, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other components.

[0010] In this specification and the like, the term "semiconductor device" refers to a device in general that can function by utilizing semiconductor characteristics. Transistors and semiconductor circuits are included in one form of semiconductor device. The semiconductor device of the embodiment described below may be, for example, a display device, an integrated circuit (IC) such as a microprocessor (Micro-Processing Unit: MPU), or a transistor used in a memory circuit.

[0011] In this specification, the term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term display device may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical members (e.g., a polarizing member, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent.

[0012] In this specification and the like, the terms "film" and "layer" may be interchangeable in some cases.

[0013] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0014] First Embodiment A semiconductor device 1 according to one embodiment of the present invention will be described with reference to FIGS.

[0015] [1. Configuration of Semiconductor Device 1] FIG. 1 is a schematic cross-sectional view showing the configuration of a semiconductor device 1 according to one embodiment of the present invention.

[0016] 1, the semiconductor device 1 includes a first transistor TR1 and a second transistor TR2 on a substrate 10. The semiconductor device 1 also includes insulating layers 11 to 14 that are provided in common to the first transistor TR1 and the second transistor TR2 and provide insulation.

[0017] The first transistor TR1 includes an insulating layer 11, an insulating layer 12, a light-shielding layer LS, an insulating layer 13, an oxide semiconductor layer OS, an insulating layer 14, and a gate electrode GE1. The insulating layer 11 is provided on a substrate 10. The insulating layer 12 is provided on the insulating layer 11. The light-shielding layer LS is provided on the insulating layer 12. The insulating layer 13 covers an upper surface and an end surface of the light-shielding layer LS and is provided on the insulating layer 12. The oxide semiconductor layer OS is provided on the insulating layer 13. The insulating layer 14 covers an upper surface and an end surface of the oxide semiconductor layer OS and is provided on the insulating layer 13. The gate electrode GE1 overlaps with the oxide semiconductor layer OS and is provided on the insulating layer 14. In the first transistor TR1, the insulating layer 11 and the insulating layer 12 function as base insulating layers, the insulating layer 13 functions as an interlayer insulating layer, and the insulating layer 14 functions as a gate insulating layer. The gate electrode GE1 is an electrode electrically connected to a gate line. The detailed configuration of the oxide semiconductor layer OS will be described later.

[0018] The second transistor TR2 includes an insulating layer 11, a silicon semiconductor layer SS, an insulating layer 12, a gate electrode GE2, an insulating layer 13, and an insulating layer 14. The insulating layer 11 is provided on a substrate 10. The silicon semiconductor layer SS is provided on the insulating layer 11. The insulating layer 12 covers the upper surface and end surfaces of the silicon semiconductor layer SS and is provided on the insulating layer 11. The gate electrode GE2 overlaps with the silicon semiconductor layer SS and is provided on the insulating layer 12. The insulating layer 13 covers the upper surface and end surfaces of the gate electrode GE2 and is provided on the insulating layer 12. The insulating layer 14 is provided on the insulating layer 13. In the second transistor TR2, the insulating layer 11 functions as a base insulating layer, the insulating layer 12 functions as a gate insulating layer, and the insulating layer 13 and the insulating layer 14 function as interlayer insulating layers. The gate electrode GE2 is an electrode electrically connected to a gate line. As the silicon semiconductor layer SS, for example, a polycrystalline silicon semiconductor is used, but is not limited thereto. As the silicon semiconductor layer SS, other silicon-based semiconductors can also be used.

[0019] The first transistor TR1 and the second transistor TR2 are electrically connected via a connection wiring CN. Specifically, the connection wiring CN directly electrically connects the oxide semiconductor layer OS of the first transistor TR1 and the second transistor TR2. The connection wiring CN functions as one of the source electrode and the drain electrode of the first transistor TR1. The connection wiring CN also functions as one of the source electrode and the drain electrode of the second transistor TR2. Note that in FIG. 1, the other of the source electrode and the drain electrode of the second transistor TR2 is omitted from illustration.

[0020] The substrate 10 can support each layer constituting the semiconductor device 1. For example, the substrate 10 can be a rigid substrate having light-transmitting properties, such as a glass substrate, a quartz substrate, or a sapphire substrate. The substrate 10 can also be a rigid substrate having no light-transmitting properties, such as a silicon substrate. The substrate 10 can also be a flexible substrate having light-transmitting properties, such as a polyimide resin substrate, an acrylic resin substrate, a siloxane resin substrate, or a fluororesin substrate. In order to improve the heat resistance of the substrate 10, impurities may be introduced into the flexible substrate.

[0021] The light-shielding layer LS can reflect or absorb light incident from the substrate 10 side. In other words, the light-shielding layer LS can block light incident on the oxide semiconductor layer OS. The light-shielding layer LS is formed in the same layer as the gate electrode GE2. That is, the light-shielding layer LS is formed of the same material as the gate electrode GE2. For example, metals such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mo), or tungsten (W), or alloys or compounds of these metals, etc., can be used as the light-shielding layer LS and the gate electrode GE2. The light-shielding layer LS may have a single-layer structure or a multilayer structure.

[0022] Each of the insulating layers 11 to 14 is made of, for example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y), aluminum oxide (AlO x ), or aluminum oxide nitride (AlO x N y ), or silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), Aluminum Nitride (AlN x ), or aluminum oxide nitride (AlN x O y ) and other nitrides can be used. Each of the insulating layers 11 to 14 may have a single-layer structure or a multilayer structure.

[0023] Here, silicon oxynitride (SiO x N y ) and aluminum oxide nitride (AlO x N y ) are oxides that contain a smaller ratio (x>y) of nitrogen (N) than oxygen (O). Silicon oxynitride (SiN x O y ) and aluminum oxide nitride (AlN x O y ) is a nitride containing a smaller ratio of oxygen than nitrogen (x>y). For convenience of explanation, silicon oxide (SiO x ) and silicon oxynitride (SiO x N y ) is simply called "silicon oxide" and silicon nitride (SiN x ) and silicon oxynitride (SiN x O y ) is sometimes simply called "silicon nitride". Similarly, aluminum oxide (AlO x ) and aluminum oxide nitride (AlO x N y ) is simply called "aluminum oxide" and aluminum nitride (AlN x ) and aluminum oxide nitride (AlN x O y ) is sometimes simply called "aluminum nitride."

[0024] The insulating layers 13 and 14 in contact with the oxide semiconductor layer OS preferably contain an oxide. When the oxide semiconductor layer OS is in contact with an oxide, oxygen can be supplied from the oxide to the oxide semiconductor layer OS by heat treatment. For example, the insulating layer 13 may have a stacked structure including silicon nitride and silicon oxide on the silicon nitride. Also, the insulating layer 14 may have a single-layer structure of silicon oxide.

[0025] The gate electrode GE1 is formed in the same layer as the connection wiring CN. That is, the gate electrode GE1 is formed of the same material as the connection wiring CN. Each of the gate electrode GE1 and the connection wiring CN has a stacked structure. Specifically, the gate electrode GE1 has a stacked structure including a first conductive layer L1 and a second conductive layer L2 on the first conductive layer L1. Also, the connection wiring CN has a stacked structure including a third conductive layer L3 and a fourth conductive layer on the third conductive layer L3. The first conductive layer L1 is formed in the same layer as the third conductive layer L3, and the second conductive layer L2 is formed in the same layer as the fourth conductive layer L4.

[0026] In the channel length direction of the first transistor TR1 (the direction from the source electrode to the drain electrode or from the drain electrode to the source electrode of the first transistor TR1), the width of the first conductive layer L1 is larger than the width of the second conductive layer L2. Therefore, in plan view, the first conductive layer L1 includes a portion exposed from the second conductive layer L2. Also, the film thickness t1 of the first conductive layer L1 is smaller than the film thickness t2 of the second conductive layer L2 (t1 < t2). The film thickness t2 of the second conductive layer L2 is three times or more the film thickness t1 of the first conductive layer L1. For example, the film thickness t1 is about 30 nm and the film thickness t2 is about 100 nm.

[0027] The first conductive layer L1 is formed of a material different from that of the second conductive layer L2. When selecting the material for each of the first conductive layer L1 and the second conductive layer L2, it is preferable that the density of the material forming the first conductive layer L1 is smaller than the density of the material forming the second conductive layer L2. As the first conductive layer L1 and the second conductive layer L2, the same material as that of the gate electrode GE2 can be used. For example, the first conductive layer L1 contains at least one of titanium (Ti) and aluminum (Al), and the material of the second conductive layer L2 contains at least one of molybdenum (Mo) and tungsten (W). However, since the first conductive layer L1 is in contact with the oxide semiconductor layer OS, it is preferable that the first conductive layer L1 contains a material that is difficult to be oxidized. For example, the first conductive layer L1 preferably has a single-layer structure of titanium or a laminated structure including titanium and aluminum on titanium.

[0028] In the first transistor TR1, a first contact hole CH1 is provided that penetrates the insulating layer 14 and exposes a part of the oxide semiconductor layer OS. Also, in the second transistor TR2, a second contact hole CH2 is provided that penetrates the insulating layers 12 to 14 and exposes a part of the silicon semiconductor layer SS. The depth of the second contact hole CH2 is greater than the depth of the first contact hole CH1. The connection wiring CN electrically connects the oxide semiconductor layer OS and the silicon semiconductor layer SS via the first contact hole CH1 and the second contact hole CH2.

[0029] As described above, the connection wiring CN includes a third conductive layer L3 formed in the same layer as the first conductive layer L1 and a fourth conductive layer formed in the same layer as the second conductive layer L2. Therefore, the film thickness t3 of the third conductive layer L3 is smaller than the film thickness t4 of the fourth conductive layer L4 (t3 < t4). The film thickness t4 of the fourth conductive layer L4 is three times or more the film thickness t3 of the third conductive layer L3. For example, the film thickness t3 is about 30 nm and the film thickness t4 is about 100 nm.

[0030] The third conductive layer L3 extends from the first contact hole CH1 to the second contact hole CH2 so as to cover the first contact hole CH1 and the second contact hole CH2. The third conductive layer L3 is in contact with the oxide semiconductor layer OS through the first contact hole CH1 and is in contact with the silicon semiconductor layer SS through the second contact hole CH2.

[0031] The fourth conductive layer L4 overlaps the second contact hole CH2 but does not overlap the first contact hole CH1. That is, in the connection wiring CN, a part of the third conductive layer L3 is exposed from the fourth conductive layer L4. The part of the third conductive layer exposed from the fourth conductive layer L4 is in contact with the oxide semiconductor layer OS via the first contact hole CH1.

[0032] Now, with reference to FIG. 2, the electrical connection between the connection wiring CN and the oxide semiconductor layer will be described.

[0033] 2 is a schematic enlarged cross-sectional view showing the configuration of a semiconductor device 1 according to one embodiment of the present invention, specifically, a cross-sectional view showing an enlarged area A in FIG.

[0034] The oxide semiconductor layer OS includes a channel region OS_1 and an impurity region OS_2 adjacent to the channel region. The channel region OS_1 has semiconductor properties. Therefore, when a voltage is applied to the gate electrode GE1, a channel that serves as a current path is formed in the channel region OS_1. The impurity region OS_2 contains an impurity element and has conductive properties. Therefore, the carrier concentration of the impurity region OS_2 is higher than that of the channel region OS_1. In other words, the channel region OS_1 has a higher electrical resistivity (or a lower electrical conductivity) than the impurity region OS_2. For example, the sheet resistance of the impurity region OS_2 is 1000 Ω / sq. or less, preferably 500 Ω / sq. or less, and more preferably 250 Ω / sq. or less. The impurity region OS_2 may be called a source region or a drain region.

[0035] The impurity element contained in the impurity region OS_2 is, for example, boron (B) or phosphorus (P), but is not limited thereto. As will be described in detail later, the impurity region OS_2 containing the impurity element can be formed by implanting the impurity element into the oxide semiconductor layer OS. The impurity region OS_2 of the oxide semiconductor layer OS can contain a larger amount of the impurity element. This means that there are more oxygen defects in the impurity region OS_2 and the impurity region OS_2 has a sufficiently large carrier concentration. Therefore, the resistance of the impurity region OS_2 is sufficiently low.

[0036] The boundary between the channel region OS_1 and the impurity region OS_2 substantially coincides with an end of the second conductive layer L2. That is, the end of the impurity region OS_2 overlaps with a portion of the first conductive layer L1 that is exposed from the second conductive layer L2.

[0037] The third conductive layer L3 is in contact with the impurity region OS_2 through the first contact hole CH1. Since the resistance of the impurity region OS_2 is sufficiently low, the electrical connection between the third conductive layer L3 and the impurity region OS_2 is ohmic contact.

[0038] [2. Structure of the oxide semiconductor layer OS] [2-1. Composition of the oxide semiconductor layer OS] The oxide semiconductor layer OS is made of an oxide semiconductor containing two or more metal elements including indium (In). As the metal elements other than indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanoids are used.

[0039] The oxide semiconductor layer OS has a light-transmitting property and a polycrystalline structure including a plurality of crystal grains. In order for the oxide semiconductor layer OS to have a polycrystalline structure, it is preferable to use an oxide semiconductor in which the ratio of indium to all metal elements is 50% or more in atomic ratio. When the ratio of indium is large, the oxide semiconductor layer OS is more likely to crystallize. In addition, it is preferable to contain gallium as a metal element other than indium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer OS is hardly inhibited by gallium.

[0040] As described above, the oxide semiconductor layer OS includes the channel region OS_1 and the impurity region OS_2, and not only the channel region OS_1 but also the impurity region OS_2 may have a polycrystalline structure. In this case, the crystal structure of the channel region OS_1 is the same as that of the impurity region OS_2.

[0041] Although the details will be described later, the oxide semiconductor layer OS has properties different from those of a conventional oxide semiconductor having a polycrystalline structure. Therefore, in order to distinguish the oxide semiconductor included in the oxide semiconductor layer OS from the conventional oxide semiconductor having a polycrystalline structure, the oxide semiconductor included in the oxide semiconductor layer OS will be referred to as a polycrystalline oxide semiconductor (Poly-OS) in the following description.

[0042] The Poly-OS included in the oxide semiconductor layer OS can be formed by sputtering and heat treatment. Here, a method for forming the oxide semiconductor layer OS will be described.

[0043] First, an oxide semiconductor film is formed by sputtering. The formed oxide semiconductor film has an amorphous structure. Here, the amorphous structure refers to a structure in which a long-range ordered structure does not exist and a periodic crystal lattice arrangement is not observed. For example, when an oxide semiconductor film having an amorphous structure is observed by X-ray diffraction (XRD), a specific peak based on a crystal structure is not obtained in the diffraction pattern. Note that an oxide semiconductor film having an amorphous structure may have a short-range ordered structure in a micro domain. However, such an oxide semiconductor film does not exhibit the characteristics of Poly-OS, and therefore can be classified as an oxide semiconductor film having an amorphous structure.

[0044] An oxide semiconductor film having an amorphous structure is formed at a low temperature. For example, the temperature of the substrate on which the oxide semiconductor film is formed is 150° C. or lower, preferably 100° C. or lower, and more preferably 50° C. or lower. When the substrate temperature is high, microcrystals are likely to be generated in the oxide semiconductor film to be formed. In addition, the oxygen partial pressure in the chamber during film formation is 1% to 10%, preferably 1% to 5%, and more preferably 2% to 4%. When the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor film due to excess oxygen contained in the oxide semiconductor. On the other hand, under conditions where the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor film becomes nonuniform, and an oxide semiconductor film containing many microcrystals or an oxide semiconductor film that does not crystallize even when heat treatment is performed is formed.

[0045] Next, the oxide semiconductor film formed by sputtering is subjected to heat treatment. The heat treatment is performed in air, but the atmosphere is not limited thereto. The heat treatment temperature is 300° C. to 500° C., and preferably 350° C. to 450° C. The heat treatment time is 15 minutes to 120 minutes, and preferably 30 minutes to 60 minutes. By performing the heat treatment, the oxide semiconductor film having an amorphous structure is crystallized, and an oxide semiconductor layer OS including Poly-OS is formed.

[0046] The composition of the oxide semiconductor layer OS is approximately equal to the composition of the sputtering target. Therefore, the composition of the metal elements of the oxide semiconductor layer OS can be specified based on the composition of the metal elements of the sputtering target. The composition of the oxide semiconductor layer OS may be specified by using an XRD method. Specifically, the composition of the metal elements of the oxide semiconductor layer OS can be specified based on the crystal structure and lattice constant of the oxide semiconductor layer OS obtained by the XRD method. Furthermore, the composition of the metal elements of the oxide semiconductor layer OS can also be specified by using an X-ray fluorescence analysis or an electron probe micro analyzer (EPMA) analysis. Note that the oxygen contained in the oxide semiconductor layer OS is not limited to this because it changes depending on the process conditions of sputtering.

[0047] [2-2. Characteristics of the oxide semiconductor layer OS] Next, characteristics of the oxide semiconductor layer OS including the Poly-OS will be described.

[0048] The oxide semiconductor layer OS has excellent etching resistance. Specifically, the etching rate of the oxide semiconductor layer OS is very small when the oxide semiconductor layer OS is etched using an etching solution for wet etching. This means that the oxide semiconductor layer OS is hardly etched by the etching solution. The etching rate of the oxide semiconductor layer OS when the oxide semiconductor layer OS is etched using an etching solution containing phosphoric acid as a main component at 40° C. (hereinafter, referred to as a “mixed acid etching solution”) is less than 3 nm / min, less than 2 nm / min, or less than 1 nm / min. The ratio of phosphoric acid in the mixed acid etching solution is 50% or more, 60% or more, or 70% or more. The mixed acid etching solution may contain acetic acid and nitric acid in addition to phosphoric acid. Note that, in an oxide semiconductor film not containing Poly-OS, for example, an oxide semiconductor film having an amorphous structure before heat treatment, the etching rate of the oxide semiconductor film when the oxide semiconductor film is etched using a mixed acid etching solution at 40° C. is 100 nm / min or more. Moreover, the etching rate when the oxide semiconductor layer OS is etched with a 0.5% hydrofluoric acid solution at room temperature is less than 5 nm / min, less than 4 nm / min, or less than 3 nm / min. Note that, in the case of an oxide semiconductor film not including Poly-OS, the etching rate when the oxide semiconductor film is etched with a 0.5% hydrofluoric acid solution at room temperature is 15 nm / min or more. Here, "40°C" includes a range of 40±5°C, and may be the temperature of the etching solution or the set temperature of the etching solution. Moreover, "room temperature" refers to 25±5°C.

[0049] An example of the oxide semiconductor layer OS is shown in Table 1. Table 1 shows the etching rates of each of the prepared samples with respect to a mixed acid etching solution ("Mixed Acid AT-2F" manufactured by Nasa Industries Co., Ltd., in which the ratio of phosphoric acid in the mixed acid etching solution is 65%) and a 0.5% hydrofluoric acid solution. When each sample was etched, the temperature of the mixed acid etching solution was 40°C, and the temperature of the 0.5% hydrofluoric acid solution was room temperature (22°C). In Table 1, Sample 1 is an oxide semiconductor layer OS containing Poly-OS, Sample 2 is an oxide semiconductor film having an amorphous structure before heat treatment, and Sample 3 is an oxide semiconductor film containing indium gallium zinc oxide (IGZO) in which the ratio of indium is less than 50%.

[0050] [Table 1]

[0051] As shown in Table 1, Sample 1 (oxide semiconductor layer OS including Poly-OS) is hardly etched using a mixed acid etching solution, and even when using a 0.5% hydrofluoric acid solution, it is etched at most 2 nm / min. Sample 1 has an etching rate of 1 / 100 or less with a mixed acid etching solution and about 1 / 10 or less with a 0.5% hydrofluoric acid solution than Sample 2 (oxide semiconductor film having an amorphous structure before heat treatment). Sample 1 also has an etching rate of 1 / 100 or less with a mixed acid etching solution than Sample 3 (oxide semiconductor film including IGZO with an indium ratio of less than 50%). That is, Sample 1 is significantly more etch-resistant than Samples 2 and 3.

[0052] Such excellent etching resistance of the oxide semiconductor layer OS containing Poly-OS is a property that cannot be obtained with conventional oxide semiconductors having a polycrystalline structure that are fabricated by processes at or below 500° C. Although the detailed mechanism behind the excellent etching resistance of the oxide semiconductor layer OS containing Poly-OS is unclear, it is thought that Poly-OS has a polycrystalline structure that differs from conventional structures.

[0053] As described above, the oxide semiconductor layer OS containing Poly-OS has a very small etching rate with respect to the etching solution. Therefore, it is very difficult to pattern the oxide semiconductor layer OS. Therefore, when forming an island-shaped oxide semiconductor layer OS, an oxide semiconductor film having an amorphous structure before heat treatment is patterned into an island shape, and then heat treatment is performed to crystallize the oxide semiconductor layer OS. In this way, an island-shaped oxide semiconductor layer OS containing Poly-OS can be formed.

[0054] [3. Method for Manufacturing Semiconductor Device 1] A method for manufacturing the semiconductor device 1 will be described with reference to FIGS.

[0055] Each of FIGS. 3 to 6 is a schematic cross-sectional view showing a method for manufacturing the semiconductor device 1 according to one embodiment of the present invention.

[0056] First, as shown in FIG. 3, on a substrate 10, an insulating layer 11, a silicon semiconductor layer SS, an insulating layer 12, a gate electrode GE2 and a light-shielding layer LS, an insulating layer 13, an oxide semiconductor layer OS, and an insulating layer 14 are formed in that order.

[0057] In forming the silicon semiconductor layer SS, impurities are implanted into the silicon semiconductor layer SS using the gate electrode GE1 as a mask. The implanted impurity element is phosphorus (P) in the case of an n-channel type, and boron (B) in the case of a p-channel type. In forming the oxide semiconductor layer OS, OS annealing is performed after patterning of an oxide semiconductor film formed by sputtering. By performing OS annealing, an oxide semiconductor layer OS including a Poly-OS is formed.

[0058] In addition, after forming the insulating layer 14, a first contact hole CH1 penetrating the insulating layer 14 and a second contact hole CH2 penetrating the insulating layers 12 to 14 are formed. A part of the oxide semiconductor layer OS is exposed in the first contact hole CH1, and a part of the silicon semiconductor layer SS is exposed in the second contact hole CH2.

[0059] Next, as shown in FIG. 4, a metal film is formed on the insulating layer 14, and then the metal film is By turning, the first conductive layer L1 of the gate electrode GE2 and the third conductive layer L3 of the connection wiring CN are formed. The third conductive layer L3 is in contact with the oxide semiconductor layer OS at the first contact hole CH1 and in contact with the silicon semiconductor layer SS at the second contact hole CH2. The first conductive layer L1 overlaps with the oxide semiconductor layer OS and is separated from the third conductive layer L3.

[0060] 5, a metal film is formed on the first conductive layer L1 and the third conductive layer, and then the metal film is patterned to form the second conductive layer L2 of the gate electrode GE1 and the fourth conductive layer L4 of the connection wiring CN. The fourth conductive layer L4 overlaps the second contact hole CH2 but does not overlap the first contact hole CH1. The second conductive layer L2 overlaps the oxide semiconductor layer OS and is separated from the fourth conductive layer L4.

[0061] 6, ions are implanted into the oxide semiconductor layer OS using the gate electrode GE1 as a mask. For example, boron (B) is implanted as an impurity element into the oxide semiconductor layer OS by ion implantation. Note that instead of boron, other impurity elements such as phosphorus (P) may be implanted into the oxide semiconductor layer OS.

[0062] During ion implantation, the second conductive layer L2 and the fourth conductive layer L4, which have a relatively high density and a relatively large thickness, have a high ability to block the implantation of the impurity element. Therefore, the impurity element is hardly implanted into the region overlapping with the second conductive layer L2 and the fourth conductive layer L4. On the other hand, the first conductive layer L1 and the third conductive layer L3 have a relatively low density and a small thickness. Therefore, the impurity element easily passes through the part of the first conductive layer L1 that does not overlap with the second conductive layer L2 and the part of the third conductive layer that does not overlap with the fourth conductive layer L4. Therefore, the impurity element is implanted into the region that does not overlap with the second conductive layer L2 and the fourth conductive layer L4. As a result, the impurity element is implanted into the region of the oxide semiconductor layer OS that does not overlap with the second conductive layer L2, and a low-resistance impurity region OS_2 is formed. Moreover, the impurity element is not implanted into the region of the oxide semiconductor layer OS that overlaps with the second conductive layer L2, and a channel region OS_1 is formed. As described above, the impurity element passes through the portion of the first conductive layer L1 that is exposed from the second conductive layer L2, but the impurity element may be included in that portion. Similarly, the impurity element passes through the portion of the third conductive layer L3 that is exposed from the fourth conductive layer L4, but the impurity element may be included in that portion.

[0063] As described above, when the second transistor TR2 is an n-channel type, the impurity element implanted into the silicon semiconductor layer SS is phosphorus. That is, the impurity element (phosphorus) contained in the silicon semiconductor layer SS is different from the impurity element (boron) implanted into the oxide semiconductor layer OS. In this case, it is necessary to protect the silicon semiconductor layer SS from the impurity element (boron) implanted into the oxide semiconductor layer OS. For this reason, a fourth conductive layer L4 is formed on the third conductive layer L3 in the second contact hole CH2 to prevent the impurity element (boron) implanted into the oxide semiconductor layer OS from being implanted into the silicon semiconductor layer SS.

[0064] When the second transistor TR2 is a p-channel type, the impurity element implanted into the silicon semiconductor layer SS is boron. When the impurity element implanted into the oxide semiconductor layer OS is phosphorus, the impurity element (boron) contained in the silicon semiconductor layer SS is different from the impurity element (phosphorus) implanted into the oxide semiconductor layer OS. In this case as well, a fourth conductive layer L4 is formed on the third conductive layer L3 in the second contact hole CH2 to prevent the impurity element (phosphorus) implanted into the oxide semiconductor layer OS from being implanted into the silicon semiconductor layer SS.

[0065] Fig. 7 shows the result of a simulation showing the concentration profile of boron implanted into the oxide semiconductor layer OS. The horizontal and vertical axes of the graph in Fig. 7 represent the distance from the surface and the boron concentration, respectively. Fig. 7 also shows the concentration profile of indium gallium zinc oxide (IGZO) as a conventional example (dotted line in Fig. 7) as well as the concentration profile of Poly-OS included in the oxide semiconductor layer OS (solid line in Fig. 7).

[0066] The simulation was performed using SILVACO's "VICTORY PROCESS" with an acceleration voltage of 30 keV and a dose of 1×10 13 cm -2 As mentioned above, Poly-OS contains a lot of indium and has a high density. Therefore, in the simulation, the densities of Poly-OS and IGZO were set to 7.179 g / cm3, respectively. 3 and 6.1 g / cm 3 It was calculated as:

[0067] As shown in FIG. 7, the distance to which boron is implanted in Poly-OS is smaller than the distance to which boron is implanted in IGZO. That is, compared with IGZO, boron is not implanted in Poly-OS to a position far from the surface. This means that the implanted boron is likely to remain in Poly-OS. In other words, Poly-OS has a high stopping power for the implanted impurity element. Therefore, the impurity element does not pass through the oxide semiconductor layer OS including Poly-OS, and the oxide semiconductor layer OS can contain more impurity elements. As a result, more oxygen defects are generated in the impurity region OS_2, and the resistance of the impurity region OS_2 can be sufficiently reduced.

[0068] In the semiconductor device 1, the impurity element is implanted into the oxide semiconductor layer OS through the first conductive layer L1 and the third conductive layer L3, so the acceleration voltage for ion implantation may be increased. In this case, the blocking power for the impurity element is prominent. Specifically, even if the impurity element passes through a conventional oxide semiconductor layer including IGZO, the impurity element remains in the oxide semiconductor layer OS including Poly-OS. Therefore, in the semiconductor device 1, the impurity region OS_2 overlapping with the first conductive layer L1 and the third conductive layer L3 is sufficiently reduced in resistance.

[0069] As described above, in the semiconductor device 1, the connection wiring CN that directly and electrically connects the oxide semiconductor layer OS and the silicon semiconductor layer SS has a laminated structure including the thin third conductive layer L3 and the thick fourth conductive layer L4. However, the fourth conductive layer L4 is not formed so as to overlap the first contact hole CH1 where the third conductive layer L3 contacts the oxide semiconductor layer OS.

[0070] Unlike the present embodiment, when an impurity element is ion-implanted in a case where a thick connection wiring is formed overlapping the first contact hole CH1, the impurity element is implanted only through the gap between the gate electrode and the connection wiring. In this case, the impurity region containing the impurity element does not overlap the first contact hole CH1. Therefore, the electrical connection between the connection wiring and the oxide semiconductor layer does not become an ohmic contact, and the second transistor TR2 does not have the desired performance. In addition, the electrical connection between the connection wiring and the oxide semiconductor layer is not stable, so the reliability of the second transistor TR2 is reduced.

[0071] On the other hand, according to the present embodiment, an impurity element is injected into the oxide semiconductor layer OS through the third conductive layer L3, so that the impurity region OS_2 can be formed by overlapping with the first contact hole CH1. Therefore, the electrical connection between the connection wiring CN and the oxide semiconductor layer OS becomes an ohmic contact, and the second transistor TR2 has a desired performance. In addition, the electrical connection between the connection wiring CN and the oxide semiconductor layer OS is stable, so that the second transistor TR2 has high reliability.

[0072] In addition, a fourth conductive layer L4 is formed in the first contact hole CH1 where the third conductive layer L3 and the silicon semiconductor layer SS are in contact. Therefore, even if the impurity contained in the silicon semiconductor layer SS is different from the impurity implanted in the oxide semiconductor layer OS, the impurity element implanted in the oxide semiconductor layer OS can be prevented from being implanted in the silicon semiconductor layer SS. This suppresses an increase in the contact resistance between the silicon semiconductor layer SS and the connection wiring CN. Therefore, a decrease in the driving capability of the second transistor TR2 can also be suppressed. Furthermore, a separate process for suppressing the implantation of undesired impurity elements into the silicon semiconductor layer SS is not required, and an increase in manufacturing costs is suppressed.

[0073] In this embodiment, a configuration has been described in which the impurity region OS_2 of the oxide semiconductor layer OS is electrically connected to the silicon semiconductor layer SS, but a configuration in which the impurity region OS_2 of the oxide semiconductor layer OS is electrically connected to a metal layer such as wiring is also possible.

[0074] <Variation 1> A modified example of this embodiment will be described with reference to Fig. 8. In the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0075] FIG. 8 is a schematic cross-sectional view showing the configuration of a semiconductor device 1A according to a modified example of one embodiment of the present invention.

[0076] The semiconductor device 1A shown in FIG. 8 is different from the semiconductor device 1 in the configuration of the fourth conductive layer L4. The third conductive layer L3 to which the fourth conductive layer L4 is in contact has the same configuration as that described above. That is, the third conductive layer L3 is in contact with the silicon semiconductor layer SS through the second contact hole CH2, and is in contact with the oxide semiconductor layer OS through the first contact hole CH1. The third conductive layer L3 also includes an extension portion EX that extends from a position in contact with the oxide semiconductor layer OS in the first contact hole CH1 toward the gate electrode GE1.

[0077] The fourth conductive layer L4 is formed between the first contact hole CH1 and the second contact hole CH2. The fourth conductive layer L4 contacts the third conductive layer L3 not only at the second contact hole CH2 but also at the first contact hole CH1. However, the fourth conductive layer L4 is not formed in the extension portion EX. That is, the end face of the fourth conductive layer L4 on the first transistor TR1 side overlaps with the first contact hole CH1.

[0078] In the semiconductor device 1A, the implantation of impurity elements into the region of the oxide semiconductor layer OS that overlaps with the first contact hole CH1 is suppressed. However, if the third conductive layer L3 is made of a material that easily absorbs oxygen, the oxygen in the region is absorbed by the third conductive layer L3 when the third conductive layer L3 contacts the region, generating oxygen defects. As a result, a source region or drain region with sufficiently low resistance is formed adjacent to the channel region OS_1.

[0079] In the semiconductor device 1A, the fourth conductive layer L4 is not formed on the extension portion EX, and therefore the same effects as those of the semiconductor device 1 can be obtained.

[0080] <Variation 2> Another modified example of this embodiment will be described with reference to Fig. 9. In the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0081] FIG. 9 is a schematic cross-sectional view showing the configuration of a semiconductor device 1B according to another modified example of the embodiment of the present invention.

[0082] The semiconductor device 1B shown in FIG. 9 is different from the semiconductor device 1 in the configuration of the gate electrode GE1. In the gate electrode GE1 of the semiconductor device 1B, the second conductive layer L2 is formed so as to cover the upper surface and end surface of the first conductive layer L1. In the channel direction, the width of the second conductive layer L2 is larger than the width of the first conductive layer L1. In addition, the second conductive layer L2 and the fourth conductive layer L4 are formed so as not to overlap the first contact hole CH1.

[0083] In the semiconductor device 1B, an impurity element can be implanted into the oxide semiconductor layer OS while the connection wiring CN is in contact with the oxide semiconductor layer OS through the first contact hole CH1. As a result, an impurity region OS_2 having a sufficiently low resistance can be formed so as to overlap the first contact hole CH1 and to be adjacent to the channel region OS_1. Therefore, the semiconductor device 1B can achieve the same effects as the semiconductor device 1.

[0084] <Variation 3> Another modified example of this embodiment will be described with reference to Fig. 10. Note that in the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0085] FIG. 10 is a schematic cross-sectional view showing the configuration of a semiconductor device 1C according to a modified example of the embodiment of the present invention.

[0086] The semiconductor device 1C shown in FIG. 10 is different from the semiconductor device 1 in the configuration of the gate electrode GE1. In the gate electrode GE1 of the semiconductor device 1C, the second conductive layer L2 is formed, but the first conductive layer L1 is not formed. That is, the second conductive layer L2 is in contact with the insulating layer 14. In addition, the second conductive layer L2 and the fourth conductive layer L4 are formed so as not to overlap with the first contact hole CH1.

[0087] In the semiconductor device 1C, an impurity element can be implanted into the oxide semiconductor layer OS in a state in which the connection wiring CN is in contact with the oxide semiconductor layer OS through the first contact hole CH1. As a result, an impurity region OS_2 with a sufficiently low resistance can be formed so as to overlap the first contact hole CH1 and be adjacent to the channel region OS_1. Therefore, the semiconductor device 1C can achieve the same effects as the semiconductor device 1.

[0088] <Modification 4> Another modified example of this embodiment will be described with reference to Fig. 11. In the following, description of the same configuration as the above-mentioned configuration may be omitted.

[0089] FIG. 11 is a schematic cross-sectional view showing the configuration of a semiconductor device 1D according to a modified example of the embodiment of the present invention.

[0090] 10 includes a metal oxide layer MO, as compared with the semiconductor device 1. That is, in the semiconductor device 1D, a metal oxide layer MO is provided below the oxide semiconductor layer OS and in contact with the oxide semiconductor layer OS. An end face of the metal oxide layer MO is substantially aligned with an end face of the oxide semiconductor layer OS. An insulating layer 14 covers the end face of the metal oxide layer MO and the upper surface and end faces of the oxide semiconductor layer OS, and is provided on the insulating layer 13.

[0091] The metal oxide layer MO can function as a buffer layer that improves the crystallinity of the oxide semiconductor layer OS. The first transistor TR1 including the oxide semiconductor layer OS with improved crystallinity further improves the field-effect mobility.

[0092] The metal oxide layer MO is made of a metal oxide containing aluminum as a main component. The ratio of aluminum contained in the metal oxide layer MO may be 5% to 70%, 10% to 60%, or 30% to 50% of the entire metal oxide layer MO. The ratio may be a mass ratio or a weight ratio.

[0093] The thickness of the metal oxide layer MO is 1 nm or more and 10 nm or less, preferably 1 nm or more and 5 nm or less. Aluminum oxide is preferably used as the metal oxide layer MO. Aluminum oxide has high barrier properties against gases such as oxygen and hydrogen. Here, the barrier properties refer to the function of suppressing the permeation of gases such as oxygen and hydrogen.

[0094] Note that the metal oxide layer MO may be a metal oxide mainly composed of a metal other than aluminum. For example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like may be used as the metal oxide layer MO.

[0095] The metal oxide layer MO can be formed by sputtering or atomic layer deposition (ALD). The metal oxide layer MO can be patterned using the oxide semiconductor layer OS as a mask. As described above, the oxide semiconductor layer 140 including Poly-OS has excellent etching resistance. Therefore, even when the metal oxide layer MO is etched in the patterning of the metal oxide layer MO, the oxide semiconductor layer 140 used as a mask is not etched. In the semiconductor device 1D, the oxide semiconductor layer OS can be used as a mask in the formation of the metal oxide layer MO, so that a photolithography process can be omitted.

[0096] In the semiconductor device 1D, an impurity element can be implanted into the oxide semiconductor layer OS in a state where the connection wiring CN is in contact with the oxide semiconductor layer OS through the first contact hole CH1. As a result, an impurity region OS_2 having a sufficiently low resistance can be formed overlapping the first contact hole CH1 and adjacent to the channel region OS_1. Therefore, the semiconductor device 1D can obtain the same effect as the semiconductor device 1. In addition, in the semiconductor device 1D, the Poy-OS is formed using the metal oxide layer MO as a buffer layer, so that the crystallinity of the oxide semiconductor layer OS including the Poly-OS is improved. As a result, the first transistor TR1 has a higher field-effect mobility.

[0097] <Second embodiment> A semiconductor device 2 according to one embodiment of the present invention will be described with reference to Fig. 12. Note that in the following, description of configurations similar to those of the first embodiment may be omitted.

[0098] FIG. 12 is a schematic cross-sectional view showing the configuration of a semiconductor device 2 according to one embodiment of the present invention.

[0099] The semiconductor device 2 shown in FIG. 12 is different from the semiconductor device 1 in the configuration of the connection wiring CN. In the connection wiring CN of the semiconductor device 2, the fourth conductive layer L4 is formed on the third conductive layer L3 between the first contact hole CH1 and the second contact hole CH2, and is not formed in the first contact hole CH1 and the second contact hole CH2. That is, the end face of the fourth conductive layer L4 does not overlap the first contact hole CH1 and the second contact hole CH2. In this case, when ion implantation is performed, the impurity element is implanted not only in the oxide semiconductor layer OS but also in the silicon semiconductor layer SS. However, in the semiconductor device 2, the impurity element contained in the silicon semiconductor layer SS is the same as the impurity element implanted in the oxide semiconductor layer OS. Specifically, the impurity element contained in the silicon semiconductor layer SS and the impurity element implanted in the oxide semiconductor layer OS are both phosphorus, or the impurity element contained in the silicon semiconductor layer SS and the impurity element implanted in the oxide semiconductor layer OS are both boron. Therefore, when an impurity element is implanted into the oxide semiconductor layer OS, even if the impurity is implanted into the silicon semiconductor layer SS, the performance of the first transistor TR1 is not deteriorated.

[0100] The second conductive layer L2 and the fourth conductive layer L4 are formed so as not to overlap the first contact hole CH1.

[0101] In the semiconductor device 2, an impurity element can be implanted into the oxide semiconductor layer OS in a state in which the connection wiring CN is in contact with the oxide semiconductor layer OS through the first contact hole CH1. As a result, an impurity region OS_2 having a sufficiently low resistance can be formed so as to overlap the first contact hole CH1 and to be adjacent to the channel region OS_1. Therefore, the semiconductor device 2 can achieve the same effects as the semiconductor device 1.

[0102] The above-described embodiments of the present invention may be combined as appropriate as long as they are not mutually inconsistent. Furthermore, those in which a person skilled in the art appropriately adds or removes components or modifies designs, or adds or omits steps or modifies conditions based on the embodiments, are also included in the scope of the present invention as long as they include the gist of the present invention.

[0103] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those which are clear from the description in this specification or which can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0104] 1, 1A, 1B, 1C, 1D, 2: semiconductor device, 10: substrate, 11, 12, 13, 14: insulating layer, CH1: first contact hole, CH2: second contact hole, CN: connection wiring, EX: extension, GE1, GE2: gate electrode, L1: first conductive layer, L2: second conductive layer, L3: third conductive layer, L4: fourth conductive layer, LS: light shielding layer, MO: metal oxide layer, OS: oxide semiconductor layer, OS_1: channel region, OS_2: impurity region, SS: silicon semiconductor layer, TR1: first transistor, TR2: second transistor

Claims

1. an oxide semiconductor layer having a polycrystalline structure including an impurity region containing an impurity element; a gate electrode on the oxide semiconductor layer; an insulating layer between the oxide semiconductor layer and the gate electrode; a first contact hole penetrating the insulating layer and exposing the impurity region; a second contact hole penetrating at least the insulating layer and having a depth greater than a depth of the first contact hole; a connection wiring electrically connecting the impurity region and a layer exposed by the second contact hole through the first contact hole and the second contact hole; the connection wiring includes a first conductive layer and a second conductive layer on the first conductive layer; a portion of the first conductive layer exposed from the second conductive layer containing the impurity element.

2. the oxide semiconductor layer further includes a channel region adjacent to the impurity region and having a higher electrical resistivity than the impurity region; the gate electrode includes a third conductive layer formed of the same layer as the second conductive layer; 2. The semiconductor device according to claim 1, wherein a boundary between said channel region and said impurity region approximately coincides with an end of said third conductive layer.

3. 3. The semiconductor device according to claim 2, wherein said gate electrode includes a fourth conductive layer formed in the same layer as said first conductive layer.

4. The semiconductor device according to claim 3 , wherein said fourth conductive layer includes a portion exposed from said third conductive layer.

5. 4. The semiconductor device according to claim 3, wherein an end face of said fourth conductive layer is covered with said third conductive layer.

6. 4. The semiconductor device according to claim 3, wherein the crystal structure of said impurity region is the same as that of said channel region.

7. The semiconductor device according to claim 1 , wherein said second conductive layer overlaps said first contact hole.

8. The semiconductor device according to claim 1 , wherein said second conductive layer overlaps said second contact hole.

9. 2. The semiconductor device according to claim 1, wherein the layer exposed by the second contact hole is a silicon semiconductor layer.

10. The semiconductor device according to claim 1 , wherein the layer exposed by the second contact hole is a metal layer.

11. 2 . The semiconductor device according to claim 1 , wherein an etching rate of the oxide semiconductor layer when the oxide semiconductor layer is etched at 40° C. with an etching solution containing phosphoric acid as a main component is less than 3 nm / min.

12. The semiconductor device according to claim 11 , wherein the etching solution contains nitric acid and acetic acid.

13. the oxide semiconductor layer is formed by performing a heat treatment on an oxide semiconductor film having an amorphous structure; The semiconductor device according to claim 11 , wherein an etching rate when the oxide semiconductor film is etched with the etching solution at 40° C. is 100 nm / min or more.

14. 2 . The semiconductor device according to claim 1 , wherein the oxide semiconductor layer is etched at a rate of less than 5 nm / min using a 0.5% hydrofluoric acid solution at room temperature.

15. the oxide semiconductor layer contains a plurality of metal elements, one of the metal elements is indium; The semiconductor device according to claim 1 , wherein an atomic ratio of said indium to said plurality of metal elements is 50% or more.

16. 2. The semiconductor device according to claim 1, wherein the impurity region has a sheet resistance of 1000 Ω / sq. or less.

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