Semiconductor device

Abstract

To provide a semiconductor device capable of reducing power loss when fixing an output signal from a level shift circuit for interfacing between different power supplies, at specific potential.SOLUTION: A semiconductor device includes: a level shift part to which a first signal at specific potential outputted from a circuit operating at a first power supply voltage is inputted through an input signal terminal and an inverted input signal terminal, and which converts the first signal to a second signal whose potential is different from the potential of the first signal, and outputs the second signal to a circuit operating at a second power supply voltage whose potential is different from the potential of the first power supply voltage; a first transistor of first polarity having a gate to which the first power supply voltage is applied, a source to which the second power supply voltage is applied, and a drain connected to the input signal terminal; and a second transistor of the first polarity having a gate to which the first power supply voltage is applied, a source to which the second power supply voltage is applied, and a drain connected to the output signal terminal.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] A technique is known for fixing (setting) an output signal of a level shift circuit for interfacing between different power supplies to a specific potential in order to ensure normal operation of an LSI (Large Scale Integration) that requires multiple power supplies. For example, Patent Document 1 discloses a semiconductor integrated circuit device that includes a level shift circuit that converts a signal amplitude corresponding to a first power supply voltage into a signal amplitude corresponding to a second power supply voltage, and a pull-up resistor that prevents the potential of the signal output from the level shift circuit from becoming unstable. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2011-129963 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the conventional technology, in order to prevent the potential of the signal from becoming unstable, that is, to fix the potential of the output signal to a specific potential, a pull-up resistor, a pull-down resistor, etc. are used in the level shift circuit. In this case, a current may flow through the pull-up resistor, etc., which may cause a large power loss. Thus, the conventional technology has room for improvement in terms of fixing the output signal of the level shift circuit for interfacing between different power supplies to a specific potential.

[0005] In consideration of the above circumstances, an object of the present disclosure is to provide a semiconductor device capable of reducing power loss when an output signal of a level shift circuit for interfacing different power supplies is fixed to a specific potential. [Means for solving the problem]

[0006] In order to solve the above problem, the semiconductor device disclosed herein includes a level shift unit that receives a first signal of a specific potential output from a circuit operating on a first power supply voltage via an input signal terminal and an inverted input signal terminal, converts the first signal into a second signal having a potential different from that of the first signal, and outputs the second signal via an output signal terminal to a circuit operating on a second power supply voltage having a potential different from that of the first power supply voltage; a first transistor of a first polarity having a gate to which the first power supply voltage is applied, a source to which the second power supply voltage is applied, and a drain to which the input signal terminal is connected; and a second transistor of the first polarity having a gate to which the first power supply voltage is applied, a source to which the second power supply voltage is applied, and a drain to which the output signal terminal is connected. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a semiconductor device capable of reducing power loss when an output signal of a level shift circuit for interfacing different power supplies is fixed to a specific potential. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing a configuration example of a power supply including a semiconductor device according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is a diagram showing a configuration example of a level shift circuit. [Diagram 3] FIG. 3 is a timing chart for explaining the operation of the semiconductor device. [Figure 4] FIG. 4 is a diagram showing a configuration example of a level shift circuit according to a comparative example. [Diagram 5] FIG. 5 is a diagram showing an example of the configuration of a power supply including a level shift circuit according to a comparative example. [Figure 6] FIG. 6 is a diagram showing the function of a power supply including a level shift circuit according to a comparative example. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, an embodiment will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and the description thereof will be omitted as appropriate.

[0010] (Embodiment) Fig. 1 is a diagram showing an example of the configuration of a power supply including a semiconductor device according to an embodiment of the present disclosure. Fig. 1 shows two external power supplies provided outside an LSI. Specifically, the two external power supplies may be interpreted as a circuit that supplies a first power supply voltage DVDD and a circuit that supplies a second power supply voltage SPVDD.

[0011] The circuit that supplies the first power supply voltage DVDD may include an internal power supply generating circuit 1, a control circuit 2, a level shift circuit 3, and a level shift circuit 4. In this disclosure, the "level shift circuit" may be interpreted as a level shifter.

[0012] The internal power supply generating circuit 1 may generate an internal power supply voltage VDDL based on a first power supply voltage DVDD.

[0013] The control circuit 2 may be considered as a circuit that operates on the internal power supply voltage VDDL generated by the internal power supply generating circuit 1. The control circuit 2 may generate and output a specific signal whose potential is the internal power supply voltage VDDL.

[0014] The level shift circuit 3 may receive as input a signal output from the control circuit 2. The level shift circuit 3 may convert the signal into a signal (first signal AMPEN) whose potential is a first power supply voltage DVDD different from the potential of the internal power supply voltage VDDL, and output the converted signal.

[0015] The level shift circuit 4 may be interpreted as a semiconductor device of the present disclosure. The level shift circuit 4 may input a first signal AMPEN of a specific potential output from the level shift circuit 3 that operates on the first power supply voltage DVDD, for example. The level shift circuit 4 may convert the first signal AMPEN to a second signal AMPEN_HV whose potential is different from that of the first signal AMPEN.

[0016] The level shift circuit 4 may output a second signal AMPEN_HV to a circuit that operates on a second power supply voltage SPVDD, the potential of which is different from the first power supply voltage DVDD. The configuration of the level shift circuit 4 will be described in detail later.

[0017] The external power supply SPVDD may include a level shift circuit 5 and a class D amplifier 6.

[0018] The level shift circuit 5 may be considered as a circuit that operates on the internal power supply voltage VDDL generated by the internal power supply generation circuit 1. The level shift circuit 5 may receive as input the signal output from the control circuit 2 and the second signal AMPEN_HV output from the level shift circuit 4.

[0019] Next, the configuration of the level shift circuit 4 will be described with reference to Fig. 2. Fig. 2 is a diagram showing an example of the configuration of the level shift circuit.

[0020] The level shift circuit 4 may include a level shift section 10, a first transistor 20, a second transistor 30, an input signal terminal IN1, an inverting input signal terminal IN2, an output signal terminal OUT1, an inverting output signal terminal OUT2, an inverter 40, an inverter 50, a transistor 60, and a transistor 70.

[0021] (Level shift section 10) The level shift unit 10 may receive a first signal AMPEN of a specific potential output from a circuit operating on a first power supply voltage DVDD via an input signal terminal IN1 and an inverted input signal terminal IN2. The circuit operating on the first power supply voltage DVDD may be interpreted as the level shift circuit 3 shown in Fig. 1. The circuit operating on the first power supply voltage DVDD may also be interpreted as the circuit operating on the internal power supply voltage VDDL shown in Fig. 1.

[0022] The level shift unit 10 may convert the first signal AMPEN into a second signal AMPEN_HV whose potential is different from that of the first signal AMPEN. The level shift unit 10 may output the second signal AMPEN_HV via the output signal terminal OUT1 to a circuit that operates on a second power supply voltage SPVDD whose potential is different from that of the first power supply voltage DVDD.

[0023] The level shift section 10 may include a third transistor 11 of a first polarity, a fourth transistor 12 of a first polarity, a fifth transistor 13 of a second polarity, a sixth transistor 14 of a first polarity, a seventh transistor 15 of a first polarity, and an eighth transistor 16 of a second polarity.

[0024] In the embodiments of the present disclosure, a transistor of a first polarity may be interpreted as a P-channel type Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), and a transistor of a second polarity may be interpreted as an N-channel type MOSFET.

[0025] The third transistor 11 may have a source to which a first power supply voltage DVDD is applied and a drain connected to the source of the fourth transistor 12. The third transistor 11 may have a gate connected to the output signal terminal OUT1, the drain of the seventh transistor 15, and the drain of the eighth transistor 16.

[0026] The fourth transistor 12 may have a source connected to the drain of the third transistor 11, and a drain connected to the drain of the fifth transistor 13, the inverted output signal terminal OUT2, and the gate of the sixth transistor 14. The fourth transistor 12 may have a gate connected to the drain of the first transistor 20, the input signal terminal IN1, and the gate of the fifth transistor 13.

[0027] The fifth transistor 13 may have a source grounded and a gate connected to the drain of the first transistor 20, the input signal terminal IN1, and the gate of the fourth transistor 12. The fifth transistor 13 may have a drain connected to the drain of the fourth transistor 12, the inverted output signal terminal OUT2, and the gate of the sixth transistor.

[0028] The sixth transistor 14 may have a source to which a first power supply voltage DVDD is applied, a drain connected to the source of the seventh transistor 15, and a gate connected to the drain of the fourth transistor 12, the inverted output signal terminal OUT2, and the drain of the fifth transistor 13.

[0029] The seventh transistor 15 may have a source connected to the drain of the sixth transistor 14. The seventh transistor 15 may have a drain connected to the drain of the second transistor 30, the gate of the third transistor 11, the output signal terminal OUT1, the drain of the eighth transistor 16, and the gate of the inverter 50. The seventh transistor 15 may have a gate connected to the inverted input signal terminal IN2, the gate of the eighth transistor 16, the drain of the transistor 60, and the drain of the transistor 70.

[0030] The eighth transistor 16 may have a source grounded and a drain connected to the drain of the second transistor 30, the gate of the third transistor 11, the output signal terminal OUT1, and the drain of the seventh transistor 15. The eighth transistor 16 may have a gate connected to the inverted input signal terminal IN2, the gate of the seventh transistor 15, the drain of the transistor 60, and the drain of the transistor 70.

[0031] (First transistor 20) The first transistor 20 may be interpreted as a transistor of a first polarity, in which a first power supply voltage DVDD is applied to the gate, a second power supply voltage SPVDD is applied to the source, and the drain is connected to the input signal terminal IN1.

[0032] The drain of the first transistor 20 may be connected to the gate of the fourth transistor 12, the gate of the fifth transistor 13, the output terminal of the inverter 40, the gate of the transistor 60, and the gate of the transistor .

[0033] When the potential of the first power supply voltage DVDD is lower than the specific potential, the first transistor 20 may be turned on to apply the second power supply voltage SPVDD to the input signal terminal IN1. The specific potential may be interpreted as the threshold voltage Vt (about 0.7 V) of the first transistor 20. This allows the fourth transistor 12 to continue in the off state and the fifth transistor 13 to continue in the on state while the potential of the first power supply voltage DVDD is lower than the specific potential.

[0034] (Second transistor 30) The second transistor 30 may be interpreted as a transistor of a first polarity, in which the first power supply voltage DVDD is applied to the gate, the second power supply voltage SPVDD is applied to the source, and the drain is connected to the output signal terminal OUT1.

[0035] The drain of the second transistor 30 may be connected to the drain of the seventh transistor 15 , the drain of the eighth transistor 16 , the gate of the third transistor 11 , and the input terminal of the inverter 50 .

[0036] When the potential of the first power supply voltage DVDD is lower than the specific potential, the second transistor 30 may be turned on to apply the second power supply voltage SPVDD to the output signal terminal OUT1. The specific potential may be interpreted as the threshold voltage Vt (e.g., about 0.7 V) of the second transistor 30. As a result, while the potential of the first power supply voltage DVDD is lower than the specific potential, the voltage level of the output AMPEN_HV of the inverter 50 is fixed to the L level.

[0037] The transistor 60 may be interpreted as a transistor of a first polarity having a gate connected to the output terminal of the inverter 40, a source to which a specific power supply voltage (e.g., the first power supply voltage DVDD) is applied, and a drain connected to the drain of the transistor 70. The drain of the transistor 60 may be connected to the inverting input signal terminal IN2, the gate of the seventh transistor 15, and the gate of the eighth transistor 16.

[0038] The transistor 70 may be interpreted as a transistor of a first polarity having a gate connected to the output terminal of the inverter 40, a source grounded, and a drain connected to the drain of the transistor 60. The drain of the transistor 70 may be connected to the inverting input signal terminal IN2, the gate of the seventh transistor 15, and the gate of the eighth transistor 16.

[0039] Next, the operation of the semiconductor device will be described with reference to Fig. 3. Fig. 3 is a timing chart for explaining the operation of the semiconductor device.

[0040] At time t1, when the first power supply voltage DVDD is not supplied, the first transistor 20 and the second transistor 30 are in an ON state. As a result, the voltage level of the gate of the inverter 50 becomes the H level, and the voltage level of the output (AMPEN_HV) of the inverter 50 is fixed to the L level.

[0041] Thereafter, the supply of the first power supply voltage DVDD starts, and the first transistor 20 and the second transistor 30 maintain the ON state until the first power supply voltage DVDD reaches the threshold voltage Vt at time t2. As a result, the voltage level of the gate of the inverter 50 maintains the H level. Therefore, the voltage level of the output (AMPEN_HV) of the inverter 50 continues to be fixed at the L level. The threshold voltage Vt may be interpreted as the gate voltage at which conduction occurs between the source and drain of the second transistor 30 and a current flows. The threshold voltage Vt may also be interpreted as the specific potential described above.

[0042] As a result, regardless of the state of the control signal, that is, regardless of whether the voltage level of the control signal is H level or L level, the output signal OUT of the level shift circuit 5 is fixed to a specific potential. Specifically, even when the first power supply voltage DVDD is not supplied (0 V) and the second power supply voltage SPVDD is supplied, it is possible to prevent the output signal OUT of the level shift circuit 5 from becoming unstable.

[0043] Therefore, it is possible to prevent the potentials of the output terminals SPP and SPM of the class-D amplifier 6 from becoming unstable. In other words, the class-D amplifier 6 can control the potentials of the output terminals SPP and SPM to be the desired potentials (i.e., the expected state). The control signal may be interpreted as a signal output from the control circuit 2, or as a signal of the first power supply voltage DVDD output from the level shift circuit 3 (first signal AMPEN).

[0044] When the potentials of the output terminals SPP and SPM of the class-D amplifier 6 are in an unstable state, for example, a large current may be generated through an external speaker, or unwanted sound may be generated.

[0045] In the level shift circuit 4, which is the semiconductor device of the present disclosure, the first transistor 20 is turned on while the potential of the first power supply voltage DVDD is lower than the specific potential, thereby applying the second power supply voltage SPVDD to the input signal terminal IN1. Also, the second transistor 30 is turned on while the potential of the first power supply voltage DVDD is lower than the specific potential, thereby applying the second power supply voltage SPVDD to the output signal terminal OUT1. As a result, while the potential of the first power supply voltage DVDD is lower than the specific potential, the fourth transistor 12 can be made to continue in the off state and the fifth transistor 13 can be made to continue in the on state. Also, while the potential of the first power supply voltage DVDD is lower than the specific potential, the voltage level of the output AMPEN_HV of the inverter 50 can be fixed to the L level. In other words, by fixing the output signal OUT of the level shift circuit 5, the generation of the large current and the generation of unnecessary sound as described above can be suppressed.

[0046] When the first power supply voltage DVDD exceeds Vt, the first transistor 20 and the second transistor 30 are turned off, and the voltage level of the gate voltage of the inverter 50 changes from the H level to the L level.

[0047] (Comparative Example) 4 is a diagram showing a configuration example of a level shift circuit according to a comparative example. A level shift section 10A of a level shift circuit 4A according to the comparative example includes a pull-down resistor R1 and a pull-up resistor R2. The voltage level of the output (AMPEN_HV) of the inverter 50 is fixed to the L level by the pull-down resistor R1 and the pull-up resistor R2.

[0048] Fig. 5 is a diagram showing an example of the configuration of a power supply including a level shift circuit according to a comparative example. As shown in Fig. 5, a circuit that supplies a first power supply voltage DVDD includes an internal power supply generating circuit 1, a control circuit 2, a level shift circuit 3, a level shift circuit 4, a reset circuit 7, and a level shift circuit 8. An external power supply SPVDD may include a level shift circuit 5, a class D amplifier 6, and a logical AND circuit 9.

[0049] In the configuration shown in FIG. 5, when a power supply voltage (first power supply voltage DVDD) is supplied and the power supply voltage rises to a voltage at which the level shift circuit 8 can operate normally, the voltage level of the output signal (POR_HV) of the level shift circuit 8 is fixed to the L level using the output signal (POR) of the reset circuit 7.

[0050] The logical product circuit 9 fixes the voltage level of the LVSFTEN signal at the L level until the logical product of the output signal (AMPEN_HV) of the level shift circuit 4A and the output signal (POR_HV) of the level shift circuit 8 is established. That is, the voltage level of the LVSFTEN signal is fixed at the L level until the first power supply voltage DVDD rises (until the first power supply voltage DVDD reaches a voltage at which the level shift circuit 8 can operate normally). As a result, the output signal OUT of the level shift circuit 5 is fixed.

[0051] The level shift circuit 4A includes a pull-down resistor R1 and a pull-up resistor R2, thereby setting the voltage level of the gate of the inverter 50 to the H level and fixing the voltage level of the output AMPEN_HV of the inverter 50 to the L level.

[0052] However, in this circuit configuration, during normal operation, when the voltage level of the first signal, the AMPEN signal, is set to the H level, two current paths are generated as shown in Figure 4, and current flows through the pull-down resistor R1 and the pull-up resistor R2, resulting in power loss.

[0053] Furthermore, this circuit is only effective up to about 1V, so it is necessary to use the reset circuit 7 and the level shift circuit 8 in combination. Therefore, adjustments are required so that the level shift circuit 5 does not malfunction until the first power supply voltage DVDD is supplied, which makes the circuit configuration complicated. In particular, the reset circuit 7, whose power supply is different from the power supply supplied to the class-D amplifier 6, is an analog circuit, so the wiring W for transmitting an analog signal from the reset circuit 7 to the level shift circuit 8 and the like must be manually routed (see FIG. 6).

[0054] In the level shift circuit 4, which is the semiconductor device of the present disclosure, while the potential of the first power supply voltage DVDD is lower than the specific potential, that is, when the first power supply voltage DVDD is not supplied, the first transistor 20 is turned on, so that the second power supply voltage SPVDD can be applied to the input signal terminal IN1. Also, while the potential of the first power supply voltage DVDD is lower than the specific potential, the second transistor 30 is turned on, so that the second power supply voltage SPVDD can be applied to the output signal terminal OUT1. As a result, while the potential of the first power supply voltage DVDD is lower than the specific potential, the fourth transistor 12 can be made to continue in the off state, and the fifth transistor 13 can be made to continue in the on state. Also, while the potential of the first power supply voltage DVDD is lower than the specific potential, the voltage level of the output AMPEN_HV of the inverter 50 can be fixed to the L level. In other words, by fixing the output signal OUT of the level shift circuit 5, the generation of the large current and the generation of unnecessary sound as described above can be suppressed.

[0055] Furthermore, the level shift circuit 4 can fix the voltage level of the output AMPEN_HV of the inverter 50 to the L level without using the pull-down resistor R1 and the pull-up resistor R2, thereby reducing the occurrence of power loss in the pull-down resistor R1 and the pull-up resistor R2.

[0056] In addition, since the reset circuit 7 and the level shift circuit 8 shown in Fig. 5 are not used in combination, adjustments to prevent malfunction of the level shift circuit 5 are not required, and the circuit configuration is simplified. In addition, the wiring W for transmitting the analog signal shown in Fig. 6 is provided, which reduces the manufacturing cost of the circuit. In addition, measures against noise generated from the wiring W are not required.

[0057] In addition, the following supplementary notes are provided in relation to the above description.

[0058] (Appendix 1) a level shift section that receives a first signal of a specific potential output from a circuit operating on a first power supply voltage via an input signal terminal and an inverted input signal terminal, converts the first signal into a second signal having a potential different from that of the first signal, and outputs the second signal via an output signal terminal to a circuit operating on a second power supply voltage having a potential different from that of the first power supply voltage; a first transistor of a first polarity, the first power supply voltage being applied to a gate thereof, the second power supply voltage being applied to a source thereof, and the drain thereof being connected to the input signal terminal; a second transistor of the first polarity, the gate of which is applied with the first power supply voltage, the source of which is applied with the second power supply voltage, and the drain of which is connected to the output signal terminal; A semiconductor device comprising:

[0059] (Appendix 2) the first transistor is turned on when a potential of the first power supply voltage is lower than a specific potential, thereby applying the second power supply voltage to the input signal terminal; 2. The semiconductor device according to claim 1, wherein the second transistor is turned on when a potential of the first power supply voltage is lower than a specific potential, thereby applying the second power supply voltage to the output signal terminal.

[0060] (Appendix 3) the level shift unit includes a third transistor of the first polarity, a fourth transistor of the first polarity, a fifth transistor of the second polarity, a sixth transistor of the first polarity, a seventh transistor of the first polarity, and an eighth transistor of the second polarity; the third transistor has a source to which the first power supply voltage is applied, a drain connected to the source of the fourth transistor, and a gate connected to the output signal terminal, the drain of the seventh transistor, and the drain of the eighth transistor; the fourth transistor has a source connected to the drain of the third transistor, a drain connected to the drain of the fifth transistor, an inverted output signal terminal, and a gate of the sixth transistor, and a gate connected to the drain of the first transistor, the input signal terminal, and a gate of the fifth transistor; the fifth transistor has a source grounded, a gate connected to the drain of the first transistor, the input signal terminal, and the gate of the fourth transistor, and a drain connected to the drain of the fourth transistor, the inverted output signal terminal, and the gate of the sixth transistor; the sixth transistor has a source to which the first power supply voltage is applied, a drain connected to the source of the seventh transistor, and a gate connected to the drain of the fourth transistor, the inverted output signal terminal, and a drain of the fifth transistor; the seventh transistor has a source connected to the drain of the sixth transistor, a drain connected to the drain of the second transistor, the gate of the third transistor, the output signal terminal, and the drain of the eighth transistor, and a gate connected to the inverted input signal terminal and the gate of the eighth transistor; The semiconductor device according to claim 1, wherein the eighth transistor has a source that is grounded, a drain that is connected to a drain of the second transistor, a gate of the third transistor, the output signal terminal, and a drain of the seventh transistor, and a gate that is connected to the inverting input signal terminal and the gate of the seventh transistor.

[0061] (Appendix 4) 4. The semiconductor device according to claim 1, wherein the level shift unit outputs the second signal to be applied to a class D amplifier. [Explanation of symbols]

[0062] 1 Internal power generation circuit 2. Control circuit 3 Level shift circuit 4 Level shift circuit 4A Level Shift Circuit 5 Level shift circuit 6 Class D Amplifiers 7 Reset Circuit 8 Level shift circuit 9 AND Circuit 10 Level shift section 10A Level Shift Unit 11 Third transistor 12 4th transistor 13 5th transistor 14 6th transistor 15 7th transistor 16 8th transistor 20 First transistor 30 Second transistor 40 Inverter 50 Inverter 60 Transistor 70 Transistor 100 Semiconductor device

Claims

1. a level shift section that receives a first signal of a specific potential output from a circuit operating on a first power supply voltage via an input signal terminal and an inverted input signal terminal, converts the first signal into a second signal having a potential different from that of the first signal, and outputs the second signal via an output signal terminal to a circuit operating on a second power supply voltage having a potential different from that of the first power supply voltage; a first transistor of a first polarity, the first power supply voltage being applied to a gate thereof, the second power supply voltage being applied to a source thereof, and the drain thereof being connected to the input signal terminal; a second transistor of the first polarity, the gate of which is applied with the first power supply voltage, the source of which is applied with the second power supply voltage, and the drain of which is connected to the output signal terminal; A semiconductor device comprising:

2. the first transistor is turned on when a potential of the first power supply voltage is lower than a specific potential, thereby applying the second power supply voltage to the input signal terminal; 2 . The semiconductor device according to claim 1 , wherein said second transistor is turned on when a potential of said first power supply voltage is lower than a specific potential, thereby applying said second power supply voltage to said output signal terminal.

3. the level shift unit includes a third transistor of the first polarity, a fourth transistor of the first polarity, a fifth transistor of the second polarity, a sixth transistor of the first polarity, a seventh transistor of the first polarity, and an eighth transistor of the second polarity; the third transistor has a source to which the first power supply voltage is applied, a drain connected to the source of the fourth transistor, and a gate connected to the output signal terminal, the drain of the seventh transistor, and the drain of the eighth transistor; the fourth transistor has a source connected to the drain of the third transistor, a drain connected to the drain of the fifth transistor, an inverted output signal terminal, and a gate of the sixth transistor, and a gate connected to the drain of the first transistor, the input signal terminal, and the gate of the fifth transistor; the fifth transistor has a source grounded, a gate connected to the drain of the first transistor, the input signal terminal, and the gate of the fourth transistor, and a drain connected to the drain of the fourth transistor, the inverted output signal terminal, and the gate of the sixth transistor; the sixth transistor has a source to which the first power supply voltage is applied, a drain connected to the source of the seventh transistor, and a gate connected to the drain of the fourth transistor, the inverted output signal terminal, and a drain of the fifth transistor; the seventh transistor has a source connected to the drain of the sixth transistor, a drain connected to the drain of the second transistor, the gate of the third transistor, the output signal terminal, and the drain of the eighth transistor, and a gate connected to the inverted input signal terminal and the gate of the eighth transistor; 2. The semiconductor device according to claim 1, wherein the eighth transistor has a source that is grounded, a drain that is connected to the drain of the second transistor, the gate of the third transistor, the output signal terminal, and the drain of the seventh transistor, and a gate that is connected to the inverting input signal terminal and the gate of the seventh transistor.

4. The semiconductor device according to claim 1 , wherein the level shift section outputs the second signal to be applied to a class D amplifier.

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