Time digital conversion device, distance measuring device, and mobile body

Abstract

To provide technology which is useful for preventing false measurement in a time digital conversion device.SOLUTION: A time digital conversion circuit comprises a first measurement block and one or a plurality of second measurement blocks. The first measurement block activates a control signal in accordance with the activation of a start signal, and measures a time from the activation of the start signal to a first edge of a common clock signal. The second measurement blocks include a lower measurement circuit and an upper measurement circuit which are enabled by activation of the control signal. The lower measurement circuit measures a time from activation of a stop signal to a second edge of the common clock signal, and the upper measurement circuit measures a time from the first edge to the second edge.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a time-to-digital conversion device, a distance measuring device, and a moving object. [Background technology]

[0002] In recent years, time-to-digital converters (TDCs) that convert time into digital signals have been used in various fields. The time-to-digital converter described in Patent Document 1 is applied to a sensor capable of capturing a three-dimensional (3D) distance image, and measures the time-of-flight of photons detected by a SPAD (Single Photon Avalanche Diode) pixel. The time-to-digital converter in Patent Document 1 also includes a coarse TDC and a fine TDC. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2013 / 034770 Summary of the Invention [Problem to be solved by the invention]

[0004] A time-to-digital conversion device that measures the time from receipt of a start signal to receipt of a stop signal cannot correctly measure the time if it receives a stop signal before receiving a start signal and reacts to the stop signal, even if it subsequently receives a start signal and the corresponding stop signal.

[0005] An object of the present invention is to provide an advantageous technique for preventing erroneous measurement in a time-to-digital conversion device. [Means for solving the problem]

[0006] The present invention relates to a time-to-digital conversion circuit, the time-to-digital conversion circuit comprising a first measurement block and one or more second measurement blocks, the first measurement block activating a control signal in response to activation of a start signal and measuring the time from the activation of the start signal to a first edge of a common clock signal, the second measurement block including a lower measurement circuit and an upper measurement circuit enabled by the activation of the control signal, the lower measurement circuit measuring the time from the activation of a stop signal to a second edge of the common clock signal, and the upper measurement circuit measuring the time from the first edge to the second edge. Effect of the Invention

[0007] According to the present invention, an advantageous technique is provided for preventing erroneous measurement in a time-to-digital conversion device. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the configuration of a distance measuring device according to an embodiment. [Diagram 2] FIG. 1 is a diagram showing the configuration of a range image sensor according to an embodiment. [Diagram 3] FIG. 2 is a diagram showing a configuration example of a measurement block that can be used as a first measurement block and a second measurement block. [Figure 4] 3A and 3B are diagrams showing configuration examples of a measurement block configured as a first measurement block and a measurement block configured as a second measurement block; [Diagram 5] FIG. 2 is a diagram showing an example of the configuration of a control circuit. [Figure 6] FIG. 4 is a diagram showing an example of the configuration of each of control circuits of a first measurement block and a second measurement block. [Figure 7] FIG. 1 is a circuit diagram showing an example of the configuration of a multi-phase VCO. [Figure 8] FIG. 2 is a circuit diagram showing a configuration example of a PLL circuit. [Figure 9] FIG. 4 is a circuit diagram showing a configuration of a signal generating circuit. [Figure 10] 1 is a diagram illustrating an example of the operation of a distance measuring device and a time-to-digital conversion device; [Figure 11]FIG. 13 is a diagram showing a modified example of a control circuit. [Figure 12] FIG. 13 is a diagram showing a first modified example of the range image sensor. [Figure 13] FIG. 13 is a diagram showing a second modified example of the range image sensor. [Figure 14] FIG. 2 is a circuit diagram showing a configuration example of a pixel. [Figure 15] FIG. 11 is a circuit diagram showing another example of the configuration of a pixel. [Figure 16] FIG. 2 is a diagram showing the configuration of a range image sensor. [Figure 17] FIG. 1 is a diagram showing an example of the configuration of a moving object. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described in detail with reference to the attached drawings. Note that the following embodiments do not limit the invention according to the claims. Although the embodiments describe a number of features, not all of these features are essential to the invention, and the features may be combined in any manner. Furthermore, in the attached drawings, the same reference numbers are used for the same or similar configurations, and duplicated descriptions are omitted.

[0010] FIG. 1 is a diagram showing the configuration of a distance measuring device RS according to an embodiment. The distance measuring device RS may be configured as, for example, a distance image generating device that generates a distance image. The distance measuring device RS measures the distance from the distance measuring device RS to an object OBJ based on the time of flight (TOF: Time Of Flight) of light. The distance measuring device RS may include, for example, a light emitting unit 110, an optical system 105, a distance image sensor 100, an image processing circuit 101, a memory 102, a monitor 103, and a control unit 104. Note that, although the distance measuring device RS is described here as including the distance image sensor 100 as one of a plurality of components, the distance image sensor 100 can also be understood as a distance measuring device. That is, the distance image sensor 100 can also be understood as the smallest component of the distance measuring device RS.

[0011] The control unit 104 controls the light emitting unit 110, the optical system 105, the range image sensor 100, the image processing circuit 101, the memory 102, and the monitor 103. The control unit 104 can be configured to send a light emitting command to the light emitting unit 110 and to send a start command START to the range image sensor 100 (its time-to-digital conversion circuit). Sending the start signal START is synonymous with activating the start signal START. The light emitting command may be the same as the start command START, or may be a signal that is activated with a predetermined time difference from the timing of activation of the start signal START.

[0012] The light emitting unit 110 emits pulsed light such as laser light in response to a light emission command. If an object OBJ exists in an area where the pulsed light is irradiated, the pulsed light may be reflected by the object OBJ and enter the optical system 105. The optical system 105 forms an optical image of the object OBJ by the incident pulsed light on a pixel array of the distance image sensor 100. The distance image sensor 100 may include a pixel array having a plurality of pixels constituting the pixel array, and a time-to-digital conversion circuit that converts the time from the reception of a start signal START to the reception of a stop signal output from each of the plurality of pixels of the pixel array into a digital signal. The pixels are preferably, for example, avalanche photodiodes, particularly SPADs (Single Photon Avalanche Diodes) that receive single photons, but may be other types of pixels, for example, event detection type pixels. The image processing circuit 101 may generate a distance image including distance information to the object OBJ based on the signal output from the time-to-digital conversion device and the known speed of light. The generated distance image can be output to the memory 102 and the monitor 103. The memory 102 stores the distance image, and the monitor 103 displays the distance image. The image processing circuit 101 may be incorporated in the distance image sensor 100.

[0013] FIG. 2 is a block diagram of the range image sensor 100. The range image sensor 100 includes a pixel array PA composed of a plurality of pixels 10 arranged to form a plurality of rows and a plurality of columns. The range image sensor 100 also includes a time digital conversion device TDCC that converts the time from the emission of the light emitting unit 110 (activation of the start signal START) to the reception of light by the pixel 10 (activation of the stop signal STOP) into a digital signal based on a signal from each of the plurality of pixels 10. The digital conversion device TDCC may include a first measurement block (TDC1) 20-1, a plurality of second measurement blocks (TDC2) 20-2, and a PLL (Phase Locked Loop) circuit 50. Here, an example in which the digital conversion device TDCC includes a plurality of second measurement blocks 20-2 will be described, but the digital conversion device TDCC may include only one second measurement block 20-2. In other words, the digital conversion device TDCC may include one or a plurality of second measurement blocks 20-2. As described below, the first measurement block 20-1 and the second measurement block 20-2 have the same configuration, but may have different configurations. The digital conversion device TDCC may optionally include a frequency divider 30, a signal generating circuit 40 and an arithmetic circuit 60.

[0014] 14 is a circuit diagram showing an example of a configuration of a pixel 10. The pixel 10 includes, for example, a SPAD 11, a quenching element 12, and a waveform shaping unit 13, and functions as a light receiving unit of pulsed light. The SPAD 11 generates a pair of charges according to incident light by photoelectric conversion. A voltage VL (first voltage) is supplied to the anode of the SPAD 11, and a voltage VH (second voltage) higher than the voltage VL supplied to the anode is supplied to the cathode of the SPAD 11. A reverse bias voltage is applied between the anode and the cathode, and the SPAD 11 is in a state where avalanche multiplication is possible. When a photon is incident on the SPAD 11 in a state where the reverse bias voltage is supplied, the charge generated by the photon causes avalanche multiplication, and an avalanche current is generated.

[0015] The quench element 12 is provided between a power supply line that supplies the voltage VH and the cathode of the SPAD 11. The quench element 12 functions as a load circuit (quench circuit) during signal multiplication by avalanche multiplication, and has the function of suppressing the voltage supplied to the SPAD 11 and suppressing the avalanche multiplication (quench operation). The quench element 12 also has the function of returning the voltage supplied to the SPAD 11 to the voltage VH by passing a current equivalent to the voltage drop caused by the quench operation (recharge operation).

[0016] The waveform shaping unit 13 can function as a signal generating unit that generates a detection pulse as a stop signal STOP in response to an output change occurring at the cathode of the SPAD 11 due to the incidence of a photon. That is, the waveform shaping unit 13 can shape the potential change at the cathode of the SPAD 11 obtained at the time of photon detection, and output a square-wave STOP signal (detection pulse). The waveform shaping unit 13 can be configured, for example, by an inverter circuit. Although FIG. 14 illustrates an example of the waveform shaping unit 13 configured by one inverter circuit, the waveform shaping unit 13 may be configured by connecting a plurality of inverter circuits in series, or may be configured by another circuit having a waveform shaping effect.

[0017] 3 is a diagram showing an example of the configuration of the measurement block 20 that can be used as the first measurement block 20-1 and the second measurement block 20-2. The measurement block 20 can be configured as either the first measurement block 20-1 or the second measurement block 20-2 depending on the signal or voltage applied to the input terminal of the measurement block 20. Of course, the first measurement block 20-1 and the second measurement block 20-2 may have different configurations.

[0018] The measurement block 20 may include, for example, a control circuit (sequencer) 21, a multiplexer 22, a polyphase VCO (Voltage Controlled Oscillator) 23, a lower encoder 24, a lower counter 25, and an upper counter 26. The upper counter 26 constitutes an upper measurement circuit 27 that generates an upper bit string of the digital data output by the measurement block 20. The polyphase VCO 23, the lower encoder 24, and the lower counter 25 constitute a lower measurement circuit 28 that generates a lower bit string of the digital data output by the measurement block 20.

[0019] The control circuit 21 may have a clock input terminal CLK and a trigger input terminal TRIG. A common clock signal TDCLK is supplied to the clock input terminal CLK. The common clock signal TDCLK may be a global clock signal commonly used in the distance measuring device RS. A start signal START is supplied to the trigger input terminal TRIG of the measurement block 20 configured as the first measurement block 20-1. On the other hand, a stop signal STOP is supplied to the trigger input terminal TRIG of the measurement block 20 configured as the second measurement block 20-2. The control circuit 21 generates a clock signal CoarseCLK and an enable signal EN according to the common clock signal TDCLK supplied to the clock input terminal CLK and the start signal START or the stop signal STOP supplied to the trigger input terminal TRIG. The clock signal CoarseCLK is a clock signal for the upper measurement circuit 27 (upper counter 26). The enable signal EN is a signal that enables the lower measurement circuit 28 (multi-phase VCO 23).

[0020] The multiplexer 22 is a switching circuit that selects either the enable signal EN or the period measurement signal PERIOD from the signal generating circuit 40 according to the operation mode, and outputs the selected signal as the enable signal ENS to the polyphase VCO 23. Here, the time-to-digital conversion device TDCC can have a distance image generation mode in which a distance image is generated, and a period measurement mode in which the periods of the lower encoder 24, the lower counter 25, and the upper counter 26 are measured. In the distance image generation mode, the multiplexer 22 outputs the enable signal EN as the enable signal ENS, and in the period measurement mode, the multiplexer 22 outputs the period measurement signal PERIOD for correction processing as the enable signal ENS. In the period measurement mode, the periods of the lower encoder 24, the lower counter 25, and the upper counter 26 are measured, and the result can be stored in the arithmetic circuit 60 as calibration data. The arithmetic circuit 60 can correct the digital data obtained in the distance image generation mode based on the calibration data.

[0021] The multi-phase VCO 23 may be an oscillator circuit, more specifically, a multi-phase output voltage-controlled oscillator circuit such as a ring oscillator circuit. When the ring oscillator circuit is composed of M (M is an integer equal to or greater than 2) inverting circuits, the multi-phase VCO 23 generates an M-bit clock signal. The details of the multi-phase VCO 23 will be described later.

[0022] The lower encoder 24 encodes the M-bit clock signal of the polyphase VCO 23 and outputs binary code data Dfine_phase. The lower counter 25 counts the number of periods of the one-phase (1-bit) clock signal of the M-bit signal of the polyphase VCO 23 and outputs binary code data Dfine_cycle.

[0023] The upper counter 26 is used only in the second measurement block 20-2. The upper counter 26 starts counting the clock signal CoarseCLK (clock signal TDCLK) in response to the rising edge of the start signal START, and stops counting in response to the rising edge of the stop signal STOP. The upper counter 26 outputs the count result as binary code data Dcoarse.

[0024] 4 is a diagram illustrating a measurement block 20 configured as a first measurement block 20-1 and a measurement block 20 configured as a second measurement block 20-2. The second measurement block 20-2 may be provided for each row of the pixel array PA, for example. A plurality of pixels 10 in each row of the pixel array PA (i.e., pixels 10 in different columns) may be selected by a selection circuit (not shown) and sequentially connected to the second measurement block 20-2.

[0025] A high level (active level) is supplied to the first control input terminal START_RCV_IN of the first measurement block 20-1. A second control input terminal START_SYNC_IN of the first measurement block 20-1 is fixed to a low level (inactive level). A first control output terminal START_RCV_OUT of the first measurement block 20-1 is connected to each of the first control input terminals START_RCV_IN of all the second measurement blocks 20-2, and supplies a first control signal START_rcv. A second control output terminal START_SYNC_OUT of the first measurement block 20-1 is connected to each of the second control input terminals START_SYNC_IN of all the second measurement blocks 20-2, and supplies a second control signal START_Sync. As described above, a start signal START is supplied to the trigger input terminal TRIG of the first measurement block 20-1, and a stop signal STOP is supplied to the trigger input terminal TRIG of the second measurement block 20-20.

[0026] FIG. 10 is a diagram illustrating an example of the operation of the distance measuring device RS and the time-to-digital conversion device TDCC. The schematic operation of the distance measuring device RS and the time-to-digital conversion device TDC will be described with reference to FIG. 3, FIG. 4, FIG. 10, etc. The first measurement block 20-1 activates the first control signal STRAT_rcv in response to the activation of the start signal START, and measures the time Tst from the activation of the start signal START to the first edge E1 of the common clock TDCLK. The first measurement block 20-1 may include a first control circuit 21 that activates the first control signal Start_rcv in response to the activation of the start signal START, and a lower measurement circuit 28 that measures the time Tst from the activation of the start signal START to the first edge E1.

[0027] The second measurement block 20-2 includes a lower measurement circuit 28 and an upper measurement circuit 27 that are enabled by the activation of the first control signal START_rcv and the second control signal START_Sync. The lower measurement circuit 28 measures the time Tstop from the activation of the stop signal STOP to the second edge E2 of the common clock TDCLK. The upper measurement circuit 27 measures the time Δt from the first edge E1 to the second edge E2.

[0028] Here, the time Δt from the activation of the start signal START to the activation of the stop signal STOP is expressed by the following formula (1), as is clear from FIG.

[0029] Δt=Tst+Tcoarse-Tstop Tst is given by a lower bit string Dfine consisting of Dfine_cycle and Dfine_cycle obtained by the lower measurement circuit 28 of the first measurement block 20-1. Tstop is given by a lower bit string Dfine consisting of Dfine_cycle and Dfine_cycle obtained by the lower measurement circuit 28 of the second measurement block 20-2. Tcoarse is given by an upper bit string Dcoarse consisting of Dcoarse obtained by the upper measurement circuit 27 of the second measurement block 20-2. The arithmetic circuit 60 generates and outputs digital data corresponding to time Δt based on these.

[0030] Fig. 5 is a circuit diagram showing a configuration example of the control circuit 21. Fig. 6 illustrates a first control circuit 21-1 which is the control circuit 20 of the measurement block 20 configured as the first measurement block 20-1. Fig. 6 also illustrates a second control circuit 21-2 which is the control circuit 20 of the measurement block 20 configured as the second measurement block 20-2.

[0031] The first control circuit 21 of the first measurement block 20-1 may activate the first control signal START_rcv in response to activation of the start signal START. Also, the first control circuit 21-1 of the first measurement block 20-1 may output, as the second control signal START_Sync, a signal obtained by synchronizing the first control signal START_rcv with the common clock signal TDCLK.

[0032] The second control circuit 21-2 of the second measurement block 20-2 causes the upper measurement circuit 27 of the second measurement block 20-2 to start measurement in response to the activation of the second control signal START_Sync following the activation of the first control signal START_rcv. In addition, the second control circuit 21-2 causes the lower measurement circuit 28 of the second measurement block 20-2 to start measurement in response to the activation of the stop signal STOP with the first control signal START_rcv being activated. In addition, the second control circuit 21-2 causes the upper measurement circuit 27 of the second measurement block 20-2 to end measurement in response to the second edge E2. In addition, the second control circuit 21-2 causes the lower measurement circuit 28 of the second measurement block 20-2 to end measurement in response to the second edge E2. In this way, the second measurement block 20-2 is enabled by the first control signal START_rcv and the second control signal START_Sync, thereby preventing malfunction due to the stop signal STOP that may arrive before the start signal START.

[0033] The first control circuit 21-1 may include a first detection circuit 211-1 that activates the first control signal START_rcv asynchronously with the common clock signal TDCLK in response to the activation of the start signal STRAT. The first control circuit 21-1 may also include a second detection circuit (212-1, 213-1) that activates the second control signal STRAT_Sync in synchronization with the common clock signal TDCLK in response to the activation of the first control signal START_rcv. The second detection circuit may include a first flip-flop 212-1 and a second flip-flop 213-1. The first flip-flop 212-1 may capture the first control signal START_rcv in response to a third edge of the common clock signal TDCLK that arrives next to the activation of the first control signal START_rcv. The second flip-flop 213-1 may generate the second control signal START_Sync by capturing the output of the first flip-flop 212-1 in response to a fourth edge of the common clock signal TDCLK that arrives next to the third edge.

[0034] The second control circuit 21-2 may include a third detection circuit 211-2 that activates its output asynchronously with the common clock signal TDCLK in response to activation of the stop signal STOP. The second control circuit 21-2 may also include a fourth detection circuit (212-2, 213-2) that activates its output in response to activation of the third detection circuit 211-2.

[0035] The fourth detection circuit may include a third flip-flop 212-2 and a fourth flip-flop 213-2. The third flip-flop 212-2 may capture the output of the third detection circuit 211-2 in response to a fifth edge of the common clock signal TDCLK arriving after the activation of the output of the third detection circuit 211-2. The fourth flip-flop 213-2 may update its own output by capturing the output of the third flip-flop 212-2 in response to a sixth edge of the common clock signal TDCLK arriving after the fifth edge.

[0036] The first control circuit 21-1 of the first measurement block 20-1 may include a first enable circuit 214-1. The first enable circuit 214-1 activates an enable signal EN in response to the activation of the first control signal START_rcv, which is the output of the first detection circuit 211-1, in response to the activation of the start signal START. This causes the measurement by the lower measurement circuit 28 of the first measurement block 20-1 to start. The first control circuit 21-1 of the first measurement block 20-1 may include a second enable circuit 218-1. The second enable circuit 218-1 may be composed of circuits 215-1, 216-1, and 217-1. Since the second control input terminal START_SYNC_IN of the first control circuit 21-1 is fixed to a low level (inactive level), the second enable circuit 218-1 does not toggle the clock signal CoarseCLK for the upper measurement circuit 27.

[0037] The second control circuit 21-2 of the second measurement block 20-2 may include a third enable circuit 214-2. The third enable circuit 214-2 activates an enable signal EN in response to the output of the third detection circuit 211-2 being activated in response to the activation of the stop signal STOP. This causes the measurement by the lower measurement circuit 28 of the second measurement block 20-2 to start. The second control circuit 21-2 of the second measurement block 20-2 may include a fourth enable circuit 218-2. The fourth enable circuit 218-2 may be composed of circuits 215-2, 216-2, and 217-2. A second control signal Start_Synx is supplied to the second control input terminal START_SYNC_IN of the second control circuit 21-2 from the second control output terminal START_SYNC_OUT of the first control circuit 21-1. When the second control signal Start_Synx is activated, the fourth enable circuit 218-2 outputs a common clock signal TDCLK as a clock signal CoarseCLK for the upper measurement circuit 27 in response thereto. As a result, the upper measurement circuit 27 of the second measurement block 20-2 starts measurement. On the other hand, when the fourth flip-flop 213-2 activates its output in response to the second edge of the common clock signal TDCLK, the fourth enable circuit 218-2 stops toggling the clock signal CoarseCLK for the upper measurement circuit 27. As a result, the upper measurement circuit 27 of the second measurement block 20-2 stops measurement.

[0038] FIG. 7 is a circuit diagram showing the configuration of the multi-phase VCO 23. The multi-phase VCO 23 can be formed of a ring oscillator circuit including M inverter circuits 231-23M. The non-inverting output node of the inverter circuit 231 is connected to the inverting input node of the inverter circuit 232, and the inverting output node of the inverter circuit 231 is connected to the non-inverting input node of the inverter circuit 232. Similarly, the inverter circuits 232-23M are connected in cascade, and the output node of the inverter circuit 23M is connected to the input node of the inverter circuit 231. An enable signal EN is input to the inverter circuits 231-23M. When the enable signal ENS becomes high level, the output signals of the output nodes of the inverter circuits 231-23M are sequentially inverted with a predetermined delay time. This allows the multi-phase VCO 23 to operate as an M-bit multi-phase oscillation circuit. When the enable signal EN21-1 becomes low level, the inversion operation of the inverter circuits 231-23M is stopped, and the M-bit output signal is reset to an initial value (initial phase). In addition, a control voltage VCTRL is applied to the multi-phase VCO 23, and the oscillation frequency and phase of the inverter circuits 231-23M can be controlled by the control voltage VCTRL. For example, the control voltage VCTRL is applied to the gate nodes of the current source transistors or load transistors that configure the inverter circuits 231-23M. This causes the delay time (phase) of the inverter circuits 231-23M to change according to the control voltage VCTRL, making it possible to control the oscillation frequency and phase of the ring oscillator circuit.

[0039] FIG. 8 is a circuit diagram showing a configuration example of the PLL circuit 50. The PLL circuit 50 is a phase-locked loop circuit. The PLL circuit 50 may include, for example, a phase comparator 51, a loop filter 52, a multi-phase VCO 54, and a frequency divider 56. The multi-phase VCO 54 is configured as a ring oscillator circuit and desirably has the same characteristics as the multi-phase VCO 23. For example, the multi-phase VCO 54 may be configured as a replica circuit having the same circuit configuration and size as the multi-phase VCO 23 on a semiconductor substrate. The frequency divider 56 divides the frequency of a 1-bit clock signal among the M bits of the multi-phase VCO 54 by 1 / N (N is an integer of 2 or more) and outputs a feedback clock signal FBCLK. That is, the feedback clock signal FBCLK is a frequency-divided signal of the oscillation period of the multi-phase VCO 54. The phase comparator 51 includes a phase comparison circuit and a charge pump circuit, and outputs a charge pump voltage obtained by integrating the phase difference between the common clock signal TDCLK and the feedback clock signal FBCLK. The loop filter 52 smoothes the charge pump voltage and outputs a control voltage VCTRL. The control voltage VCTRL is supplied to the multi-phase VCO 54, and the phase of the multi-phase VCO 54 is controlled by the control voltage VCTRL. As a result, the common clock signal TDCLK and the feedback clock signal FBCLK obtained by dividing the output signal of the multi-phase VCO 54 are in phase. The control voltage VCTRL is also supplied to the multi-phase VCO 23 of each TDC 20. The multi-phase VCO 23 of the TDC 20 oscillates at a frequency N times (N is an integer equal to or greater than 2) the frequency of the clock signal TDCLK, and the phases of the multi-phase VCOs 23 are synchronized. In this way, the frequencies and phases of the multi-phase VCOs 23 of the multiple TDCs 20 are controlled by the common PLL circuit 50, and are therefore robust to manufacturing processes, voltages, and temperatures. Therefore, even if the element sizes of the multi-phase VCOs 23 and 53 are reduced, the characteristic fluctuations in the multiple TDCs 20 can be suppressed, and high-precision time-to-digital conversion can be realized while reducing power consumption.

[0040] The frequency divider 30 and the signal generating circuit 40 generate a signal PERIOD for the period measurement mode. FIG. 9 is a circuit diagram showing the configuration of the signal generating circuit 40. The signal generating circuit 40 may include flip-flops 41, 42 and a gate 43. The flip-flops 41, 42 are D-type flip-flops and are connected in cascade. An input node D of the flip-flop 41 is fixed to a high level (power supply voltage), and an output node N1 of the flip-flop 41 is connected to an input node D of the flip-flop 42. A common clock signal TDCLK is supplied to the clock nodes of the flip-flops 41, 42. A non-inverting input node of the gate 43 is connected to the node N1, and an inverting input node of the gate 43 is connected to a node N2. After the reset signal RESET supplied to the reset nodes of the flip-flops 41, 42 becomes low level, the node N1 becomes high level at the rising edge of the clock signal TDCLK. At the rising edge of the clock signal TDCLK one period later, the node N2 becomes high level. As a result, a signal PERIOD that goes high during one cycle of the clock signal TDCLK is output from the output node of the gate 43. Also, in the preceding stage of the signal generating circuit 40, the frequency divider 30 divides the frequency of the clock signal TDCLK, making it possible to generate a signal PERIOD that goes high every two or four cycles of the clock signal TDCLK.

[0041] FIG. 11 shows a modified control circuit 21'. The control circuit 21' is a modified control circuit 21. The control circuit 21' has the second control input terminal START_Sync_IN and the second control input terminal START_Sync_OUT removed. The first control signal START_rcv driven by the control circuit 21' of the first measurement block 20-1 is received at the first control input terminal START_RCV_IN of the control circuit 21' of the second measurement block 20-2. The first control input terminal START_RCV_IN is connected to the set terminal of the circuit 217 (SR latch) of the second enable circuit 218-1. Therefore, in the control circuit 21' of the second measurement block 20-2, the second enable circuit 218-1 enables the upper measurement circuit 27 in response to the activation of the first control signal START_rcv. That is, in this modified example, the control circuit 21' of the second measurement block 20-2 enables the measurement in the second measurement block 20-2 in response to the activation of the first control signal START_rcv. In other words, (measurement at) the second measurement block 20-2 is enabled by the first measurement block 20-1 activating the first control signal START_rcv.

[0042] Fig. 12 is a diagram showing a first modified example of the range image sensor 100. In the first modified example, one second measurement block 20-2 is provided for one pixel 10. Fig. 13 is a diagram showing a second modified example of the range image sensor 100. In the second modified example, a plurality of pixels 10 constituting a pixel array are divided into a plurality of groups, each group being made up of at least two pixels 10, and one second measurement block 20-2 being provided for one group. From another perspective, each group may be made up of pixels 10 belonging to two consecutive rows and at least two consecutive columns.

[0043] FIG. 15 shows another example of the configuration of the pixel 10. In the example of the configuration of FIG. 15, the pixel 10 is an event detection type pixel. The pixel 10 may include a logarithmic response unit 410, a buffer 420, a differentiation circuit 430, and a comparator 440. The logarithmic response unit 410 may include a photoelectric conversion element 411 and a current-voltage conversion unit 416. The photoelectric conversion element 411 may be a photodiode that does not cause avalanche multiplication. When pulsed light is incident on the photoelectric conversion element 411, the photoelectric conversion element 411 generates a photocurrent by photoelectric conversion. The current-voltage conversion unit 416 logarithmically converts the photocurrent into a pixel voltage Vp. The current-voltage conversion unit 416 may include N-type transistors 412 and 415, a capacitance 413, and a P-type transistor 414.

[0044] The source of N-type transistor 412 is connected to the cathode of photoelectric conversion element 411, and the drain is connected to a power supply terminal. P-type transistor 414 and N-type transistor 415 are connected in series between a power supply line and a ground line. The connection point of P-type transistor 414 and N-type transistor 415 is connected to the gate of N-type transistor 412 and the input terminal of buffer 420. The connection point of N-type transistor 412 and photoelectric conversion element 411 is connected to the gate of N-type transistor 415. A bias voltage Vb1 is applied to the gate of P-type transistor 414. Capacitor 413 is disposed between the gate of N-type transistor 412 and the gate of N-type transistor 415.

[0045] Buffer 420 may include P-type transistors 421 and 422. P-type transistors 421 and 422 are connected in series between a power supply line and a ground line. The gate of P-type transistor 422 is connected to logarithmic response unit 410, and the connection point of P-type transistors 421 and 422 is connected to differentiation circuit 430. A bias voltage Vb2 is applied to the gate of P-type transistor 421.

[0046] The differentiation circuit 430 includes a capacitance 431, P-type transistors 432 and 433, and an N-type transistor 435. The differentiation circuit 430 may further include a capacitance 434. The P-type transistor 433 and the N-type transistor 435 are connected in series between a power supply line and a ground line. A bias voltage Vdiff is applied to the gate of the N-type transistor 435. The capacitance 431 is inserted between the buffer 420 and the input terminal 491. The capacitance 431 supplies a current corresponding to the time differential of the pixel voltage Vp from the buffer 420 to the input terminal 491. The capacitance 434 may be disposed between the gate and drain of the P-type transistor 433, but the capacitance 434 may be omitted.

[0047] In response to the initialization signal Trs, the P-type transistor 432 shorts the gate and drain of the P-type transistor 433, and sets the differentiated signal Vout to its initial value.

[0048] The comparator 440 may include a P-type transistor 441 and an N-type transistor 442. The P-type transistor 441 and the N-type transistor 442 are connected in series between a power supply line and a ground line. The gate of the P-type transistor 441 is connected to the differentiation circuit 430. A threshold voltage Vth is applied to the gate of the N-type transistor 442. A stop signal STOP is output from the connection point of the P-type transistor 441 and the N-type transistor 442.

[0049] FIG. 16 shows a configuration example of the range image sensor 100. In this configuration example, the range image sensor 100 has a stacked structure of multiple substrates. The range image sensor 100 includes a sensor substrate (first substrate) 1 and a circuit substrate (second substrate) 2 stacked on top of each other, and the sensor substrate 1 and the circuit substrate 2 are electrically connected to each other. The range image sensor 100 is a back-illuminated type, in which light is incident from a first surface of the sensor substrate 1, and the circuit substrate 2 is disposed on a second surface of the sensor substrate 1. The sensor substrate 1 has a first semiconductor layer and a first wiring structure. The circuit substrate 2 has a second semiconductor layer and a second wiring structure. The second semiconductor layer, the second wiring structure, the first wiring structure, and the first semiconductor layer are stacked in this order to form the range image sensor 100.

[0050] The sensor substrate 1 and the circuit substrate 2 may be diced chips, but are not limited to chips. For example, each substrate may be a wafer. Also, each substrate may be stacked in a wafer state and then diced, or may be chipped and then stacked and bonded. The sensor substrate 1 is provided with a pixel region 1a including an array of the SPAD 11 of each of the multiple pixels 10, and the circuit substrate 2 is provided with a circuit region 2a for processing signals detected by the pixel region 1a. In the circuit region 2a, circuits 10' other than the SPAD 11 of the pixel 10, such as the TDC 20, the frequency divider 30, the signal generating circuit 40, the PLL circuit 50, and the arithmetic circuit 60, are arranged.

[0051] An application example of the range image sensor 100 will be described below. Fig. 17(a) shows a configuration example of a device mounted on a vehicle as an on-board camera. The device 300 has a distance measurement unit 303 and a collision determination unit 304. The distance measurement unit 303 is configured by the above-mentioned range image sensor 100, and measures the distance to an object. The distance information is information related to the distance to the object, etc. The collision determination unit 304 determines whether or not there is a possibility of a collision based on the distance measured by the distance measurement unit 303.

[0052] The device 300 is connected to a vehicle information acquisition device 310 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. In addition, the device 300 is connected to a control ECU 320, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 304. In addition, the device 300 is also connected to an alarm device 330 that issues an alarm to the driver based on the judgment result of the collision judgment unit 304. For example, when the judgment result of the collision judgment unit 304 indicates that there is a high possibility of a collision, the control ECU 320 instructs the vehicle to apply the brakes, stop the accelerator, suppress the engine output, etc., to avoid the collision and reduce damage. The alarm device 330 warns the user through alarm output such as sound, display of alarm information on the screen of a car navigation system, etc., and vibration of the seat belt and steering wheel. These devices of the device 300 function as a mobile object control unit that controls the operation of controlling the vehicle as described above.

[0053] In this embodiment, the device 300 measures distances around the vehicle, for example, in front or behind. Fig. 17(b) shows the device when measuring distances in front of the vehicle (distance measurement range 350). A vehicle information acquisition device 310, which serves as a distance measurement control means, sends an instruction to the device 300 or the distance measurement unit 303 to perform a distance measurement operation. This configuration can further improve the accuracy of distance measurement.

[0054] Although the above describes the control of avoiding collision with other vehicles, the present embodiment can also be applied to control of automatic driving by following other vehicles, control of automatic driving so as not to deviate from lanes, etc. Furthermore, the device is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present embodiment can be applied to devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, in addition to moving bodies.

[0055] The disclosure of the present specification includes the following configurations. (Item 1) A first measurement block and one or more second measurement blocks; the first measurement block activates a control signal in response to activation of a start signal, and measures a time from the activation of the start signal to a first edge of a common clock signal; the second measurement block includes a lower measurement circuit and an upper measurement circuit that are enabled by activation of the control signal; the lower-level measurement circuit measures the time from activation of a stop signal to a second edge of the common clock signal, and the upper-level measurement circuit measures the time from the first edge to the second edge. A time-to-digital conversion circuit. (Item 2) the first measurement block includes a first control circuit that activates the control signal in response to activation of the start signal, and a measurement circuit that measures the time from activation of the start signal to the first edge; 2. The time-to-digital conversion circuit according to item 1. (Item 3) the first control circuit outputs a signal obtained by synchronizing the control signal in accordance with the common clock signal as a second control signal; the second measurement block includes a second control circuit; the second control circuit causes the higher-level measurement circuit to start measurement in response to the second control signal being activated following the activation of the control signal; causing the lower-level measurement circuit to start measurement in response to the stop signal being activated while the control signal is activated; 3. The time-to-digital conversion circuit according to item 2. (Item 4) the second control circuit causes the higher-level measurement circuit to end measurement in response to the second edge; 4. The time-to-digital conversion circuit according to item 3. (Item 5) the second control circuit causes the lower level measurement circuit to terminate measurement in response to the second edge; 5. The time-to-digital conversion circuit according to item 3 or 4. (Item 6) the first control circuit includes a first detection circuit that activates the control signal asynchronously with the common clock signal in response to activation of the start signal, and a second detection circuit that activates the second control signal in synchronization with the common clock signal in response to activation of the control signal; the second detection circuit includes a first flip-flop that captures the control signal in response to a third edge of the common clock signal that arrives following activation of the control signal, and a second flip-flop that generates the second control signal by capturing an output of the first flip-flop in response to a fourth edge of the common clock signal that arrives following the third edge. 6. A time-to-digital conversion circuit according to any one of items 3 to 5. (Item 7) the second control circuit includes a third detection circuit that activates its output asynchronously with the common clock signal in response to activation of the stop signal, and a fourth detection circuit that activates its output in synchronization with the common clock signal in response to activation of the output of the third detection circuit, the fourth detection circuit includes a third flip-flop that captures the output of the third detection circuit in response to a fifth edge of the common clock signal that arrives following activation of the output of the third detection circuit, and a fourth flip-flop that updates its own output by capturing the output of the third flip-flop in response to a sixth edge of the common clock signal that arrives following the fifth edge. 7. A time-to-digital conversion circuit according to any one of items 3 to 6. (Item 8) The second measurement block has the same configuration as the first measurement block. 6. A time-to-digital conversion circuit according to any one of claims 1 to 5. (Item 9) a pixel array having a plurality of pixels; A time-to-digital conversion circuit according to any one of items 1 to 8, The second measurement blocks of the time-to-digital conversion circuit are arranged to receive a plurality of stop signals output from the pixel array. A distance measuring device comprising: (Item 10) The plurality of pixels are arranged to form a plurality of rows and a plurality of columns, The second measurement blocks are provided to respectively correspond to the rows of the pixel array. 10. A distance measuring device according to item 9, characterized in that (Item 11) The pixels are arranged in a plurality of rows and a plurality of columns; The second measurement blocks are provided to respectively correspond to the pixels of the pixel array. 10. A distance measuring device according to item 9, characterized in that (Item 12) The plurality of pixels are arranged to form a plurality of rows and a plurality of columns, and the plurality of pixels are divided into a plurality of groups; The second measurement blocks are provided to correspond to the groups of the pixel array, respectively. 10. The distance measuring device according to item 9, (Item 13) Each of the plurality of pixels includes an avalanche photodiode. 13. A distance measuring device according to any one of items 9 to 12. (Item 14) each of the plurality of pixels includes an event detection pixel; 13. A distance measuring device according to any one of items 9 to 12. (Item 15) A light emitting portion; a control unit that sends a light emission command to the light emission unit and sends a start command to the time-to-digital conversion circuit; 15. The distance measuring device according to any one of items 9 to 14, further comprising: (Item 16) A mobile object, A distance measuring device according to any one of items 9 to 15, a control unit for controlling the moving object based on an output of the distance measuring device; A moving object comprising:

[0056] The invention is not limited to the above-described embodiments, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0057] TDCC: time-to-digital conversion circuit, 20-1: first measurement block, 20-2: second measurement block, 27: upper measurement circuit, 28: lower measurement circuit

Claims

1. A first measurement block and one or more second measurement blocks; the first measurement block activates a control signal in response to activation of a start signal, and measures a time from the activation of the start signal to a first edge of a common clock signal; the second measurement block includes a lower measurement circuit and an upper measurement circuit that are enabled by activation of the control signal; the lower-order measurement circuit measures the time from activation of a stop signal to a second edge of the common clock signal, and the upper-order measurement circuit measures the time from the first edge to the second edge. A time-to-digital conversion circuit.

2. the first measurement block includes a first control circuit that activates the control signal in response to activation of the start signal, and a measurement circuit that measures a time from activation of the start signal to the first edge; 2. The time-to-digital conversion circuit according to claim 1 .

3. the first control circuit outputs, as a second control signal, a signal obtained by synchronizing the control signal in accordance with the common clock signal; the second measurement block includes a second control circuit; the second control circuit causes the higher-level measurement circuit to start measurement in response to the second control signal being activated following the activation of the control signal; causing the lower-level measurement circuit to start measurement in response to the stop signal being activated while the control signal is activated; 3. The time-to-digital conversion circuit according to claim 2.

4. the second control circuit causes the higher-level measurement circuit to end measurement in response to the second edge; 4. The time-to-digital conversion circuit according to claim 3.

5. the second control circuit causes the lower level measurement circuit to terminate measurement in response to the second edge; 4. The time-to-digital conversion circuit according to claim 3.

6. the first control circuit includes a first detection circuit that activates the control signal asynchronously with the common clock signal in response to activation of the start signal, and a second detection circuit that activates the second control signal in synchronization with the common clock signal in response to activation of the control signal; the second detection circuit includes a first flip-flop that captures the control signal in response to a third edge of the common clock signal that arrives following activation of the control signal, and a second flip-flop that generates the second control signal by capturing an output of the first flip-flop in response to a fourth edge of the common clock signal that arrives following the third edge.

4. The time-to-digital conversion circuit according to claim 3.

7. the second control circuit includes a third detection circuit that activates its output asynchronously with the common clock signal in response to activation of the stop signal, and a fourth detection circuit that activates its output in synchronization with the common clock signal in response to activation of the output of the third detection circuit, the fourth detection circuit includes a third flip-flop which captures the output of the third detection circuit in response to a fifth edge of the common clock signal which arrives next to activation of the output of the third detection circuit, and a fourth flip-flop which updates its own output by capturing the output of the third flip-flop in response to a sixth edge of the common clock signal which arrives next to the fifth edge.

4. The time-to-digital conversion circuit according to claim 3.

8. The second measurement block has the same configuration as the first measurement block.

2. The time-to-digital conversion circuit according to claim 1 .

9. a pixel array having a plurality of pixels; A time-to-digital conversion circuit according to any one of claims 1 to 8, the second measurement blocks of the time-to-digital conversion circuit are arranged to receive a plurality of stop signals output from the pixel array; A distance measuring device comprising:

10. The plurality of pixels are arranged to form a plurality of rows and a plurality of columns, the second measurement blocks are provided to correspond to the rows of the pixel array, respectively; 10. The distance measuring device according to claim 9.

11. The pixels are arranged in a plurality of rows and a plurality of columns; the second measurement blocks are provided to correspond to the pixels of the pixel array, respectively; 10. The distance measuring device according to claim 9.

12. The plurality of pixels are arranged to form a plurality of rows and a plurality of columns, and the plurality of pixels are divided into a plurality of groups; the second measurement blocks are provided to correspond to the groups of the pixel array, respectively; 10. The distance measuring device according to claim 9.

13. Each of the plurality of pixels includes an avalanche photodiode.

10. The distance measuring device according to claim 9.

14. each of the plurality of pixels includes an event detection pixel; 10. The distance measuring device according to claim 9.

15. A light emitting portion; a control unit that sends a light emission command to the light emission unit and sends a start command to the time-to-digital conversion circuit; 10. The distance measuring device according to claim 9, further comprising:

16. A mobile object, A distance measuring device according to claim 9 ; a control unit for controlling the moving object based on an output of the distance measuring device; A moving object comprising:

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