Reference voltage circuit

Abstract

To provide a reference voltage circuit comprising a differential amplifier circuit capable of a stable constant voltage operation even if a collector voltage of an NPN transistor temperature-changes and is input to the reference voltage circuit.SOLUTION: A voltage adjusting circuit 30 is provided between commonly connected sources and commonly connected back gates of first and second PMOS transistors 1 and 2, which are input units of a differential amplifier circuit 10. The voltage generated by the voltage adjusting circuit 30 is adjusted so as to increase the voltages between the sources and the back gates of the first and second PMOS transistors 1 and 2 in accordance with a voltage drop caused by the temperature rise of a collector voltage of an NPN transistor input to one of the input units of the differential amplifier circuit 10.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a reference voltage circuit. [Background technology]

[0002] There is known a reference voltage circuit that differentially amplifies two input voltages and outputs a reference voltage. In a reference voltage circuit having a differential amplifier circuit, the voltage input to the input terminal of the differential amplifier circuit is, for example, a voltage based on the voltage of a PN junction element having a PN junction surface such as a diode. In a reference voltage circuit having a differential amplifier circuit, in order to stably operate at a constant voltage, it is common for each transistor constituting the differential amplifier circuit to operate in a saturation region also called a pentode region. A bandgap reference voltage circuit (hereinafter simply referred to as a "reference voltage circuit") using an NPN bipolar transistor (hereinafter simply referred to as an "NPN transistor") at the input of the differential amplifier circuit has been proposed (see, for example, Patent Document 1).

[0003] An example of a conventional differential amplifier circuit provided in a reference voltage circuit is, for example, a differential amplifier circuit (3) shown in FIG. 6 of Patent Document 2. In the differential amplifier circuit (3) illustrated in Patent Document 2, a PMOS transistor (hereinafter simply referred to as a "PMOS transistor") (P32), which is an example of a P-channel field effect transistor (FET), is turned on, and an NMOS transistor (hereinafter simply referred to as an "NMOS transistor") (N31), which is an example of an N-channel FET connected to the drain of the PMOS transistor (P32), is turned on, so that a first current flows through the PMOS transistor (P32) and the NMOS transistor (N31). In addition, a PMOS transistor (P33) is turned on, and an NMOS transistor (N32), which is connected to the drain of the PMOS transistor (P33), is turned on, so that a second current flows through the NMOS transistor N32 and the PMOS transistor (P33). The differential amplifier circuit (3) compares the first current and the second current, performs differential amplification, and outputs an output voltage from an output terminal (at least one of O1 and O2).

[0004] A reference voltage circuit equipped with a conventional differential amplifier circuit, as shown in FIG. 14 of Patent Document 1, for example, generates two voltages (VA, VB) based on the output voltage of the differential amplifier circuit, and inputs these voltages as a first input voltage and a second input voltage to the differential amplifier circuit, respectively, thereby obtaining a reference voltage (VREF) that is negative feedback controlled and has no temperature dependency. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 10-303658 [Patent Document 2] JP 2005-136473 A Summary of the Invention [Problem to be solved by the invention]

[0006] However, in a conventional reference voltage circuit having a differential amplifier circuit composed of two PMOS transistors and two NMOS transistors as described in Patent Document 1, it is difficult to perform constant voltage operation at a low power supply voltage of, for example, 2 V or less. More specifically, in a conventional reference voltage circuit, the voltage supplied to the input terminal of the differential amplifier circuit may drop too much as the external temperature changes.

[0007] In order to operate the reference voltage circuit at a constant voltage, it is necessary to saturate each MOS transistor constituting the differential amplifier circuit of the reference voltage circuit in order to obtain stable operation. Here, an example will be described in which the conventional differential amplifier circuit is the differential amplifier circuit (3) described in Patent Document 2, and the collector voltage of an NPN transistor with the collector and base connected (so-called diode connection) is used as the input voltage of the differential amplifier circuit (3).

[0008] In the differential amplifier circuit (3), when the voltage applied to the gate of the PMOS transistor (P32) drops due to an external factor such as a temperature change, the source voltage of the PMOS transistor (P32) drops. The drop in the source voltage of the PMOS transistor (P32) lowers the drain-source voltage of the PMOS transistor (P32), so the PMOS transistor (P32) may not be able to operate in saturation. In other words, the PMOS transistor (P32) may operate in desaturation. On the other hand, when the voltage applied to the gate of the PMOS transistor (P32) rises, the source voltage of the PMOS transistor (P32) rises, and the drain-source voltage of the PMOS transistor (P31) operating as a current source drops, so that the PMOS transistor (P31) may operate in desaturation. When the PMOS transistor (P31) operates in desaturation, the PMOS transistor (P31) may not be able to pass a predetermined constant current. As described above, in the conventional circuit configuration, there was a restriction (narrow voltage range in which saturated operation is possible) required for the source voltage of the PMOS transistor (P32), making it difficult to keep the minimum operating voltage that can be input as the power supply voltage (VDD) low while causing each MOS transistor to operate in saturated mode.

[0009] The present invention has been made in consideration of the above-mentioned circumstances and has an object to provide a reference voltage circuit including a differential amplifier circuit that can stably operate at a constant voltage while keeping the minimum operating voltage lower than in the past, even if a voltage based on the voltage of a PN junction element, such as the collector voltage of a diode-connected NPN transistor, changes due to an external temperature change and is input to the differential amplifier circuit. [Means for solving the problem]

[0010] According to an embodiment of the present invention, there is provided a reference voltage circuit comprising: a differential amplifier circuit having a gate of a first PMOS transistor and a gate of a second PMOS transistor as an input; a drain of a first NMOS transistor and a drain of a second NMOS transistor connected to a drain of the first PMOS transistor and the drain of the second PMOS transistor; a source and a back gate of the first NMOS transistor and the drain of the second NMOS transistor connected to a ground terminal; a first terminal connected to a commonly connected source of the first PMOS transistor and the drain of the second PMOS transistor; a second terminal connected to a commonly connected back gate of the first PMOS transistor and the drain of the second PMOS transistor; and a power supply terminal connected to a power supply terminal, the differential amplifier circuit including a voltage adjustment circuit capable of adjusting a voltage between the first terminal and the second terminal, the voltage adjustment circuit being configured to increase or decrease a voltage generated between the first terminal and the second terminal in response to a change in an input voltage of the differential amplifier circuit. Effect of the Invention

[0011] According to the present invention, even if the minimum operating voltage of the differential amplifier circuit in the reference voltage circuit is kept low, it is possible to stabilize the saturation operation of each MOS transistor constituting the differential amplifier circuit in a situation in which the voltage input to the differential amplifier circuit changes due to external temperature changes. [Brief description of the drawings]

[0012] [Figure 1] 1 is a circuit diagram illustrating an example of the configuration of a reference voltage circuit according to an embodiment of the present invention. [Diagram 2] 2 is a circuit diagram showing a configuration example of a differential amplifier circuit in the reference voltage circuit according to the embodiment; [Diagram 3] 2 is a circuit diagram showing a first configuration example of a voltage adjustment circuit of a differential amplifier circuit in the reference voltage circuit according to the present embodiment. FIG. [Figure 4] 4 is a circuit diagram showing a configuration example of a differential amplifier circuit in a reference voltage circuit according to a first comparative example. [Diagram 5]11 is a circuit diagram showing a configuration example of a differential amplifier circuit in a reference voltage circuit according to a second comparative example. FIG. [Figure 6] 11 is a circuit diagram showing a modified example (second configuration example) of the voltage adjustment circuit of the differential amplifier circuit in the reference voltage circuit according to the present embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Hereinafter, a reference voltage circuit according to an embodiment of the present invention will be described with reference to the drawings. [Entire reference voltage circuit] FIG. 1 is a circuit diagram showing an overall configuration of a reference voltage circuit 100, which is an example of a reference voltage circuit according to an embodiment of the present invention.

[0014] The reference voltage circuit 100 includes a VDD terminal 11 which supplies a voltage VDD which is an example of a power supply voltage, a GND terminal 12 which supplies a ground voltage GND which is different from the voltage VDD, a VREF output terminal 50 which outputs a reference voltage VREF, a differential amplifier circuit 10, a buffer 20, a reference voltage source 15, a reference voltage source 16, a resistor 21, and a resistor 22. The reference voltage source 15 comprises an output 25 and a transistor 5 as a first NPN transistor. The reference voltage source 16 comprises an output 26, a resistor 23 and a transistor 6 as a second NPN transistor.

[0015] The differential amplifier circuit 10 includes a power supply terminal, a ground terminal, an inverting input terminal (-), a non-inverting input terminal (+), and an output terminal To. The power supply terminal of the differential amplifier circuit 10 is connected to a VDD terminal 11. The ground terminal of the differential amplifier circuit 10 is connected to a GND terminal 12. The non-inverting input terminal (+) is connected to an output terminal 25. The inverting input terminal (-) is connected to an output terminal 26. The output terminal To is connected to a VREF output terminal 50 via a buffer 20. A resistor 21 and a resistor 22 are connected to a connection point N1 between the buffer 20 and the VREF output terminal 50.

[0016] Here, of the two ends of the resistor 21, the end connected to the connection point N1 is referred to as a first end, and the other end is referred to as a second end. The first and second ends of the resistor 22 are also referred to in the same manner as the first and second ends of the resistor 21.

[0017] The emitter of the transistor 5 is connected to the GND terminal 12. The base and collector of the transistor 5 are directly connected to an output terminal 25 of the reference voltage source 15 and a second terminal of the resistor 21. The emitter of the transistor 6 is connected to the GND terminal 12. The base and collector of the transistor 6 are directly connected to each other and to a first terminal of the resistor 23. The second terminal of the resistor 23 is connected to the output terminal 26 of the reference voltage source 16 and the second terminal of the resistor 22.

[0018] The operation of the reference voltage circuit 100 will be described. In this description, it is assumed that the distribution of the sizes of the resistors 21, 22, 23, the transistors 5, and 6 has been appropriately selected in advance. If the output terminal of the buffer 20 is disconnected from the connection point N1 and the voltage of the connection point N1 is gradually increased from zero, the voltage of the output terminal 25 of the reference voltage source 15 will hardly increase from a certain specific value. On the other hand, in the case of the same manner of increasing the voltage of the connection point N1, the voltage of the output terminal 26 of the reference voltage source 16 is lower than the voltage of the output terminal 25 near zero, but continues to rise gently even after reaching a certain specific value, and becomes higher than the voltage of the output terminal 25. In other words, the high-low relationship between the voltage of the output terminal 25 and the voltage of the output terminal 26 is reversed halfway.

[0019] If the voltage at connection point N1 is adjusted so that the voltage at output terminal 25 of reference voltage source 15 and the voltage at output terminal 26 of reference voltage source 16 become equal, the voltage at connection point N1 will become a constant voltage that is independent of temperature, etc.

[0020] If the voltage of output terminal 25 of reference voltage source 15 is input to the non-inverting input terminal (+) of differential amplifier circuit 10, the voltage of output terminal 26 of reference voltage source 16 is input to the inverting input terminal (-), the signal from output terminal To is input to buffer 20, and current is supplied from the output terminal of buffer 20 to resistors 21 and 22 through connection point N1, then a constant reference voltage VREF that is independent of temperature, etc., as mentioned above, will appear at VREF output terminal 50 connected to connection point N1.

[0021] [Differential amplifier circuit] FIG. 2 is a circuit diagram showing a configuration example of a differential amplifier circuit 10 which is an example of a differential amplifier circuit included in the reference voltage circuit according to this embodiment.

[0022] The differential amplifier circuit 10 includes PMOS transistors 1 and 2 and NMOS transistors 3 and 4 that form a differential pair, and a voltage adjustment circuit 30 including a first terminal 30a, a second terminal 30b, and a power supply terminal 30c. Here, the non-inverting input terminal (+) and the inverting input terminal (-) of the differential amplifier circuit 10 correspond to the gate of the PMOS transistor 1 and the gate of the PMOS transistor 2, respectively. The power supply terminal of the differential amplifier circuit 10 corresponds to the power supply terminal 30c in the voltage adjustment circuit 30. In addition, the ground terminal of the differential amplifier circuit 10 corresponds to the back gates and sources of the NMOS transistors 3 and 4. The output terminal To is connected to the connection point between the drain of the PMOS transistor 2 and the drain of the NMOS transistor 4.

[0023] The drains of the PMOS transistor 1 and the PMOS transistor 2 are connected to the drains of the NMOS transistor 3 and the NMOS transistor 4. The sources of the NMOS transistor 3 and the NMOS transistor 4 are connected to a GND terminal 12. The PMOS transistor 1 and the PMOS transistor 2 have a common source which is a connection point N2 where their sources are connected to each other, and a common backgate which is a connection point N3 where their backgates are connected to each other.

[0024] The voltage adjustment circuit 30 is a circuit having a function of adjusting the voltage applied between the first terminal 30a and the second terminal 30b. In the voltage adjustment circuit 30, the first terminal 30a is connected to a connection point N2, and the second terminal 30b is connected to a connection point N3. The power supply terminal 30c is connected to the VDD terminal 11. The voltage applied between the first terminal 30a and the second terminal 30b is configured to have a positive temperature coefficient T2 (>0) that is equal to or smaller than the absolute value of the temperature coefficient T1, from the viewpoint of reducing the influence of the voltage input to the differential amplifier circuit 10, i.e., the voltage of the PN junction element, on the negative temperature coefficient T1 (<0). Here, since it is known that the temperature coefficient T1 is -2 mV / °C, the collector voltage (corresponding to the voltage Vf listed in Table 1) of the transistor 5 (FIG. 1) varies between 0.4 V and 0.7 V. The temperature coefficient T2 is determined by the voltage applied between the first terminal 30a and the second terminal 30b (V R7 The range is set between 0.2mV / ℃ and 0.4mV / ℃ as calculated from the

[0025] FIG. 3 is a circuit diagram showing a configuration example of a voltage adjustment circuit 30, which is an example (first configuration example) of a voltage adjustment circuit in a differential amplifier circuit included in the reference voltage circuit according to this embodiment.

[0026] The voltage adjustment circuit 30 includes a variable resistor 7a having a resistance value with a positive temperature coefficient and configured to be adjustable in resistance, and a constant current source 8b supplying a predetermined constant current. A first terminal and a second terminal of the variable resistor 7a are connected to a first terminal 30a and a second terminal 30b of the voltage adjustment circuit 30, respectively. A first terminal and a second terminal of the constant current source 8b are connected to a power supply terminal 30c and a second terminal 30b of the voltage adjustment circuit 30, respectively. The voltage adjustment circuit 30 is configured to be able to adjust the voltage value of the voltage having a positive temperature coefficient applied between the first terminal 30a and the second terminal 30b by adjusting the resistance value of the variable resistor 7a.

[0027] Next, the operation of a reference voltage circuit (first to third embodiments: FIG. 1) including a differential amplifier circuit 10 will be described, focusing on the differential amplifier circuit 10 where the differences are most noticeable, while comparing it with a reference voltage circuit (first comparative example) including a differential amplifier circuit 210 (see FIG. 4 described later) and a reference voltage circuit (second comparative example) including a differential amplifier circuit 310 (see FIG. 5 described later). In order to match the conditions with the differential amplifier circuit 10, it is assumed that the voltage input to the gates of PMOS transistors 91 and 92 is the same as the voltage input to the gates of PMOS transistors 1 and 2, that is, the voltage output from reference voltage sources 15 and 16.

[0028] (First Comparative Example) FIG. 4 is a circuit diagram showing a configuration example of a differential amplifier circuit 210 of a reference voltage circuit according to a first comparative example. The differential amplifier circuit 210 includes a PMOS transistor 90 receiving a bias voltage Vbias at its gate, PMOS transistors 91 and 92 that form a differential pair, and NMOS transistors 93 and 94, and essentially corresponds to the differential amplifier circuit (3) shown in FIG. 6 of Patent Document 2.

[0029] A brief description will be given of the operation of the differential amplifier circuit 210. In the differential amplifier circuit 210, a voltage is input to the gate of the PMOS transistor 91 corresponding to the non-inverting input terminal INP and to the gate of the PMOS transistor 92 corresponding to the inverting input terminal INN. In order to make it possible to compare with the differential amplifier circuit 10, it is assumed that the voltage input to each gate of the PMOS transistors 91 and 92 is a voltage based on the voltage of a PN junction element.

[0030] The source voltage of PMOS transistors 91 and 92 automatically reaches a voltage that is higher than the midpoint voltage between the gate voltage of PMOS transistor 91 and the gate voltage of PMOS transistor 92 (hereinafter referred to as the "common-mode input voltage") by the absolute value of the gate threshold voltage of PMOS transistors 91 and 92.

[0031] Therefore, the difference voltage between the gate voltage of PMOS transistor 91 and the gate voltage of PMOS transistor 92 ideally appears regardless of the common-mode input voltage and is proportional to the difference between the drain current of PMOS transistor 91 and the drain current of PMOS transistor 92. The current mirror circuit formed by NMOS transistor 93 and NMOS transistor 94 converts the change in the difference between the drain current of PMOS transistor 91 and the drain current of PMOS transistor 92 into a change in voltage, and outputs it to the output terminal To of the differential amplifier circuit 210.

[0032] Here, we will explain the drain-source voltages of the PMOS transistors 91 and 92. The source voltages of the PMOS transistors 91 and 92 are higher than the gate voltages of the PMOS transistors 91 and 92 by the absolute value of the gate threshold voltages of the PMOS transistors 91 and 92. The drain voltage of the PMOS transistor 91 is the drain and gate voltages of the NMOS transistor 93 because the drain and gate of the NMOS transistor 93 are directly connected.

[0033] Therefore, the absolute value of the drain-source voltage of the PMOS transistor 91 is calculated by adding the absolute values ​​of the gate threshold voltages of the PMOS transistors 91 and 92 to the gate voltages of the PMOS transistors 91 and 92 and subtracting the gate threshold voltage of the NMOS transistor 93 from the sum.

[0034] When the temperature rises in and around the differential amplifier circuit 210, around the PMOS transistor 91, (I) the voltage input to the gate of the PMOS transistor 91 decreases, (II) the absolute value of the gate threshold voltage of the PMOS transistor 91 decreases, and (III) the gate threshold voltage of the NMOS transistor 93 decreases. Considering that the drain of the PMOS transistor 91 and the drain and gate of the NMOS transistor 93 form the same node, the fluctuations due to (II) and (III) decrease the source voltage and drain voltage of the PMOS transistor 91, respectively, so that the fluctuations are offset in terms of the drain-source voltage of the PMOS transistor 91. As a result, of (I) to (III), (I) the decrease in the voltage input to the gate of the PMOS transistor 91 affects the fluctuation in the absolute value of the drain-source voltage of the PMOS transistor 91.

[0035] When the temperature rises in the reference voltage circuit including the differential amplifier circuit 210 and the reference voltage sources 15 and 16, the absolute value of the drain-source voltage of the PMOS transistor 91 decreases. Therefore, when the temperature rise exceeds a predetermined value, the absolute value of the drain-source voltage of the PMOS transistor 91 falls below the lower limit value at which operation in the saturation region can be maintained, and operation in the saturation region cannot be ensured.

[0036] (Second Comparative Example) FIG. 5 is a circuit diagram showing a configuration example of a differential amplifier circuit 310 of a reference voltage circuit according to a second comparative example. The differential amplifier circuit 310 differs from the differential amplifier circuit 210 in that it further includes an NMOS transistor 95, but is otherwise substantially the same. Therefore, in describing the differential amplifier circuit 310, components that are substantially the same as those in the differential amplifier circuit 210 will be denoted by the same reference numerals and redundant description will be omitted.

[0037] The drain and gate of the NMOS transistor 95 are connected to the source of the PMOS transistor 90 and the common backgate of the PMOS transistors 91 and 92, i.e., the connection point N3. The source of the NMOS transistor 95 is connected to the common source of the PMOS transistors 91 and 92, i.e., the connection point N2. The backgate of the NMOS transistor 95 is connected to the GND terminal 12.

[0038] In the differential amplifier circuit 310 configured in this manner, a substrate bias voltage V BS is a voltage based on the PN junction in the NMOS transistor 95. However, the substrate bias voltage V BS Since the temperature characteristic of the differential amplifier circuit 310 is a negative temperature characteristic, when the temperature rises in the reference voltage circuit including the differential amplifier circuit 310 and the reference voltage sources 15 and 16, the substrate bias voltage V BS Similarly, the voltage input to the gate of the PMOS transistor 91 also drops.

[0039] (First to third examples) On the other hand, in the differential amplifier circuit 10 including the voltage adjustment circuit 30, the voltage of the common backgate of the PMOS transistors 1 and 2, i.e., the connection point N3, is raised by the potential difference generated across both ends (the first end 30a and the second end 30b) of the voltage adjustment circuit 30. By adopting a configuration that raises the voltage of the connection point N3, the absolute values ​​of the substantial gate threshold voltages of the PMOS transistors 1 and 2 are made larger than the absolute values ​​of the gate threshold voltages of the PMOS transistors 91 and 92.

[0040] In the differential amplifier circuit 10, since the PMOS transistors 1 and 2 have an absolute value of the drain-source voltage substantially larger than the absolute value of the drain-source voltage of the PMOS transistors 91 and 92, the differential amplifier circuit 10 can ensure operation in the saturation region for a wider range of temperature rises. That is, the temperature range in which the differential pair can operate correctly can be expanded for the differential amplifier circuit 210. It is also important that the voltage difference generated in the voltage adjustment circuit 30 is appropriately small in response to the small voltage generated by the temperature change of the gate voltage of the PMOS transistors 1 and 2, which corresponds to the input voltage of the differential amplifier circuit.

[0041] The voltage adjustment circuit 30 adjusts the voltage across both ends to increase or decrease in response to a change in the input voltage of the differential amplifier circuit 10, thereby generating a body bias effect in the PMOS transistors 1 and 2. The voltage between the source and the body (backgate) of the PMOS transistors 1 and 2 is a body bias voltage V BS The substrate bias voltage V BS Using this, the threshold voltage Vth of the PMOS transistors 1 and 2 is expressed by the following equation (1).

[0042]

number

[0043] According to the formula (1), the threshold voltage Vth of the PMOS transistors 1 and 2 is the absolute value of the substrate bias voltage |V BS As the back gate voltage becomes higher relative to the source voltage, that is, the positive substrate bias voltage V BSWhen a voltage of 1 V is applied, a reverse bias is applied to the PN junction between the P-type channel formed by inversion on the channel surface of the PMOS transistors 1 and 2 and the N-type well (hereinafter referred to as the "reverse bias applied state"). In the reverse bias applied state, the depletion layer expands and the positive charge in the depletion layer increases compared to the state where no reverse bias is applied. The increase in the positive charge in the depletion layer increases the gate voltage to form the channel, so a larger voltage is required, and the threshold voltage |Vth| of the PMOS transistors 1 and 2 is therefore increased.

[0044] In order to keep the minimum operating voltage that can be used as the voltage VDD low, it is necessary to reduce the drain-source voltage Vds at which the PMOS transistors 1 and 2 operate in saturation. The drain-source voltage Vds required for the PMOS transistors 1 and 2 to operate in saturation is expressed as follows, using the gate-source voltage Vgs and the threshold voltage Vth: Vds ≥ Vgs - Vth (2) Therefore, in order to reduce the drain-source voltage Vds at which the PMOS transistors 1 and 2 operate in saturation, the overdrive voltage (Vgs-Vth), that is, the right-hand side of equation (2), should be reduced.

[0045] In the differential amplifier circuit 10 including the voltage adjustment circuit 30, the voltage difference between both ends (the first end 30a and the second end 30b) of the voltage adjustment circuit 30 is adjusted so as to satisfy the above-mentioned formula (2) within the expected operating temperature range. Here, assuming that the circuit is operated at a constant voltage of 2 V, which is an example of a low voltage, the absolute value of the substrate bias voltage |V BS Since the upper limit that satisfies equation (2) is about 0.36 V, | is adjusted to a positive voltage of 0.36 V or less.

[0046] However, the absolute value of the substrate bias voltage |V BSIf | is low, the effect of increasing the threshold voltage due to the backgate effect cannot be obtained sufficiently, so it is preferably adjusted to 0.07 V or more and 0.36 V or less, and more preferably adjusted to a predetermined range including 0.20 V, that is, 0.10 V or more and 0.30 V or less, that is, near 0.2 V. In this embodiment, the absolute value |V BS In the three examples, the absolute value of the substrate bias voltage |V BS The examples are referred to as the first embodiment, the second embodiment, and the third embodiment in ascending order of | (see Table 1 below for details).

[0047] In addition, the substrate bias voltage V BS By making the temperature characteristic of the reference voltage circuit 100 positive, when a temperature change occurs in the reference voltage circuit 100, the substrate bias voltage V BS In other words, when the temperature rises in the reference voltage circuit 100, the voltage input to the gate of the PMOS transistor 1 drops, but the substrate bias voltage V BS Change the value.

[0048] Next, the first to third examples, the first comparative example, and the second comparative example will be described with specific numerical examples given in Tables 1 and 2. Here, cases (1) to (5) in Tables 1 and 2 correspond to the first comparative example, the first example, the second example, the third example, and the second comparative example, respectively.

[0049] In Table 1, VDD1 is the voltage VDD required for the saturated operation of the PMOS transistor 1 or 91, VDD2 is the voltage VDD required for the saturated operation of the NMOS transistor 3 or 93, Vf is the collector voltage of the transistor 5, Vgsp is the gate-source voltage of the PMOS transistor 1 or 91, Vdsp is the drain-source voltage of the PMOS transistor 1 or 91, and Vgsn is the gate-source voltage of the NMOS transistor 3 or 93, which is the same as the drain-source voltage Vdsn of the NMOS transistor 3 or 93. I8is the terminal voltage of the constant current source 8b, V R7 is the voltage across the variable resistor 7a.

[0050] The threshold voltage Vthp of the PMOS transistor 1 or 91 is expressed by the absolute value of the substrate bias voltage |V BS |V R7 The threshold voltage Vthn of the NMOS transistor 3 or 93 can be calculated by substituting the absolute value of the substrate bias voltage |V BS This is the value when |=0V. Furthermore, the judgment column in Table 1 shows the result of judgment based on formula (2), and indicates by the presence or absence of a circle whether the following formulas (3) and (4) are satisfied for the PMOS transistor 1 or 91 and the NMOS transistor 3 or 93. If formula (3) is satisfied, a circle is placed in the column for formula (3), and if formula (4) is satisfied, a circle is placed in the column for formula (4). Vdsp ≥ Vgsp - Vthp (3) Vdsn ≥ Vgsn - Vthn (4)

[0051] [Table 1]

[0052] Table 1 shows whether each of the cases (1) to (5) satisfies the above-mentioned formulas (3) and (4) at −40° C., which is a representative value on the lower side of the continuous temperature range including at least −40° C. to 125° C., and at 125° C., which is a representative value on the higher side. Here, the threshold voltage Vthp of the PMOS transistor 1 or 91 is expressed by the absolute value of the substrate bias voltage |V BS |V R7 The threshold voltage Vthn of the NMOS transistor 3 or 93 can be calculated by substituting the absolute value of the substrate bias voltage |V BS This is the value when |=0V.

[0053] In case (1) (first comparative example), V R7 =|V BSAlthough | is a fixed value of 0 V and cannot be adjusted, there exist VDD1 and VDD2 that satisfy the above-mentioned expressions (3) and (4) at -40°C and 125°C. In case (5) (second comparative example), by connecting an NMOS transistor 95, V R7 =|V BS In this example, the differential amplifier circuit 310 is configured so that V | is 0.4 V at -40° C. and 0.5 V at 125° C. In case (5) (second comparative example), VDD1 and VDD2 exist that satisfy the above-mentioned expressions (3) and (4). In case (5), V R7 =|V BS In order to change |, it is necessary to change the characteristics or operating conditions of the NMOS transistor 95, which is more difficult than adjusting the resistance value of a resistor or the value of a current flowing through the resistor.

[0054] On the other hand, in case (2) (first embodiment), case (3) (second embodiment), case (4) and (third embodiment), the resistance value of the variable resistor 7a is adjusted to V R7 =|V BS Therefore, we can adjust V to satisfy the above formula (2). R7 The differential amplifier circuit 10 can change the threshold voltage Vthp of the PMOS transistors 1 and 2 by searching for the value of V R7 =|V BS The adjustment of V R7 =|V BS In cases (2), (3), and (4) shown in Table 1, the resistance value of the variable resistor 7a is adjusted to adjust V R7 =|V BS can be adjusted to 0.07 V, 0.20, and 0.30 at −40° C., and 0.10, 0.23, and 0.36 V at 125° C. In this case, VDD1 and VDD2 that satisfy the above-mentioned formula (2) can be obtained.

[0055] [Table 2]

[0056] Table 2 shows the calculation results for VDD1 and VDD2 shown in Table 1. The minimum operating voltage for the differential amplifier circuits 10, 210, and 310 (Figs. 2, 4, and 5) is VDDmax shown in Table 2. VDDmax is the higher of VDD1 and VDD2. A circle in the judgment column indicates that VDDmax is 2V or less, and a cross indicates that VDDmax is not 2V or less, i.e., VDDmax is greater than 2V.

[0057] As shown in Table 2, in cases (1) and (5), i.e., the differential amplifier circuit 210 and the differential amplifier circuit 310, the minimum operating voltage VDDmax exceeds 2.0 V. R7 =|V BS However, in the voltage range below 0.07 V (case (1)) or above 0.4 V (case (5)), even if PMOS transistors 91 and 92 and NMOS transistors 93 and 94 can be used in the saturation region, the minimum operating voltage VDDmax cannot be suppressed to 2.0 V or less.

[0058] On the other hand, in cases (2), (3), and (4), that is, in the differential amplifier circuit 10, the minimum operating voltage VDDmax is 2.0 V or less. R7 =|V BS It can be seen that by setting | so that VDDmax is 2.0V or less and the PMOS transistors 1, 2 and NMOS transistors 3, 4 are usable in the saturation region at a positive voltage of approximately 0.36V or less, preferably in the range of 0.07V to 0.36V, and more preferably in the range of about 0.2V, it is possible to use the PMOS transistors 1, 2 and the NMOS transistors 3, 4 in the saturation region while keeping the minimum operating voltage VDDmax at a low voltage of 2.0V or less.

[0059] As described above, the reference voltage circuit 100 supplies the substrate bias voltage V BSThe reference voltage circuit 100 includes a differential amplifier circuit 10 having a voltage adjustment circuit 30 that can easily adjust the voltage difference between the common source and common backgate of the PMOS transistors 1 and 2. By including the differential amplifier circuit 10, the reference voltage circuit 100 can adjust and apply a voltage between the common source and common backgate of the PMOS transistors 1 and 2 so that the potential of the common backgate is higher than the potential of the common source. Since the potential difference between the common source and common backgate of the PMOS transistors 1 and 2 can be adjusted, the magnitude of the backgate effect applied to the PMOS transistors 1 and 2 can be adjusted.

[0060] The reference voltage circuit 100 includes a differential amplifier circuit 10 configured to be able to adjust the magnitude of the backgate effect applied to the PMOS transistors 1 and 2. Therefore, even if the drain-source voltages of the PMOS transistors 1 and 2 are configured to be small when no substrate bias effect is applied, it is possible to ensure stable operation of the PMOS transistors 1 and 2 and the NMOS transistors 3 and 4 in the saturation region in an environment where the input voltage fluctuates due to temperature changes.

[0061] Conversely, if the operable range in the saturation region of the differential amplifier circuit 10 is designed to be approximately the same as the operable range in the saturation region of the differential amplifier circuit 210, the absolute value of the drain-source voltage in a state in which the substrate bias effect is not applied to the PMOS transistors 1 and 2 can be designed to be smaller than the absolute value of the drain-source voltage of the PMOS transistors 91 and 92. In other words, the voltage VDD supplied to the differential amplifier circuit 10 can be made lower than the voltage VDD supplied to the differential amplifier circuit 210.

[0062] According to the reference voltage circuit 100, the voltage regulated by the voltage regulation circuit 30, i.e., the substrate bias voltage V BS has a positive temperature coefficient, which is opposite in polarity to the temperature coefficient of the voltage input to the gate of the PMOS transistor 1 of the differential amplifier circuit 10. Therefore, according to the reference voltage circuit 100, in response to a change in the voltage input to the gate of the PMOS transistor 1, the substrate bias voltage V BScan be varied.

[0063] In addition, since the reference voltage circuit 100 includes the differential amplifier circuit 10, the magnitude of the substrate bias effect can be easily adjusted and applied, so that the substrate bias voltage V 100 can be set to a value that satisfies both a lower minimum operating voltage and ensures stable operation of the PMOS transistors 1 and 2 and the NMOS transistors 3 and 4 in the saturation region. BS More specifically, the circuit is designed so that the terminal voltage between the first terminal 30a and the second terminal 30b is within a range of 0.07V to 0.36V over a predetermined temperature range, such as the temperature range in which the circuit is expected to be used. The absolute value of the gate threshold voltage of the PMOS transistors 1 and 2 increases by an amount corresponding to the set terminal voltage between the first terminal 30a and the second terminal 30b, and the source voltage of the PMOS transistors 1 and 2 increases accordingly. As a result, the absolute value of the drain-source voltage of the PMOS transistors 1 and 2 increases, enabling the differential amplifier circuit 10 to operate stably.

[0064] Therefore, according to the reference voltage circuit of this embodiment, even if the minimum operating voltage of the differential amplifier circuit is kept low, it is possible to stabilize the saturation operation of each MOS transistor constituting the differential amplifier circuit under a situation in which the voltage input to the differential amplifier circuit changes due to an external temperature change. Since the reference voltage circuit of this embodiment can keep the minimum operating voltage that can be used as the power supply voltage VDD low, it can contribute to energy saving of semiconductor integrated circuits such as linear regulators that include the reference voltage circuit of this embodiment.

[0065] The present invention is not limited to the above-described embodiment, and can be implemented in various forms other than the above-described embodiment at the implementation stage, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention. For example, the above-described differential amplifier circuit 10 is an example including a voltage adjustment circuit 30, but the differential amplifier circuit 10 may include a voltage adjustment circuit 30A instead of the voltage adjustment circuit 30 (see FIG. 6).

[0066] FIG. 6 is a circuit diagram showing a configuration example of a voltage adjustment circuit 30A which is a modified example (second configuration example) of the voltage adjustment circuit of the differential amplifier circuit in the reference voltage circuit according to this embodiment.

[0067] The voltage adjustment circuit 30A includes a fixed resistor 7b having a predetermined resistance value and a variable current source 8a configured to be able to adjust the current value to be supplied, and is configured to be able to adjust the voltage between a first terminal 30a and a second terminal 30b. According to the voltage adjustment circuit 30A, the first terminal and the second terminal of the fixed resistor 7b are connected to the first terminal 30a and the second terminal 30b of the voltage adjustment circuit 30A, respectively. The first terminal and the second terminal of the variable current source 8a are connected to the power supply terminal 30c and the second terminal 30b of the voltage adjustment circuit 30A, respectively.

[0068] Thus, the voltage adjustment circuit 30A differs from the voltage adjustment circuit 30 in that it has a fixed resistor 7b instead of the variable resistor 7a and a variable current source 8a instead of the constant current source 8b, but in other respects is not substantially different from the voltage adjustment circuit 30. The voltage adjustment circuit 30A adjusts the voltage between the first terminal 30a and the second terminal 30b by adjusting the current value of the current supplied by the variable current source 8a.

[0069] These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0070] 100 Reference voltage circuit 10,10A differential amplifier circuit 11 VDD pin 12 GND terminal 1 PMOS transistor 2 PMOS transistor 3. NMOS Transistor 4 NMOS transistor 15 Reference voltage source 16 Reference Voltage Source 30,30A voltage regulation circuit 7a Variable Resistor 7b Fixed resistance 8a variable current source 8b constant current source 21, 22, 23 Resistance 5,6 Transistors

Claims

1. The gates of the first PMOS transistor and the second PMOS transistor are input, a drain of a first NMOS transistor and a drain of a second NMOS transistor are connected to a drain of the first PMOS transistor and a drain of the second PMOS transistor, respectively; the sources and back gates of the first NMOS transistor and the second NMOS transistor are connected to a ground terminal; a differential amplifier circuit including a first terminal connected to the commonly connected sources of the first PMOS transistor and the second PMOS transistor, a second terminal connected to the commonly connected back gates of the first PMOS transistor and the second PMOS transistor, and a power supply terminal connected to a power supply terminal, the differential amplifier circuit including a voltage adjustment circuit capable of adjusting a voltage between the first terminal and the second terminal; The voltage adjustment circuit is configured so that a voltage generated between a first terminal and a second terminal increases or decreases in response to a change in an input voltage of the differential amplifier circuit. A reference voltage circuit comprising:

2. The gates of the first PMOS transistor and the second PMOS transistor are input, a drain of a first NMOS transistor and a drain of a second NMOS transistor are connected to a drain of the first PMOS transistor and a drain of the second PMOS transistor, respectively; the sources and back gates of the first NMOS transistor and the second NMOS transistor are connected to a ground terminal; a differential amplifier circuit including a first terminal connected to the commonly connected sources of the first PMOS transistor and the second PMOS transistor, a second terminal connected to the commonly connected back gates of the first PMOS transistor and the second PMOS transistor, and a power supply terminal connected to a power supply terminal, the differential amplifier circuit including a voltage adjustment circuit having a current source connected between the power supply terminal and the second terminal and a resistor connected between the first terminal and the second terminal; The resistor is a variable resistor whose resistance value is adjustable so that the voltage generated across both ends of the resistor increases or decreases in response to a change in the input voltage of the differential amplifier circuit. A reference voltage circuit comprising:

3. The gates of the first PMOS transistor and the second PMOS transistor are input, a drain of a first NMOS transistor and a drain of a second NMOS transistor are connected to a drain of the first PMOS transistor and a drain of the second PMOS transistor, respectively; the sources and back gates of the first NMOS transistor and the second NMOS transistor are connected to a ground terminal; a differential amplifier circuit including a first terminal connected to the commonly connected sources of the first PMOS transistor and the second PMOS transistor, a second terminal connected to the commonly connected back gates of the first PMOS transistor and the second PMOS transistor, and a power supply terminal connected to a power supply terminal, the differential amplifier circuit including a voltage adjustment circuit having a current source connected between the power supply terminal and the second terminal and a resistor connected between the first terminal and the second terminal; The current source is a variable current source capable of adjusting a current value so that a voltage generated across both ends of the resistor increases or decreases in response to a change in an input voltage of the differential amplifier circuit. A reference voltage circuit comprising:

4. The voltage adjustment circuit is configured to generate a voltage that is lower than the gate voltage or the threshold voltage of the first PMOS transistor and the second PMOS transistor over a predetermined temperature range, and has a temperature coefficient of opposite polarity to that of a voltage input to the gate of the first PMOS transistor.

4. The reference voltage circuit according to claim 1, wherein:

5. The voltage adjustment circuit is configured to be capable of generating a voltage between a first terminal and a second terminal of not less than 0.10 V and not more than 0.30 V across the predetermined temperature range.

5. The reference voltage circuit according to claim 4.

Images