Display device

Abstract

To provide a novel display device.SOLUTION: A display device has first to fifth p-channel transistors and an n-channel transistor. A gate of the fifth p-channel transistor and a gate of the n-channel transistor, which operate in the same timing, are connected to separate nodes. A gate of the first p-channel transistor is directly connected to the gate of the n-channel transistor. The gate of the fifth p-channel transistor is electrically connected to the gate of the first p-channel transistor via a source and a drain of the third p-channel transistor.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in the present specification etc. relates to an object, a method, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter). More specifically, examples of the technical field of one embodiment of the present invention disclosed in the present specification etc. include a semiconductor device, a display device, a light-emitting device, a power storage device, an optical device, an imaging device, a lighting device, an arithmetic device, a control device, a storage device, an input device, an output device, an input / output device, a signal processing device, an arithmetic processing device, an electronic computer, an electronic device, a driving method thereof, or a manufacturing method thereof. [Background technology]

[0003] Display devices have become increasingly commoditized as a result of recent technological innovations, and in order to gain a competitive edge in this environment, there is a demand for products with higher added value.

[0004] For example, a display device using a transistor having an oxide semiconductor in a semiconductor layer having a channel formation region (also referred to as an OS transistor) and a transistor having low temperature polysilicon (LTPS transistor) in a semiconductor layer having a channel formation region is known (see Patent Document 1). A display device using an OS transistor and an LTPS transistor can be a display device with high added value such as high definition, low power consumption, high switching speed, and / or a narrow frame of the panel. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2021 / 053707 Summary of the Invention [Problem to be solved by the invention]

[0006] Patent Document 1 discloses a configuration in which the above-mentioned OS transistor and LTPS transistor are used in a gate line driver circuit. In a part of the gate line driver circuit, a so-called complementary circuit configuration is disclosed in which the OS transistor is used as an n-channel transistor and the LTPS transistor is used as a p-channel transistor. In the complementary circuit configuration, for example, when an L-level signal is supplied to the gate, the n-channel transistor is in an off state and the p-channel transistor is in an on state. A driver circuit having a complementary circuit configuration is effective in reducing power consumption.

[0007] However, in a complementary circuit configuration, when a signal that has not yet dropped sufficiently to the L level is supplied to the gate, the p-channel transistor may be turned on while the n-channel transistor may not be turned off, which may result in malfunctions in a drive circuit having a complementary circuit configuration, increased power consumption, and / or transistor degradation.

[0008] An object of one embodiment of the present invention is to provide a display device capable of suppressing an increase in power consumption.Another object of one embodiment of the present invention is to provide a display device capable of reducing manufacturing costs.Another object of one embodiment of the present invention is to provide a highly reliable display device.Another object of one embodiment of the present invention is to provide a novel display device.

[0009] The problems listed above do not prevent the existence of other problems. It is not necessary for one embodiment of the present invention to solve all of the problems listed above. Problems other than the problems listed above will become apparent from the description of this specification, drawings, claims, etc., and problems other than the problems listed above can be extracted from the description of this specification, drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a display device including a gate line driver circuit. A unit circuit included in the gate line driver circuit includes first to fifth p-channel transistors and an n-channel transistor. One of a source or a drain of the first p-channel transistor is electrically connected to a first clock signal line. One of a source or a drain of the second p-channel transistor is electrically connected to a first power supply line. The other of the source or the drain of the first p-channel transistor is electrically connected to the other of the source or the drain of the second p-channel transistor. A gate of the first p-channel transistor is electrically connected to one of a source or a drain of a third p-channel transistor. The gate of the first p-channel transistor is directly connected to the gate of the n-channel transistor. The gate of the third p-channel transistor is electrically connected to a second power supply line. A display device in which the other of the source or the drain of the third p-channel transistor is electrically connected to one of the source or the drain of a fourth p-channel transistor, the other of the source or the drain of the third p-channel transistor is electrically connected to a gate of a fifth p-channel transistor, the gate of the fourth p-channel transistor is electrically connected to a second clock signal line, one of the source or the drain of the fifth p-channel transistor is electrically connected to a first power supply line, the other of the source or the drain of the fifth p-channel transistor is electrically connected to a gate of a second p-channel transistor, the other of the source or the drain of the fifth p-channel transistor is electrically connected to one of the source or the drain of an n-channel transistor, and the other of the source or the drain of the n-channel transistor is electrically connected to a second power supply line.

[0011] In one embodiment of the present invention, in the display device, the n-channel transistor preferably includes a first semiconductor layer, and the first semiconductor layer preferably includes an oxide semiconductor.

[0012] In one embodiment of the present invention, the display device preferably includes the first to fifth p-channel transistors each having a second semiconductor layer, and the second semiconductor layer includes silicon.

[0013] One embodiment of the present invention is a display device including a gate line driver circuit. A unit circuit included in the gate line driver circuit includes first to seventh p-channel transistors and an n-channel transistor. One of a source or a drain of the first p-channel transistor is electrically connected to a first clock signal line. One of a source or a drain of the second p-channel transistor is electrically connected to a first power supply line. The other of the source or the drain of the first p-channel transistor is electrically connected to the other of the second p-channel transistor. A gate of the first p-channel transistor is electrically connected to one of a source or a drain of a third p-channel transistor. The gate of the first p-channel transistor is directly connected to the gate of the n-channel transistor. The gate of the third p-channel transistor is electrically connected to a second power supply line. The other of the source or the drain of the third p-channel transistor is electrically connected to one of a source or a drain of a fourth p-channel transistor. the other of the source or drain of the fifth p-channel transistor is electrically connected to one of the source or drain of a sixth p-channel transistor, the other of the source or drain of the third p-channel transistor is electrically connected to the gate of a fifth p-channel transistor, the gate of the fourth p-channel transistor is electrically connected to a second clock signal line, one of the source or drain of the fifth p-channel transistor is electrically connected to a first power supply line, the other of the source or drain of the fifth p-channel transistor is electrically connected to the gate of a second p-channel transistor, the other of the source or drain of the fifth p-channel transistor is electrically connected to a gate of a seventh p-channel transistor, the other of the source or drain of the fifth p-channel transistor is electrically connected to one of the source or drain of an n-channel transistor, the other of the source or drain of the n-channel transistor is electrically connected to a second power supply line, the gate of the sixth p-channel transistor is electrically connected to a first clock signal line, and the other of the source or drain of the sixth p-channel transistor isThe display device is electrically connected to one of a source or a drain of a seventh p-channel transistor, and the other of the source or the drain of the seventh p-channel transistor is electrically connected to a first power supply line.

[0014] In one embodiment of the present invention, in the display device, the n-channel transistor preferably includes a first semiconductor layer, and the first semiconductor layer preferably includes an oxide semiconductor.

[0015] In one embodiment of the present invention, the display device preferably includes the first to seventh p-channel transistors each having a second semiconductor layer, and the second semiconductor layer includes silicon.

[0016] Other aspects of the present invention will be described in the following embodiment and in the drawings. Effect of the Invention

[0017] One embodiment of the present invention can provide a display device in which an increase in power consumption can be suppressed. Another embodiment of the present invention can provide a display device in which manufacturing costs can be reduced. Another embodiment of the present invention can provide a display device with high reliability. Another embodiment of the present invention can provide a novel display device.

[0018] The effects listed above do not preclude the existence of other effects. It is not necessary for one embodiment of the present invention to have all of the effects listed above. Effects other than the effects listed above will become apparent from the description of this specification, drawings, claims, etc., and it is possible to extract effects other than the effects listed above from the description of this specification, drawings, claims, etc. [Brief description of the drawings]

[0019] [Figure 1] 1(A) and 1(B) are a block diagram and a circuit diagram illustrating a display device. [Diagram 2]2(A) and 2(B) are circuit diagrams illustrating the display device. [Diagram 3] FIG. 3 is a timing chart illustrating the display device. [Figure 4] 4(A) and 4(B) are circuit diagrams illustrating the display device. [Diagram 5] 5(A) and 5(B) are circuit diagrams illustrating the display device. [Figure 6] 6(A) and 6(B) are circuit diagrams illustrating the display device. [Figure 7] 7A and 7B are a circuit diagram and a timing chart illustrating the operation of a display device. [Figure 8] 8(A) and 8(B) are circuit diagrams illustrating the display device. [Figure 9] 9(A) and 9(B) are circuit diagrams illustrating a display device. [Figure 10] 10(A) and 10(B) are circuit diagrams illustrating a display device. [Figure 11] 11(A) and 11(B) are circuit diagrams illustrating a display device. [Figure 12] 12(A) and 12(B) are circuit diagrams illustrating a display device. [Figure 13] 13A to 13C are circuit diagrams illustrating a display device. [Figure 14] 14A to 14C are circuit diagrams illustrating a display device. [Figure 15] 15A to 15C are circuit diagrams illustrating a display device. [Figure 16] 16(A) and 16(B) are circuit diagrams illustrating a display device. [Figure 17] 17A to 17C are circuit diagrams illustrating a display device. [Figure 18] 18A to 18C are circuit diagrams illustrating a display device. [Figure 19]19A to 19C are circuit diagrams illustrating a display device. [Figure 20] 20A to 20C are circuit diagrams illustrating a display device. [Figure 21] FIG. 21 is a timing chart illustrating the display device. [Figure 22] 22(A) and 22(B) are circuit diagrams illustrating a display device. [Diagram 23] 23(A) and 23(B) are circuit diagrams illustrating a display device. [Figure 24] 24(A) and 24(B) are circuit diagrams illustrating a display device. [Diagram 25] 25(A) and 25(B) are circuit diagrams illustrating a display device. [Figure 26] FIG. 26 is a circuit diagram illustrating the display device. [Figure 27] 27(A) and 27(B) are circuit diagrams illustrating a display device. [Figure 28] FIG. 28 is a perspective view showing a configuration example of a display device. [Figure 29] 29A to 29C are cross-sectional views showing configuration examples of a display device. [Diagram 30] 30(A) and 30(B) are cross-sectional views showing configuration examples of a display device. [Diagram 31] FIG. 31 is a plan view showing a configuration example of a display device. [Diagram 32] 32(A) and 32(B) are cross-sectional views showing configuration examples of a display device. [Diagram 33] FIG. 33 is a plan view showing a configuration example of a display device. [Diagram 34] FIG. 34 is a plan view showing a configuration example of a display device. [Diagram 35] FIG. 35 is a plan view showing a configuration example of a display device. [Diagram 36] FIG. 36 is a plan view showing a configuration example of a display device. [Figure 37]37A to 37D are circuit diagrams showing configuration examples of display devices. [Figure 38] 38(A) to 38(C) are circuit diagrams showing configuration examples of display devices. [Figure 39] 39(A) and 39(B) are diagrams showing an example of an electronic device. [Diagram 40] 40(A) to 40(D) ​​are diagrams showing examples of electronic devices. [Diagram 41] 41(A) to 41(G) are diagrams showing examples of electronic devices. [Diagram 42] 42(A1) to 42(A7) and 42(B1) to 42(B6) are diagrams showing the term "connection" in this specification. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0020] Hereinafter, the embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways. Therefore, it is easily understood by those skilled in the art that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, one aspect of the present invention should not be interpreted as being limited to the description of the embodiments.

[0021] In this specification and the like, a configuration shown in each embodiment can be appropriately combined with a configuration shown in another embodiment to form one aspect of the present invention. In addition, when multiple configurations are shown in one embodiment, these configurations can be appropriately combined to form one aspect of the present invention.

[0022] In addition, in the drawings explaining the embodiments, the same reference numerals may be used in common between different drawings for the same parts or parts having similar functions in the configuration of the invention, and the repeated description may be omitted. In addition, in the drawings, when the same functions are indicated, for example, the hatching patterns may be the same and no particular reference numerals may be attached. In addition, in the drawings, for example, in perspective views and plan views, the illustration of some components may be omitted in order to make it easier to understand. In addition, in the drawings, for example, the illustration of some hidden lines may be omitted. In addition, in the drawings, for example, the illustration of hatching patterns may be omitted.

[0023] Also, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Thus, the drawings are not limited to, for example, their size or aspect ratio. The drawings are schematic illustrations of ideal examples, and are not limited to, for example, shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be unintentionally thinned by a process such as etching, but these may not be reflected in the drawings to facilitate understanding. Also, for example, in an actual circuit operation, variations in voltage or current may occur due to noise or timing deviation, but these may not be reflected in the drawings to facilitate understanding.

[0024] In addition, in this specification and drawings, the components of the present invention may be classified by function and shown as independent elements. However, it may be difficult to separate the components by function, and one element may be involved in multiple functions, or one function may be involved across multiple elements. Therefore, the elements shown in this specification and drawings are not limited to the description, and may be rephrased appropriately.

[0025] In addition, in this specification and drawings, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, a distinguishing reference numeral such as "A", "b", "_1", "[n]", or "[m,n]" may be added to the reference numeral. In addition, when explaining matters common to multiple elements to which a distinguishing reference numeral is added, or when it is not necessary to distinguish between them, the distinguishing reference numeral may not be added.

[0026] (Embodiment 1) A display device according to one embodiment of the present invention will be described with reference to the drawings. The display device described in this embodiment includes a gate line driver circuit that outputs an output signal for selecting pixels on a row-by-row basis.

[0027] <Example of display device configuration> Fig. 1A is an example of a block diagram of a display device according to one embodiment of the present invention, and Fig. 1B is an example of a circuit diagram illustrating a shift register included in a gate line driver circuit included in the display device in Fig. 1A.

[0028] The display device 300 shown in FIG. 1A includes a display portion 362 and a gate line driver circuit 364. The display portion 362 includes a pixel portion 345 including pixels 370 arranged in m rows and n columns (m and n are both integers of 2 or more). The gate line driver circuit 364 includes a shift register 350 that outputs output signals OUT_1 to OUT_m for selecting the pixels 370 in each row provided in the pixel portion 345. The shift register 350 includes a plurality of unit circuits 100 that output an output signal in response to a clock signal and a start pulse signal. Note that a unit circuit is a circuit that outputs output signals (also referred to as pulse signals or selection signals) for one row in a shift register included in a gate line driver circuit. The unit circuit may be referred to as a pulse signal output circuit or a selection signal output circuit.

[0029] The display unit 362 and the gate line driver circuit 364 include an OS transistor and an LTPS transistor. The OS transistor and the LTPS transistor can be thin film transistors (TFTs). Since the thin film transistors can be formed on a light-transmitting substrate such as a glass substrate, the display device 300 can be increased in size and reduced in cost. Furthermore, since the gate line driver circuit 364 can be formed on the substrate together with the display unit 362, it is possible to narrow the frame and / or reduce the number of components such as an external driver circuit.

[0030] The display unit 362 and the gate line driver circuit 364 may have a circuit configuration in which the OS transistor is an n-channel transistor and the LTPS transistor is a p-channel transistor. In other words, the display unit 362 and the gate line driver circuit 364 may have a complementary circuit configuration. In the case of an inverter circuit, for example, a complementary circuit configuration can be achieved by applying a potential of the same logic level to the gates of both transistors to turn one of them on and the other off. In this case, the current flowing between the power supply lines can be reduced by providing an n-channel transistor and a p-channel transistor between the power supply lines, thereby achieving low power consumption. Note that a configuration in which an LTPS transistor and an OS transistor are combined may be referred to as LTPO.

[0031] 1B includes unit circuits 100_1 to 100_m (m is an integer of 2 or more) as the plurality of unit circuits 100. The unit circuits 100_1 to 100_m are connected to a wiring 101, a wiring 102, a power supply line 103, a power supply line 104, a wiring 105, and a wiring 106, respectively.

[0032] The wiring 101 is a wiring that transmits a clock signal CK1 to the unit circuits 100_1 to 100_m provided in each row. The wiring 102 is a wiring that transmits a clock signal CK2 to the unit circuits 100_1 to 100_m provided in each row. The wirings 101 and 102 may be referred to as clock signal lines. In the unit circuits 100_1 to 100_m illustrated in FIG. 1B, terminals connected to the wirings 101 and 102 are illustrated as CK1 and CK2.

[0033] The power supply line 103 is a power supply line that transmits a power supply potential, for example, a potential VDD, to the unit circuits 100_1 to 100_m provided in each row. The power supply line 104 is a power supply line that transmits a power supply potential, for example, a potential VSS, to the unit circuits 100_1 to 100_m provided in each row. In the unit circuits 100_1 to 100_m illustrated in FIG. 1B, a terminal connected to the power supply line 103 is illustrated as VDD, and a terminal connected to the power supply line 104 is illustrated as VSS.

[0034] The wiring 105 is a wiring that transmits a control signal, for example, a start pulse signal SP, to the unit circuit 100_1 provided in the first row. The wiring 105 may be referred to as a signal line. In the unit circuit 100_1 illustrated in FIG. 1B, a terminal connected to the wiring 105 is illustrated as SP. Note that in the unit circuits 100_2 to 100_m provided in the second and subsequent rows illustrated in FIG. 1B, an output signal output by the unit circuit 100 in the previous row functions as a control signal. Therefore, a terminal connected to the wiring 106 in the previous row is illustrated as SP.

[0035] The wiring 106 is a wiring that transmits output signals OUT_1 to OUT_m output by the unit circuits 100_1 to 100_m provided in each row. The wiring 106 may be referred to as an output signal line. In the unit circuits 100_1 to 100_m illustrated in FIG. 1B, a terminal connected to the wiring 106 is illustrated as OUT. Note that, as described above, in the unit circuits 100_1 to 100_m-1 illustrated in FIG. 1B, the output signals OUT_1 to OUT_m-1 are also control signals for the following row. In other words, the wiring 106 that outputs the output signals OUT_1 to OUT_m-1 also functions as a signal line that transmits a control signal.

[0036] <Configuration example of unit circuit 100> Fig. 2(A) is an example of a circuit diagram of a unit circuit 100 that can be applied to the unit circuits 100_1 to 100_m in Fig. 1(B). Fig. 2(B) is a circuit symbol that represents the circuit diagram of the unit circuit 100 shown in Fig. 2(A). The circuit diagram shown in Fig. 1(B) is illustrated using the circuit symbol in Fig. 2(B).

[0037] The unit circuit 100 includes transistors Tp1 to Tp5, a transistor Tn1, and a capacitor Cp. The unit circuit 100 is connected to the wiring 101, the wiring 102, the power supply line 103, the power supply line 104, the wiring 105, and the wiring 106 described in FIG.

[0038] One of the source or drain of the transistor Tp1 is connected to the wiring 101. One of the source or drain of the transistor Tp2 is connected to the power supply line 103. The other of the source or drain of the transistor Tp1 is connected to the other of the source or drain of the transistor Tp2. The other of the source or drain of the transistor Tp1 is connected to the wiring 106. The gate of the transistor Tp1 is connected to one of the source or drain of the transistor Tp3. The gate of the transistor Tp1 is connected to the gate of the transistor Tn1. One electrode of the capacitor Cp is connected to the other of the source or drain of the transistor Tp1. The other electrode of the capacitor Cp is connected to the gate of the transistor Tp1. The gate of the transistor Tp3 is connected to the power supply line 104. The other of the source or drain of the transistor Tp3 is connected to one of the source or drain of the transistor Tp4. The other of the source or drain of the transistor Tp3 is connected to the gate of the transistor Tp5. The other of the source or drain of the transistor Tp4 is connected to the wiring 105. The gate of the transistor Tp4 is connected to the wiring 102. One of the source and the drain of the transistor Tp5 is connected to the power supply line 103. The other of the source and the drain of the transistor Tp5 is connected to the gate of the transistor Tp2. The other of the source and the drain of the transistor Tp5 is connected to one of the source and the drain of the transistor Tn1. The other of the source and the drain of the transistor Tn1 is connected to the power supply line 104.

[0039] In the circuit diagram shown in FIG. 2(A), each node is labeled for ease of understanding. For example, in FIG. 2(A), the node connected to the gate of transistor Tn1 is designated as node N1. In FIG. 2(A), the node connected to the gate of transistor Tp5 is designated as node N2. In FIG. 2(A), the node connected to the gate of transistor Tp2 is designated as node N3. Note that a node refers to an element (e.g., a wiring) that allows the connection of elements that constitute a circuit. Therefore, a "node connected to A" refers to a wiring that is connected to A and can be considered to have the same potential as A.

[0040] The transistors Tp1 to Tp5 are p-channel transistors. The semiconductor layers of the transistors Tp1 to Tp5, each having a channel formation region, contain silicon. Examples of silicon used in the semiconductor layers of the transistors Tp1 to Tp5 include single crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, LTPS transistors having low-temperature polysilicon in the semiconductor layer are preferable. The transistors Tp1 to Tp5 are LTPS transistors, which can have high field-effect mobility and favorable frequency characteristics. The transistors Tp1 to Tp5 may be referred to as first to fifth p-channel transistors.

[0041] Note that the transistor Tp1 connected to the wiring 106 that outputs an output signal may be referred to as a pull-up transistor, and the transistor Tp2 may be referred to as a pull-down transistor. The transistor Tp3 having a function of making the potential or voltage of the node N1 and the node N2 different from each other may be referred to as a potential adjustment transistor or a voltage adjustment transistor.

[0042] The transistor Tn1 is an n-channel transistor. The n-channel transistor is preferably an OS transistor including an oxide semiconductor in a semiconductor layer having a channel formation region.

[0043] The OS transistor has a very low off-state current because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more. The off-state current of an OS transistor per 1 μm of channel width at room temperature is 1×10 -12 A or less, 1aA(1×10 -18 A) Below, 1zA(1×10 -21 A) or less, or 1yA (1×10 -24 A) or less. Therefore, by providing the transistor Tn1 between the power supply lines 103 and 104 and turning it off, the current flowing between the power supply lines can be made extremely small. This allows the power consumption of the display device to be reduced.

[0044] Moreover, the off-current of the OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Moreover, the on-current of the OS transistor is unlikely to decrease even in a high-temperature environment. Furthermore, the OS transistor can perform a good switching operation even in an environment of 125° C. or higher and 150° C. or lower because the ratio of the on-current to the off-current is large. Thus, a semiconductor device using an OS transistor can operate stably and with high reliability even in a high-temperature environment. That is, by using an OS transistor as the transistor included in the gate line driver circuit 364, the reliability of the display device can be improved.

[0045] In addition, the OS transistor has a high withstand voltage between the source and drain (also referred to as drain withstand voltage). Therefore, the OS transistor operates stably even when driven at a high voltage. For example, the OS transistor can be used as a transistor connected to a node to which a high voltage is applied in the unit circuit 100. Therefore, the reliability of a gate line driver circuit including an OS transistor can be improved.

[0046] The OS transistor can be provided in a layer different from that of the LTPS transistor. In this case, a layer including the LTPS transistor and a layer including the OS transistor can be provided so as to overlap each other. This configuration can reduce the area occupied by the gate line driver circuit 364. In particular, in a display device using an organic EL element, a plurality of types of gate line driver circuits are formed. Therefore, when the gate line driver circuit 364 is adopted in a display device using an organic EL element, the area in which the gate line driver circuit 364 can be arranged is reduced. In such a case, it is particularly preferable to provide the OS transistor in a layer different from that of the LTPS transistor to reduce the area occupied by the gate line driver circuit 364.

[0047] The OS transistor may have a gate or may have a gate and a backgate. The OS transistor preferably has a backgate. When the OS transistor has a backgate, the threshold voltage of the OS transistor can be increased or decreased by applying a predetermined potential to the backgate of the OS transistor. Alternatively, the on-current of the OS transistor can be increased by connecting the backgate of the OS transistor to the gate.

[0048] Note that the OS transistor and the LTPS transistor can have various structures, such as a planar type, a staggered type, a fin type, a tri-gate type, a top-gate type, a bottom-gate type, or a dual-gate type (a structure in which gates are arranged on both sides (e.g., above and below) of a channel formation region).

[0049] The transistor Tn1 may be a transistor other than an OS transistor. Any n-channel transistor with a higher withstand voltage than the LTPS transistor used as a p-channel transistor can be used as the transistor Tn1. For example, in an n-channel LTPS transistor, by increasing the channel length, increasing the thickness of the gate insulating film, or the like, the withstand voltage can be increased, and thus the transistor Tn1 can be used as an n-channel transistor with a higher withstand voltage than the LTPS transistor used as a p-channel transistor.

[0050] <Operation example of unit circuit 100> FIG. 3 is a timing chart illustrating the operation of the unit circuit 100 shown in the circuit diagram of FIG.

[0051] CK1 in FIG. 3 is a clock signal supplied to the wiring 101. CK2 in FIG. 3 is a clock signal supplied to the wiring 102. SP in FIG. 3 is a control signal supplied to the wiring 105. N1 to N3 in FIG. 3 represent changes in the potentials of the nodes N1 to N3. OUT in FIG. 3 is an output signal output to the wiring 106. In addition, times t1 to t7 are added to FIG. 3 to explain the operation.

[0052] Figures 4(A) to 6(B) are circuit diagrams that show the operation at times t1 to t7 shown in Figure 3. In Figures 4(A) to 6(B), the circuit symbols of transistors that are in the off state are shown with a cross mark superimposed thereon. Also, in Figures 4(A) to 6(B), the current that flows when the transistor is in the on state is shown with a thick arrow.

[0053] In the following description, the power supply line 103 is at a potential VDD (hereafter referred to as VDD), and the power supply line 104 is at a potential VSS (hereafter referred to as VSS). A p-channel transistor is turned on when the logical level of a signal applied to the gate is L level (low level), and turned off when it is H level (high level). An n-channel transistor is turned on when the logical level of a signal applied to the gate is H level, and turned off when it is L level. Therefore, the logical level at which a transistor is turned on may be called the on level, and the logical level at which a transistor is turned off may be called the off level. The H level refers to the high potential level of a control signal or clock signal, or a potential based on VDD. The L level refers to the low potential level of a control signal or clock signal, or a potential based on VSS.

[0054] Fig. 4(A) is a diagram explaining the operation during the period from time t1 to t2 shown in Fig. 3. CK1, CK2, SP, VDD, and VSS turn on the transistors Tp1, Tp3 to Tp5, and turn off the transistors Tp2 and Tn1. OUT becomes the H level potential of CK1. N1 and N2 become the L level of SP. N3 becomes VDD, that is, the H level.

[0055] FIG. 4(B) is a diagram explaining the operation during the period from time t2 to t3 shown in FIG. 3. CK1, CK2, SP, VDD, and VSS turn on the transistors Tp1, Tp3, and Tp5, and turn off the transistors Tp2, Tp4, and Tn1. OUT becomes the H-level potential of CK1. N1 and N2 are in an electrically floating state (floating) because the transistor Tp4 is turned off. Therefore, N1 and N2 hold the L-level of SP. N3 remains at VDD, that is, the H-level.

[0056] Fig. 5(A) is a diagram for explaining the operation during the period from time t3 to t4 shown in Fig. 3. CK1, CK2, SP, VDD, and VSS turn on the transistors Tp1 and Tp5, and turn off the transistors Tp2 to Tp4 and the transistor Tn1.

[0057] During the period from time t3 to t4, transistor Tp4 is in the off state, so N1 and N2 are floating. Capacitor Cp maintains the potential difference between the electrodes at both ends, so the potential of N1 fluctuates as the potential of OUT changes. Specifically, as CK1 changes from H level to L level, the potential of OUT also drops, and the potential of N1 also drops. As the potential of N1 drops, transistor Tp3 turns off because its gate-source voltage (Vgs) becomes equal to or greater than the threshold voltage (Vth<0). N2 becomes VSS-Vth, which is smaller than VSS by the threshold voltage (Vth) of transistor Tp3, and N1 becomes a potential smaller than VSS-Vth. Transistor Tp3, which is a potential adjustment transistor, can make the potential of a signal of the same logic level, for example, L level, different between N1 and N2.

[0058] OUT can be lowered to VSS by making N1 have a potential smaller than VSS-Vth. N3 remains at VDD, that is, the H level.

[0059] In one embodiment of the present invention, in order to control the on state of the transistor Tn1 and the off state of the transistor Tp5, which are operated at the same logic level, with different potentials, the gate of the transistor Tn1 is connected to a node N1 and the gate of the transistor Tp5 is connected to a node N2.

[0060] The potential of the node N1 is lower than the potential of the node N2. The potential of the node N1 can be set to an off-level signal for the transistor Tn1, which is an n-channel transistor, to more reliably turn it off. Since the potential of the node N1 is lower than VSS, this may cause deterioration and dielectric breakdown of the transistor. However, since the transistor Tn1 is an OS transistor, this deterioration and dielectric breakdown can be prevented.

[0061] Also, VSS-Vth of node N2 is higher than the potential of node N1. By using the potential of node N2 as an on-level signal for transistor Tp5, which is a p-channel transistor, the transistor can be turned on without inducing deterioration and dielectric breakdown. Since the potential of node N2 is lower than that of node N1, deterioration and / or dielectric breakdown of other transistors Tp3 and Tp4 connected to node N2 can be prevented.

[0062] FIG. 5B is a diagram explaining the operation during the period from time t4 to t5 shown in FIG. 3. CK1, CK2, SP, VDD, and VSS turn on the transistors Tp1, Tp3, and Tp5, and turn off the transistors Tp2, Tp4, and Tn1. OUT becomes the H level potential of CK1. N1 and N2 become floating because the transistor Tp4 is turned off. Therefore, N1 and N2 hold the L level of SP. N3 remains at VDD, that is, the H level.

[0063] 6A is a diagram for explaining the operation during the period from time t5 to t6 shown in FIG. 3. CK1, CK2, SP, VDD, and VSS turn on the transistors Tp2 to Tp4 and the transistor Tn1, and turn off the transistors Tp1 and Tp5. OUT becomes VDD. N1 and N2 become the H level potential of SP. N3 becomes VSS, that is, the L level.

[0064] FIG. 6B is a diagram explaining the operation during the period from time t6 to t7 shown in FIG. 3. CK1, CK2, SP, VDD, and VSS turn on the transistors Tp2, Tp3, and Tn1, and turn off the transistors Tp1, Tp4, and Tp5. OUT remains at VDD. N1 and N2 are floating because the transistor Tp4 is turned off. Therefore, N1 and N2 hold the H level of SP. N3 remains at VSS, that is, the L level.

[0065] <Configuration example of unit circuit 100A> Fig. 7(A) is a circuit diagram of a unit circuit 100A having a different configuration from the unit circuit 100 described in Fig. 2(A). Note that in the description of Fig. 7(A), the above description of the configuration overlapping with the description of Fig. 2(A) is used, and the description may be omitted.

[0066] The unit circuit 100A includes transistors Tp1 to Tp7, a transistor Tn1, and a capacitor Cp. The unit circuit 100A is applicable to the unit circuits 100_1 to 100_m included in the shift register 350 described in FIG. 1B. The unit circuit 100A is connected to a wiring 101, a wiring 102, a power supply line 103, a power supply line 104, a wiring 105, and a wiring 106.

[0067] One of the source or drain of the transistor Tp1 is connected to the wiring 101. One of the source or drain of the transistor Tp2 is connected to the power supply line 103. The other of the source or drain of the transistor Tp1 is connected to the other of the source or drain of the transistor Tp2. The other of the source or drain of the transistor Tp1 is connected to the wiring 106. The gate of the transistor Tp1 is connected to one of the source or drain of the transistor Tp3. The gate of the transistor Tp1 is connected to the gate of the transistor Tn1. One electrode of the capacitor Cp is connected to the other of the source or drain of the transistor Tp1. The other electrode of the capacitor Cp is connected to the gate of the transistor Tp1. The gate of the transistor Tp3 is connected to the power supply line 104. The other of the source or drain of the transistor Tp3 is connected to one of the source or drain of the transistor Tp4. The other of the source or drain of the transistor Tp3 is connected to one of the source or drain of the transistor Tp6. The other of the source or drain of the transistor Tp3 is connected to the gate of the transistor Tp5. The other of the source or drain of the transistor Tp4 is connected to the wiring 105. The gate of the transistor Tp4 is connected to the wiring 102. One of the source or drain of the transistor Tp5 is connected to the power supply line 103. The other of the source or drain of the transistor Tp5 is connected to the gate of the transistor Tp2. The other of the source or drain of the transistor Tp5 is connected to the gate of the transistor Tp7. The other of the source or drain of the transistor Tp5 is connected to one of the source or drain of the transistor Tn1. The other of the source or drain of the transistor Tn1 is connected to the power supply line 104. The gate of the transistor Tp6 is connected to the wiring 101. The other of the source or drain of the transistor Tp6 is connected to one of the source or drain of the transistor Tp7. The other of the source or drain of the transistor Tp7 is connected to the power supply line 103.

[0068] The transistors Tp1 to Tp7 are p-channel transistors. The semiconductor layers of the transistors Tp1 to Tp7, which have channel formation regions, contain silicon. Examples of silicon used in the semiconductor layers of the transistors Tp1 to Tp7 include single crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, LTPS transistors having low-temperature polysilicon in the semiconductor layer are preferable. The transistors Tp1 to Tp7, which are LTPS transistors, can have high field-effect mobility and favorable frequency characteristics. The transistors Tp1 to Tp7 may be referred to as first to seventh p-channel transistors.

[0069] The transistor Tn1 is an n-channel transistor. The n-channel transistor is preferably an OS transistor including an oxide semiconductor in a semiconductor layer having a channel formation region.

[0070] <Operation example of unit circuit 100A> Fig. 7(B) is a timing chart for explaining the operation of the unit circuit 100A shown in Fig. 7(A). Figs. 8(A) to 11(B) are circuit diagrams for diagrammatically showing the operation at times t1 to t9 shown in Fig. 7(B). In Fig. 7(B), times t1 to t9 are added to explain the operation. In the explanation of Fig. 7(B) and Fig. 8(A) to Fig. 11(B), the explanation of the configurations overlapping with the explanation of Fig. 3 and Fig. 4(A) to Fig. 6(B) may be omitted by citing the above explanation.

[0071] Fig. 8(A) is a diagram explaining the operation during the period from time t1 to t2 shown in Fig. 7(B). CK1, CK2, SP, VDD, and VSS turn on the transistors Tp1, Tp3 to Tp5, and turn off the transistors Tp2, Tp6, Tp7, and Tn1. OUT becomes the H level potential of CK1. N1 and N2 become the L level of SP. N3 becomes VDD, that is, the H level.

[0072] Fig. 8(B) is a diagram explaining the operation during the period from time t2 to t3 shown in Fig. 7(B). CK1, CK2, SP, VDD, and VSS turn on the transistors Tp1, Tp3, and Tp5, and turn off the transistors Tp2, Tp4, Tp6, Tp7, and the transistor Tn1. OUT becomes the H level potential of CK1. N1 and N2 become floating because the transistors Tp4, Tp6, and Tp7 are turned off. Therefore, N1 and N2 hold the L level of SP. N3 remains at VDD, that is, the H level.

[0073] Fig. 9(A) is a diagram for explaining the operation during the period from time t3 to t4 shown in Fig. 7(B). CK1, CK2, SP, VDD, and VSS turn on the transistors Tp1, Tp5, and Tp6, and turn off the transistors Tp2 to Tp4, Tp7, and the transistor Tn1.

[0074] During the period from time t3 to t4, transistors Tp4 and Tp7 are in the off state, so N1 and N2 are floating. Capacitor Cp maintains the potential difference between the electrodes at both ends, so the potential of N1 fluctuates as OUT changes. Specifically, as CK1 changes from H level to L level, the potential of N1 also drops. As the potential of N1 drops, transistor Tp3 turns off because its gate-source voltage (Vgs) becomes equal to or greater than the threshold voltage (Vth<0). N2 becomes VSS-Vth, which is smaller than VSS by the threshold voltage (Vth) of transistor Tp3, and N1 becomes at a potential lower than VSS-Vth. Transistor Tp3, which is a potential adjustment transistor, can make the potential of a signal of the same logical level, for example, L level, different between N1 and N2.

[0075] OUT can be lowered to VSS by making N1 have a potential smaller than VSS-Vth. N3 remains at VDD, that is, the H level.

[0076] In one embodiment of the present invention, in order to control the on state of the transistor Tn1 and the off state of the transistor Tp5, which are operated at the same logic level, with different potentials, the gate of the transistor Tn1 is connected to a node N1 and the gate of the transistor Tp5 is connected to a node N2.

[0077] The potential of the node N1 is lower than the potential of the node N2. The potential of the node N1 can be set to an off-level signal for the transistor Tn1, which is an n-channel transistor, to more reliably turn it off. Since the potential of the node N1 is lower than VSS, this may cause deterioration and dielectric breakdown of the transistor. However, since the transistor Tn1 is an OS transistor, this deterioration and dielectric breakdown can be prevented.

[0078] Also, VSS-Vth of node N2 is higher than the potential of node N1. By using the potential of node N2 as an on-level signal for transistor Tp5, which is a p-channel transistor, the transistor can be turned on without inducing deterioration and dielectric breakdown. Since the potential of node N2 is lower than that of node N1, deterioration and / or dielectric breakdown of other transistors Tp3 and Tp4 connected to node N2 can be prevented.

[0079] Fig. 9(B) is a diagram for explaining the operation during the period from time t4 to t5 shown in Fig. 7(B). CK1, CK2, SP, VDD, and VSS turn on the transistors Tp1, Tp3, and Tp5, and turn off the transistors Tp2, Tp4, Tp6, Tp7, and the transistor Tn1. OUT becomes the H level potential of CK1. N1 and N2 become floating because the transistors Tp4, Tp6, and Tp7 are turned off. Therefore, N1 and N2 hold the L level of SP. N3 remains at VDD, that is, the H level.

[0080] Fig. 10(A) is a diagram explaining the operation during the period from time t5 to t6 shown in Fig. 7(B). CK1, CK2, SP, VDD, and VSS turn on the transistors Tp2 to Tp4, Tp7, and the transistor Tn1, and turn off the transistors Tp1, Tp5, and Tp6. OUT becomes VDD. N1 and N2 become the H level potential of SP. N3 becomes VSS, that is, the L level.

[0081] Fig. 10(B) is a diagram explaining the operation during the period from time t6 to t7 shown in Fig. 7(B). CK1, CK2, SP, VDD, and VSS turn on the transistors Tp2, Tp3, Tp7, and the transistor Tn1, and turn off the transistors Tp1, Tp4, Tp5, and Tp6. OUT remains at VDD. N1 and N2 become floating because the transistors Tp4 and Tp6 are turned off. Therefore, N1 and N2 hold the H level of SP. N3 remains at VSS, that is, the L level.

[0082] FIG. 11(A) is a diagram for explaining the operation during the period from time t7 to t8 shown in FIG. 7(B). CK1, CK2, SP, VDD, and VSS turn on the transistors Tp2, Tp3, Tp6, Tp7, and the transistor Tn1, and turn off the transistors Tp1, Tp4, and Tp5. OUT remains at VDD. N1 and N2 are at VDD, that is, H level, because the transistors Tp6 and Tp7 are turned on. With this configuration, N1 and N2 are periodically supplied with H level, so the transistor Tp1, which is a pull-up transistor, can be continuously turned off. N3 remains at VSS, that is, L level.

[0083] Fig. 11(B) is a diagram explaining the operation during the period from time t8 to t9 shown in Fig. 7(B). CK1, CK2, SP, VDD, and VSS turn on the transistors Tp2, Tp3, Tp7, and the transistor Tn1, and turn off the transistors Tp1, Tp4, Tp5, and Tp6. OUT remains at VDD. N1 and N2 become floating because the transistors Tp4 and Tp6 are turned off. Therefore, N1 and N2 hold VDD, that is, H level. N3 remains at VSS, that is, L level.

[0084] <Modification 1 of the unit circuit 100A> The following describes modified examples of the unit circuit 100A described above. In the following description of the modified examples of the unit circuit 100A, the configurations that overlap with the description of the unit circuit 100A in FIG. 7A above may be omitted by citing the above description.

[0085] In the unit circuit 100A, the transistor or a wiring to which the transistor Tp5 is connected can have the configurations shown in FIGS.

[0086] In the unit circuit 100B1 shown in FIG. 12A, one of the source and drain of the transistor Tp5 is connected to the wiring 102 in the unit circuit 100A. This configuration reduces the number of transistors connected to the power line 103, thereby reducing the load on the power line 103. In addition, the potential of one of the source and drain of the transistor Tp5 can be changed, thereby suppressing deterioration of the transistor Tp5. In addition, during the period from time t1 to t2, the node N3 can be set to L level, and the transistors Tp2 and Tp7 can be turned on. By turning on the transistor Tp2, VDD can be output to OUT. This makes it easier to set OUT to an H level potential.

[0087] In the unit circuit 100B2 shown in FIG. 12B, one of the source and drain of the transistor Tp5 is connected to the wiring 105 in the unit circuit 100A. This configuration reduces the number of transistors connected to the power line 103, thereby reducing the load on the power line 103. In addition, the potential of one of the source and drain of the transistor Tp5 can be changed, thereby suppressing deterioration of the transistor Tp5. In addition, during the period from time t1 to t2, the node N3 can be set to L level, and the transistors Tp2 and Tp7 can be turned on. By turning on the transistor Tp2, VDD can be output to OUT. Therefore, it is easy to set OUT to an H level potential.

[0088] 13A illustrates a unit circuit 100B3 in which the gate of the transistor Tp5 in the unit circuit 100A is connected to the wiring 101. With this configuration, the number of transistors connected to the node N2 can be reduced, thereby reducing the parasitic capacitance of the node N2.

[0089] 13B illustrates a unit circuit 100B4 in which the gate of the transistor Tp5 is connected to the wiring 101 and one of the source and drain of the transistor Tp5 is connected to the wiring 102 in the unit circuit 100A. This configuration corresponds to a combination of the modified examples illustrated in the unit circuits 100B1 and 100B3. In this manner, one embodiment of the present invention can also have a configuration in which the modified examples described above are combined. With this configuration, the load on the power supply line 103 can be reduced and the parasitic capacitance of the node N2 can be reduced.

[0090] In the unit circuit 100B5 illustrated in FIG. 13C, in the unit circuit 100A, the gate of the transistor Tp5 is connected to the wiring 101 and one of the source or drain of the transistor Tp5 is connected to the wiring 105. This configuration corresponds to a combination of the modified examples illustrated in the unit circuits 100B2 and 100B3. In this manner, in one embodiment of the present invention, the above modified examples can be combined. This configuration can reduce the load on the power supply line 103 and the parasitic capacitance of the node N2. Furthermore, the potential of one of the source or drain of the transistor Tp5 can be changed, which can suppress deterioration of the transistor Tp5.

[0091] 14A illustrates a unit circuit 100B6 in which the gate of the transistor Tp5 in the unit circuit 100A is connected to the wiring 102. With this configuration, the number of transistors connected to the node N2 can be reduced, thereby reducing the parasitic capacitance of the node N2.

[0092] 14B illustrates a unit circuit 100B7 having a configuration in which the gate of the transistor Tp5 is connected to the wiring 102 and one of the source and drain of the transistor Tp5 is connected to the wiring 101 in the unit circuit 100A. This corresponds to a combination of the modified examples illustrated in the unit circuits 100B1 and 100B6. In this manner, one embodiment of the present invention can also have a configuration in which the modified examples described above are combined. With this configuration, the load on the power supply line 103 can be reduced and the parasitic capacitance of the node N2 can be reduced.

[0093] 14C illustrates a unit circuit 100B8 having the same configuration as the unit circuit 100A, except that the gate of the transistor Tp5 is connected to the wiring 102 and one of the source and drain of the transistor Tp5 is connected to the wiring 106. This corresponds to a combination of the modified examples illustrated in the unit circuits 100B2 and 100B6. In this manner, one embodiment of the present invention can also have a combination of the modified examples described above. This configuration can reduce the load on the power supply line 103 and the parasitic capacitance of the node N2.

[0094] <Modification 2 of the unit circuit 100A> In the unit circuit 100A, the wiring or the transistor to which the transistor Tn1 is connected can have the configurations shown in FIGS.

[0095] 15A illustrates a unit circuit 100A in which the other of the source and the drain of the transistor Tn1 is connected to the wiring 101. This configuration can reduce the number of transistors connected to the power supply line 104, thereby reducing the load on the power supply line 104. In addition, the potential of the other of the source and the drain of the transistor Tn1 can be changed, thereby suppressing deterioration of the transistor Tn1.

[0096] In the unit circuit 100C2 shown in FIG. 15B, the other of the source and drain of the transistor Tn1 is connected to the wiring 102 in the unit circuit 100A. This configuration reduces the number of transistors connected to the power line 104, thereby reducing the load on the power line 104. In addition, the potential of the other of the source and drain of the transistor Tn1 can be changed, thereby suppressing deterioration of the transistor Tn1. In addition, in the period from time t3 to t4, the other of the source and drain of the transistor Tn1 can be set to an H level, thereby making it easier to turn off the transistor Tn1. At this time, a large voltage is applied to the transistor Tn1, but by using an OS transistor as the transistor Tn1, deterioration and dielectric breakdown of the transistor Tn1 can be prevented.

[0097] 15C illustrates a unit circuit 100C3 in which the other of the source and the drain of the transistor Tn1 is connected to the wiring 105 in the unit circuit 100A. This configuration reduces the number of transistors connected to the power supply line 104, thereby reducing the load on the power supply line 104. In addition, the potential of the other of the source and the drain of the transistor Tn1 can be changed, thereby suppressing deterioration of the transistor Tn1.

[0098] The modified examples of the unit circuits 100C1 to 100C3 can be combined with the modified examples of the unit circuits 100B1 to 100B8 described above. With this configuration, the load of the power line 103 can be reduced and / or the parasitic capacitance of the node N2 can be reduced.

[0099] <Modification 3 of the unit circuit 100A> In the unit circuit 100A, the transistors or wirings to which the transistors Tp6 and Tp7 are connected can have the configurations shown in FIGS.

[0100] 16A illustrates a unit circuit 100A in which the other of the source and the drain of the transistor Tp7 is connected to the wiring 102. This configuration reduces the number of transistors connected to the power supply line 103, thereby reducing the load on the power supply line 103. In addition, the potential of the other of the source and the drain of the transistor Tp7 can be changed, thereby suppressing deterioration of the transistor Tp7.

[0101] 16B illustrates a unit circuit 100D2 in which the other of the source and the drain of the transistor Tp7 is connected to the wiring 106 in the unit circuit 100A. This configuration reduces the number of transistors connected to the power supply line 103, thereby reducing the load on the power supply line 103. In addition, the potential of the other of the source and the drain of the transistor Tp7 can be changed, thereby suppressing deterioration of the transistor Tp7.

[0102] 17A illustrates a unit circuit 100D3 in which the other of the source or drain of the transistor Tp7 is connected to the node N2 and one of the source or drain of the transistor Tp6 is connected to the power supply line 103 in the unit circuit 100A. This configuration allows the transistor Tp6 to be connected to the node N2 via the transistor Tp7, thereby reducing the effect of noise on the node N2 of the clock signal CK1 provided to the gate of the transistor Tp6. In addition, the potential of one of the source or drain of the transistor Tp6 can be changed, thereby suppressing deterioration of the transistor Tp6.

[0103] 17B illustrates a unit circuit 100D4 in the unit circuit 100A, in which the other of the source or drain of the transistor Tp7 is connected to the node N2, and one of the source or drain of the transistor Tp6 is connected to the wiring 102. With this configuration, the transistor Tp6 can be connected to the node N2 via the transistor Tp7, and therefore the effect of noise on the node N2 of the clock signal CK1 provided to the gate of the transistor Tp6 can be reduced. In addition, the potential of one of the source or drain of the transistor Tp6 can be changed, and therefore degradation of the transistor Tp6 can be suppressed.

[0104] 17C illustrates a unit circuit 100D5 in the unit circuit 100A, in which the other of the source or the drain of the transistor Tp7 is connected to the node N2, and one of the source or the drain of the transistor Tp6 is connected to the wiring 106. With this configuration, the transistor Tp6 can be connected to the node N2 via the transistor Tp7, thereby reducing the effect of noise on the node N2 of the clock signal CK1 provided to the gate of the transistor Tp6.

[0105] 18A shows a unit circuit 100D6 in which the transistor Tp6 is omitted from the unit circuit 100A. This configuration can reduce the number of transistors in the unit circuit. It can also reduce the effect of noise on the node N2 of the clock signal CK1 applied to the gate of the transistor Tp6.

[0106] 18B illustrates a unit circuit 100D7 in which the transistor Tp6 is omitted from the unit circuit 100A, and the other of the source and the drain of the transistor Tp7 is connected to the wiring 102. This configuration corresponds to a combination of the modified examples illustrated in the unit circuit 100D1 and the unit circuit 100D6. In this manner, one embodiment of the present invention can also have a configuration in which the above modified examples are combined. With this configuration, the number of transistors included in the unit circuit can be reduced, and the load on the power supply line 103 can be reduced.

[0107] 18C illustrates a unit circuit 100D8 in which the transistor Tp6 is omitted from the unit circuit 100A, and the other of the source and the drain of the transistor Tp7 is connected to the wiring 101. With this configuration, the number of transistors included in the unit circuit can be reduced, and the load on the power supply line 103 can be reduced.

[0108] The modified examples of the unit circuits 100D1 to 100D8 can be combined with the modified examples of the unit circuits 100B1 to 100B8 and the unit circuits 100C1 to 100C3 described above. This configuration can reduce the load on the power line 103, reduce the parasitic capacitance of the node N2, and / or reduce the number of transistors.

[0109] <Modification 4 of the unit circuit 100A> In the unit circuit 100A, the wiring or transistor to which the transistor Tp4 is connected can have the configurations shown in Figures 19(A) to 20(C). The unit circuits 100E1 to 100E6 shown in Figures 19(A) to 20(C) each have a configuration in which a transistor Tp8 is added. The transistor Tp8 is a p-channel transistor like the transistors Tp1 to Tp7.

[0110] 19(A) illustrates a configuration in which the gate of the transistor Tp4 in the unit circuit 100A is connected to a wiring 105, and the other of the source or drain of the transistor Tp4 is connected to a wiring 102. Also, in the unit circuit 100E1, a configuration is illustrated in which the gate of the transistor Tp8 is connected to a wiring 107, one of the source or drain is connected to a node N2, and the other of the source or drain is connected to a power line 103. With this configuration, N1 and N2 can periodically supply an H level regardless of the state of the transistor Tp4, so that the transistor Tp1, which is a pull-up transistor, can be continuously kept in an off state.

[0111] The wiring 107 functions as a reset line to which a reset signal is supplied. The reset signal is a signal for periodically supplying an H-level potential to the node N2.

[0112] 19(B) illustrates a configuration in which, in the unit circuit 100A, the gate of the transistor Tp4 is connected to a wiring 105, and the other of the source or drain of the transistor Tp4 is connected to a power supply line 104. Also, in the unit circuit 100E2, the gate of the transistor Tp8 is connected to a wiring 107, one of the source or drain is connected to a node N2, and the other of the source or drain is connected to a power supply line 103. With this configuration, N1 and N2 can periodically supply an H level regardless of the state of the transistor Tp4, so that the transistor Tp1, which is a pull-up transistor, can be continuously kept in an off state.

[0113] 19C shows a unit circuit 100E3 in which the gate of the transistor Tp4 and the other of the source and drain of the transistor Tp4 are connected to the wiring 105 in the unit circuit 100A. Also, in the unit circuit 100E3, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and drain is connected to the node N2, and the other of the source and drain is connected to the power line 103. With this configuration, N1 and N2 can periodically supply an H level regardless of the state of the transistor Tp4, so that the transistor Tp1, which is a pull-up transistor, can be continuously turned off. Also, the wiring 102 can be omitted.

[0114] In the unit circuit 100E4 shown in FIG. 20(A), in the unit circuit 100A, the gate of the transistor Tp4 is connected to the wiring 105, and the other of the source and drain of the transistor Tp4 is connected to the wiring 102. In the unit circuit 100E4, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and drain is connected to the node N2, and the other of the source and drain is connected to the wiring 101. With this configuration, N1 and N2 can periodically supply an H level regardless of the state of the transistor Tp4, so that the transistor Tp1, which is a pull-up transistor, can be continuously turned off. In addition, the number of transistors connected to the power supply line 103 due to the addition of the transistor Tp8 does not increase, so that an increase in the load on the power supply line 103 can be suppressed.

[0115] In the unit circuit 100E5 shown in FIG. 20(B), in the unit circuit 100A, the gate of the transistor Tp4 is connected to the wiring 105, and the other of the source and drain of the transistor Tp4 is connected to the power supply line 104. In the unit circuit 100E5, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and drain is connected to the node N2, and the other of the source and drain is connected to the wiring 101. With this configuration, N1 and N2 can periodically supply the H level regardless of the state of the transistor Tp4, so that the transistor Tp1, which is a pull-up transistor, can be continuously turned off. In addition, since the number of transistors connected to the power supply line 103 due to the addition of the transistor Tp8 does not increase, an increase in the load on the power supply line 103 can be suppressed. In addition, the wiring 102 can be omitted.

[0116] In the unit circuit 100E6 shown in FIG. 20(C), the gate of the transistor Tp4 and the other of the source and drain of the transistor Tp4 are connected to the wiring 105 in the unit circuit 100A. Also, in the unit circuit 100E6, the gate of the transistor Tp8 is connected to the wiring 107, one of the source and drain is connected to the node N2, and the other of the source and drain is connected to the wiring 101. With this configuration, N1 and N2 can periodically supply the H level regardless of the state of the transistor Tp4, so that the transistor Tp1, which is a pull-up transistor, can be continuously turned off. In addition, since the number of transistors connected to the power supply line 103 due to the addition of the transistor Tp8 does not increase, an increase in the load on the power supply line 103 can be suppressed. Also, the wiring 102 can be omitted.

[0117] The modified examples of the unit circuits 100E1 to 100E6 can be combined with the modified examples of the unit circuits 100B1 to 100B8, the unit circuits 100C1 to 100C3, and the unit circuits 100D1 to 100D8 described above. This configuration can reduce the load on the power line 103, reduce the parasitic capacitance of the node N2, and / or reduce the number of transistors.

[0118] In order to explain an example of the operation of the circuit diagrams shown in Figures 19(A) to 20(C), Figure 21 shows a timing chart of the unit circuit 100E3 shown in Figure 19(C). Figures 22(A) to 25(B) are circuit diagrams that typically show the operation at times t1 to t9 shown in Figure 21. In the explanation of Figures 21 and 22(A) to 25(B), the above explanations of the configurations that overlap with the explanations of Figures 7(B) and 8(A) to 11(B) may be omitted by citing the above explanations.

[0119] RE shown in Fig. 21 is a reset signal supplied to the wiring 107. Others, CK1, CK2, SP, N1, N2, N3, and OUT, are the same as those described in Fig. 7(B).

[0120] Fig. 22(A) is a diagram for explaining the operation during the period from time t1 to t2 shown in Fig. 21. CK1, CK2, SP, RE, VDD, and VSS turn on the transistors Tp1, Tp3 to Tp5, and turn off the transistors Tp2, Tp6, Tp7, Tp8, and the transistor Tn1. OUT becomes the H level potential of CK1. N1 and N2 become the L level of SP. N3 becomes VDD, that is, the H level.

[0121] FIG. 22B is a diagram for explaining the operation during the period from time t2 to t3 shown in FIG. 21. CK1, CK2, SP, RE, VDD, and VSS turn on the transistors Tp1, Tp3, and Tp5, and turn off the transistors Tp2, Tp4, Tp6, Tp7, Tp8, and the transistor Tn1. OUT becomes the H level potential of CK1. N1 and N2 become floating because the transistors Tp4, Tp6, Tp7, and Tp8 are turned off. Therefore, N1 and N2 hold the L level of SP. N3 remains at VDD, that is, the H level.

[0122] Fig. 23(A) is a diagram for explaining the operation during the period from time t3 to t4 shown in Fig. 21. CK1, CK2, SP, RE, VDD, and VSS turn on the transistors Tp1, Tp5, and Tp6, and turn off the transistors Tp2 to Tp4, Tp7, Tp8, and the transistor Tn1.

[0123] During the period from time t3 to t4, transistors Tp4, Tp7, and Tp8 are in the off state, so N1 and N2 are floating. Capacitor Cp maintains the potential difference between the electrodes at both ends, so the potential of N1 fluctuates as OUT changes. Specifically, as CK1 changes from H level to L level, the potential of N1 also drops. As the potential of N1 drops, transistor Tp3 turns off because its gate-source voltage (Vgs) becomes equal to or greater than the threshold voltage (Vth<0). N2 becomes VSS-Vth, which is smaller than VSS by the threshold voltage (Vth) of transistor Tp3, and N1 becomes at a potential lower than VSS-Vth. Transistor Tp3, which is a potential adjustment transistor, can make the potential of a signal of the same logic level, for example, L level, different between N1 and N2.

[0124] OUT can be lowered to VSS by making N1 have a potential smaller than VSS-Vth. N3 remains at VDD, that is, the H level.

[0125] In one embodiment of the present invention, in order to control the on state of the transistor Tn1 and the off state of the transistor Tp5, which are operated at the same logic level (L level), with different potentials, the gate of the transistor Tn1 is connected to a node N1 and the gate of the transistor Tp5 is connected to a node N2.

[0126] The potential of the node N1 is lower than the potential of the node N2. The potential of the node N1 can be set to an off-level signal for the transistor Tn1, which is an n-channel transistor, to more reliably turn it off. Since the potential of the node N1 is lower than VSS, this may cause deterioration and dielectric breakdown of the transistor. However, since the transistor Tn1 is an OS transistor, this deterioration and dielectric breakdown can be prevented.

[0127] Also, VSS-Vth of node N2 is higher than the potential of node N1. By using the potential of node N2 as an on-level signal for transistor Tp5, which is a p-channel transistor, the transistor can be turned on without inducing deterioration and dielectric breakdown. Since the potential of node N2 is lower than that of node N1, deterioration and / or dielectric breakdown of the other transistors Tp3, Tp4, and Tp8 connected to node N2 can be prevented.

[0128] FIG. 23B is a diagram for explaining the operation during the period from time t4 to t5 shown in FIG. 21. CK1, CK2, SP, RE, VDD, and VSS turn on the transistors Tp1, Tp3, and Tp5, and turn off the transistors Tp2, Tp4, Tp6, Tp7, Tp8, and the transistor Tn1. OUT becomes the H level potential of CK1. N1 and N2 become floating because the transistors Tp4, Tp6, Tp7, and Tp8 are turned off. Therefore, N1 and N2 hold the L level of SP. N3 remains at VDD, that is, the H level.

[0129] FIG. 24(A) is a diagram for explaining the operation during the period from time t5 to t6 shown in FIG. 21. CK1, CK2, SP, RE, VDD, and VSS turn on the transistors Tp2, Tp3, Tp7, Tp8, and the transistor Tn1, and turn off the transistors Tp1, Tp4, Tp5, and Tp6. OUT becomes VDD. N1 and N2 become H level because the transistor Tp8 is turned on. With this configuration, the H level is periodically supplied to N1 and N2, so the transistor Tp1, which is a pull-up transistor, can be continuously turned off. N3 becomes VSS, that is, L level.

[0130] FIG. 24(B) is a diagram for explaining the operation during the period from time t6 to t7 shown in FIG. 21. CK1, CK2, SP, RE, VDD, and VSS turn on the transistors Tp2, Tp3, Tp7, and the transistor Tn1, and turn off the transistors Tp1, Tp4, Tp5, Tp6, and Tp8. OUT remains at VDD. N1 and N2 become floating because the transistors Tp4, Tp6, and Tp8 are turned off. Therefore, N1 and N2 hold VDD, that is, H level. N3 remains at VSS, that is, L level.

[0131] FIG. 25(A) is a diagram for explaining the operation during the period from time t7 to t8 shown in FIG. 21. CK1, CK2, SP, RE, VDD, and VSS turn on the transistors Tp2, Tp3, Tp6, Tp7, and the transistor Tn1, and turn off the transistors Tp1, Tp4, Tp5, and Tp8. OUT remains at VDD. N1 and N2 are at H level because the transistors Tp6 and Tp7 are on. With this configuration, N1 and N2 are periodically supplied with H level, so the transistor Tp1, which is a pull-up transistor, can be continuously turned off. N3 remains at VSS, that is, L level.

[0132] FIG. 25(B) is a diagram for explaining the operation during the period from time t8 to t9 shown in FIG. 21. CK1, CK2, SP, RE, VDD, and VSS turn on the transistors Tp2, Tp3, Tp7, and the transistor Tn1, and turn off the transistors Tp1, Tp4, Tp5, Tp6, and Tp8. OUT remains at the potential of VDD on the power line 103. N1 and N2 are floating because the transistors Tp4, Tp6, and Tp8 are turned off. Therefore, VDD, that is, H level, is maintained at N1 and N2. N3 remains at VSS, that is, L level.

[0133] <Fifth Modification of Unit Circuit 100A> In the unit circuit 100A, the node N1 to which the transistor Tp3 is connected can have the configuration shown in Fig. 26. The unit circuit 100F shown in Fig. 26 is configured to include transistors Tp3_A and Tp3_B as transistors that function as the transistor Tp3. The transistors Tp3_A and Tp3_B are p-channel transistors like the transistors Tp1 to Tp7.

[0134] 26, a potential adjusting transistor can be provided between the node N1 and the transistor Tp6. The potential of the node N1 is lower than VSS, which may cause deterioration and dielectric breakdown of the transistor, but the provision of the transistor Tp3_B makes the potential of the node between the transistors Tp6 and Tp3_B approximately the same as the potential of the node N2. As a result, the deterioration and / or dielectric breakdown of the transistor Tp6 can be prevented.

[0135] Furthermore, by providing the transistor Tp3_A, the VSS-Vth of the node N2 can be made higher than the potential of the node N1. By making the potential of the node N2 an on-level signal of the transistor Tp5, which is a p-channel transistor, the transistor can be turned on without inducing deterioration and dielectric breakdown. The potential of the node N2 is lower than that of the node N1, and deterioration and / or dielectric breakdown of the other transistors Tp4 and Tp5 connected to the node N2 can be prevented.

[0136] The modified example of the unit circuit 100F can be combined with the modified examples of the unit circuits 100B1 to 100B8, the unit circuits 100C1 to 100C3, the unit circuits 100D1 to 100D8, and the unit circuits 100E1 to 100E6 described above. This configuration can reduce the load on the power line 103, reduce the parasitic capacitance of the node N2, and / or reduce the number of transistors.

[0137] <Modification 6 of the unit circuit 100A> In the unit circuit 100A, a plurality of output signals OUT can be provided. The unit circuit 100G shown in FIG. 27A has wirings 106P and 106N for outputting output signals. The wiring 106P outputs an output signal OUTP corresponding to the output signal OUT output by the unit circuit 100A. The wiring 106N outputs an output signal OUTN in response to a change in the potential of the node N3. FIG. 27B shows a circuit diagram of a shift register 350 including the unit circuit 100G shown in FIG. 27A. The unit circuits 100G_1 to 100G_m provided in each row can be the unit circuit 100G shown in FIG. 27A.

[0138] As shown in FIG. 27B, the output signal OUTP is suitable as a selection signal for turning on a p-channel transistor. The output signal OUTN is suitable as a selection signal for turning on an n-channel transistor. Therefore, the configuration of the unit circuit 100G can be suitably used in a pixel circuit having an LTPO configuration.

[0139] The modified example of the unit circuit 100G can be combined with the modified examples of the unit circuits 100B1 to 100B8, the unit circuits 100C1 to 100C3, the unit circuits 100D1 to 100D8, the unit circuits 100E1 to 100E6, and the unit circuit 100F. This configuration can reduce the load on the power line 103, reduce the parasitic capacitance of the node N2, and / or reduce the number of transistors.

[0140] In the unit circuit 100, the unit circuit 100A, the unit circuits 100B1 to 100B8, 100C1 to 100C3, the unit circuits 100D1 to 100D8, the unit circuits 100E1 to 100E6, the unit circuit 100F, and the unit circuit 100G, as well as a unit circuit formed by combining these, the gate of the transistor Tn1 may be connected to the node N2. By connecting the gate of the transistor Tn1 to the node N2, deterioration and / or dielectric breakdown of the transistor Tn1 can be prevented. This makes it easier to use an LTPS transistor as the transistor Tn1. Of course, even if the gate of the transistor Tn1 is connected to the node N2, it is also possible to adopt an OS transistor as the transistor Tn1.

[0141] In the unit circuit described in this embodiment, the load driven by the transistor Tp1 is larger than the loads driven by the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, the W (channel width) / L (channel length) of the transistor Tp1 is preferably larger than the W / L of the transistor Tp3. The W / L of the transistor Tp1 is preferably larger than the W / L of the transistor Tp4. The W / L of the transistor Tp1 is preferably larger than the W / L of the transistor Tp5. The W / L of the transistor Tp1 is preferably larger than the W / L of the transistor Tp6. The W / L of the transistor Tp1 is preferably larger than the W / L of the transistor Tp7. The W / L of the transistor Tp1 is preferably larger than the W / L of the transistor Tp8. In addition, the load driven by the transistor Tp1 is larger than the sum of the loads driven by the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, it is preferable that the W / L of the transistor Tp1 is greater than the sum of the W / L of the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. It goes without saying that it is preferable that the W / L of the transistor Tp1 is greater than the sum of the W / L of at least two of the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. For example, it is preferable that the W / L of the transistor Tp1 is greater than the sum of the W / L of the transistors Tp3, Tp4, Tp5, Tp6, and Tp7, and is greater than the sum of the W / L of the transistors Tp3, Tp4, and Tp5.

[0142] In the unit circuit described in this embodiment, the load driven by the transistor Tp2 is larger than the loads driven by the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, the W (channel width) / L (channel length) of the transistor Tp2 is preferably larger than the W / L of the transistor Tp3. The W / L of the transistor Tp2 is preferably larger than the W / L of the transistor Tp4. The W / L of the transistor Tp2 is preferably larger than the W / L of the transistor Tp5. The W / L of the transistor Tp2 is preferably larger than the W / L of the transistor Tp6. The W / L of the transistor Tp2 is preferably larger than the W / L of the transistor Tp7. The W / L of the transistor Tp2 is preferably larger than the W / L of the transistor Tp8. In addition, the load driven by the transistor Tp2 is larger than the sum of the loads driven by the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, it is preferable that the W / L of the transistor Tp2 is greater than the sum of the W / L of the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. It goes without saying that it is preferable that the W / L of the transistor Tp2 is greater than the sum of the W / L of at least two of the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. For example, it is preferable that the W / L of the transistor Tp2 is greater than the sum of the W / L of the transistors Tp3, Tp4, Tp5, Tp6, and Tp7, and is greater than the sum of the W / L of the transistors Tp3, Tp4, and Tp5.

[0143] In the unit circuit described in this embodiment, the transistor Tp1 changes the potential of OUT, whereas the transistor Tp2 maintains the potential of OUT. The load of the transistor Tp1 is very large. Therefore, it is preferable that the W / L of the transistor Tp1 is larger than the W / L of the transistor Tp2. In addition, the load driven by the transistor Tp1 is larger than the sum of the loads driven by the transistors Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, it is preferable that the W / L of the transistor Tp1 is larger than the sum of the W / L of the transistors Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. It goes without saying that it is preferable that the W / L of the transistor Tp1 is larger than the sum of at least two W / Ls of the transistors Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8.

[0144] In the unit circuit described in the present embodiment, when an OS transistor is used as the transistor Tn1 and LTPS transistors are used as the transistors Tp1, Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8, the mobility of the transistor Tn1 is smaller than the mobility of the transistors Tp1, Tp2, Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, the W / L of the transistor Tn1 is preferably larger than the W / L of the transistor Tp1. The W / L of the transistor Tn1 is preferably larger than the W / L of the transistor Tp2. The W / L of the transistor Tn1 is preferably larger than the W / L of the transistor Tp3. The W / L of the transistor Tn1 is preferably larger than the W / L of the transistor Tp4. The W / L of the transistor Tn1 is preferably larger than the W / L of the transistor Tp5. The W / L of the transistor Tn1 is preferably larger than the W / L of the transistor Tp6. The W / L of the transistor Tn1 is preferably larger than the W / L of the transistor Tp7. The W / L of the transistor Tn1 is preferably larger than the W / L of the transistor Tp8. However, since the transistor Tp1 charges and discharges a large load, the W / L of the transistor Tp1 may be larger than that of the transistor Tn1.

[0145] The signal from the SP is transmitted to the gate of the transistor Tp1 via the transistors Tp4 and Tp3. Therefore, by increasing the driving capabilities of the transistors Tp4 and Tp3, the operating speed can be improved. Therefore, the W / L of the transistor Tp3 is preferably larger than the W / L of the transistor Tp5. The W / L of the transistor Tp3 is preferably larger than the W / L of the transistor Tp6. The W / L of the transistor Tp3 is preferably larger than the W / L of the transistor Tp7. The W / L of the transistor Tp3 is preferably larger than the W / L of the transistor Tp8. The W / L of the transistor Tp4 is preferably larger than the W / L of the transistor Tp5. The W / L of the transistor Tp4 is preferably larger than the W / L of the transistor Tp6. The W / L of the transistor Tp4 is preferably larger than the W / L of the transistor Tp7. The W / L of the transistor Tp4 is preferably larger than the W / L of the transistor Tp8.

[0146] This embodiment mode can be combined with other embodiment modes as appropriate.

[0147] (Embodiment 2) In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS.

[0148] <Perspective and cross-sectional views of a display device> Fig. 28 shows a perspective view of the display device 300A, and Fig. 29(A) shows a cross-sectional view of the display device 300A. Fig. 29(B) and Fig. 29(C) are diagrams illustrating examples of the configuration of transistors in the cross-sectional view of Fig. 29(A).

[0149] The display device 300A has a configuration in which a substrate 352 and a substrate 351 are bonded together. In Fig. 28, the substrate 352 is indicated by a dashed line.

[0150] The display device 300A has a display unit 362, a connection unit 340, a gate line driving circuit 364, wiring 365, etc. Fig. 28 shows an example in which an IC 373 and an FPC 372 are mounted on the display device 300A. Therefore, the configuration shown in Fig. 28 can also be said to be a display module having the display device 300A, an IC (integrated circuit), and an FPC.

[0151] The connection unit 340 is provided on the outside of the display unit 362. The connection unit 340 can be provided along one side or multiple sides of the display unit 362. The connection unit 340 may be single or multiple. FIG. 28 shows an example in which the connection unit 340 is provided so as to surround the four sides of the display unit. The connection unit 340 connects the common electrode of the light-emitting device to the conductive layer, thereby making it possible to supply a potential to the common electrode.

[0152] The gate line driving circuit 364 may be, for example, the gate line driving circuit 364 having the unit circuit 100 or the unit circuit 100A described in the first embodiment.

[0153] The wiring 365 has a function of supplying signals and power to the display portion 362 and the gate line driver circuit 364. The signals and power are input to the wiring 365 from the outside via the FPC 372 or from the IC 373.

[0154] 28 shows an example in which an IC 373 is provided on a substrate 351 by a chip on glass (COG) method or a chip on film (COF) method. For example, an IC having a signal line driver circuit can be used as the IC 373. The display device 300A and the display module may be configured without an IC. The IC may be mounted on an FPC by a COF method or the like.

[0155] Figure 29(A) shows an example of a cross section of a portion of the region including the FPC 372 of the display device 300A, a portion of the gate line driving circuit 364, a portion of the display unit 362, a portion of the connection portion 340, and a portion of the region including the end portion.

[0156] A display device 300A shown in FIG. 29A includes a layer 301 having a transistor 201 and a transistor 202 between a substrate 351 and a substrate 352, a light-emitting device 330, and the like.

[0157] The light-emitting device 330 has a conductive layer 311, a conductive layer 312 on the conductive layer 311, and a conductive layer 326 on the conductive layer 312. The conductive layer 311, the conductive layer 312, and the conductive layer 326 may all be called pixel electrodes, or some of them may be called pixel electrodes. The light-emitting device 330 may use a self-luminous light-emitting device such as an LED (Light Emitting Diode), an organic EL (Electro Luminescence) element (also called an OLED (Organic LED)), an inorganic EL element, or a semiconductor laser. Examples of the LED include a mini LED and a micro LED. In the following description, a case where an organic EL element is applied will be described.

[0158] The conductive layer 311 is connected to the transistor 202 provided in the display portion 362 through an opening provided in the insulating layer 324. For example, a conductive layer functioning as a reflective electrode can be used for the conductive layer 311 and the conductive layer 312. For example, a conductive layer functioning as a transparent electrode can be used for the conductive layer 326.

[0159] A recess is formed in the conductive layer 311 so as to cover an opening provided in the insulating layer 324. A layer 328 is embedded in the recess. The layer 328 has a function of planarizing the recess of the conductive layer 311. A conductive layer 312 is provided over the conductive layer 311 and the layer 328. A region overlapping with the recess of the conductive layer 311 can also be used as a light-emitting region, and the aperture ratio of the pixel can be increased.

[0160] The layer 328 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for the layer 328. In particular, the layer 328 is preferably formed using an insulating material.

[0161] An insulating layer containing an organic material can be suitably used for the layer 328. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, precursors of these resins, or the like can be applied for the layer 328. Also, a photosensitive resin can be used for the layer 328. The photosensitive resin can be a positive type material or a negative type material.

[0162] By using a photosensitive resin, the layer 328 can be formed only by the steps of exposure and development, and the influence of dry etching, wet etching, or the like on the surface of the conductive layer 311 can be reduced. In addition, by forming the layer 328 using a negative photosensitive resin, the layer 328 can be formed using the same photomask (exposure mask) as that used for forming the openings in the insulating layer 324 in some cases.

[0163] The upper and side surfaces of the conductive layer 312 and the conductive layer 326 are covered with the layer 313. Therefore, the entire area where the conductive layer 312 is provided can be used as the light-emitting area of ​​the light-emitting device 330, thereby increasing the aperture ratio of the pixel.

[0164] The side surfaces of the layer 313 are covered by an insulating layer 325 and an insulating layer 327, respectively. A sacrificial layer 318 is located between the layer 313 and the insulating layer 325. A layer 314 is provided on the layer 313, the insulating layer 325, and the insulating layer 327. A common electrode 315 is provided on the layer 314. The layer 314 and the common electrode 315 are each a continuous film provided in common to a plurality of light-emitting devices 330. In addition, a protective layer 331 is provided on the light-emitting devices 330.

[0165] The protective layer 331 and the substrate 352 are bonded via an adhesive layer 342. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting device 330. In FIG. 29(A), the space between the substrates 352 and 351 is filled with the adhesive layer 342, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 342 may be provided so as not to overlap with the light-emitting device. Also, the space may be filled with a resin different from the adhesive layer 342 provided in a frame shape.

[0166] In the connection portion 340, a conductive layer 323 is provided on an insulating layer 324. The conductive layer 323 is an example of a laminated structure of a conductive film obtained by processing the same conductive film as the conductive layer 311, a conductive film obtained by processing the same conductive film as the conductive layer 312, and a conductive film obtained by processing the same conductive film as the conductive layer 326. The end of the conductive layer 323 is covered with a sacrificial layer 318, an insulating layer 325, and an insulating layer 327. In addition, a layer 314 is provided on the conductive layer 323, and a common electrode 315 is provided on the layer 314. The conductive layer 323 and the common electrode 315 are connected via the layer 314. Note that the layer 314 may not be formed in the connection portion 340. In this case, the conductive layer 323 and the common electrode 315 are directly connected to each other.

[0167] The display device 300A is, for example, a top emission type. Light L emitted by the light emitting device is emitted to the substrate 352 side. The substrate 352 is preferably made of a material that is highly transparent to visible light. The pixel electrode includes a material that reflects visible light, and the counter electrode (common electrode 315) includes a material that transmits visible light. The display device may be a bottom emission type.

[0168] The insulating layer 220 is provided to cover the transistor. The insulating layer 324 is provided to cover the transistor and functions as a planarization layer. Note that the number of insulating layers covering the transistor is not limited, and each insulating layer may be a single layer or two or more layers.

[0169] At least one of the insulating layers covering the transistors is preferably made of a material that is difficult for impurities such as water and hydrogen to diffuse into. This allows the insulating layer to function as a barrier layer. With this configuration, it is possible to effectively prevent impurities from diffusing into the transistors from the outside, thereby improving the reliability of the display device.

[0170] For example, the insulating layer 220 may be a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, etc. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, a neodymium oxide film, etc. Alternatively, two or more of the above insulating films may be stacked.

[0171] An organic insulating film can be suitably used for the insulating layer 324 functioning as a planarizing layer. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.

[0172] A connection portion 204 is provided in a region of the substrate 351 where the substrate 352 does not overlap. In the connection portion 204, the wiring 365 is connected to the FPC 372 via a conductive layer 366 and a connection layer 203. The conductive layer 366 is an example of a laminated structure of a conductive film obtained by processing the same conductive film as the conductive layer 311, a conductive film obtained by processing the same conductive film as the conductive layer 312, and a conductive film obtained by processing the same conductive film as the conductive layer 326. On the upper surface of the connection portion 204, the conductive layer 366 is exposed. This allows the connection portion 204 and the FPC 372 to be connected via the connection layer 203.

[0173] It is preferable to provide a light-shielding layer 317 on the surface of the substrate 352 facing the substrate 351. The light-shielding layer 317 can be provided between adjacent light-emitting devices 330, on the connection section 340, on the gate line driving circuit 364, and the like. In addition, various optical members can be arranged on the outside of the substrate 352. Examples of the optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, an antistatic film that suppresses adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches due to use, an impact absorbing layer, and the like may be arranged on the outside of the substrate 352.

[0174] By providing the protective layer 331 covering the light emitting device 330, it is possible to prevent impurities such as water from entering the light emitting device 330, thereby improving the reliability of the light emitting device.

[0175] The substrate 351 and the substrate 352 may each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting device is extracted. When a flexible material is used for the substrate 351 and the substrate 352, the flexibility of the display device can be increased. A polarizing plate may be used for the substrate 351 or the substrate 352.

[0176] Substrate 351 and substrate 352 can each be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. One or both of substrates 351 and 352 may be made of glass having a thickness sufficient to provide flexibility.

[0177] When a circularly polarizing plate is laminated on a display device, it is preferable that the display device has a substrate having high optical isotropy. A substrate having high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small).

[0178] The adhesive layer 342 may be made of various curing adhesives, such as a photo-curing adhesive such as an ultraviolet curing adhesive, a reaction curing adhesive, a heat curing adhesive, or an anaerobic adhesive. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, a material with low moisture permeability, such as epoxy resin, is preferable. A two-part mixed resin may also be used. An adhesive sheet or the like may also be used.

[0179] The connection layer 203 may be made of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0180] A layer 301 including a transistor is provided between the substrate 351 and the insulating layer 220. The layer 301 includes a transistor 201 and a transistor 202. The transistor 201 is, for example, the OS transistor described in the above embodiment 1. The transistor 202 is the LTPS transistor described in the above embodiment 1. The transistors 201 and 202 are formed over a substrate 351. The transistors 201 and 202 can be manufactured using the same material and in the same process.

[0181] 29B is an enlarged view of a cross section including the transistor 201. FIG. 29C is an enlarged view of a cross section including the transistor 202. As described in Embodiment 1, in one embodiment of the present invention, an OS transistor which is an n-channel transistor and an LTPS transistor which is a p-channel transistor are used as transistors included in the gate line driver circuit 364. The transistor 201 illustrated in FIG. 29B can be an n-channel transistor, and the transistor 202 illustrated in FIG. 29C can be a p-channel transistor.

[0182] The transistor 201 includes an insulating layer 211, a conductive layer 212A, an insulating layer 213, an insulating layer 214, a semiconductor layer 215, an insulating layer 216, a conductive layer 217, an insulating layer 218, and conductive layers 219a and 219b stacked in this order on a substrate 351. The insulating layer 213, the insulating layer 214, and a part of the insulating layer 218 function as a gate insulating layer of the transistor 201. The conductive layer 212A functions as a bottom gate electrode of the transistor 201. The conductive layer 217 functions as a top gate electrode of the transistor 201. The conductive layers 219a and 219b function as source electrodes or drain electrodes.

[0183] The semiconductor layer 215 includes a metal oxide such as In-Ga-Zn oxide. The conductive layer 219a and the conductive layer 219b are connected to a low-resistance region 215n of the semiconductor layer 215 through openings provided in the insulating layer 216 and the insulating layer 218, respectively. The low-resistance region 215n can also be referred to as a region having a lower resistance than the channel formation region of the transistor 201, a region having a higher carrier concentration, a region having a higher oxygen vacancy density, a region having a higher impurity concentration, or an n-type region. For example, the low-resistance region 215n is a region including an impurity element. Examples of the impurity element include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. The low-resistance region 215n preferably includes boron or phosphorus. The low-resistance region 215n may include two or more of the above elements.

[0184] The transistor 202 includes a semiconductor layer 210, an insulating layer 211, a conductive layer 212B, an insulating layer 213, an insulating layer 214, an insulating layer 216, an insulating layer 218, and conductive layers 219c and 219d stacked in this order over a substrate 351. A part of the insulating layer 211 functions as a gate insulating layer of the transistor 202. The conductive layer 212B functions as a top gate electrode of the transistor 202. The conductive layers 219c and 219d function as source and drain electrodes.

[0185] The semiconductor layer 210 includes silicon such as low-temperature polysilicon. The conductive layer 219c and the conductive layer 219d are connected to the low-resistance region 210p of the semiconductor layer 210 through openings provided in the insulating layer 211, the insulating layer 213, the insulating layer 214, the insulating layer 216, and the insulating layer 218, respectively. The low-resistance region 210p can be referred to as a region having a lower resistance than the channel formation region of the transistor 202, a region having a higher impurity concentration, or a region of p-type. For example, the low-resistance region 210p is a region containing an impurity element for forming a p-channel type transistor. When forming a p-channel type transistor, boron and / or aluminum may be added to the low-resistance region 210p. In addition, the above-mentioned impurities may be added to the channel formation region of the transistor 202 in order to control the threshold voltage of the transistor 202.

[0186] Components other than the semiconductor layers of the transistor 201 and the transistor 202 can be formed in the same process, which can prevent an increase in the number of processes even when two types of transistors are mixed.

[0187] Materials that can be used for the gate electrode, source electrode, and drain electrode of a transistor, as well as conductive layers such as various wirings and electrodes that constitute a display device, include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, as well as alloys containing such metals as main components, etc. Films containing these materials can be used as a single layer or a laminated structure.

[0188] As the conductive material having light transmitting properties, conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, zinc oxide containing gallium, or graphene can be used. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing the metal materials can be used. Alternatively, nitrides of the metal materials (for example, titanium nitride) or the like may be used. Note that the metal materials or alloy materials (or their nitrides) are used in a thin film thickness that is thin enough to have light transmitting properties. Also, a laminated film of the above materials can be used as the conductive layer. For example, the use of a laminated film of an alloy of silver and magnesium and indium tin oxide can increase the conductivity. These can also be used for conductive layers such as various wirings and electrodes constituting a display device, and conductive layers (conductive layers functioning as pixel electrodes or common electrodes) of a light emitting device.

[0189] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0190] In addition, the conductive layer 217 functioning as a top gate electrode in FIG. 29(B) may be omitted. For example, FIG. 30(A) shows a schematic cross-sectional view of a display device 300A_1 including a transistor 201A in which the conductive layer 217 functioning as a top gate electrode is omitted. FIG. 30(B) shows an enlarged cross-sectional view including the transistor 201A shown in FIG. 30(A). Note that detailed description of the display device 300A_1 and the transistor 201A will be omitted because they have many parts in common with the display device 300A and the transistor 201 described in FIG. 29(A) and FIG. 29(B).

[0191] 31 is a plan view of a case where the transistor 201A and the transistor 202 shown in FIG. 29(C) and FIG. 30(A) and (B) are applied to a unit circuit included in a gate line driving circuit 364, such as the unit circuit 100G described in Embodiment 1. FIG. 31 is an example of a plan view of the unit circuit 100G, and is not limited to this.

[0192] 31 illustrates a unit circuit 100G that outputs to a gate line on the kth row (k is an integer greater than or equal to 1 and less than or equal to m). In the unit circuit 100G, the transistor Tn1, which is an n-channel OS transistor, can be provided with reference to the transistor 201A illustrated in FIG. 30B, and the transistors Tp1 to Tp7, which are p-channel LTPS transistors, can be provided with reference to the transistor 202 illustrated in FIG. 29C.

[0193] FIG. 31 illustrates, as examples, a power supply line 103 that transmits VDD, a power supply line 104 that transmits VSS, a wiring 101 that transmits a clock signal CK1, a wiring 102 that transmits a clock signal CK2, a wiring 106P that transmits an output signal OUTP, a wiring 106N that transmits an output signal OUTN, a wiring 105_k-1 that transmits a signal equivalent to an output signal OUTP_k-1 of the previous stage, and a wiring 105_k that transmits a signal equivalent to an output signal OUTP_k to the next stage.

[0194] 31 illustrates, as an example, a conductive layer 401, a conductive layer 402, a semiconductor layer 403, a semiconductor layer 404, a contact hole 405, and a contact hole 406 for forming wiring, a transistor, and a capacitor. The conductive layer 401 is provided in the same layer as the conductive layers 212A and 212B described in FIG. 29(C) and FIG. 30(B). The conductive layer 402 is provided in the same layer as the conductive layers 219a to 219d described in FIG. 29(C) and FIG. 30(B). The semiconductor layer 403 is provided in the same layer as the semiconductor layer 215 described in FIG. 30(B). The semiconductor layer 404 is provided in the same layer as the semiconductor layer 210 described in FIG. 29(C). The contact hole 405 is an opening for connecting the conductive layer 401 and the conductive layer 402. The contact hole 406 is an opening for connecting the conductive layer 402 and the semiconductor layer 215 (or the semiconductor layer 210).

[0195] 31, a transistor 201A in which the conductive layer 217 functioning as a top gate electrode is omitted is applied to the transistor Tn1. This can eliminate the step of providing the conductive layer 217, which is expected to improve yield.

[0196] In Fig. 31, the capacitor Cp can be formed by overlapping the conductive layer 401 and the conductive layer 402 with an insulating layer interposed therebetween. In a region other than where the capacitor Cp is provided, the overlapping of the conductive layer 401 and the conductive layer 402 may increase the intersection capacitance of the wiring. For this reason, it is preferable to reduce the intersection capacitance of the wiring by providing a notch in the conductive layer. With this configuration, it is possible to reduce noise in the transmitted signal, and to reduce signal delay or waveform rounding.

[0197] 31, it is preferable to arrange the power supply lines 103 and 104 transmitting VDD and VSS on the outer side (away from the transistors Tn1, Tp1 to Tp8) of the wirings 101 and 102 transmitting the clock signals CK1 and CK2. This configuration can reduce the cross capacitance between the wirings 101 and 102 transmitting the clock signals CK1 and CK2 and the power supply lines 103 and 104 transmitting VDD and VSS. Therefore, this configuration can reduce noise in the transmitted signals, signal delays, and waveform rounding.

[0198] 31, the transistors Tp1 and Tp2 preferably have a larger overlapping area between the conductive layer 401 and the semiconductor layer 215 (or the semiconductor layer 210) than the transistors Tn1 and Tp3 to Tp7. This structure can increase the channel width of the transistor and the amount of current flowing through the transistor. This allows high-speed charging and discharging of the wiring that transmits the output signal OUTP, which has a large load.

[0199] As described in the first embodiment, in the unit circuit, the load driven by the transistors Tp1 and Tp2 is larger than the load driven by the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. Therefore, as shown in Fig. 31, it is preferable that the W (channel width) / L (channel length) of the transistors Tp1 and Tp2 is larger than that of the transistors Tp3, Tp4, Tp5, Tp6, Tp7, and Tp8. W (channel width) / L (channel length) can be calculated from the area of ​​the region where the semiconductor layer 404 and the conductive layer 401 overlap, as shown in Fig. 31.

[0200] Note that the conductive layer 212A functioning as a bottom gate electrode in FIG. 29B may be omitted. For example, FIG. 32A shows a schematic cross-sectional view of a display device 300A_2 including a transistor 201B in which the conductive layer 212A functioning as a bottom gate electrode is omitted. FIG. 32B shows an enlarged cross-sectional view including the transistor 201B shown in FIG. 32A. Note that detailed description of the display device 300A_2 and the transistor 201B will be omitted because they have many common parts with the display device 300A and the transistor 201 described in FIG. 29A and FIG. 29B.

[0201] FIG. 33 is a plan view of a case where the transistor 201B and the transistor 202 shown in FIG. 29(C) and FIG. 32(A) and (B) are applied to a unit circuit included in the gate line driving circuit 364, for example, the unit circuit 100G described in the first embodiment. The unit circuit 100G in FIG. 33 is an example of a plan view, and is not limited to this. In the description of the plan view shown in FIG. 33, repeated description of the configuration common to the plan view shown in FIG. 32 will be omitted. Detailed description of the display device 300A_2 and the transistor 201B will be omitted because there are many parts common to the display device 300A and the transistor 201 described in FIG. 29(A) and FIG. 29(B).

[0202] Fig. 33 illustrates a unit circuit 100G_2 that outputs to a gate line in the kth row. In the unit circuit 100G_2, the transistor Tn1, which is an n-channel OS transistor, can be provided with reference to the transistor 201B illustrated in Fig. 32B, and the transistors Tp1 to Tp7, which are p-channel LTPS transistors, can be provided with reference to the transistor 202 illustrated in Fig. 29C.

[0203] 33 illustrates, as an example, a conductive layer 401, a conductive layer 402, a semiconductor layer 403, a semiconductor layer 404, a contact hole 405, a contact hole 406, a conductive layer 407, and a contact hole 408 for forming wiring, a transistor, and a capacitor. The conductive layer 401 is provided in the same layer as the conductive layer 212B described in FIG. 29(C). The conductive layer 402 is provided in the same layer as the conductive layers 219a to 219d described in FIG. 29(C) and FIG. 32(B). The semiconductor layer 403 is provided in the same layer as the semiconductor layer 215 described in FIG. 32(B). The semiconductor layer 404 is provided in the same layer as the semiconductor layer 210 described in FIG. 29(C). The contact hole 405 is an opening for connecting the conductive layer 401 and the conductive layer 402. The contact hole 406 is an opening for connecting the conductive layer 402 to the semiconductor layer 215 (or the semiconductor layer 210). The conductive layer 407 is provided in the same layer as the conductive layer 217 described in FIG. 32(B). The contact hole 408 is an opening for connecting the conductive layer 402 to the conductive layer 407.

[0204] In the plan view of the unit circuit 100G_A shown in FIG. 33, the transistor 201B, which does not include the conductive layer 212A functioning as a bottom gate electrode, is applied to the transistor Tn1. Therefore, the conductive layer 407 can be used to connect wirings and provide an element such as a capacitor. For example, the capacitor Cp shown in FIG. 33 is provided with the conductive layer 402 and the conductive layer 407 sandwiching an insulating layer (corresponding to the insulating layer 216 shown in FIG. 32(B)). The insulating layer of the capacitor Cp is an insulating layer corresponding to the gate insulating film of the transistor 201B. Therefore, a configuration can be adopted in which the capacitor is provided using an insulating layer with a thin film thickness. As a result, it is possible to reduce the area occupied by the capacitor Cp, reduce noise in a transmitted signal, and reduce signal delay or waveform rounding.

[0205] As described in the first embodiment, in the unit circuit, the load driven by the transistor Tp1 is larger than the load driven by the transistor Tp2. Therefore, it is preferable that the W / L of the transistor Tp1 is larger than the W / L of the transistor Tp2. For example, as shown in the plan view of the unit circuit 100G_B in FIG. 34, it is preferable that the W (channel width) / L (channel length) of the transistor Tp1 is larger than that of the transistor Tp2. The W (channel width) / L (channel length) can be calculated from the area of ​​the region where the semiconductor layer 404 and the conductive layer 401 overlap as shown in FIG. 34.

[0206] As described in the first embodiment, in the unit circuit, the mobility of the transistor Tn1 is smaller than that of the transistors Tp1 to Tp7. Therefore, it is preferable that the W / L of the transistor Tn1 is larger than that of the transistors Tp1 to Tp7. For example, as shown in the plan view of the unit circuit 100G_C in FIG. 35, it is preferable that the W (channel width) / L (channel length) of the transistor Tn1 is larger than that of the transistors Tp3 to Tp7. The W (channel width) / L (channel length) can be calculated from the area of ​​the region where the semiconductor layer 403 and the conductive layer 401 overlap as shown in FIG. 35.

[0207] As described in the first embodiment, in the unit circuit, the SP supplied to the wiring 105_k-1 is transmitted to the gate of the transistor Tp1 through the transistors Tp3 and Tp4. Therefore, the operation speed can be improved by increasing the driving capabilities of the transistors Tp3 and Tp4. Therefore, it is preferable that the W / L of the transistors Tp3 and Tp4 is larger than the W / L of the transistors Tp5 to Tp7. For example, as shown in the plan view of the unit circuit 100G_D in FIG. 36, it is preferable that the W (channel width) / L (channel length) of the transistors Tp3 and Tp4 is larger than that of the transistors Tp5 to Tp7. The W (channel width) / L (channel length) can be calculated from the area of ​​the region where the semiconductor layer 404 and the conductive layer 401 overlap as shown in FIG. 36.

[0208] Note that although Figures 29(A), 30(A), and 32(A) illustrate configurations in which transistors 201 and 202 are provided in the gate line driver circuit 364 and the display portion 362, respectively, the transistor provided in the display portion 362 may be only transistor 201 or only transistor 202, that is, transistors having the same structure may be used as the transistors included in the display portion 362.

[0209] For example, it is preferable to use LTPS transistors such as the transistor 202 for all the transistors included in the pixel circuit of the display unit 362 that drives the light-emitting device. As silicon used for the semiconductor layer of the LTPS transistor, in addition to low-temperature polysilicon, single crystal silicon, polycrystalline silicon, amorphous silicon, and the like can be used. The LTPS transistor is particularly preferable because it has high field-effect mobility and good frequency characteristics.

[0210] Note that it is preferable to use an OS transistor such as the transistor 201 as at least one of the transistors included in a pixel circuit of the display unit 362 that drives the light-emitting device. The OS transistor has an extremely high field-effect mobility compared to a transistor using amorphous silicon. In addition, the OS transistor has an extremely small off-state current and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of the display device.

[0211] A display device with low power consumption and high driving capability can be realized by using LTPS transistors for some of the transistors included in a pixel circuit and OS transistors for the other parts. As a more preferable example, it is preferable to use OS transistors as transistors that function as switches for controlling conduction / non-conduction between wirings and to use LTPS transistors as transistors for controlling current.

[0212] For example, one of the transistors provided in the pixel circuit functions as a transistor for controlling the current flowing through the light-emitting device, and can be called a drive transistor. One of the source and drain of the drive transistor is connected to the pixel electrode of the light-emitting device. It is preferable to use an LTPS transistor as the drive transistor. This makes it possible to increase the current flowing through the light-emitting device in the pixel circuit.

[0213] On the other hand, the other transistor provided in the pixel circuit functions as a switch for controlling the selection and non-selection of the pixel, and can also be called a selection transistor. The gate of the selection transistor is connected to a gate line, and one of the source and drain is connected to a source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of the pixel even if the frame frequency is significantly reduced (for example, 1 fps or less), so that power consumption can be reduced by stopping the driver when displaying a still image.

[0214] <Block diagram of display device> 37A shows a block diagram of a display device 300A. The display device 300A includes a display portion 362, a gate line driver circuit 364, an IC 373, and the like.

[0215] The display unit 362 has a plurality of pixels 363 arranged in a matrix. The pixels 363 have sub-pixels 370R, 370G, and 370B. The sub-pixels 370R, 370G, and 370B each have a light-emitting device that functions as a display device.

[0216] The pixel 363 is connected to a wiring GL, a wiring SLR, a wiring SLG, and a wiring SLB. The wiring SLR, the wiring SLG, and the wiring SLB are each connected to an IC 373. The wiring GL is connected to a gate line driving circuit 364. The wiring GL is a wiring to which the output signal OUT described in the first embodiment is output. The IC 373 functions as a source line driving circuit (also referred to as a source driver), and the gate line driving circuit 364 functions as a gate line driving circuit (also referred to as a gate driver). The wiring GL functions as a gate line, and the wiring SLR, the wiring SLG, and the wiring SLB each function as a source line.

[0217] Subpixel 370R has a light-emitting device that emits red light. Subpixel 370G has a light-emitting device that emits green light. Subpixel 370B has a light-emitting device that emits blue light. This allows display device 300A to perform full-color display. Note that pixel 363 may have subpixels that have light-emitting devices that emit other colors of light. For example, pixel 363 may have a subpixel that has a light-emitting device that emits white light, or a subpixel that has a light-emitting device that emits yellow light, in addition to the above three subpixels.

[0218] The wiring GL is connected to the sub-pixels 370R, 370G, and 370B arranged in the row direction (extension direction of the wiring GL). The wiring SLR, wiring SLG, and wiring SLB are connected to the sub-pixels 370R, 370G, and 370B (not shown) arranged in the column direction (extension direction of the wiring SLR, etc.), respectively.

[0219] Fig. 37(B) shows an example of a circuit diagram of a pixel 370 that can be applied to the subpixels 370R, 370G, and 370B. The pixel 370 has a transistor M1, a transistor M2, a transistor M3, a capacitor C1, and a light-emitting device EL. A wiring GL and a wiring SL are connected to the pixel 370. The wiring SL corresponds to any one of the wiring SLR, the wiring SLG, and the wiring SLB shown in Fig. 37(A).

[0220] The transistor M1 has a gate connected to the wiring GL, one of its source and drain connected to the wiring SL, and the other connected to one electrode of the capacitor C1 and the gate of the transistor M2. The transistor M2 has a source and drain connected to the wiring AL, and the other connected to one electrode of the light-emitting device EL, the other electrode of the capacitor C1, and one of the source and drain of the transistor M3. The transistor M3 has a gate connected to the wiring GL, and the other of its source and drain connected to the wiring RL. The light-emitting device EL has the other electrode connected to the wiring CL.

[0221] The wiring SL is supplied with a data potential D. The wiring GL is supplied with a selection signal. The selection signal includes a potential for turning on a transistor and a potential for turning off a transistor.

[0222] A reset potential is applied to the wiring RL. An anode potential is applied to the wiring AL. A cathode potential is applied to the wiring CL. In the pixel 370, the anode potential is higher than the cathode potential. The reset potential applied to the wiring RL can be a potential such that the potential difference between the reset potential and the cathode potential is smaller than the threshold voltage of the light-emitting device EL. The reset potential can be a potential higher than the cathode potential, the same potential as the cathode potential, or a potential lower than the cathode potential.

[0223] The transistor M1 and the transistor M3 function as switches. The transistor M2 functions as a transistor for controlling a current flowing through the light-emitting device EL. For example, it can be said that the transistor M1 functions as a selection transistor and the transistor M2 functions as a drive transistor.

[0224] Here, it is preferable that LTPS transistors be used as all of the transistors M1 to M3. Alternatively, it is preferable that OS transistors be used as the transistors M1 and M3 and that an LTPS transistor be used as the transistor M2. Alternatively, it is preferable that OS transistors be used as all of the transistors M1 to M3.

[0225] The OS transistor can realize an extremely small off-current. Therefore, due to the small off-current, the charge accumulated in the capacitor connected in series with the transistor can be held for a long period of time. Therefore, it is preferable to use transistors to which an oxide semiconductor is applied, particularly for the transistors M1 and M3 connected in series with the capacitor C1. By using transistors having an oxide semiconductor as the transistors M1 and M3, it is possible to prevent the charge held in the capacitor C1 from leaking through the transistor M1 or the transistor M3. In addition, since the charge held in the capacitor C1 can be held for a long period of time, it is possible to display a still image for a long period of time without rewriting the data of the pixel 370.

[0226] 37B, the transistors M1 to M3 are represented as n-channel transistors, but p-channel transistors can also be used. For example, a transistor that passes a current through the light-emitting device EL can be a p-channel transistor, and the other transistors can be n-channel transistors.

[0227] A transistor having a pair of gates overlapping with a semiconductor layer therebetween can be used as the transistor included in the pixel 370. In a transistor having a pair of gates, a configuration in which the pair of gates are connected to each other and the same potential is applied has advantages in that the on-current of the transistor is increased and saturation characteristics are improved. A potential for controlling a threshold voltage of the transistor may be applied to one of the pair of gates. A constant potential may be applied to one of the pair of gates to improve the stability of the electrical characteristics of the transistor. For example, one gate of the transistor may be connected to a wiring to which a constant potential is applied, or may be connected to its own source or drain.

[0228] 37C shows an example of a pixel 370 in which the transistors M1 and M3 each have a pair of gates. The transistors M1 and M3 each have a pair of gates connected to each other. With this configuration, the period during which data is written to the pixel 370 can be shortened.

[0229] 37D is an example in which a transistor having a pair of gates is used for the transistor M2 in addition to the transistors M1 and M3. The pair of gates of the transistor M2 are connected. By using such a transistor for the transistor M2, the saturation characteristics are improved, making it easier to control the emission luminance of the light-emitting device EL, and the display quality can be improved.

[0230] Fig. 38(A) shows a block diagram of a display device 300B different from that shown in Fig. 37(A). The display device 300B includes a display unit 362, a gate line driving circuit 364, a light emission control driving circuit 384, and an IC 373. In Fig. 38(A), the same reference numerals are used for the parts common to Fig. 37(A), and the description thereof will be omitted.

[0231] The display unit 362 has a plurality of pixels 363 arranged in a matrix. The pixel 363 has sub-pixels 371R, 371G, and 371B. Each of the sub-pixels 371R, 371G, and 371B has a light-emitting device that functions as a display device.

[0232] The pixel 363 is connected to the wiring GLP, the wiring GLN, the wiring EMI, the wiring SLR, the wiring SLG, and the wiring SLB. The gate line driving circuit 364 is a gate line driving circuit having the unit circuit 100G described in the first embodiment. As shown in FIG. 38(B), the wirings GLP and GLN are wirings to which the output signals OUTP and OUTN output by the unit circuit 100G described in the first embodiment are supplied. The light emission control driving circuit 384 is a circuit that outputs timing signals for controlling the light emission of the light emitting devices in the sub-pixels 371R, 371G, and 371B. The wiring EMI is a wiring that transmits a timing signal for controlling the light emission of the light emitting devices.

[0233] Fig. 38C shows an example of a circuit diagram of a pixel 371 that can be applied to the subpixels 371R, 371G, and 371B. The pixel 371 includes transistors M11 to M17, a capacitor C2, and a light-emitting device EL. The pixel 371 is also connected to a wiring GLP_k, a wiring GLP_k-1, a wiring GLN_k, a wiring EMI_k, an initialization line INI, and a wiring SL. The wiring SL corresponds to any one of the wirings SLR, SLG, and SLB shown in Fig. 38A.

[0234] The transistors M11 to M14 are p-channel transistors using an LTPS transistor or the like. The transistor M15 is an n-channel transistor using an OS transistor or the like. The transistors M11 to M17, the capacitor C2, and the light-emitting device EL are connected as shown in FIG. 38C.

[0235] A data potential D is applied to the wiring SL. A selection signal for selecting a p-channel transistor is applied to the wiring GLP. A selection signal for selecting an n-channel transistor is applied to the wiring GLN. An initialization potential is applied to the initialization line INI. The unit circuit 100G described in the first embodiment can output signals for selecting transistors of different polarities. Therefore, in the pixel 371 having a p-channel transistor and an n-channel transistor illustrated in FIG. 38(C), transistors of different polarities can be selected at different timings. As a result, it is not necessary to provide a plurality of unit circuits that output selection signals at different timings, which leads to reduction in the circuit area and reduction in power consumption.

[0236] Additionally, in the display device 300B, a circuit configuration can be obtained in which p-channel transistors such as LTPS transistors and n-channel transistors such as OS transistors are used in both the pixel 371 included in the display unit 362 and the unit circuit 100G included in the gate line driving circuit 364. Therefore, the transistors in the display unit 362 and the gate line driving circuit 364 can be manufactured in a common process, which can reduce manufacturing costs.

[0237] This embodiment mode can be combined with other embodiment modes as appropriate.

[0238] (Embodiment 3) In this embodiment, electronic devices according to one embodiment of the present invention will be described with reference to FIGS. 39 to 41. The electronic devices according to this embodiment include a display device according to one embodiment of the present invention in a display portion. The display device according to one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device can be used in the display portion of various electronic devices.

[0239] Examples of electronic devices include electronic devices with relatively large screens, such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.

[0240] An electronic device 6500 shown in FIG. 39(A) is a portable information terminal that can be used as a smartphone.

[0241] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0242] The display device of one embodiment of the present invention can be applied to the display portion 6502.

[0243] FIG. 39(B) is a schematic cross-sectional view including the end portion of the housing 6501 on the microphone 6506 side.

[0244] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0245] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

[0246] In an area outside the display unit 6502, a part of the display panel 6511 is folded back, and the folded back part is connected to an FPC 6515. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0247] The display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. In addition, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while suppressing the thickness of the electronic device. In addition, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0248] 40A shows an example of a television set. In a television set 7100, a display portion 7000 is incorporated in a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0249] The display device of one embodiment of the present invention can be applied to the display portion 7000.

[0250] 40A can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using an operation key or a touch panel provided on the remote control 7111, the channel and volume can be operated, and an image displayed on the display portion 7000 can be controlled.

[0251] The television device 7100 includes a receiver and a modem. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network via a modem, one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication can be performed.

[0252] 40B shows an example of a laptop personal computer. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. A display portion 7000 is incorporated in the housing 7211.

[0253] The display device of one embodiment of the present invention can be applied to the display portion 7000.

[0254] 40(C) and 40(D) ​​show an example of digital signage.

[0255] 40C includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0256] 40D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0257] In FIG. 40C and FIG. 40D, the display device of one embodiment of the present invention can be applied to the display portion 7000.

[0258] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effect of, for example, advertisements.

[0259] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used for providing information such as route information or traffic information, the intuitive operation can improve usability.

[0260] 40(C) and 40(D), it is preferable that the digital signage 7300 or the digital signage 7400 can cooperate with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user via wireless communication. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0261] In addition, a game can be executed on the digital signage 7300 or the digital signage 7400 using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.

[0262] The electronic devices shown in Figures 41(A) to 41(G) have a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0263] The electronic devices shown in Figures 41(A) to 41(G) have various functions. For example, they may have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing a program or data recorded in a recording medium, and the like. Note that the functions of the electronic devices are not limited to these, and they may have various functions. The electronic devices may have multiple display units. In addition, the electronic devices may have a function of providing a camera or the like in the electronic device, taking still images or videos, and storing them in a recording medium (external or built-in to the camera), a function of displaying the taken images on the display unit, and the like.

[0264] The electronic devices shown in FIGS. 41A to 41G will be described in detail below.

[0265] FIG. 41A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on a plurality of surfaces. FIG. 41A shows an example in which three icons 9050 are displayed. Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, and phone calls, titles of e-mail or SNS, sender names, date and time, time, remaining battery power, and radio wave intensity. Alternatively, the icon 9050 or the like may be displayed at a position where the information 9051 is displayed.

[0266] 41(B) is a perspective view showing a mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of a display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and determine, for example, whether to answer a call.

[0267] 41C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, computer games, etc. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0268] FIG. 41(D) is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and reception with another information terminal and can be charged through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0269] 41(E) to 41(G) are perspective views showing a foldable mobile information terminal 9201. FIG. 41(E) is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 41(G) is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 41(F) is a perspective view of a state in the middle of changing from one of FIG. 41(E) and FIG. 41(G) to the other. The mobile information terminal 9201 has excellent portability in a folded state, and has excellent viewability of the display due to a seamless wide display area in an unfolded state. A display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0270] This embodiment mode can be combined with other embodiment modes as appropriate.

[0271] (Additional Notes Regarding the Description of the Present Specification, etc.) The above embodiment and each configuration in the embodiment will be described below with additional notes.

[0272] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0273] In addition, the content (or a part of the content) described in one embodiment may be applied to, combined with, or replaced by another content (or a part of the content) described in that embodiment, and / or the content (or a part of the content) described in one or more other embodiments.

[0274] The contents described in the embodiments refer to contents described in each embodiment using various figures or contents described using text in the specification.

[0275] In addition, a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, with another figure (or a part thereof) described in that embodiment, and / or with a figure (or a part thereof) described in one or more other embodiments to form even more figures.

[0276] In addition, in the present specification and the like, in the block diagrams, the components are classified by function and shown as mutually independent blocks. However, in actual circuits and the like, it is difficult to separate the components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, and may be rephrased appropriately.

[0277] In addition, in the drawings, the size, layer thickness, or region are shown at an arbitrary size for convenience of explanation. Therefore, they are not necessarily limited to the scale. Note that the drawings are shown diagrammatically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing deviations.

[0278] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode, or first terminal) and "the other of the source or drain" (or second electrode, or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. The source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, etc.

[0279] In addition, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed.

[0280] In addition, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage is a potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may be changed depending on the reference potential.

[0281] In this specification and the like, the terms "film" and "layer" can be interchanged. For example, the term "conductive layer" can be changed to the term "conductive film". Or, for example, the term "insulating film" can be changed to the term "insulating layer".

[0282] In this specification, a switch refers to a device that has a function of controlling whether a current flows or not by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0283] In this specification, the channel length refers to, for example, in a plan view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between the source and drain in a region where a channel is formed.

[0284] In this specification, the channel width refers to, for example, the length of the region where a semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap, or the length of the portion where a source and a drain face each other in a region in which a channel is formed.

[0285] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be regarded as being short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor is a state in which a current can flow between the source and drain. Therefore, the "on state" of a transistor may be referred to as the "conducting state" of the transistor.

[0286] In this specification, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0287] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the "gate voltage", the voltage between the drain and the source (drain-source) may be referred to as the "drain voltage", and the voltage between the backgate and the source (backgate-source) may be referred to as the "backgate voltage". Also, the current flowing from the drain to the source may be referred to as the "drain current".

[0288] In this specification, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification, the off-state current and the current flowing from the gate to the source and drain (also referred to as a gate leakage current) may also be referred to as leakage current.

[0289] In this specification, "connection" includes, by way of example, "electrical connection".

[0290] In addition, when the term "electrical connection" is used to define the connection relationship of circuit elements as a physical object, "electrical connection" includes, for example, "direct connection" and "indirect connection." As an example, "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch. Note that wiring is not a circuit element). On the other hand, as an example, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0291] Here, when "A and B are indirectly connected", it means the following connection relationship, for example. In other words, if there is a timing when an electric signal is exchanged or an electric potential interaction occurs between A and B during the operation period of the circuit, assuming that the circuit is operating, such a circuit can be defined as "A and B are indirectly connected" as an object. Even if there is a timing when an electric signal is not exchanged or an electric potential interaction occurs between A and B during the operation period of the circuit, it can be defined as "A and B are indirectly connected". It should be noted that "A and B are indirectly connected" is a definition of the connection relationship of circuit elements as an object. Therefore, for example, even if a power supply voltage is not supplied to a circuit and the circuit is not operating, it can be defined as "A and B are indirectly connected" as an object (however, for example, this is limited to the case where an electric signal is exchanged or an electric potential interaction occurs between A and B during the operation period of the circuit when a power supply voltage is supplied to the circuit and the circuit operates).

[0292] Specific examples of "indirect connection" are shown below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors, as shown in FIG. 42(A1) and FIG. 42(A2). Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. In the case of "A and B are indirectly connected", it is assumed that, assuming that the circuit is operating, there is a timing at which one transistor between A and B is in an on state, a conductive state, or a state in which a current can flow at least once. Note that the case of "A and B are indirectly connected" includes a timing at which one transistor between A and B is in an off state or a non-conductive state. In the case where "A and B are indirectly connected", if multiple transistors are connected between A and B, each of the multiple transistors between A and B has a timing at least once in an on state, a conductive state, or a state in which a current can flow, assuming that the circuit is operating. In other words, in the case where "A and B are indirectly connected", it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which a current can flow at the same time. Therefore, in the case where "A and B are indirectly connected", the multiple transistors between A and B may have a timing at which they are in an off state or a non-conductive state at the same time or at different times. As another example, as shown in FIG. 42(A3), if A and C are connected via the source and drain of a transistor TrP and B and C are connected via the source and drain of a transistor TrQ, it can be specified that "A and C are indirectly connected", "B and C are indirectly connected", or "A and B are indirectly connected". However, as will be described later, when a constant potential V is supplied to C from a power supply or GND, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0293] Thus, examples of cases where it can be said that there is an "indirect connection" and cases where it cannot be said that there is an "indirect connection" are given. Here, we will show another example of a case where it cannot be said that there is an "indirect connection". Even if there is a case where an electric signal is exchanged between A and B or an interaction of potentials occurs during the operation period of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected". An example of such an exceptional case is a case where A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected". A specific example of a case where A and B are connected via an insulator is a case where a capacitive element is connected between A and B as shown in FIG. 42(A4). Another example of a case where A and B are connected via an insulator is a case where a gate insulating film of a transistor is interposed between A and B as shown in FIG. 42(A5). In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected".

[0294] Another example of a case where it cannot be said that "A and B are indirectly connected" is a case where there is no timing when an electric signal is exchanged or potential interaction occurs between A and B. As an example, as shown in Figures 42(A6) and 42(A7), a plurality of transistors are connected via their sources and drains to the path from A to B, and a constant potential V is supplied to a node between the transistors from a power supply or GND. In this case, it cannot be said that "A and B are indirectly connected", but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected". In addition, in Figure 42(A3), if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply or GND, etc., the connection relationship will be the same as in Figure 42(A6) and Figure 42(A7), so it cannot be said that "A and B are indirectly connected," but it can be said that "A and C are indirectly connected" or "B and C are indirectly connected."

[0295] Although an example of "indirect connection" has been given above, as an example, the provision of "indirect connection" is included in the provision of "electrical connection," so when "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0296] Next, a specific example of the case of "direct connection" is shown. As an example of the case where "A and B are directly connected", there is a case where A and B are connected without a circuit element between them, as shown in Fig. 42(B1), Fig. 42(B2), and Fig. 42(B3). When A and B are connected to a power supply that supplies a constant potential V or GND without a circuit element between them, as shown in Fig. 42(B4) and Fig. 42(B5), it can be said that "A and B are directly connected", "A and V are directly connected", or "B and V are directly connected". It can also be said that "A and B are directly connected" when A (or B) is connected to a constant potential V through the source and drain of a transistor, as shown in Fig. 42(B6). It can also be said that "A and B are directly connected". It can be said that A and V or B and V are connected through the source and drain of a transistor, and therefore cannot be said to be directly connected, but rather that "A and V are indirectly connected" or "B and V are indirectly connected".

[0297] Although an example of a "direct connection" has been given above, as an example, the provision of a "direct connection" is included in the provision of an "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected." [Explanation of symbols]

[0298] Tp1-Tp8 transistors Tn1 Transistor 101 Wiring 102 Wiring 103 Power line 104 Power line 105 Wiring 106 Wiring 107 Wiring

Claims

1. A display device having a gate line driving circuit, The unit circuit of the gate line driver circuit includes first to fifth p-channel transistors and an n-channel transistor, one of a source and a drain of the first p-channel transistor is electrically connected to a first clock signal line; one of a source and a drain of the second p-channel transistor is electrically connected to a first power supply line; the other of the source and the drain of the first p-channel transistor is electrically connected to the other of the source and the drain of the second p-channel transistor; a gate of the first p-channel transistor is electrically connected to one of a source and a drain of the third p-channel transistor; a gate of the first p-channel transistor is directly connected to a gate of the n-channel transistor; a gate of the third p-channel transistor is electrically connected to a second power supply line; the other of the source and the drain of the third p-channel transistor is electrically connected to one of the source and the drain of the fourth p-channel transistor; the other of the source and the drain of the third p-channel transistor is electrically connected to the gate of the fifth p-channel transistor; a gate of the fourth p-channel transistor is electrically connected to a second clock signal line; one of a source and a drain of the fifth p-channel transistor is electrically connected to the first power supply line; the other of the source and the drain of the fifth p-channel transistor is electrically connected to the gate of the second p-channel transistor; the other of the source and the drain of the fifth p-channel transistor is electrically connected to one of the source and the drain of the n-channel transistor; the other of the source and the drain of the n-channel transistor is electrically connected to the second power supply line; Display device.

2. In claim 1, The n-channel transistor has a first semiconductor layer, The first semiconductor layer includes an oxide semiconductor. Display device.

3. In claim 1 or 2, each of the first to fifth p-channel transistors has a second semiconductor layer; The second semiconductor layer comprises silicon. Display device.

4. A display device having a gate line driving circuit, The unit circuit of the gate line driver circuit includes first to seventh p-channel transistors and an n-channel transistor, one of a source and a drain of the first p-channel transistor is electrically connected to a first clock signal line; one of a source and a drain of the second p-channel transistor is electrically connected to a first power supply line; the other of the source and the drain of the first p-channel transistor is electrically connected to the other of the source and the drain of the second p-channel transistor; a gate of the first p-channel transistor is electrically connected to one of a source and a drain of the third p-channel transistor; a gate of the first p-channel transistor is directly connected to a gate of the n-channel transistor; a gate of the third p-channel transistor is electrically connected to a second power supply line; the other of the source and the drain of the third p-channel transistor is electrically connected to one of the source and the drain of the fourth p-channel transistor; the other of the source and the drain of the third p-channel transistor is electrically connected to one of the source and the drain of the sixth p-channel transistor; the other of the source and the drain of the third p-channel transistor is electrically connected to the gate of the fifth p-channel transistor; a gate of the fourth p-channel transistor is electrically connected to a second clock signal line; one of a source and a drain of the fifth p-channel transistor is electrically connected to the first power supply line; the other of the source and the drain of the fifth p-channel transistor is electrically connected to the gate of the second p-channel transistor; the other of the source and the drain of the fifth p-channel transistor is electrically connected to the gate of the seventh p-channel transistor; the other of the source and the drain of the fifth p-channel transistor is electrically connected to one of the source and the drain of the n-channel transistor; the other of the source and the drain of the n-channel transistor is electrically connected to the second power supply line; a gate of the sixth p-channel transistor is electrically connected to the first clock signal line; the other of the source and the drain of the sixth p-channel transistor is electrically connected to one of the source and the drain of the seventh p-channel transistor; the other of the source and the drain of the seventh p-channel transistor is electrically connected to the first power supply line; Display device.

5. In claim 4, The n-channel transistor has a first semiconductor layer, The first semiconductor layer includes an oxide semiconductor. Display device.

6. In claim 4 or 5, each of the first to seventh p-channel transistors has a second semiconductor layer; The second semiconductor layer comprises silicon. Display device.

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