Selective deposition of carbon film and uses thereof
Through selective deposition of carbon film technology, the problem of difficult control of the growth rate and volume changes of metal oxide columns in the semiconductor industry is solved, and the self-alignment and precise growth of carbon columns are achieved, and the accuracy and reliability of the structure are improved.
Patent Information
- Application Number
- JP2024216311
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2018-11-23
- Filing Date
- 2024-12-11
- Publication Date
- 2025-04-10
AI Technical Summary
In the semiconductor industry, it is difficult for the prior art to effectively control the growth rate and volume changes of metal oxide columns, resulting in structural damage, adhesion problems and residual metal problems, which in turn affects the formation of self-aligned structures.
Through selective deposition of carbon film technology, carbon precursors react with metal surfaces to form carbon columns, and self-alignment and precise growth of carbon columns are achieved by fine control of deposition parameters and surface treatment.
The efficient and precise growth of carbon columns is achieved, structural damage and adhesion problems are avoided, and the accuracy and reliability of self-aligned structures are improved.
Smart Images
Figure 2025060669000001_ABST
Abstract
Description
[Technical field]
[0001]
[0001] Embodiments of the present disclosure generally relate to methods and materials for selectively depositing carbon films. Some embodiments of the present disclosure relate to methods for forming carbon pillars. Some embodiments of the present disclosure relate to methods for forming self-aligned vias. [Background technology]
[0002]
[0002] The semiconductor industry faces many challenges in the pursuit of device miniaturization with the rapid scaling of nanoscale features. These challenges include the introduction of complex manufacturing steps such as multiple lithography steps and integration of high performance materials. To keep pace with device miniaturization, selective deposition has shown promise as a potential solution to eliminate costly lithography steps by simplifying integration schemes.
[0003]
[0003] Selective deposition of materials can be achieved in a variety of ways. Chemical precursors may selectively react with one surface compared to another (metal or dielectric) surface. Process parameters such as pressure, substrate temperature, precursor partial pressure, and / or gas flow can be adjusted to tailor the chemical reaction rate of a particular surface reaction. Another possible scheme includes surface pretreatments that can be used to activate or deactivate the surface of interest to the incoming film deposition precursors.
[0004]
[0004] Thus, there is a continuing need in the art for methods for selectively depositing films, and more specifically, for methods for selectively depositing carbon films.
[0005]
[0005] Self-aligned metal oxide pillars can be formed through oxidation of gap-fill metal films. Metal is deposited in a hole or trench structure and then oxidized to form a metal oxide. Volume expansion during oxidation pushes the pillars out of the hole or trench. The pillars grow selectively from the bottom up only from the metal.
[0006] However, there can be challenges in controlling the rate and amount of volume expansion of the metal to form the metal oxide columns. First, the sudden change in stress can lead to degradation of the native structure. This can cause tall columns to bend when the CD is small. Second, the sudden change in volume can lead to adhesion issues between the metal oxide pillars and the substrate. Third, residual unoxidized metal can remain at the bottom of the trench.
[0007]
[0007] Therefore, there is a need in the art for alternative methods of fabricating self-aligned structures.
[0008]
[0008] In general, an integrated circuit (IC) refers to a set of electronic devices, such as transistors, formed on a small chip of semiconductor material, typically silicon. An IC usually includes one or more metallization layers with metal lines for connecting the electronic devices of the IC to each other and to external connections. Layers of interlayer dielectric material are usually disposed between the metallization layers of an IC for insulation.
[0009]
[0009] As integrated circuits shrink in size, the spacing between metal lines decreases. Typically, interconnect structures are fabricated using planar processes that involve aligning and connecting one metallization layer to another.
[0010]
[0010] Typically, the patterning of metal lines in a metallization layer is performed independently of the vias on that metallization layer. However, conventional via fabrication techniques do not provide perfect via self-alignment. In conventional techniques, vias formed to connect lines in an upper metallization layer to a lower metallization layer are often misaligned with respect to the lines in the lower metallization layer. Misalignment of vias and lines increases via resistance and leads to potential shorts to wrong metal lines. Misalignment of vias and lines can cause device failures, reduce yields, and increase manufacturing costs.
[0011] Therefore, there is a need in the art for a method for fabricating fully self-aligned vias. Summary of the Invention
[0012]
[0012] One or more embodiments of the present disclosure are directed to a method of selectively depositing a carbon film. The method includes providing a substrate comprising a first material and a second material. The first material has an exposed first material surface. The second material has an exposed second material surface. The first material comprises a metal. The substrate is exposed to a carbon precursor to form a carbon film having a first thickness on the exposed first material surface and a second thickness on the exposed second material surface. The first thickness is greater than the second thickness.
[0013]
[0013] An additional embodiment of the present disclosure is directed to a method of forming a carbon pillar. The method includes providing a substrate comprising a first metal-containing material and a second dielectric material. The first metal-containing material has an exposed first surface having a first dimension. The second dielectric material has an exposed second surface. The exposed first surface and the exposed second surface form a substrate surface. Exposing the substrate to a carbon precursor to form a carbon pillar comprising a carbon material on the exposed first surface. The carbon pillar and the exposed first surface have the same first dimension.
[0014]
[0014] A further embodiment of the present disclosure is directed to a method of forming a self-aligned via. The method includes recessing a first conductive line in a first insulating layer of a substrate. The first conductive line extends along a first direction in the first insulating layer. Forming carbon pillars in the recessed first conductive line. Depositing a second insulating layer between the carbon pillars. Removing the carbon pillars to form trenches in the second insulating layer. Depositing a third insulating layer in the recessed first conductive line trench to form a filled trench. Selectively etching the third insulating layer from the filled trench to form a via opening in the first conductive line. [Brief description of the drawings]
[0015] [Figure 1A] FIG. 2 illustrates an exemplary substrate for selectively depositing carbon films according to some embodiments. [Figure 1B] FIG. 2 illustrates an exemplary substrate having a carbon film selectively deposited thereon, according to some embodiments. [Diagram 2] 1A-1D illustrate a method for selectively depositing a carbon film or forming carbon pillars according to some embodiments. [Figure 3A] 1A-1D illustrate exemplary substrates for forming carbon pillars according to some embodiments. [Figure 3B] FIG. 2 illustrates an exemplary substrate having carbon pillars formed thereon, according to some embodiments. [Figure 4] 1 is a cross-sectional view of an electronic device structure providing a fully self-aligned via according to some embodiments. [Diagram 5] 2 is a cross-sectional view of an electronic device structure after a conductive material has been deposited thereon, according to some embodiments. [Figure 6] 2 is a cross-sectional view of an electronic device structure after the conductive material has been planarized to form conductive lines in accordance with some embodiments. [Figure 7] 4A-4D are cross-sectional views of electronic device structures after recessing conductive lines according to some embodiments. [Figure 8] 1 is a cross-sectional view of an electronic device structure after carbon pillars are formed on conductive lines according to some embodiments. [Figure 9] FIG. 2 is a cross-sectional view of an electronic device structure after a second insulating material has been deposited around the carbon pillars, according to some embodiments. [Figure 10] 4 is a cross-sectional view of an electronic device structure after the second insulating material has been planarized in accordance with some embodiments. [Figure 11] 2A-2C are cross-sectional views of an electronic device structure after the carbon pillars have been removed and trenches have been formed, according to some embodiments. [Figure 12] FIG. 2 is a cross-sectional view of an electronic device structure after an etch stop layer is deposited according to some embodiments. [Figure 13]FIG. 2 is a cross-sectional view of an electronic device structure after a third insulating material is deposited on the etch stop layer to form a filled trench, according to some embodiments. [Figure 14] FIG. 2 is a cross-sectional view of an electronic device structure after the third insulating material and the etch stop layer have been selectively removed from the filled trench to form a via opening, according to some embodiments. [Figure 15] 4 is a cross-sectional view of an electronic device structure after a second conductive material has been deposited in the via opening according to some embodiments. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0016]
[0032] In the accompanying figures, similar components and / or features may have the same reference numbers. Furthermore, various components of the same type may be distinguished by following the reference number with a dash and a second number that distinguishes between the similar components. It is noted that if only a first reference number is used in this specification, the description applies to any similar components that have the same first reference number, regardless of the second reference number.
[0017]
[0033] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of construction or process routines set forth in the following description as the present disclosure is capable of other embodiments and of being practiced or carried out in various ways.
[0018]
[0034] As used herein, "substrate", "substrate surface", and the like refer to any substrate or material surface formed on the substrate on which processing is performed. For example, substrate surfaces on which processing may be performed include, but are not limited to, materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be exposed to pretreatment processes that polish, etch, reduce, oxidize, hydroxylate (or generate or graft targeted chemical moieties to impart chemical functionality), anneal, or bake the substrate surface. In addition to directly treating the surface of the substrate itself, the present disclosure contemplates that any of the disclosed film processing steps may be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlayers as the context indicates. Thus, for example, if a film / layer or a portion of a film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer may be referred to as the substrate surface. The composition of a given substrate surface will depend on the material being deposited and the particular chemistry used.
[0019]
[0035] As used herein and in the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species capable of reacting with the substrate surface.
[0020]
[0036] Some embodiments of the present disclosure provide a method for selectively depositing a carbon film. In some embodiments, the carbon film is selectively deposited on a metal-containing surface over a different surface. As used herein and in the appended claims, phrases such as "selectively depositing a film on one surface over another surface" mean that a first amount of film is deposited on the first surface, a second amount of film is deposited on the second surface, the second amount of film being less than the first amount of film, or no film is deposited on the second surface.
[0021]
[0037] The term "rather than" as used in this regard does not refer to the physical orientation of one surface over another, but rather to the relationship of the thermodynamic or kinetic properties of a chemical reaction with one surface relative to the other. For example, selectively depositing a carbon film on a metal surface over a dielectric surface means that the carbon film deposits on the metal surface and little or no carbon film deposits on the dielectric surface; alternatively, the formation of a carbon film on a metal surface is thermodynamically or kinetically favored compared to the formation of a carbon film on a dielectric surface.
[0022]
[0038] Some embodiments of the present disclosure advantageously provide a method for selectively depositing a carbon film on a first surface over a second surface. Some embodiments of the present disclosure provide a method for depositing a carbon film that is performed at a relatively low temperature. Some embodiments of the present disclosure advantageously provide a method for depositing a carbon film without the use of a plasma reactant or plasma treatment. In some embodiments, the first surface comprises a metal and the second surface comprises a dielectric.
[0023]
[0039] 1A illustrates an exemplary substrate 100 in accordance with one or more embodiments of the present disclosure. Substrate 100 includes a first material 110 and a second material 120. First material 110 has an exposed first material surface 115. Second material 120 has an exposed second material surface 125.
[0024]
[0040] The first material 110 comprises a metal. In some embodiments, the metal comprises or consists essentially of one or more of Ti, Co, Ni, Cu, Ru, Rh, Pd, Ag, Hf, Ta, W, Re, Ir, Pt, or Au. In some embodiments, the metal comprises or consists essentially of one or more of Ti, Hf, Ta, or W. In some embodiments, the metal comprises or consists essentially of one or more of Co, Ni, Ru, Rh, Pd, or Re. In some embodiments, the metal comprises or consists essentially of one or more of Cu, Pd, Ag, Ir, Pt, or Au. As used herein and in the appended claims, terms such as "consisting essentially of" mean that the subject material or composition is greater than or equal to about 95%, 98%, 99%, or 99.5% of the stated material.
[0025]
[0041] In some embodiments, the first material 110 comprises a substantially pure metal or metal alloy. In other words, the first material 110 may consist essentially of metal atoms. In some embodiments, the first material 110 comprises metallic and non-metallic elements. In some embodiments, the first material 110 comprises a metal nitride, a metal carbide, a metal silicide, a metal oxide, a metal sulfide, a metal selenide, a metal telluride, or a combination thereof.
[0026]
[0042] In some embodiments, the second material 120 comprises a dielectric material. In some embodiments, the second material 120 comprises silicon.
[0027]
[0043] 2 illustrates a method of forming a carbon film on a substrate 100, in accordance with one or more embodiments of the present disclosure. The method 200 generally begins at 202, where a substrate is provided upon which a carbon film is to be formed. The term "provided" as used in this context means that the substrate is placed in a location or environment for further processing.
[0028]
[0044] At 204, a carbon film is formed on the substrate 100. The carbon film may be formed via a chemical vapor deposition process (CVD) or the like. Referring also to FIG. 1B, at 204, the substrate 100 is exposed to a carbon precursor to form a carbon film 130 having a first thickness T1 on the exposed first material surface 115 and a second thickness T2 on the exposed second material surface 125. The first thickness T1 is greater than the second thickness T2. For purposes of understanding, the second thickness T2 is shown in FIG. 1B. In some embodiments, the second thickness T2 is minimal or absent.
[0029]
[0045] The selectivity of a deposition process is generally expressed as a multiple of the growth rate. For example, if a film grows 25 times faster on one surface than on another, the process is said to have a selectivity of 25:1. In this regard, a higher ratio indicates a more selective process. In some embodiments, the method has a selectivity of about 10:1 or greater, about 25:1 or greater, about 50:1 or greater, or about 100:1 or greater.
[0030]
[0046] The carbon precursor may include any suitable carbon-containing species. In some embodiments, the carbon precursor consists essentially of carbon and hydrogen atoms. In some embodiments, the carbon precursor includes C1-C4 hydrocarbons, C1-C6 hydrocarbons, or C1-C8 hydrocarbons. As used in this regard, C1-C4, etc., refers to species having a number of carbon atoms ranging from 1 to 4. In some embodiments, the carbon precursor includes at least one unsaturated bond. In some embodiments, the carbon precursor includes C 2 H 2 , C 2 H 4 , C 3 H 6 , or C.H. 4 In the case of a gaseous composition, the term "consisting essentially of" refers to the active ingredients of the composition without diluents, carriers, or inert gases.
[0031]
[0047] In some embodiments, the substrate is exposed to a carbon precursor that includes an additional reactant or diluent. In some embodiments, the additional reactant or diluent is hydrogen gas (H 2 ), nitrogen gas (N 2 ) or argon gas (Ar). In some embodiments, when provided as part of the carbon precursor, hydrogen gas (H 2 ) is not provided as a diluent, carrier or inert gas.
[0032]
[0048] The flow rate of the carbon precursor can be any suitable flow rate, including, but not limited to, a flow rate in the range of about 1 to about 5000 sccm, or in the range of about 2 to about 4000 sccm, or in the range of about 3 to about 3000 sccm, or in the range of about 5 to about 2000 sccm, or in the range of about 10 to about 2000 sccm.
[0033]
[0049] The carbon precursor may be provided to establish any suitable pressure around the substrate (i.e., within the processing chamber), including, but not limited to, a pressure in the range of about 1 Torr to about 3000 Torr, or in the range of about 2 Torr to about 1500 Torr, or in the range of about 100 Torr to about 1000 Torr, or in the range of about 500 Torr to about 1000 Torr. In some embodiments, the substrate is exposed to the carbon precursor at about atmospheric pressure (e.g., 760 Torr).
[0034]
[0050] The temperature of the substrate during deposition may be controlled, for example, by setting the temperature of the substrate support or susceptor. In some embodiments, the substrate is maintained at a temperature in the range of about 100° C. to about 700° C., or in the range of about 100° C. to about 500° C., or in the range of about 300° C. to about 500° C. In some embodiments, the substrate is maintained at a temperature of about 700° C. or less, about 500° C. or less, or about 300° C. or less.
[0035]
[0051] The time for which the substrate is exposed to the carbon precursor gas can be any suitable time necessary to allow a carbon film of a predetermined thickness to be formed on the exposed first material surface. For example, the substrate can be exposed to the carbon precursor for about 10 minutes to about 5 hours, or about 30 minutes to about 3 hours, or about 1 hour to about 2 hours.
[0036]
[0052] In some embodiments, the carbon film is formed at a rate of about 20 nm / hr or more, about 25 nm / hr or more, about 30 nm / hr or more, about 40 nm / hr or more, or about 50 nm / hr or more, hi some embodiments, the carbon film is formed at a rate in the range of about 25 nm / hr to about 50 nm / hr.
[0037]
[0053] In some embodiments, the method for selectively depositing a carbon film is performed as a thermal process without using a plasma reactant, in other words, in some embodiments, the method is performed without a plasma.
[0038]
[0054] It is then determined whether the metal film has reached a predetermined thickness at 206. If the predetermined thickness has not been reached, the method 200 returns to 204 to continue forming the metal film until the predetermined thickness is reached. Once the predetermined thickness is reached, the method 200 may end or proceed to 208 for optional further processing.
[0039]
[0055] Some embodiments of the present disclosure provide methods of forming carbon pillars, hi some embodiments, the carbon pillars are selectively formed on a metal-containing surface over a different surface.
[0040]
[0056] Some embodiments of the present disclosure advantageously provide a method of forming carbon pillars on a first surface rather than a second surface. Some embodiments of the present disclosure provide a method of forming carbon pillars that is performed at a relatively low temperature. Some embodiments of the present disclosure advantageously provide a method of forming carbon pillars without the use of plasma reactants or plasma treatments. Some embodiments of the present disclosure provide a method of forming carbon pillars that provides pillars without a "mushroom" effect. In some embodiments, the first surface comprises a metal and the second surface comprises a dielectric material.
[0041]
[0057] Referring to the figures, FIG. 3A illustrates an exemplary substrate 300 according to one or more embodiments of the present disclosure. The substrate 300 includes a first material 310 and a second material 320. The first material 310 has an exposed first surface 315 having a first material dimension D1. The second material 320 has an exposed second surface 325. The exposed first surface 315 and the exposed second surface 325 form a substrate surface. In some embodiments, the first material 310 includes a metal-containing material. In some embodiments, the second material 320 includes a dielectric material. Thus, the first material 310 may be referred to as a first metal-containing material and the second material 320 may be referred to as a second dielectric material.
[0042]
[0058] The first material 310 comprises a metal. In some embodiments, the metal comprises or consists essentially of one or more of Co, Ni, Ru, Rh, Pd, or Re. Without wishing to be bound by theory, the inventors have discovered that all of these metals catalyze the deposition of carbon and have high levels of carbon solubility. These factors combine to enable a deposition process from vapor precursor to dissolved carbon species to solid deposited carbon pillars. Without wishing to be bound by theory, it is believed that this mechanism results in orthogonal growth rather than mushrooming of the carbon pillars.
[0043]
[0059] In some embodiments, the first material 310 comprises a substantially pure metal or metal alloy. In other words, the first material 310 may consist essentially of metal atoms. In some embodiments, the first material 310 comprises metallic and non-metallic elements. In some embodiments, the first material 310 comprises a metal nitride, a metal carbide, a metal silicide, a metal oxide, a metal sulfide, a metal selenide, a metal telluride, or a combination thereof.
[0044]
[0060] In some embodiments, the second material 320 comprises a dielectric material. In some embodiments, the second material 320 comprises silicon.
[0045]
[0061] 3A, the exposed first surface 315 is recessed from the exposed second surface 325 to form a substrate feature 305. The substrate feature 305 includes at least one sidewall 322 of the second material 320 and a bottom 312 of the exposed first surface 315.
[0046]
[0062] Alternatively, in some embodiments, substrate 300 does not include feature 305 as shown in Figure 3A. For these embodiments, substrate 300 appears like substrate 100 of Figure 1A. In other words, in some embodiments, the exposed first surface is substantially coplanar with the exposed second surface. As used herein and in the appended claims, the term "substantially coplanar" means that the exposed first surface and the exposed second surface are coplanar within ±2 nm.
[0047]
[0063] The method of forming the carbon pillars is similar to the method of forming the carbon film shown in Figure 2. The method 200 generally begins at 202, where a substrate is provided upon which the carbon pillars will be formed.
[0048]
[0064] At 204, carbon pillars are formed on the substrate. The carbon pillars may be formed via a chemical vapor deposition process (CVD) or the like. Referring also to FIG. 3B, at 204, the substrate 300 is exposed to a carbon precursor to form a carbon pillar 330 comprising a carbon material. The carbon pillar 330 extends above the exposed second surface 325. The carbon pillar 330 has a first dimension D1 that is substantially the same as the exposed first surface 315. In some embodiments, substantially no carbon material is deposited on the exposed second surface 325.
[0049]
[0065] In some embodiments, the carbon pillars 330 have sides 335 that are substantially orthogonal to the substrate surface. In some embodiments, the carbon pillars 330 have sides 335 that are substantially orthogonal to the exposed second surface 325. As used in this regard, two surfaces may be described as substantially orthogonal if the angle formed at the junction of the surfaces is 90°±10°.
[0050]
[0066] The reactants and process parameters described above for the selective deposition of carbon films are the same reactants and process parameters for the formation of carbon pillars.
[0051]
[0067] It is then determined whether the carbon pillars have reached a predetermined thickness at 206. If the predetermined thickness has not been reached, the method 200 returns to 204 to continue forming the carbon pillars until the predetermined thickness is reached. Once the predetermined thickness is reached, the method 200 may end or proceed to 208 for optional further processing.
[0052]
[0068] Some embodiments of the present disclosure provide a method of forming a fully self-aligned via. In one embodiment, a first metallization layer is formed in a first insulating layer of a substrate, the first metallization layer including a set of first conductive lines extending along a first direction. A second insulating layer is formed in the first insulating layer. A second metallization layer is formed in a third insulating layer over the first metallization layer, the set of second conductive lines extending along a second direction. A via is formed between the first metallization layer and the second metallization layer. The via is self-aligned to one of the first conductive lines along the second direction. As described in more detail below, the via is self-aligned to one of the second conductive lines along the first direction. In one embodiment, the first and second directions intersect each other at an angle. In one embodiment, the first and second directions are substantially perpendicular to each other.
[0053]
[0069] In one embodiment, a fully self-aligned via is fabricated using a selective pillar deposition technique. In one embodiment, a conductive line in a first insulating layer of a substrate is recessed. The conductive line extends along a first direction in the first insulating layer. Pillars are formed in the recessed conductive line. A second insulating layer is deposited between the pillars. The pillars are removed to form a trench. A third insulating layer is deposited on the second insulating layer and in the trench. As described in more detail below, the third insulating layer is selectively etched relative to the second insulating layer to form a via opening in one of the conductive lines.
[0054]
[0070] In one embodiment, a fully self-aligned via is a via that is self-aligned along at least two directions relative to conductive lines in the lower and upper metallization layers, in one embodiment, the fully self-aligned via is defined in one direction by a hardmask and in another direction by an underlying insulating layer, as described in more detail below.
[0055]
[0071] One or more embodiments provide a fully self-aligned via, advantageously eliminating via misalignment issues and avoiding shorts to incorrect metal lines. Fully self-aligned vias offer the advantages of lower via resistance and capacitance over conventional vias. Self-aligned via embodiments provide perfect alignment between vias and conductive lines of metallization layers with virtually no error, advantageously increasing device yields and reducing device costs.
[0056]
[0072] If the vias are printed close to each other, i.e. closer than the minimum pitch obtainable by lithography, the set of via mask layers is split into multiple masks. For example, instead of defining the vias in the metal with one lithography-etch sequence, two or more lithography-etch sequences are used to avoid shorting closely spaced vias. Some embodiments of the present disclosure are directed to a pillar growth process in which all vias are defined as crossovers between two metal layers so that adjacent vias do not short to each other. In some embodiments, multiple vias may be defined using one large lithography feature located on multiple cross points. In this case, all areas where the metal layers overlap under the defined large lithography openings form vias.
[0057]
[0073] Additionally, the disclosed methods advantageously provide pillars that are easier to remove than metal oxide pillars. In some embodiments, the carbon pillars are removed by a dry etching process. Without being bound by theory, it is believed that the dry etching process used to remove the carbon pillars is easier to perform than the oxygen-based ashing processes typically used to etch metal oxide materials.
[0058]
[0074] In the following description, numerous specific details are set forth, such as specific materials, chemicals, dimensions of elements, etc., to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to one of ordinary skill in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor manufacturing processes, techniques, materials, equipment, etc. have not been described in detail to avoid unnecessarily obscuring this description. One of ordinary skill in the art will be able to use the included description to implement the appropriate functionality without undue experimentation.
[0059]
[0075] One or more embodiments of the present disclosure are directed to a method and apparatus for providing a fully self-aligned via. Various aspects of the present disclosure are described with reference to detailed processes shown in the figures. Those skilled in the art will understand that the scope of the present disclosure is not limited to the specific details set forth in the figures, and that portions of the process can be modified or omitted.
[0060]
[0076] 4-6 are cross-sectional views of a substrate 401 providing a fully self-aligned via or gap, according to some embodiments. Referring to FIG. 6, the lower metallization layer (Mx) includes a set of conductive lines 603 extending along the axis of the insulating layer 402 of the substrate 401. The method may begin at FIG. 4, where a trench 404 is formed in the insulating layer 402. Referring to FIG. 5, a conductive layer 503 is deposited in the trench 404. Referring to FIG. 6, if necessary, the first conductive layer 403 is planarized to the surface of the insulating layer 402.
[0061]
[0077] In some embodiments, the substrate 401 comprises a semiconductor material, such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), InP, GaAs, InGaAs, InAIAs, other semiconductor materials, or any combination thereof. In some embodiments, the substrate 401 is a semiconductor-on-isolation (SOI) substrate that includes a bulk lower substrate, an intermediate insulating layer, and an upper single crystal layer. The upper single crystal layer can include any of the materials listed above, such as silicon. In various embodiments, the substrate 401 can be, for example, an organic substrate, a ceramic substrate, a glass substrate, or a semiconductor substrate. Although some examples of materials that can form the substrate are described herein, any material that can serve as a foundation on which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic devices, or any other electronic devices) can be built is within the spirit and scope of the present disclosure.
[0062]
[0078] In some embodiments, the substrate 401 includes one or more metallization interconnect layers for an integrated circuit. In some embodiments, the substrate 401 includes interconnects, e.g., vias, configured to connect the metallization layers. In some embodiments, the substrate 401 includes electronic devices, e.g., transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices separated by an electrically insulating layer, e.g., an interlayer dielectric, a trench isolation layer, or any other insulating layer known to those skilled in the art of electronic device manufacturing. In some embodiments, the substrate includes one or more buffer layers to accommodate lattice mismatch between the substrate 401 and one or more layers on the substrate 401 and to confine lattice dislocations and defects.
[0063]
[0079] The insulating layer 402 can be any material suitable for insulating adjacent devices to prevent leakage. In some embodiments, the electrically insulating layer 402 is an oxide layer, such as, for example, silicon dioxide, or any other electrically insulating layer as dictated by the electronic device design. In some embodiments, the insulating layer 402 comprises an inter-layer dielectric (ILD). In some embodiments, the insulating layer 402 is a low-k dielectric, including, but not limited to, materials such as, for example, silicon dioxide, silicon oxide, carbon-doped oxide ("CDO"), such as, for example, carbon-doped silicon dioxide, porous silicon dioxide, silicon nitride, or any combination thereof.
[0064]
[0080] In some embodiments, the insulating layer 402 comprises a dielectric material having a dielectric constant value less than 5. In some embodiments, the insulating layer 402 comprises a dielectric material having a dielectric constant value less than 2. In some embodiments, the insulating layer 402 comprises a nitride, an oxide, a polymer, a phosphosilicate glass, a fluorosilicate (SiOF) glass, an organosilicate glass (SiOCH), other electrically insulating layers as determined by the electronic device design, or any combination thereof. In some embodiments, the insulating layer 402 may comprise a photosensitive material such as polyimide, epoxy, benzocyclobutene (BCB), and WPR series materials, or spin-on glass.
[0065]
[0081] In some embodiments, insulating layer 402 is a low-k interlevel dielectric to separate one metal line from another metal line in substrate 401. In some embodiments, the thickness of insulating layer 402 is approximately in the range of about 10 nanometers (nm) to about 2 microns (μm).
[0066]
[0082] In some embodiments, the insulating layer 402 is deposited using one of a number of deposition techniques, such as, but not limited to, chemical vapor deposition ("CVD"), physical vapor deposition ("PVD"), molecular beam epitaxy ("MBE"), metalorganic chemical vapor deposition ("MOCVD"), atomic layer deposition ("ALD"), spin-on, or other insulating deposition techniques known to those skilled in the art of microelectronic device manufacturing.
[0067]
[0083] In some embodiments, the composition of the insulating layer 402 is similar to the second material 120 described above.
[0068]
[0084] In some embodiments, the lower metallization layer Mx, including the conductive lines 603, is part of the back-end metallization of the electronic device. Referring to Figure 4, in some embodiments, the insulating layer 402 is patterned and etched using a hard mask to form trenches 404 using one or more patterning and etching techniques well known to those skilled in the art of microelectronic device manufacturing. In some embodiments, the size of the trenches 404 in the insulating layer 402 is determined by the size of the conductive lines 603 that will be formed later in the process.
[0069]
[0085] In some embodiments, forming the conductive line 603 includes filling the trench 404 with a layer of conductive material. In some embodiments, a base layer (not shown) is first deposited on the interior sidewalls and bottom of the trench 404, and then the conductive layer 503 is deposited on the base layer. In some embodiments, the base layer includes a conductive seed layer (not shown) deposited on a conductive barrier layer (not shown). The seed layer may include copper, and the conductive barrier layer may include metals such as aluminum, titanium, tantalum, tantalum nitride, etc. The conductive barrier layer may be used to prevent diffusion of conductive materials, such as copper, from the seed layer into the insulating layer 402. Additionally, the conductive barrier layer may be used to provide adhesion to the seed layer (e.g., copper).
[0070]
[0086] In some embodiments, a conductive barrier layer is deposited on the sidewalls and bottom of the trench 404 to form a base layer, and then a seed layer is deposited on the conductive barrier layer. In another embodiment, the conductive base layer includes a seed layer that is deposited directly on the sidewalls and bottom of the trench 404. Each of the conductive barrier layer and the seed layer may be deposited using any thin film deposition technique known to those skilled in the art of semiconductor manufacturing, such as sputtering, blanket deposition, etc. In one embodiment, each of the conductive barrier layer and the seed layer has a thickness in the approximate range of about 1 nm to about 100 nm. In some embodiments, the barrier layer may be a thin dielectric that is etched to establish electrical conductivity to the underlying metal layer. In some embodiments, the barrier layer may be omitted entirely, and a "self-forming barrier" may be created using appropriate doping of the copper lines.
[0071]
[0087] In some embodiments, the conductive layer 503, e.g., copper, is deposited on a copper base layer seed layer by an electroplating process. In some embodiments, the conductive layer is deposited in the trench 404 using a damascene process known to those skilled in the art of microelectronic device manufacturing. In one embodiment, the conductive layer is deposited on the seed layer in the trench 404 using a selective deposition technique, such as, but not limited to, electroplating, electroless, CVD, PVD, MBE, MOCVD, ALD, spin-on, or other deposition technique known to those skilled in the art of microelectronic device manufacturing.
[0072]
[0088] In some embodiments, the selection of the material of the conductive layer 503 of the conductive line 603 determines the selection of the material of the seed layer. For example, if the material of the conductive line 1003 includes copper, the material of the seed layer also includes copper. In some embodiments, the conductive line 603 includes a metal, such as copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hi), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Au), platinum Pl, indium (In), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), zinc (Zn), cadmium (Cd), or any combination thereof.
[0073]
[0089] In alternative embodiments, examples of conductive materials that may be used for the conductive lines 603 of the metallization layer Mx include, but are not limited to, metals, such as copper, tantalum, tungsten, ruthenium, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof.
[0074]
[0090] In some embodiments, the composition of the conductive lines is similar to the first material 110 described above.
[0075]
[0091] Referring to FIG. 6, in some embodiments, chemical mechanical polishing ("CMP") techniques well known to those skilled in the art of microelectronic device manufacturing are used to remove portions of conductive layer 503 to make the top of conductive line 603 uniform with the top of insulating layer 402.
[0076]
[0092] In one non-limiting example, the thickness of the conductive lines 603 is approximately in the range of about 15 nm to about 1000 nm. In one non-limiting example, the thickness of the conductive lines 603 is approximately in the range of about 20 nm to about 200 nm. In one non-limiting example, the width of the conductive lines 603 is approximately in the range of about 5 nm to about 500 nm. In one non-limiting example, the spacing (pitch) between the conductive lines 603 is approximately in the range of about 2 nm to about 500 nm. In a more specific non-limiting example, the spacing (pitch) between the conductive lines 603 is approximately in the range of about 5 nm to about 50 nm.
[0077]
[0093] In some embodiments, the lower metallization layer Mx is configured to connect to other metallization layers (not shown) In some embodiments, the metallization layer Mx is configured to provide electrical contact to electronic devices, such as transistors, memories, capacitors, resistors, optoelectronic devices, switches, and any other active and passive electronic devices separated by an electrical insulating layer, such as an interlayer dielectric, a trench insulating layer, or any other insulating layer known to those skilled in the art of electronic device manufacturing.
[0078]
[0094] Figure 7 is a view similar to Figure 6 after the conductive lines 603 have been recessed in accordance with some embodiments. The conductive lines 603 are recessed to a predetermined depth to form recessed conductive lines 703. As shown in Figure 7, trenches 702 are formed in the insulating layer 402. Each trench 702 has sidewalls 704 that are part of the insulating layer 402 and a bottom that is a top surface 705 of the recessed conductive lines 603.
[0079]
[0095] In some embodiments, the depth of trench 702 is about 10 nm to about 500 nm. In some embodiments, the depth of trench 702 is about 10% to about 100% of the thickness of the conductive line. In some embodiments, conductive line 603 is recessed using one or more wet etches, dry etches, or a combination of techniques well known to those skilled in the art of electronic device manufacturing.
[0080]
[0096] FIG. 8 is a view similar to FIG. 7 after self-aligned selective growth pillars 801 have been formed on the recessed conductive lines 703, according to one or more embodiments. The self-aligned selective growth pillars 801 may be formed according to methods described herein for forming carbon pillars 330. As shown in FIG. 8, the array of self-aligned selective growth pillars 801 has the same pattern as the set of recessed conductive lines 703. As shown in FIG. 8, the pillars 801 extend substantially perpendicularly from the top surface of the recessed conductive lines 703. As shown in FIG. 8, the pillars 801 extend in the same direction as the conductive lines 603. As shown in FIG. 8, the pillars 801 are separated by gaps 803. In some embodiments, the height 805 of the pillars 801 is approximately in the range of about 5 angstroms (Å) to about 10 microns (μm).
[0081]
[0097] Figure 9 is a view similar to Figure 8 after a second insulating layer 901 has been deposited to overfill the gaps between pillars 801, according to some embodiments. For convenience, the second insulating layer 901 may also be referred to simply as insulating layer 901. As shown in Figure 9, the insulating layer 901 is deposited on opposing sides 902 and tops 903 of the pillars 801, and through the gaps 803 of the portions of the insulating layer 402 between the pillars 801.
[0082]
[0098] In some embodiments, the insulating layer 901 is a low-k gap-fill layer. In one embodiment, the insulating layer 901 is a flowable silicon oxide (FSiOx) layer. In some embodiments, the insulating layer 901 is an oxide layer, such as silicon dioxide, or any other electrically insulating layer as determined by the electronic device design. In some embodiments, the insulating layer 901 is an interlayer dielectric (ILD). In some embodiments, the insulating layer 901 is a low-k dielectric, including but not limited to materials such as silicon dioxide, silicon oxide, carbon-based materials, such as porous carbon films, carbon-doped oxides ("CDO"), such as carbon-doped silicon dioxide, porous silicon dioxide, porous silicon oxide carbide hydride (SiOCH), silicon nitride, or any combination thereof. In some embodiments, the insulating layer 901 is a dielectric material having a dielectric constant value less than 3. In some embodiments, insulating layer 901 is a dielectric material having a dielectric constant value approximately in the range of about 2.2 to about 2.7. In some embodiments, insulating layer 901 comprises a dielectric material having a dielectric constant value of less than 2. In some embodiments, insulating layer 901 represents one of the insulating layers described above with respect to insulating layer 402.
[0083]
[0099] In some embodiments, insulating layer 901 is a low-k interlayer dielectric to separate one metal line from another. In some embodiments, insulating layer 901 is deposited using one of a number of deposition techniques, such as, but not limited to, CVD, spin-on, ALD, PVD, MBE, MOCVD, or other low-k insulating layer deposition techniques known to those skilled in the art of microelectronic device manufacturing.
[0084]
[0100] 10 is a view similar to FIG. 9 after the second insulating layer 901 has been chemically mechanically planarized (CMP) to expose the tops 903 of the pillars 801. The CMP process can be any suitable planarization process known to those of skill in the art. In some embodiments, the second insulating layer 901 is deposited such that the tops of the insulating layer 901 are level with or slightly below the tops 903 of the pillars 801, and no CMP process is performed.
[0085]
[0101] Figure 11 is a view similar to Figure 10 after pillars 801 have been removed to form trenches 1101. Etching can be performed by any suitable etching technique known to those of skill in the art in this portion of the process, or any other portion of the process incorporating etching. In some embodiments, the etching process is one or more dry etches or wet etches.
[0086]
[0102] 12 is a view similar to FIG. 11 after deposition of an etch stop layer 1201 on the second insulating layer 901. The etch stop layer 1201 is optional and may be absent in some embodiments. In some embodiments, the etch stop layer may be AlO x Without being bound by theory, the etch stop layer 1201 may be particularly useful when the second insulating layer 901 and the third insulating layer 1301 are similar in composition.
[0087]
[0103] FIG. 13 is a view similar to FIG. 12 after gap filling trench 1101 with third insulating layer 1301. Third insulating layer 1301 fills trench 1101 and contacts etch stop layer 1201 (as shown) or recessed conductive line 703 (if etch stop layer 1201 is not present). Third insulating layer 1301 can be any suitable dielectric material as described above with respect to insulating layer 402 or second insulating layer 901. In some embodiments, third insulating layer 1301 comprises a flowable film. In some embodiments, the flowable film comprises one or more of silicon oxide or silicon oxycarbide. In some embodiments, third insulating layer 1301 comprises a spin-on low-k material.
[0088]
[0104] 13, the third insulating layer 1301 has a height that is greater than the pillars 801. In other words, the thickness of the third insulating layer 1301 is thick enough to cover the pillars 801. In some embodiments, the third insulating layer 1301 is formed such that the top of the third insulating layer 1301 is substantially flush with the pillars 801 or slightly below the tops 903 of the pillars 801.
[0089]
[0105] Figure 14 is a view similar to Figure 13 after selectively etching the third insulating layer 1301 and etch stop layer 1201 (if present) to form via opening 1401 and expose recessed conductive line 703. In some embodiments, the third insulating layer 1301 may be selectively etched by a dual damascene etch process.
[0090]
[0106] The dual damascene etch can be performed by any suitable method known to one of ordinary skill in the art. Briefly, a mask (not shown) is applied or placed adjacent to the insulating layer 1301 and an etching process is performed through the mask. The etching process penetrates the insulating layer 1301. The sides of the etching process may extend to the sides of the insulating layer 402 and the second insulating layer 901. The etching removes the etch stop layer 1201 between the adjacent stacks of the insulating layer 402 and the second insulating layer 901, exposing the recessed conductive line 703. The top view shows a rectangular etch in the insulating layer 1301 exposing the recessed conductive line 703, along with the etch stop layer 1201 surrounding the via opening 1401.
[0091]
[0107] 15 is a view similar to FIG. 14 after depositing a second conductive material 1501 in the via openings 1401. In some embodiments, the second conductive material 1501 is deposited to form a second conductive line connecting the multiple via openings. The second conductive material 1501 may be any suitable metal and may be deposited by any suitable deposition technique. The second conductive line extends in a second direction that is different from the first direction of the first conductive line described above.
[0092]
[0108] As used throughout this specification, the terms "one embodiment," "particular embodiment," "one or more embodiments," or "embodiments" mean that a particular feature, structure, material, or characteristic described in connection with an embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in a particular embodiment," "in one embodiment," or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.
[0093]
[0109] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made in the disclosed methods and apparatus without departing from the spirit and scope of the disclosure. Thus, it is intended that the present disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.
Claims
1. 1. A method for selectively depositing a carbon film, comprising: providing a substrate comprising a first material and a second material, the first material having an exposed first material surface and the second material having an exposed second material surface, the first material comprising a metal; exposing the substrate to a carbon precursor to form a carbon film having a first thickness on the exposed first material surface and a second thickness on the exposed second material surface, the first thickness being greater than the second thickness; The method includes:
2. The method of claim 1 , wherein the first material comprises a substantially pure metal or a metal alloy.
3. The method of claim 1 , wherein the first material comprises a metal nitride, a metal carbide, a metal silicide, a metal oxide, a metal sulfide, a metal selenide, a metal telluride, or a combination thereof.
4. The method of claim 1 , wherein the second material comprises a dielectric material.
5. The method of claim 1 , wherein the carbon precursor further comprises hydrogen gas, nitrogen gas, or argon gas.
6. 1. A method of forming a carbon pillar, comprising: providing a substrate comprising a first metal-containing material and a second dielectric material, the first metal-containing material having an exposed first surface having a first dimension and the second dielectric material having an exposed second surface, the exposed first surface and the exposed second surface forming a substrate surface; exposing the substrate to a carbon precursor to form carbon pillars comprising a carbon material on the exposed first surface, the carbon pillars and the exposed first surface having the same first dimension; The method includes:
7. The method of claim 6 , wherein the first metal-containing material comprises cobalt.
8. The method of claim 6 , wherein the carbon precursor comprises at least one unsaturated bond.
9. The method of claim 6 , wherein the carbon precursor comprises hydrogen gas, nitrogen gas, or argon gas.
10. The method of claim 6 , wherein the exposed second surface is substantially free of deposited carbon material.
11. 7. The method of claim 6, wherein the exposed first surface is recessed from the exposed second surface to form a substrate feature, the substrate feature including at least one sidewall of the second dielectric material and a bottom of the exposed first surface, and the carbon pillar extends above the exposed second surface.
12. The method of claim 11 , wherein the carbon pillars have sides that are substantially perpendicular to the substrate surface.
13. 1. A method of forming a self-aligned via, comprising the steps of: recessing a first conductive line on a first insulating layer on a substrate, the first conductive line extending along a first direction on the first insulating layer; forming a carbon pillar on the recessed first conductive line; depositing a second insulating layer between the carbon pillars; removing the carbon pillars to form trenches in the second insulating layer; depositing a third insulating layer over the recessed first conductive line in the trench to form a filled trench; selectively etching the third insulating layer from the filled trench to form a via opening to the first conductive line; The method includes:
14. 14. The method of claim 13, further comprising depositing a substantially conformal etch stop layer after removing the carbon pillars and before depositing the third insulating layer.
15. depositing a second conductive material in the via opening; depositing a plurality of second conductive lines on the second insulating layer and in contact with the second conductive material in the via opening, the second conductive lines extending along a second direction on the second insulating layer; The method of claim 13 further comprising: