Light-emitting device

Abstract

To provide a display device having an excellent boosting function.SOLUTION: The display device is provided with pixels having a function for adding data (boosting function). A boosting capacitor is provided in the pixel, which adds the data by capacitive coupling and supplies the data to the display device. By arranging the boosting capacitor and a data holding capacitor in an overlapping manner, a capacitance value of the boosting capacitor can be increased. Thus, the excellent boosting function can be given to the pixel without significantly impairing an aperture ratio or fineness.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, operation method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] A technology for constructing a transistor using a metal oxide formed on a substrate is attracting attention. For example, a transistor using zinc oxide or an In-Ga-Zn oxide is used for the display device. The technology used for the switching element is disclosed in Patent Document 1 and Patent Document 2. .

[0005] In addition, a memory device using a transistor with extremely low off-state current as a memory cell is disclosed in the patent document This is disclosed in reference 3. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A [Patent Document 3] JP 2011-119674 A Summary of the Invention [Problem to be solved by the invention]

[0007] A general display device is used to drive a dispersion type liquid crystal device and a tandem type light emitting device. This requires a voltage higher than the driving voltage of the chair.

[0008] In such a case, a high-output source driver is used, or a boost function is added to the pixel circuit. A voltage higher than the output of the source driver may be generated and supplied to the display device. In this case, a general pixel circuit can be used, but the cost and power consumption of the source driver are There is a problem with it getting higher.

[0009] In the latter case, a general-purpose source driver can be used. By applying a boost function to drive the source driver, the output voltage of the source driver can be reduced. However, if a boosting function is provided in the pixel, elements such as transistors, capacitors, and wiring will be required. Therefore, the boosting capability and the pixel aperture ratio or definition are It's a trade-off.

[0010] An object of one embodiment of the present invention is to provide a display device having an excellent boosting function. Alternatively, a display device having both an excellent boosting function and a high aperture ratio or high definition is provided. One of the purposes is to provide a display device with a voltage equal to or higher than the output voltage of the source driver. It is an object of the present invention to provide a display device that can be supplied to a display device. It is an object of the present invention to provide a display device capable of increasing the brightness of an image.

[0011] Another object is to provide a display device with low power consumption. One of the objectives is to provide a display device that is easy to use. Another objective is to provide a new display device, etc. Another object of the present invention is to provide a method for driving the display device. Another object is to provide a novel semiconductor device or the like.

[0012] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0013] One embodiment of the present invention relates to a display device having an excellent boosting function.

[0014] One aspect of the present invention is a liquid crystal display device having a first capacitor, a second capacitor, and a display element in a pixel. The first capacitor and the second capacitor are electrically connected to the display element. The capacitor has a structure in which a first conductive layer, a first dielectric layer, and a second conductive layer are laminated in that order. The second capacitor has a structure in which a second conductive layer, a second dielectric layer, and a third conductive layer are arranged in that order. The first capacitor and the second capacitor are stacked in this order. A display device having an area.

[0015] The second capacitor preferably has a larger capacitance than the first capacitor.

[0016] The pixel further includes a first transistor, a second transistor, and a third transistor; one of the source and drain of the first transistor is electrically connected to the second conductive layer one of the source and drain of the second transistor and the third transistor One of the source or drain can be electrically connected to the third conductive layer.

[0017] The pixel has a light-emitting element as a display element, and the pixel further has a fourth transistor and a fifth transistor. a fourth transistor, the gate of which is electrically connected to the second conductive layer; The source or drain of the fourth transistor is connected to the source of the fifth transistor. Alternatively, one of the drain electrodes and one of the electrodes of the light emitting element are electrically connected to the third conductive layer. It is possible.

[0018] Alternatively, the pixel has a liquid crystal element as a display element, and one electrode of the liquid crystal element is a second conductive The layer can be electrically connected.

[0019] The first to third transistors each have a metal oxide in a channel formation region. It is preferable that the second conductive layer comprises a metal oxide. In, Zn, and M (M is Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, It is preferable that the alloy has at least one of these metals, i.e., Nd or Hf). Effect of the Invention

[0020] By using one embodiment of the present invention, a display device having an excellent boosting function can be provided. Alternatively, a display device having both an excellent boosting function and a high aperture ratio or high definition is provided. Alternatively, a voltage higher than the output voltage of the source driver can be supplied to the display device. It is possible to provide a display device capable of increasing the brightness of a displayed image. It is possible to provide a display device capable of doing so.

[0021] Alternatively, a display device with low power consumption can be provided. Alternatively, a novel display device or the like can be provided. It is also possible to provide a method for operating the display device. Alternatively, a novel semiconductor device or the like can be provided. It can be provided. [Brief description of the drawings]

[0022] [Figure 1] FIG. 1 is a diagram illustrating a pixel circuit. [Diagram 2] 2A and 2B are diagrams illustrating the configuration of a capacitor. [Diagram 3] 3A and 3B are diagrams illustrating the configuration of a capacitor. [Figure 4] 4A to 4C are diagrams illustrating a pixel circuit. [Diagram 5] FIG. 5 is a diagram illustrating a pixel circuit. [Figure 6] FIG. 6 is a timing chart illustrating the operation of the pixel circuit. [Figure 7] Fig. 7A is a diagram illustrating a pixel circuit, and Fig. 7B is a diagram illustrating a configuration of a capacitor. [Figure 8]8A and 8B are diagrams illustrating a pixel circuit. [Figure 9] FIG. 9 is a diagram illustrating a pixel circuit. [Figure 10] FIG. 10 is a diagram illustrating a pixel circuit. [Figure 11] FIG. 11 is a diagram illustrating a pixel circuit. [Figure 12] 12A and 12B are diagrams for explaining a pixel layout. [Figure 13] 13A and 13B are diagrams for explaining a pixel layout. [Figure 14] 14A and 14B are diagrams for explaining a pixel layout. [Figure 15] 15A to 15C are diagrams illustrating pixel layouts. [Figure 16] 16A and 16B are diagrams for explaining a pixel layout. [Figure 17] 17A and 17B are diagrams for explaining a pixel layout. [Figure 18] 18A and 18B are diagrams for explaining a pixel layout. [Figure 19] FIG. 19 is a diagram illustrating a display device. [Figure 20] 20A to 20C are diagrams illustrating a display device. [Figure 21] 21A and 21B are diagrams illustrating a touch panel. [Figure 22] 22A and 22B are diagrams illustrating a display device. [Figure 23] FIG. 23 is a diagram illustrating a display device. [Figure 24] 24A and 24B are diagrams illustrating a display device. [Diagram 25] 25A and 25B are diagrams illustrating a display device. [Figure 26] 26A to 26E are diagrams illustrating a display device. [Figure 27] 27A to 27C are diagrams illustrating transistors. [Figure 28] 28A to 28C are diagrams illustrating transistors. [Figure 29] 29A and 29B are diagrams illustrating a transistor. [Diagram 30] 30A to 30F are diagrams illustrating an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention may be modified in various ways in form and detail without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0024] In addition, even if a circuit diagram shows a single element, it may not have any functional problems. If there is no need for a single element, the element may be composed of multiple elements. For example, In some cases, multiple resistors may be connected in series or parallel. In some cases, the signal processing unit 10 may be divided and placed in multiple positions.

[0025] In addition, one conductor may have multiple functions such as wiring, electrodes, and terminals. In this specification, the same element may be referred to by multiple names. Even if the circuit diagram shows direct connections between elements, in reality The elements may be connected via one or more conductors, and in this specification This configuration is also included in the category of direct connection.

[0026] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0027] One embodiment of the present invention is a display device provided with a pixel having a function of adding data (a boosting function). The pixel is a pixel that is arranged to receive first data and second data supplied from a source driver. The third data is then output to a display device (also called a display element). Therefore, it can display a voltage higher than the voltage output from the source driver. It is possible to supply a display device with a relatively high operating voltage to a general-purpose source driver. Alternatively, the output voltage of the source driver can be reduced. This allows the display device to operate with reduced power consumption.

[0028] To enhance the boost function, it is preferable to use a capacitor with a relatively large capacitance. However, there is a trade-off between the area of ​​the capacitor and the aperture ratio of the pixel or the resolution of the pixel array. In one embodiment of the present invention, a boost capacitor and a data storage capacitor are By stacking the bottom layers, the area occupied by the boost capacitor and the capacitance value are increased. Therefore, it is possible to provide excellent boosting function to the pixels without significantly compromising the aperture ratio or definition. It can be given.

[0029] FIG. 1 is a circuit diagram of a pixel included in a display device of one embodiment of the present invention. A transistor 101, a transistor 102, a transistor 103, and a transistor 104, A transistor 105, a capacitor 106, a capacitor 107, and a light emitting device 108. The light-emitting device is also called a light-emitting element.

[0030] One of the source and drain of the transistor 101 is connected to one electrode of the capacitor 107. The gate of the transistor 104 and one electrode of the capacitor 106 are electrically connected to each other. The other electrode of the capacitor 107 is connected to one of the source and drain of the transistor 102. and electrically connected to one of the source and drain of the transistor 103. One of the source or drain of the transistor 104 is connected to the source or drain of the transistor 105. One of the electrodes of the input terminal is connected to one electrode of the light emitting device 108 and the other electrode of the capacitor 106. are electrically connected.

[0031] The capacitor 107 has a function of adding data by capacitive coupling. The pixel has a boosting function. The capacitor 106 has a function of retaining data.

[0032] As shown in FIG. 1 and the above description, the capacitor 106 and the capacitor 107 are electrically connected in series. Therefore, one electrode of the capacitor 106 and one electrode of the capacitor 107 are connected to each other. A common conductive layer can be used for one of the electrodes 07.

[0033] 2A and 2B are conventional examples of layouts, and the capacitor 1 in the pixel circuit shown in FIG. 2A shows a simplified layout of the MOSFET 106 and the capacitor 107. 2B also shows the electrical connections with other elements. FIG. 1 is a cross-sectional view taken along line 1-A2.

[0034] The capacitor 107 is configured by laminating a conductive layer 51, a dielectric layer 61, and a conductive layer 52. The capacitor 106 is configured by laminating a conductive layer 53, a dielectric layer 61, and a conductive layer 52. The conductive layer 51 and the conductive layer 53 are formed from a conductive film formed in the same process. Moreover, the conductive layer 52 can be used as a common electrode.

[0035] In this way, the process for forming the capacitors 106 and 107 and the structure thereof are simple. However, since they are formed side by side in a limited area, the capacitance values ​​of each are mutually correlated. It becomes a dead-end relationship.

[0036] 3A and 3B are schematic diagrams of capacitor 106 and capacitor 107 according to one embodiment of the present invention. FIG. 3A is a top view showing the electrical connections to other elements. Fig. 3B is a cross-sectional view taken along dashed line B1-B2 shown in Fig. 3A. .

[0037] The capacitor 107 is configured by laminating a conductive layer 51, a dielectric layer 61, and a conductive layer 52. The capacitor 106 is formed by stacking a conductive layer 52, a dielectric layer 62, and a conductive layer 54. The above configuration can be adopted.

[0038] In other words, the capacitors 106 and 107 share the conductive layer 52 as a common electrode. Therefore, the capacitor 106 and the capacitor 107 may have an overlapping area. The 07 is less subject to area constraints, allowing for greater design freedom.

[0039] The capacitor 107 is also arranged in the area where the capacitor 106 in the conventional example is arranged. The area (capacitance value) of the capacitor 107 can be increased. In addition, the dielectric layer 62 and the conductive layer 54 are provided with a conductor. Since elements forming transistors, etc. are used, no additional steps are required. The physical layout will be described in detail later.

[0040] The connection between the elements of the pixel shown in FIG. 1 and various wirings will be described. The gate of the transistor 102 is electrically connected to a wiring 126. The gate of the transistor 103 is electrically connected to the wiring 125. A gate of the transistor 105 is electrically connected to a wiring 127.

[0041] The other of the source and the drain of the transistor 101 is electrically connected to a wiring 121. The other of the source and the drain of the transistor 102 is electrically connected to a wiring 122. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 124. The other of the source and the drain of the transistor 104 is electrically connected to the wiring 123. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 124. The other electrode of the light emitting device 108 is electrically connected to a wiring 129.

[0042] The wirings 125, 126, and 127 function as gate lines and are electrically connected to the gate driver. The wirings 121 and 122 function as source lines, and The driver can be electrically connected to the

[0043] The wirings 123 and 129 can function as power supply lines. For example, the wiring 123 A high potential is supplied to the wiring 129 and a low potential is supplied to the wiring 129, so that the light emitting device 108 is sequentially turned on. It can be bias operated (light emitting).

[0044] The wiring 124 is connected to a reference potential (V ref ) can be provided. For example, V ref " can be 0V, GND potential, etc. Or, a specific potential "V ref " can also be used.

[0045] Here, one of the source or drain of the transistor 101 and one of the capacitors 106 A wiring that connects the electrode of the transistor 104, one electrode of the capacitor 107, and the gate of the transistor 104. The line is a node NM. One of the source or drain of the transistor 102 and the capacitor The other electrode of the transistor 107 is connected to either the source or the drain of the transistor 103. The wiring is designated as node NA.

[0046] The transistor 101 can write the potential of the wiring 121 to the node NM. The transistor 102 has a function of writing the potential of the wiring 122 to the node NA. The transistor 103 supplies a reference potential (V ref ) function The transistor 104 may have a light emitting device according to the potential of the node NM. The transistor 105 can have a function of controlling the current flowing to the node 108. A function of fixing the source potential of the transistor 104 when writing data to the NM, and It may have the ability to control the timing of the operation of the light device 108 .

[0047] The node NM is connected to the node NA through the capacitor 107. When node NM is in a floating state, the potential change of node NA is added by capacitive coupling. The addition of the potential at the node NM will now be described.

[0048] First, the first data (weight: “W”) is written to the node NM. At this time, is the reference potential “V ref " is supplied to the capacitor 107, and "WV ref " to be held Next, the node NA is made floating and the second data (data: “D”) is input to the node NA. ) to supply.

[0049] At this time, the capacitance of the capacitor 107 is C 107 , the capacitance value of node NM is C NM So, The potential of the node NM is "W+(C 107 / (C 107 +C NM ))×(DV ref ) " where C 107 Increase the value of C NM If we can ignore the value of “C 107 / (C 107 +C NM )" approaches 1, and the potential of node NM becomes "W+DV ref " and everyone Can.

[0050] Therefore, “W” = “D”, “V ref "=0V, and C 107 C NM Compared to If it is large enough, the potential of the node NM approaches "2D". In other words, the output of the source driver Thus, a third data ("2D") having a potential approximately twice as high as the first data ("2D") can be generated at the node NM.

[0051] In addition, “V ref If "is "-W" or "-D", the potential of node NM is set to "3D". You can also get closer.

[0052] The pixel's boost function allows the light-emitting device 10 to operate even if the output voltage of the source driver is small. 8, the voltage required for the operation of the light emitting device 108 can be generated to operate properly. This can be done.

[0053] As described above, the capacitance of the capacitor 107 is determined by the capacitance of the node NM (including the capacitor 106). In one embodiment of the present invention, the capacitance value of the capacitor 106 is preferably sufficiently larger than that of the capacitor 106. Since the capacitor 107 is formed to have an overlapping area, the capacitor It is easy to increase the area occupied by the capacitor 107. It is easy to increase the potential, and the potential addition function (boosting function) described above can be improved. Cut.

[0054] Nodes NM and NA act as holding nodes. Transistors connected to each node By turning on the transistor, data can be written to each node. By making the transistor non-conductive, the data can be held in each node. By using a transistor with extremely low off-state current as the resistor, leakage current can be suppressed. This makes it possible to hold the potential of each node for a long period of time. In this study, we used a transistor that uses a metal oxide for the channel formation region (hereafter, OS transistor). It is preferable that

[0055] Specifically, an OS transistor is applied to any one of the transistors 101, 102, and 103. Alternatively, it is preferable to use OS transistors for all the transistors in a pixel. Also, when operating within an allowable range of leakage current, Si may be used as a channel. A transistor having a gate electrode formed in the gate insulating film (hereinafter, referred to as a silicon transistor) may be used. In addition, an OS transistor and a Si transistor may be used in combination. The transistors used are those with amorphous silicon, those with crystalline silicon (microcrystalline Silicon, low-temperature polysilicon, single crystal silicon) .

[0056] The semiconductor material used for the OS transistor is preferably a material having an energy gap of 2 eV or more. Alternatively, a metal oxide having a polarization of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium. -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Since it exhibits high mobility characteristics, it is suitable for use in transistors that operate at high speed.

[0057] Since the energy gap of the semiconductor layer of the OS transistor is large, the current is several yA / μm (channel The device exhibits extremely low off-state current characteristics, with a current value per 1 μm of filter width. OS transistors have many drawbacks, such as impact ionization, avalanche breakdown, and short channel effects. Unlike silicon transistors, it has characteristics such as no defects such as SiO2, and can form highly reliable circuits. In addition, the electrical conductivity caused by the non-uniformity of crystallinity, which is a problem in silicon transistors, can be reduced. OS transistors are also less likely to have variations in characteristics.

[0058] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (M is aluminum). Umium, titanium, gallium, germanium, yttrium, zirconium, lanthanum, and selenium In-MZ containing one or more of the following metals: tin, neodymium, or hafnium The film can be expressed as an n-type oxide. Representative examples of In-M-Zn-type oxides include: It can be formed by sputtering or ALD (Atomic Layer Deposition). Alternatively, the insulating layer 14 may be formed by a deposition method.

[0059] A sputtering tube used to form In-M-Zn oxide by sputtering. The atomic ratio of the metal elements in the get preferably satisfies In≧M and Zn≧M. The atomic ratio of the metal elements in the sputtering target is In:M:Zn=1:1:1. , In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4 :2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M: The preferred ratios are Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratio of each layer is the atomic ratio of the metal elements contained in the sputtering target. This includes a variation of plus or minus 40% in the ratio.

[0060] The semiconductor layer is made of an oxide semiconductor having a low carrier density. Carrier density is 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 Further details are below. Preferably 1 x 1013 / cm 3 Less than or equal to 1×10 11 / cm 3 The following is further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than 10 ... Such oxide semiconductors can be used as high-purity intrinsic or substantially high-purity oxide semiconductors. This oxide semiconductor has a low density of defect states and has stable characteristics. It can be said that this is an oxide semiconductor that

[0061] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer are determined. It is preferable to appropriately set the density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. stomach.

[0062] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is contained, oxygen vacancies increase and the semiconductor layer becomes n-type. The concentrations of cations and carbon (obtained by secondary ion mass spectrometry) were calculated using a ratio of 2×10 18 atom s / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0063] In addition, alkali metals and alkaline earth metals generate carriers when bonded to oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration that can be obtained is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 a toms / cm 3 To the following:

[0064] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, the electrons that serve as carriers This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5×10 18 atoms / cm 3 It is preferable to do the following:

[0065] In addition, when hydrogen is contained in the oxide semiconductor that constitutes the semiconductor layer, the oxide that bonds with the metal atom Since oxygen reacts with oxygen to form water, oxygen vacancies may be formed in the oxide semiconductor. If the channel formation region in the conductor contains oxygen vacancies, the transistor will be normally on. In addition, defects in which hydrogen has entered an oxygen vacancy can act as donors and In addition, some of the hydrogen atoms bond with the metal atoms, resulting in the generation of carrier electrons. It may combine with hydrogen to generate electrons, which are carriers. A transistor including an oxide semiconductor having such a structure tends to be normally-on.

[0066] A defect in which hydrogen has entered an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate the defects. Therefore, in this specification, the acid concentration is evaluated based on the carrier concentration. As a parameter of the compound semiconductor, we assume a state in which no electric field is applied, rather than the donor concentration. In other words, the "carrier concentration" described in this specification and the like is This can sometimes be rephrased as "donor concentration."

[0067] Therefore, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. In oxide semiconductors, secondary ion mass spectrometry (SIMS) The hydrogen concentration obtained by mass spectrometry was calculated as 1×10 20 a toms / cm 3 Less than 1 x 10 19 atoms / cm 3 Less than, more preferably is 5 x 10 18 atoms / cm 3 less than 1×10 18 atoms / c m 3 The oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used as the transistor chip. By using it in the channel forming region, stable electrical characteristics can be imparted.

[0068] The semiconductor layer may also have a non-single crystal structure. The non-single crystal structure may have a c-axis oriented structure. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystal structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0069] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not contain a crystalline component. Alternatively, the oxide film having an amorphous structure is, for example, a completely amorphous structure having no crystal parts. stomach.

[0070] In addition, the semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC structure region, or a crystalline structure region. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminate structure. It may have a structure.

[0071] In the following, we will discuss a CAC (Cloud-Aligned Crystalline) semiconductor layer, which is one form of a non-single crystal semiconductor layer. This article explains the configuration of the omposite OS.

[0072] CAC-OS is, for example, an oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are present in the oxide semiconductor. The region having the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixture of particles with sizes of 2 nm or more or less, or close to that size, in a mosaic or patch pattern It is also called.

[0073] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more of the following: tantalum, tungsten, or magnesium. It may be included.

[0074] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide is one of the CAC-OS) a-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0.) or indium zinc oxide In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (GaO X3 (X3 is a real number greater than 0) . ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0. The material is separated into a mosaic shape. The mosaic InO X1 , or In X2 Zinc Y2 O Z2 was distributed uniformly in the film. This is a cloud-like configuration.

[0075] In other words, CAC-OS is X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Assume that the In concentration is higher than in region 2.

[0076] IGZO is a common name and refers to a compound made of In, Ga, Zn, and O. A typical example is InGaO3(ZnO). m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O3(ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of the crystalline compounds include those which are

[0077] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0078] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. In a material composition containing a, Zn, and O, some of the nanoparticles are observed to be mainly composed of Ga. The regions where the In nanoparticles are observed are the same as those where the In nanoparticles are observed as the main component. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0079] It should be noted that the CAC-OS does not include a laminated structure of two or more films having different compositions. For example, a structure consisting of two layers, a film mainly made of In and a film mainly made of Ga, is not included. do not have.

[0080] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 but In some cases, it may be difficult to observe a clear boundary between the region that is the main component and the region that is the main component.

[0081] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected types of sodium, etc. are included, CAC-OS will The region observed is a nanoparticle of the metal element as the main component, and the region observed is a nanoparticle of In as the main component. The nanoparticle-like regions are randomly distributed in a mosaic pattern. say.

[0082] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas and The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. Or, it is preferable to set it to 0% or more and 10% or less.

[0083] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, no clear peaks are observed from the X-ray diffraction measurement. It can be seen that the orientation of the regions in the ab plane direction and the c-axis direction is not observed.

[0084] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron diffraction pattern obtained by irradiating the sample, a ring-shaped area of ​​high brightness (phosphorescence) is observed. The electron diffraction pattern is a ring region, and multiple bright spots are observed in the ring region. Therefore, the crystal structure of CAC-OS does not have orientation in the planar direction and the cross-sectional direction. It can be seen that it has a nano-crystal structure.

[0085] For example, in the CAC-OS of In-Ga-Zn oxide, the energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) The EDX mapping obtained using scopy revealed that GaO X3 The area where is the main component And, In X2 Zinc Y2 O Z2 , or InO X1 The areas where the main component is It can be confirmed that the compound has a structure similar to that shown in FIG.

[0086] CAC-OS has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It has different properties from ZO compounds. That is, CAC-OS is GaO X3 The main ingredients are In a certain area, X2 Zinc Y2 O Z2 , or InO X1 The region where is the main component and The phase is separated into two layers, and the regions each containing one element as a main component are arranged in a mosaic pattern.

[0087] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y 2O Z2 , or InO X1 The carriers flow through the area where the main component is oxidized. Therefore, the In X2 Zinc Y2 O Z2 , or In O X1 The region in which the main component is distributed in a cloud-like shape in the oxide semiconductor is a region in which a high electric field Effective mobility (μ) can be achieved.

[0088] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InO X This region has higher insulating properties than the region where GaO X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching performance. Switching operation can be achieved.

[0089] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Absolutely no Relationship and In X2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the By using this, a high on-current (I on ), and high field-effect mobility (μ It is possible.

[0090] In addition, semiconductor devices using CAC-OS have high reliability. S is suitable as a constituent material for various semiconductor devices.

[0091] Note that the circuit configuration of the pixel shown in FIG. 1 is an example. For example, as shown in FIG. One electrode of the light-emitting device 108 is electrically connected to the wiring 123, and the other electrode of the light-emitting device 108 is The pole may be electrically connected to the other of the source or drain of the transistor 104 .

[0092] Alternatively, as shown in FIG. 4B, one of the source or drain of the transistor 104 and the light emitting diode A transistor 109 is connected between one electrode of the device 108 and the transistor 109. By providing the transistor 109, the timing of light emission can be arbitrarily controlled. In addition, the configurations shown in Figures 4A and 4B may be combined.

[0093] As shown in FIG. 4C, the wiring 124 connected to the transistor 105 is connected to the circuit 40. The circuit 40 can be electrically connected to a reference potential (V ref ) source, Trans The sensor 104 has at least one of a function for acquiring electrical characteristics of the sensor 104 and a function for generating correction data. It is possible.

[0094] Also, as shown in FIG. 5, in the vertical direction (the direction in which the source lines (wirings 121 and 122) extend), The gate line (wiring 125) may be shared between two adjacent pixels. Pixel 10[n,m] located in row and column m (n and m are natural numbers greater than or equal to 1) and pixel 10[n,m] located in row n+1 FIG. 1 is a diagram illustrating a pixel 10[n+1,m] arranged in the mth column. The basic structure of the pixel 10 is as follows: 1, but the wiring 125 also functions as the wiring 126. Line 126 is omitted.

[0095] The gate of the transistor 102 in the pixel 10[n,m] is electrically connected to the wiring 125[n+1]. The wiring 125[n+1] is connected to the transistor 101 of the pixel 10[n+1,m]. and the gate of the transistor 103 are electrically connected to each other.

[0096] The gate of the transistor 102 of the pixel 10[n+1,m] is electrically connected to the wiring 125[n+2]. Although not shown in the figure, the wiring 125[n+2] is connected to the pixel 10[n+2, m], the gate of the transistor 101 and the gate of the transistor 103 are electrically connected to each other. can be.

[0097] In the pixel 10 according to one embodiment of the present invention, the writing of the first data (weight) and the writing of the second data ( There are two write operations: writing weights and writing data. The weights and data come from different source lines. The timing for writing data to one pixel and the timing for writing weights to the other pixel are Therefore, the timing of writing to the transistors The gates of the transistors can be connected to a common gate line.

[0098] By sharing the gate line between two pixels, the number of gate lines per pixel is effectively reduced from three to two. This allows the pixel aperture ratio to be increased, and the gate driver operation can be simplified. Since the gate wiring that requires simplification and charging / discharging is reduced, power consumption can also be reduced.

[0099] Next, the operation of the two pixels shown in FIG. 5 will be described with reference to the timing chart shown in FIG. The following description will be given of a data potential that is approximately twice the data potential output by the source driver due to the operation of the pixel 10. 4 is an example of an operation of supplying a data potential to a display device.

[0100] In this operation description, a high potential is represented by "H" and a low potential is represented by "L". The weight to be supplied to pixel 10[n+1,m] is “W1”, the image data is “D1”, and the weight to be supplied to pixel 10[n+1,m] is “D2”. The weight to be supplied is "W2" and the image data is "D2". ref For example, 0 V, GND potential or a specific potential can be used.

[0101] In addition, a high potential is constantly supplied to the wiring 123, and a low potential is constantly supplied to the wiring 129. The line 124 is connected to a reference potential (V ref ) is always supplied. If there is no potential, there may be a period during which these potentials are not supplied.

[0102] In addition, in the distribution, coupling, or loss of potential, the circuit configuration, operation timing, etc. Detailed changes due to capacitive coupling using a capacitor are not taken into account. Although the capacitance ratio of the capacitor to the connected element depends on the capacitance ratio of the capacitor, for the sake of clarity, Therefore, the capacitance value of the element is assumed to be sufficiently small.

[0103] In the period T1, the wiring 121 is supplied with "W1".

[0104] If the potential of the wiring 125[n] is set to “H” and the potential of the wiring 127[n] is set to “H” during the period T1, In the pixel 10[n,m], the transistor 102 is turned on, and the voltage at the node NA[n,m] The potential is “V ref This operation is a relay for the subsequent addition operation (capacitive coupling operation). This is a set operation.

[0105] In addition, the transistor 101 is turned on, and the potential of the wiring 121[m] is applied to the node NM[n,m]. Also, the transistor 105 is turned on, and the source potential of the transistor 104 is "V ref This operation is a weight writing operation for pixel 10[n,m]. Therefore, when the source potential of the transistor 104 is stable, the node NM[n,m] is supplied with a potential " W1” is written.

[0106] During the period T2, “W2” is supplied to the wiring 121, and “D1” is supplied to the wiring 122. will be done.

[0107] In the period T2, the potential of the wiring 125[n] is set to “L”, the potential of the wiring 127[n] is set to “H”, If the potential of 25[n+1] is “H” and the potential of wiring 127[n+1] is “H”, At this time, "W1" is held at node NM[n,m]. In addition, the capacitor 107 is ref " is retained.

[0108] In addition, the transistor 103 is non-conductive and the transistor 102 is conductive, so that the node NA[n ,m] becomes the potential “D1” of the wiring 122[m]. "D1-V ref " is connected to the node NM[n,m] according to the capacitance ratio of the capacitor 107 and the node NM[n,m]. NM[n,m]. This operation is an addition operation at pixel 10[n,m], The potential of node NM[n,m] is “W1+(D1-V ref )'". In this case, "V ref If "=0, the potential of the node NM[n,m] becomes "W1+D1'".

[0109] In addition, in pixel 10[n+1,m], the transistor 102 is turned on, and the node NA[n +1,m] is the potential of “V refThis operation is called the "capacitive coupling operation". This is a reset operation to perform the above.

[0110] In addition, the transistor 101 is turned on, and the potential of the wiring 121[m] is applied to the node NM[n+1,m]. Also, the transistor 105 is turned on, and the source voltage of the transistor 104 is The 1st place is "V ref This operation is to write the weight at pixel 10[n+1,m]. In this operation, the source potential of the transistor 104 is stable, and the node NM[n+1, m] is written with a potential “W2”.

[0111] In period T3, the wiring 122 is supplied with “D2”.

[0112] In the period T3, the potential of the wiring 127[n] is set to “L”, the potential of the wiring 125[n+1] is set to “L”, If the potential of the line 127[n+1] is set to “H” and the potential of the wiring 125[n+2] is set to “H”, In element 10[n,m], transistor 105 becomes non-conductive, and node NM[n,m] In response to the potential, a current flows through the transistor 104, causing the light-emitting device 108 to emit light.

[0113] In addition, in pixel 10[n+1,m], transistor 103 is non-conductive and transistor 1 02 becomes conductive, and the potential of the node NA[n+1,m] becomes the potential “D2” of the wiring 122[m]. At this time, the change in node NA, “D2-V ref " is the capacitor 107 and the node It is added to node NM[n+1,m] according to the capacity ratio of NM[n+1,m]. is an addition operation in pixel 10[n+1,m], and the potential of node NM[n+1,m] is "W2+(D2-V ref )'". In this case, "V refIf "=0, the node The potential of NM[n+1,m] becomes “W2+D2'”.

[0114] The potential of the wiring 127[n+1] is set to “L” and the potential of the wiring 125[n+2] is set to “L”. Then, in pixel 10[n+1,m], transistor 105 becomes non-conductive, and node A current flows through the transistor 104 in response to the potential of NM[n+1,m], and the light emitting device 10 8 lights up.

[0115] In the above operation, if W1=D1 or W2=D2, and the capacity of the node NM is If the capacitance of the capacitor 107 is sufficiently smaller than that of the capacitor 107, then "W1+D1'" is close to "2D1", W2+D2'" is close to "2D2". Therefore, the data output by the source driver A data potential approximately twice the data potential of the pixel can be supplied to the display device.

[0116] So far, we have explained examples of using light-emitting devices as display devices, but we have also considered liquid crystal devices (LCDs). FIG. 7A shows a pixel circuit using a liquid crystal device as a display device. One electrode of the liquid crystal device 110 is electrically connected to the node NM. The other electrode of the device 110 is electrically connected to the wiring 130. The other electrode of the pixel 131 is electrically connected to the wiring 131. Note that the elements common to the pixel shown in FIG. The same reference numerals are used and the description will be omitted.

[0117] FIG. 7B is a top view showing a simplified layout of the capacitors 106 and 107. The capacitors 106 and 107 have the same configuration as those shown in FIGS. 3A and 3B. It is possible.

[0118] The wiring 130 and the wiring 131 may be electrically connected. For example, the wirings 130 and 131 are connected to reference terminals such as GND and 0V. A potential or any arbitrary potential can be applied.

[0119] The other of the source and drain of the transistor 103 is electrically connected to the wiring 123. 8A, it may be electrically connected to the wiring 131. Alternatively, it may be electrically connected to the wiring 130. Alternatively, the other electrode of the capacitor 106 may be electrically connected to the wiring 123. This may continue.

[0120] Also, as shown in FIG. 8B, the capacitor 106 may be omitted. In addition, an OS transistor can be used as the transistor connected to the node NM. The transistor has an extremely small leakage current, so the capacitor 106 that functions as a storage capacitor Even if the transistor is omitted, the display can be maintained for a relatively long time. Even in cases where the display period can be shortened by high-speed operation, such as field sequential driving, It is effective to omit the capacitor 106. By omitting the capacitor 106, the aperture ratio is improved. Alternatively, the transmittance of the pixel can be improved.

[0121] In addition, even when a liquid crystal device is used, the gate line can be shared between two pixels aligned vertically. As shown in FIG. 9, when a liquid crystal device is used, a gate line is shared between two pixels. By using this technology, the number of gate lines per pixel can be reduced from two to one. For an explanation of the operation of adding potentials in the NM, refer to the operation when a light-emitting device is used. can be done.

[0122] In addition, in a pixel according to one embodiment of the present invention, a backgate is provided in a transistor as shown in FIG. In FIG. 10, the back gate is electrically connected to the front gate. This shows a structure in which the back gate is connected to the transistor, which has the effect of increasing the on-current. The transistor may be electrically connected to a wiring that can supply a constant potential. The threshold voltage of the transistor can be controlled.

[0123] In addition, in a pixel according to one embodiment of the present invention, as shown in FIG. In the pixel, the weight and data are written at different times, so The source line for supplying the signal can be made common. However, in this configuration, and in the configuration shown in FIG. Therefore, it is not possible to combine this with a configuration in which a gate line is shared between two pixels.

[0124] Next, an example of the layout of a pixel having the light-emitting device shown in FIG. 1 will be described with reference to FIGS. 12A and 12B. 12B, 13A, 13B, 14A, 14B, and 15A to 15C. In order to mainly explain the configuration of the capacitor, The device and some of its components are shown in Figs. 12A, 12B, 13A, 13B, and 14A, 14B, and 15A to 15C, and the description thereof will be omitted. 12A, 12B, 13A, 13B, 14A, 14B, and 15A to 1 5C uses the same reference numerals as in FIG. 1, FIG. 3A, and FIG. 3B.

[0125] 12A and 12B show the conductive layer 51, the dielectric layer 61, and 12A is a top view of the conductive layer 52a. 2B is a cross-sectional view taken along dashed line C1-C2 shown in FIG. 2A.

[0126] The conductive layer 51 is connected to the wiring 125, the wiring 126, the wiring 127, and the backplane of the transistor 104. The wiring 125 can be formed in the same process as the gate electrode of the transistor 101. The wiring 126 also functions as a back gate electrode of the transistor 102. The wiring 127 also functions as a back gate electrode of the transistor 105. The conductive layer 51 also functions as a back gate electrode. There can be.

[0127] The dielectric layer 61 is formed in the same process as the back gate insulating films of the transistors 101 to 105. The dielectric layer 61 may be an inorganic insulating layer such as a silicon oxide film. can be done.

[0128] The conductive layer 52a is a low-resistance semiconductor layer. After the semiconductor layer is formed, impurities are introduced. The semiconductor layer is formed by applying a low resistance to the semiconductor layers of the transistors 101 to 105. It can be formed using the same process as in the above.

[0129] In transistors, the gate electrode is used as a mask to control the region where impurities are introduced. The region overlapping with the gate electrode becomes a high resistance region, and the other region becomes a low resistance region. The high resistance region acts as a channel formation region, and the low resistance region acts as a source region or a drain region. The low resistance region is, for example, an oxide semiconductor such as IGZO that has low resistance. The conductive layer 52a can be formed in the same manner as the low resistance region. This can be done.

[0130] In this manner, the capacitor 107 can be formed.

[0131] Next, referring to FIG. 13A and FIG. 13B, the conductive layer 52 which functions as an electrode of the capacitor 106 is 13A is a top view. FIG. 13B is a cross-sectional view of the dashed line shown in FIG. 13A. FIG. 2 is a cross-sectional view taken along the line C1-C2.

[0132] The conductive layer 52b has an area overlapping with the conductive layer 52a. Since the conductive layer 52b is electrically connected directly to the conductive layer 52a, the two have the same potential. And conductive layer 52a can be considered to be the same as conductive layer 52 shown in FIG. 3B.

[0133] A protective layer 63 is provided on each transistor and the conductive layer 52a. For example, an inorganic insulating layer such as a silicon oxide film can be used.

[0134] The conductive layer 52a is a region to which either the source or the drain of the transistor 101 extends. The protective layer 63 overlapping the source or drain of the transistor 101 has an opening. The conductive layer 52b is provided with a region overlapping the conductive layer 52a via the protective layer 63. A part of the conductive layer 52b is also provided in the opening 160, and the conductive layer 52b is formed to have a conductive It is in direct electrical contact with layer 52a.

[0135] The conductive layer 52b is connected to the wiring 124 and the source electrode or drain electrode of each transistor. The conductive layer 52b can be formed in a common process with the corresponding connection wiring. A low resistance metal layer or the like can be used.

[0136] Next, the configuration of capacitor 106 will be described with reference to Figures 14A and 14B. FIG. 14A is a top view, and FIG. 14B is a cross-sectional view taken along dashed line C1-C2 shown in FIG. 14A. The capacitor 106 includes a conductive layer 52b, a dielectric layer 62a, and a dielectric layer 62b. and a conductive layer 54 are laminated.

[0137] A dielectric layer 62a is provided over each transistor and the conductive layer 52b. For example, an inorganic insulating layer such as a silicon oxide film or a silicon nitride film can be used. The dielectric layer 62a also functions as a protective film for the transistor.

[0138] The dielectric layer 62b is provided on the dielectric layer 62a. The dielectric layer 62b may include, for example, an acrylic resin. An organic insulating layer such as polyimide or silicide can be used. The dielectric layer 62a and the dielectric layer 62b are both That is, the dielectric layer 62a and the dielectric layer 62b function as the dielectric layer of the dielectric layer 6 of FIG. It can be considered to be the same as the dielectric layer 62 shown in FIG.

[0139] The conductive layer 54 is provided on the dielectric layer 62b so as to have an area overlapping the conductive layer 52b. The conductive layer 54 can be formed in the same process as the wirings 122 and 123. The conductive layer 54 may be, for example, a low resistance metal layer.

[0140] As a result, the capacitor 107 and the capacitor 106 are connected to each other with the conductive layer 52 as a common electrode. The configuration may have overlapping regions.

[0141] The conductive layer 52a, which is a semiconductor layer having a low resistance, has a higher resistance than the metal layer. As shown in FIG. 15A, a plurality of openings 165 are provided in the protective layer 63 to allow the conductive layer 52a and the conductive layer 5 2b may be increased to reduce the effect of resistance. It can also be said that the configuration has multiple

[0142] In addition, the configuration of the capacitor 106 shown in FIG. 14A and FIG. 14B is formed relatively thick on the dielectric layer. Since the organic insulating layer is included, it may be difficult to increase the capacitance. As shown in FIG. 1, the conductive layer 54 may be provided in contact with the dielectric layer 62a. The organic insulating layer (dielectric layer 62b) may be provided on the dielectric layer 62a and the conductive layer 54. stomach.

[0143] Alternatively, as shown in FIG. 15C, the organic insulating layer (dielectric layer 62b) overlaps with the conductive layer 52b. An opening may be provided in the region, and a conductive layer 54 may be provided in the opening. In this configuration, the dielectric layer is formed of a single inorganic insulating layer (dielectric layer 62a), so the capacitance value It becomes easier to increase

[0144] In the above, an example in which two different capacitors overlap each other has been described. A configuration with three capacitors, one of which has an overlapping area with the other two capacitors. In the case where the pixel circuit has two capacitors, one of the capacitors may be connected to the other The capacitor can be connected in parallel with one of the capacitors.

[0145] Regarding the above configuration, FIG. 16A, FIG. 16B, FIG. 17A, FIG. 17B, FIG. 18A, and FIG. 18B are used. Here, the pixel includes a capacitor 107, a capacitor 106a, a capacitor The capacitor 106a and the capacitor 106b are connected in parallel to form a capacitance. An example in which the capacitor 107 is connected in parallel will be described. In addition, in FIG. 12A, FIG. 12B, FIG. 13A, FIG. 13B, FIG. 14A, FIG. 14B, and 15A to 15C, detailed description will be omitted.

[0146] 16A and 16B show the conductive layer 51a, the dielectric layer 61, and The laminated state of the conductive layer 52a and the conductive layer 51b constituting the capacitor 106a and the dielectric layer 61 16A is a top view, and FIG. 16B is a diagram showing a laminated state of the conductive layer 52a. 16B is a cross-sectional view taken along dashed line D1-D2 shown in FIG. 16A.

[0147] The conductive layer 51a and the conductive layer 51b are connected to the wiring 125, the wiring 126, the wiring 127, and the transistor 128. The conductive layer 51a can be formed in the same process as the back gate electrode of the transistor 104. The conductive layer 51b is provided separately on the same surface.

[0148] The dielectric layer 61 is formed in the same process as the back gate insulating films of the transistors 101 to 105. It can be achieved.

[0149] The conductive layer 52a is formed by a process common to the semiconductor layers of the transistors 101 to 105 and The conductive layer 52a can be formed by a process for reducing the resistance of the conductive layer. An oxide conductive layer made of an oxide semiconductor such as GZO with reduced resistance can be used.

[0150] As a result, the capacitor 107 and the capacitor 106a, which have the conductive layer 52a as a common electrode, can be formed.

[0151] Next, referring to FIG. 17A and FIG. 17B, the conductive layer 5 which functions as an electrode of the capacitor 106b is 17A is a top view of the 2b shown in FIG. 17A. FIG. 2 is a cross-sectional view taken along line D1-D2.

[0152] The conductive layer 52b has an area overlapping with the conductive layer 52a. 2a and the opening 160 are electrically connected directly (see FIG. 17A). This becomes electric potential.

[0153] The conductive layer 51b is conductive through an opening 161 provided in the dielectric layer 61 and the protective layer 63. It is electrically connected to the connection wiring 55 formed in the same process as the layer 52b (see FIG. 17A). The connection wiring 55 is also electrically connected to the transistor 104 and the transistor 105. To be continued.

[0154] Next, the capacitor 106b will be described with reference to Figs. 18A and 18B. Fig. 18B is a cross-sectional view taken along dashed line D1-D2 shown in Fig. 18A. The capacitor 106b includes a conductive layer 52b, a dielectric layer 62a and a dielectric layer 62b, and A conductive layer 54 is laminated on the insulating layer 52 .

[0155] A dielectric layer 62a is provided over each of the transistors and the conductive layer 52b. The dielectric layer 62a and the dielectric layer 62b are both formed of a It functions as the dielectric layer of the capacitor 106b.

[0156] The conductive layer 54 is provided on the dielectric layer 62b so as to have an area overlapping the conductive layer 52b. do.

[0157] As a result, the capacitor 107, the capacitor 106a, and the capacitor 107b each having the conductive layer 52 as a common electrode are formed. The conductive layer 54 is connected to the dielectric layer 62a and the capacitor 106b. The layer 62b is electrically connected directly to the connection wiring 55 through an opening 162 (FIG. 18A). Therefore, the conductive layer 54 and the conductive layer 51b have the same potential. The capacitor 106a and the capacitor 106b are connected in parallel and function as the capacitor 106. It is possible.

[0158] The configurations shown in FIGS. 15A to 15C can also be applied to the configurations shown in FIGS. 18A and 18B. It is possible.

[0159] FIG. 19 is a diagram illustrating a display device according to one embodiment of the present invention. The display device includes a pixel array 11. 1, a source driver 20, and a gate driver 30. The pixel array 11 is The pixel 12 has the capacitance C1 described in the present embodiment. The pixel has a laminated structure of a capacitor and has a boost function. The figure is simply illustrated, and wirings connected to the elements of the pixel according to one embodiment of the present invention are provided. can be done.

[0160] The source driver 20 and the gate driver 30 are implemented using sequential circuits such as shift registers. There can be.

[0161] The source driver 20 and the gate driver 30 are implemented by COF (chip on fiber). lm) method, COG (chip on glass) method, TCP (tape carrier) method A method of attaching an IC chip externally using a method such as the R package method can be used. Alternatively, a transistor manufactured using a process common to the pixel array 11 may be used to manufacture a pixel array. It may be fabricated on the same substrate as the array 11 .

[0162] Although the gate driver 30 is shown to be disposed on one side of the pixel array 11, Alternatively, two of them may be arranged facing each other with the intervening pixel 11 to divide the driving row.

[0163] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0164] (Embodiment 2) In this embodiment, a configuration example of a display device using a liquid crystal device and a display device using a light-emitting device are described. In this embodiment, the configuration of the display device described in the first embodiment will be described. Description of the elements, operations and functions of the display device will be omitted.

[0165] The display device described in this embodiment can include the pixel described in Embodiment 1. The scanning line driving circuit described below is a gate driver, and the signal line driving circuit is a source driver. Equivalent to driver.

[0166] 20A to 20C are diagrams illustrating the structure of a display device in which one embodiment of the present invention can be used. It is.

[0167] In FIG. 20A, a display unit 215 is provided on a first substrate 4001. A sealant 4005 is provided, and the display portion 215 is disposed between the sealant 4005 and the second substrate 400. It is sealed by 6.

[0168] In FIG. 20A, the scanning line driving circuit 221a, the signal line driving circuit 231a, and the signal line driving circuit 23 2a and the common line driving circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline semiconductor. The common line driving circuit 241a is formed of the wiring 123, It has the function of supplying a specified potential to terminals 24, 129, 130, 131, etc.

[0169] A scanning line driving circuit 221a, a common line driving circuit 241a, a signal line driving circuit 231a, and a signal Various signals and potentials are applied to the line driver circuit 232a via a flexible printed circuit (FPC). The signal is supplied via a digital signal processor (DPC) 4018.

[0170] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 of the drive circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. The device is implemented in a different area than the area in which it is installed.

[0171] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COF (Chip On Film) method, COG (Chip On Glass) The tape carrier package (TCP) method can be used. .

[0172] FIG. 20B shows an integrated circuit included in the signal line driving circuit 231a and the signal line driving circuit 232a. This shows an example of mounting 4042 by the COG method. Also, part or the whole of the driving circuit is It is possible to form a system-on-panel by forming the display unit 215 on the same substrate. .

[0173] In FIG. 20B, the scanning line driving circuit 221a and the common line driving circuit 241a are In this example, the driving circuit is formed on the same substrate as the pixel circuit in the display unit 215. By forming the die, the number of parts can be reduced, and the productivity can be improved. do.

[0174] In FIG. 20B, a display unit 215 and a scanning line driving circuit are provided on a first substrate 4001. A sealant 4005 is provided so as to surround the wiring 221a and the common line driving circuit 241a. In addition, the display unit 215, the scanning line driving circuit 221a, and the common line driving circuit 24 A second substrate 4006 is provided on the upper surface of the display unit 215, the scanning line driving circuit, and the like. The wiring 221a and the common line driver circuit 241a are formed by a first substrate 4001 and a seal material 4005. The display device is sealed by the second substrate 4006 and the second substrate 4007 .

[0175] In addition, in FIG. 20B, a signal line driving circuit 231a and a signal line driving circuit 232a are formed separately. Although an example in which the first substrate 4001 is mounted is shown, the present invention is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as a part of the signal line driver circuit or a scanning line driver circuit. Alternatively, a part of the circuit may be formed separately and mounted. The signal line driver circuit 232a and the signal line driver circuit 231a may be formed on the same substrate as the display unit 215. .

[0176] The display device includes a panel in which a display device is sealed, and a control unit connected to the panel. This may also include modules in which ICs, etc. including controllers are mounted.

[0177] In addition, the display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor is the Si transistor or the OS transistor described in Embodiment 1. A transistor can be applied.

[0178] The structure of the transistors in the peripheral driver circuits and the pixel circuits in the display area is The transistors in the peripheral driver circuit are all the same or different. The transistors may have the same structure, or may have two or more types of transistor structures. Similarly, the transistors in the pixel circuit may all have the same structure. Alternatively, the semiconductor device may have transistors with two or more different structures.

[0179] In addition, an input device 4200 can be provided on the second substrate 4006. The display device shown in FIG. 20C is provided with an input device 4200, which functions as a touch panel. It is possible.

[0180] There is no limitation on the detection device (also called a sensor element) included in the touch panel of one embodiment of the present invention. There are various sensors that can detect the proximity or contact of a sensing object such as a finger or stylus. The sensor can be applied as a sensing device.

[0181] The sensor type may be, for example, a capacitance type, a resistive film type, a surface acoustic wave type, or an infrared type. Various methods can be used, such as a pressure-sensitive method, an optical method, or a pressure-sensitive method.

[0182] In this embodiment, a touch panel having a capacitance type detection device will be described as an example. do.

[0183] The capacitive touch sensor includes a surface capacitive touch sensor and a projected capacitive touch sensor. The electrostatic capacitance type includes the self-capacitance type and the mutual capacitance type. This is preferable because it enables simultaneous multi-point detection.

[0184] The touch panel according to one embodiment of the present invention is formed by bonding a display device and a detection device that are separately manufactured. A detection device is provided on one or both of a substrate supporting a display device and an opposing substrate. Various configurations can be applied, such as a configuration in which electrodes constituting a sensor are provided.

[0185] 21A and 21B show an example of a touch panel. FIG. 21A shows a touch panel 4210. FIG. 21B is a perspective schematic diagram of the input device 4200. Note that for clarity, Therefore, only representative components are shown.

[0186] The touch panel 4210 is constructed by bonding a display device and a detection device that are separately manufactured. It is a completion.

[0187] The touch panel 4210 includes an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0188] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 4237. , a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 is The electrode 4228 can be electrically connected to the wiring 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wires 4239. and electrically connects to each of the plurality of wirings 4238. 3b may be provided.

[0189] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, In addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also used. may be applied.

[0190] 22A and 22B are cross-sectional views of the area indicated by the chain line N1-N2 in FIG. The display device shown in FIG. 22A and FIG. 22B has an electrode 4015. The electrode 4015 is an FPC4 4018 and a terminal of the anisotropic conductive layer 4019. In FIG. 22A and FIG. 22B, the electrode 4015 is made of an insulating layer 4112, an insulating layer 4111, and an insulating It is electrically connected to wiring 4014 in an opening formed in edge layer 4110 .

[0191] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The conductive layer is made of the same material.

[0192] The display unit 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are In FIG. 22A and FIG. 22B, the transistors included in the display unit 215 are 4010 and a transistor 4011 included in the scanning line driver circuit 221a. In addition, in FIG. 22A and FIG. 22B, the transistor 4010 and the transistor 4 A bottom-gate transistor is shown as an example of 011, but a top-gate transistor is also shown. It may be a gyroscope.

[0193] In FIG. 22A and FIG. 22B, an insulating layer is formed on transistor 4010 and transistor 4011. 22B, a partition wall 4510 is formed on the insulating layer 4112. It has been made.

[0194] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4111. The semiconductor device has an electrode 4017 formed thereon. The electrode 4017 functions as a back gate electrode. It is possible.

[0195] The display device shown in FIG. 22A and FIG. 22B further includes a capacitor 4020. 4020 is an electrode 4021 formed in the same process as the gate electrode of the transistor 4010. , an insulating layer 4103, and electrodes formed in the same process as the source electrode and the drain electrode. The configuration of the capacitor 4020 is not limited to this, and other conductive layers may be used. and an insulating layer.

[0196] The transistor 4010 provided in the display portion 215 is electrically connected to the display device. 22A is an example of a liquid crystal display device using a liquid crystal device as a display device. In A, a liquid crystal device 4013, which is a display device, has a first electrode layer 4030, a second The liquid crystal layer 4008 is sandwiched between the electrode layer 4031 and the liquid crystal layer 4008. An insulating layer 4032 and an insulating layer 4033 functioning as an alignment film are provided on the second electrode. The layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 are 031 is superimposed via a liquid crystal layer 4008.

[0197] As the liquid crystal device 4013, a liquid crystal device to which various modes are applied can be used. For example, VA (Vertical Alignment) mode, TN (Twis ted Nematic mode, IPS (In-Plane-Switching) mode ASM (Axially Symmetric aligned Micro-c ell) mode, OCB (Optically Compensated Bend) mode mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode ECB (Electrically Controlled Birefringe) LCD devices that use NV mode, VA-IPS mode, guest host mode, etc. can be used.

[0198] In addition, the liquid crystal display device shown in this embodiment may be a normally black type liquid crystal display device, for example. A transmissive liquid crystal display device using a vertical alignment (VA) mode may be used. The code is MVA (Multi-Domain Vertical Alignment). nt) mode, PVA (Patterned Vertical Alignment) mode, ASV (Advanced Super View) mode, etc. can.

[0199] A liquid crystal device is a device that controls the transmission or non-transmission of light by the optical modulation action of liquid crystals. The optical modulation of liquid crystals is caused by the electric field applied to the liquid crystal (horizontal electric field, vertical electric field, etc.). The liquid crystal used in liquid crystal devices is Thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC:Pol ymer Dispersed Liquid Crystal), ferroelectric liquid crystal, antiferroelectric Dielectric liquid crystals can be used. These liquid crystal materials can be cholesteric depending on the conditions. phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc.

[0200] FIG. 22A shows an example of a liquid crystal display device having a vertical electric field type liquid crystal device. In one embodiment, a liquid crystal display device having a lateral electric field type liquid crystal device can be applied. When the in-plane switching mode is adopted, a liquid crystal that exhibits a blue phase without using an alignment film may be used. The Lou phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the cholesteric phase The blue phase appears just before the transition from the crystalline phase to the isotropic phase. Therefore, in order to improve the temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is prepared. The liquid crystal composition containing the liquid crystal exhibiting the blue phase and the chiral agent is used for the liquid crystal layer 4008. The speed is short and the liquid crystal exhibits optical isotropy. In addition, the liquid crystal exhibits a blue phase and contains a chiral agent. The composition does not require alignment treatment and has low viewing angle dependency. Since the rubbing process is unnecessary, electrostatic damage caused by the rubbing process is prevented. This can prevent the liquid crystal display device from being damaged or broken during the manufacturing process. do.

[0201] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0202] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. In addition, the above-mentioned backlight and sidelight may be used. Micro LEDs or the like may be used as the light source.

[0203] In the display device shown in FIG. 22A, a light-shielding layer 4006 is provided between the second substrate 4006 and the second electrode layer 4031. A layer 4132, a coloring layer 4131, and an insulating layer 4133 are provided.

[0204] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, etc. Examples of the material for the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. In addition, a laminated film of a film containing the material of the colored layer may be used for the light-shielding layer. A film containing a material for a colored layer that transmits light of a certain color and a material for a colored layer that transmits light of a different color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0205] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, or dyes. The light-shielding layer and the colored layer are formed by, for example, an ink-jet method. The electrode can be formed using:

[0206] The display device shown in FIG. 22A and FIG. 22B has an insulating layer 4111 and an insulating layer 4104. The insulating layer 4111 and the insulating layer 4104 are formed using an insulating layer that is not easily permeated by impurity elements. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, the It is possible to prevent the intrusion of impurities.

[0207] Furthermore, a light-emitting device can be used as a display device included in a display device. As the device, for example, an EL device utilizing electroluminescence is applied. An EL device includes a layer containing a light-emitting compound between a pair of electrodes (an "EL layer"). A voltage greater than the threshold voltage of the EL device is applied between a pair of electrodes. When a potential difference is created, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes recombine in the EL layer, and the luminescent compound contained in the EL layer It glows.

[0208] The EL device may be, for example, an organic EL device or an inorganic EL device. It is possible to use LEDs (including micro LEDs) that use compound semiconductors as light-emitting materials. is also an EL element, and LEDs can also be used.

[0209] In addition to the light-emitting compound, the EL layer may be formed by using a material having a high hole-injecting property and a material having a high hole-transporting property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The insulating layer may include a material having high electron-transporting and hole-transporting properties.

[0210] The EL layer can be formed by a variety of methods, including deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0211] Inorganic EL devices are classified into dispersed inorganic EL devices and thin-film inorganic EL devices depending on the element structure. Dispersion-type inorganic EL devices are classified into two types: dispersed-type and non-dispersion-type. Dispersion-type inorganic EL devices have particles of light-emitting material dispersed in a binder. The light-emitting mechanism utilizes the donor and acceptor levels. The thin-film inorganic EL device uses a donor-acceptor recombination type luminescence. The structure is sandwiched between dielectric layers, which are then sandwiched between electrodes. The light-emitting mechanism is metal ions. This is a localized emission that utilizes the inner-shell electron transition of fluorine. An explanation will be given using an organic EL device.

[0212] In a light-emitting device, at least one of a pair of electrodes needs to be transparent in order to extract light. Then, a transistor and a light-emitting device are formed on the substrate, and the substrate is Top emission structure that extracts light, or emits light from the substrate side Bottom emission structure and dual emission structure that emits light from both sides There are light-emitting devices with a mission structure, and any light-emitting device with an injection structure can be applied. can.

[0213] FIG. 22B shows a light-emitting display device ("EL display device") that uses a light-emitting device as a display device. The light-emitting device 4513, which is a display device, is an example of the display unit 215. The light emitting device 4513 is electrically connected to the transistor 4010 provided in the light emitting device 4513. The structure is a laminated structure of a first electrode layer 4030, a light emitting layer 4511, and a second electrode layer 4031. However, the present invention is not limited to this configuration. In addition, the configuration of the light emitting device 4513 can be changed appropriately.

[0214] The partition 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is continuous. It is preferable to form the inclined surface so as to have a curvature.

[0215] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers may be laminated. Either way is fine.

[0216] The color of light emitted by the light-emitting device 4513 can be white, red, or green depending on the material that constitutes the light-emitting layer 4511. , blue, cyan, magenta, or yellow, etc.

[0217] As a method for realizing color display, a white light-emitting device 4513 is combined with a colored layer. There are two methods: one is to combine the two, and the other is to provide a light-emitting device 4513 with a different light-emitting color for each pixel. The former method is more productive than the latter method. On the other hand, the latter method requires a light-emitting layer for each pixel. Since it is necessary to make 4511 separately, this method is less productive than the former method. The method can obtain a luminescence color with higher color purity than the former method. By providing a microcavity structure to the light-emitting device 4513, the color purity can be further improved. can be increased to.

[0218] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. The child dots can be used in a light-emitting layer to function as a light-emitting material.

[0219] The second electrode is disposed in order to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting device 4513. A protective layer may be formed on the electrode layer 4031 and the partition wall 4510. The protective layer may be silicon nitride. Silicon, silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxynitride Aluminum, aluminum oxide nitride, DLC (Diamond Like Carbon), etc. Also, the first substrate 4001, the second substrate 4006, and the seal The space sealed by the material 4005 is sealed with a filler 4514. To prevent exposure to the outside air, a protective film (lamination) with high airtightness and low outgassing is used. packaging (enclosure) in a covering material (such as a protective film or ultraviolet curing resin film) is preferred.

[0220] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Also, filler 4514 may contain a desiccant.

[0221] The sealing material 4005 is made of glass materials such as glass frit, or two-liquid mixed resin. Resin materials such as heat-curable resin, photocurable resin, and thermosetting resin can be used. Also, the sealant 4005 may contain a desiccant.

[0222] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be installed on the exit surface of the light-emitting device. Optical films such as retardation films (lambda / 4 plates, lambda / 2 plates), and color filters are appropriately installed. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. The convex surface can be used to diffuse reflected light and reduce glare with an anti-glare treatment.

[0223] In addition, by making the light-emitting device into a microcavity structure, light with high color purity can be extracted. In addition, by combining a microcavity structure with a color filter, This reduces glare and improves visibility of the displayed image.

[0224] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer) that apply a voltage to the display device In the case of the layer (also called the counter electrode layer, etc.), the direction of the light to be extracted and the location where the electrode layer is provided The light transmitting property or the light reflective property can be selected depending on the pattern structure of the electrode layer.

[0225] The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide In addition, a conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. This can be done.

[0226] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or an alloy thereof, or a metal nitride thereof. .

[0227] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer of two or more of aniline, pyrrole and thiophene, Its derivatives are also included.

[0228] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0229] As shown in FIG. 23, the transistors and capacitors have regions where they overlap in the height direction. For example, the transistors 4011 and 4021 that form the driver circuit may have a stack structure. By overlapping the transistor 4021 and the transistor 4022, a display device with a narrow frame can be obtained. In addition, a transistor 4010, a transistor 4023, and a capacitor 4 If the 020 and 021 are arranged so that they overlap, the aperture ratio and resolution can be improved. In addition, in FIG. 23, a stack structure is applied to the liquid crystal display device shown in FIG. 22A. Although an example is shown, it may be applied to the EL display device shown in FIG. 22B.

[0230] In addition, in the pixel circuit, a transparent conductive film with high transparency to visible light is used for the electrodes and wiring. By doing so, it is possible to increase the light transmittance within the pixel, and thus to substantially improve the aperture ratio. In addition, when an OS transistor is used, the semiconductor layer also has a light-transmitting property. The aperture ratio can be increased. This is because the transistors are not stacked. It is also effective in

[0231] Furthermore, a display device may be configured by combining a liquid crystal display device and a light emitting device.

[0232] The light emitting device is disposed on the opposite side of the display surface or on the edge of the display surface. The light-emitting device has a function of supplying light. The light-emitting device can also be called a backlight.

[0233] Here, the light emitting device is a plate- or sheet-shaped light guide portion (also called a light guide plate) that emits light of different colors. The light emitting device may be disposed near a side surface of the light guide. When placed next to the light guide, the light can be emitted from the side of the light guide to the inside. The light-emitting device has a mechanism for extracting light from the display panel. Light can be uniformly irradiated onto the pixel area. Alternatively, light can be emitted directly below the pixel without providing a light guide. The device may be arranged in a manner such that

[0234] The light emitting device may have three light emitting devices of red (R), green (G), and blue (B). It is preferable that the light emitting device further includes a white (W) light emitting device. Light emitting diodes (LEDs) are used for is preferred.

[0235] Furthermore, the light-emitting device has a full width at half maximum (FWHM) of its emission spectrum. th at Half Maximum) is 50 nm or less, preferably 40 nm or less; More preferably, the thickness is 30 nm or less, and even more preferably, the thickness is 20 nm or less. It is preferable that the light-emitting device has a small full width at half maximum of the emission spectrum. The smaller the better, but it can be set to, for example, 1 nm or more. This allows for color display. When the display is turned on, it is possible to provide a vivid display with high color reproducibility.

[0236] In addition, red light emitting devices have an emission spectrum peak wavelength of 625 nm or more and 650 nm or less. It is preferable to use an element located within a range of m or less. Also, the green light emitting device is An element whose emission spectrum peak wavelength is in the range of 515 nm to 540 nm It is preferable to use a blue light emitting device having an emission spectrum with a peak wavelength of 44 It is preferable to use elements lying in the range of 5 nm to 470 nm.

[0237] The display device sequentially blinks the three color light emitting devices and drives the pixels in sync with this. The driving method is a filter driving method. This can also be called field sequential driving.

[0238] Field sequential driving allows for the display of vivid color images. In addition, by using the above driving method, it is possible to display smooth moving images. This eliminates the need to configure a pixel with multiple sub-pixels of different colors, and reduces the effective reflective area (effective surface area) of a single pixel. Since the display area (also called the aperture ratio) can be increased, a bright display can be achieved. Since there is no need to provide a color filter to the pixel, the transmittance of the pixel can also be improved. Furthermore, the manufacturing process can be simplified, and the manufacturing cost can be reduced. It can be reduced.

[0239] 24A and 24B are schematic cross-sectional views of a display device capable of field sequential driving. This is an example. The first substrate 4001 of the display device has a backlight capable of emitting RGB colors. In field sequential driving, the light units for each of the RGB colors are Since colors are expressed through time-division emission, color filters are not required.

[0240] The backlight unit 4340a shown in FIG. 24A has a diffuser plate 4352 directly below the pixels. A plurality of light emitting devices 4342 are provided on the light emitting device 4342. The light emitted from 4342 to the first substrate 4001 side is diffused to make the brightness on the display surface uniform. If necessary, a polarizer is provided between the light emitting device 4342 and the diffusion plate 4352. A light plate may be provided. Also, the diffusion plate 4352 may not be provided if it is not necessary. The optical layer 4132 may be omitted.

[0241] The backlight unit 4340a can be equipped with many light emitting devices 4342. Therefore, a bright display is possible. In addition, a light guide plate is not required, and the light of the light emitting device 4342 is The light emitting device 4342 may have a light diffusing function if necessary. A lens 4344 may be provided.

[0242] The backlight unit 4340b shown in FIG. 24B has a diffuser plate 4352 directly below the pixels. The light guide plate 4341 is provided at the end of the light guide plate 4341. The light guide plate 4341 has an uneven shape on the side opposite to the diffusion plate 4352. The guided light can be scattered by the uneven surface and emitted in the direction of the diffusion plate 4352.

[0243] The light emitting device 4342 can be fixed to a printed circuit board 4347. In B, the light emitting devices 4342 for each of the R, G, and B colors are illustrated as overlapping, but The light emitting devices 4342 of each color of R, G, and B may be arranged side by side. In the case of 341, a reflective layer that reflects visible light is provided on the side opposite to the light emitting device 4342. 4348 may also be provided.

[0244] The backlight unit 4340b can reduce the number of light-emitting devices 4342. Therefore, it is possible to achieve a low-cost and thin structure.

[0245] The liquid crystal device may be a light scattering type liquid crystal device. It is preferable to use an element having a composite material of liquid crystal and polymer. A polymer network type liquid crystal device can be used. Using LC (Polymer Network Liquid Crystal) elements This is also fine.

[0246] The light-scattering liquid crystal device is a device in which liquid is injected into the three-dimensional network structure of a resin part sandwiched between a pair of electrodes. The material used for the liquid crystal portion is, for example, nematic liquid crystal. The resin portion can be made of a photocurable resin. The fat may be, for example, a monofunctional monomer such as an acrylate or a methacrylate, a diacrylate, Multifunctional monomers such as triacrylate, dimethacrylate, and trimethacrylate, Alternatively, a polymerizable compound in which these are mixed can be used.

[0247] Light-scattering liquid crystal devices use the anisotropy of the refractive index of liquid crystal materials to transmit or scatter light. The resin portion may also have anisotropy in refractive index. When the liquid crystal molecules are aligned in a certain direction according to the voltage applied to the liquid crystal device, A direction occurs in which the difference in the refractive index between the liquid crystal portions becomes smaller, and the light incident along that direction is scattered by the liquid crystal portion. Therefore, the light scattering type liquid crystal device appears transparent from this direction. On the other hand, when the alignment of the liquid crystal molecules becomes random according to the applied voltage, Since there is no significant change in the difference in refractive index between the liquid crystal section and the resin section, the incident light is scattered by the liquid crystal section. Therefore, the light-scattering liquid crystal device remains opaque regardless of the viewing direction.

[0248] FIG. 25A shows a liquid crystal device 4013 of the display device of FIG. 24A being a light scattering type liquid crystal device 401. The light scattering type liquid crystal device 4016 has a liquid crystal part and a resin part. The semiconductor device has a composite layer 4009 that supports the semiconductor device, as well as a first electrode layer 4030 and a second electrode layer 4031 . The elements related to the field sequential driving are the same as those in FIG. 24A, but the light scattering type liquid crystal When the device 4016 is used, the alignment film and the polarizing plate are not required. Although 035 is shown in spherical form, it may also be cylindrical.

[0249] FIG. 25B shows a liquid crystal device 4013 of the display device of FIG. 24B as a light scattering type liquid crystal device 401. 24B, the light scattering type liquid crystal device 4016 is replaced with a voltage It operates in a mode where it transmits light when no voltage is applied and scatters light when a voltage is applied. By adopting this configuration, the normal state (the state where no display is made) ) can be used as a transparent display device. In this case, when the light scattering operation is performed, It is possible to display in color.

[0250] Modified examples of the display device shown in FIG. 25B are shown in FIGS. 26A to 26E. In FIG. 26E, for clarity, some elements of FIG. 25B are used and other elements are omitted. is.

[0251] FIG. 26A shows a configuration in which the first substrate 4001 functions as a light guide plate. The outer surface of 4001 may be provided with an uneven shape. In this configuration, a light guide plate is provided separately. Since the light guide plate does not need to be a light guide plate, the manufacturing cost can be reduced. Since there is no attenuation, the light emitted by the light emitting device 4342 can be used efficiently. do.

[0252] FIG. 26B shows a configuration in which light is incident from the vicinity of the end of the composite layer 4009. At the interface with the second substrate 4006 and at the interface between the composite layer 4009 and the first substrate 4001 By utilizing total reflection, light can be emitted from the light scattering type liquid crystal device to the outside. The resin portion of the first substrate 4001 and the second substrate 4006 have a refractive index larger than that of the first substrate 4001 and the second substrate 4006. Use materials that are suitable for the purpose.

[0253] The light emitting device 4342 may be provided not only on one side of the display device but also on the other side as shown in FIG. The light emitting device may be provided on two sides facing each other. Furthermore, the light emitting device may be provided on three or four sides. By providing 4342 on multiple sides, it is possible to compensate for light attenuation, making it possible to create a large-area display device. It can also be used for other purposes.

[0254] FIG. 26D shows that the light emitted from the light emitting device 4342 is reflected by the display device through the mirror 4345. This configuration makes it easier to guide light to the display device from a certain angle. Therefore, the total reflected light can be obtained efficiently.

[0255] FIG. 26E is a configuration having a stack of layers 4003 and 4004 on a composite layer 4009. One of the layers 4003 and 4004 is a support such as a glass substrate, and the other is an inorganic film. It can be formed by a coating film or film of organic resin. The resin portion of the layer 4002 is made of a material having a refractive index larger than that of the layer 4004. A material with a refractive index greater than 4003 is used.

[0256] A first interface is formed between composite layer 4009 and layer 4004, and layer 4004 and layer 400 A second interface is formed between the first interface and the second interface. The light that passes through can be totally reflected at the second interface and returned to the composite layer 4009. This allows efficient use of the light emitted by the light emitting device 4342.

[0257] The configurations in FIG. 25B and FIG. 26A to FIG. 26E can be combined with each other. can.

[0258] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0259] (Embodiment 3) In this embodiment mode, the transistors described in the above embodiment modes can be replaced with An example of a transistor that can be used will be described with reference to the drawings.

[0260] The display device of one embodiment of the present invention includes a bottom-gate transistor or a top-gate transistor. The present invention can be fabricated using various types of transistors, such as transistors. The semiconductor layer materials and transistor structures used can be easily replaced to suit the production line. It is possible.

[0261] [Bottom-gate transistor] FIG. 27A shows a channel-protected transistor, which is a type of bottom-gate transistor. In FIG. 27A, the transistor 810 is a cross-sectional view in the channel length direction. The transistor 810 is formed on a substrate 771. The transistor 810 is formed on an insulating layer 772 on the substrate 771. The electrode 746 is provided with the semiconductor layer 74 on the insulating layer 726. 2. The electrode 746 can function as a gate electrode. The insulating layer 726 can function as a gate insulating layer. It can function as such.

[0262] In addition, an insulating layer 741 is provided on a channel formation region of the semiconductor layer 742. 42, and has an electrode 744a and an electrode 744b on the insulating layer 726. Electrode 744a can function as either a source electrode or a drain electrode. A part of the electrode 744a and the electrode 744b can function as the other of the source electrode and the drain electrode. A portion of the pole 744 b is formed on the insulating layer 741 .

[0263] The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs during the formation of the electrode 744a and the electrode 744b is suppressed. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel forming region 742 from being etched.

[0264] The transistor 810 includes an insulating layer 741 and an electrode 744a. A layer 728 is provided, and an insulating layer 729 is provided on the insulating layer 728 .

[0265] When an oxide semiconductor is used for the semiconductor layer 742, at least At least in the portion in contact with the semiconductor layer 742, oxygen is taken from a portion of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material capable of generating oxygen vacancies in the semiconductor layer 742. The resulting region has an increased carrier concentration, which makes it n-type, and the region is called an n-type region (n + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742 to fill the oxygen vacancies. Examples of materials that can produce this include tungsten and titanium. do.

[0266] The source region and the drain region are formed in the semiconductor layer 742, whereby the electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0267] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a between the semiconductor layer 742 and the electrode 744b, and between the semiconductor layer 742 and the electrode 744b, It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0268] The insulating layer 729 has a function of preventing or reducing diffusion of impurities from the outside into the transistor. It is preferable to form the insulating layer 729 using a material having the above structure. It is also possible.

[0269] An electrode 723 that can function as a back gate electrode is provided on the insulating layer 729. The electrode 723 can be formed using the same material and method as the electrode 746. A configuration without 3 may also be used.

[0270] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the potential of the back electrode, the transistor threshold The voltage can be varied.

[0271] Both the electrode 746 and the electrode 723 can function as a gate electrode. The insulating layer 726, the insulating layer 728, and the insulating layer 729 each serve as a gate insulating layer. The electrode 723 can function as a gate insulating layer. This is also fine.

[0272] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 810, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as the "back gate electrode." When the transistor 810 is used as a top-gate transistor, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0273] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, 6 and the electrode 723 are set to the same potential, the region in which carriers flow in the semiconductor layer 742 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 810 increases, the field effect mobility increases.

[0274] Therefore, transistor 810 is a transistor having a large on-current relative to its area. That is, the area of ​​the transistor 810 is determined based on the required on-current. It can be made smaller.

[0275] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity The back gate electrode is larger than the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0276] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, This can prevent light from entering the semiconductor layer from the side. This prevents the semiconductor layer from being photodegraded. This can prevent degradation of electrical characteristics, such as a shift in the threshold voltage of a transistor. .

[0277] FIG. 27B shows a channel of a channel-protection type transistor 820 having a different configuration from that shown in FIG. 27A. Transistor 820 has a structure similar to that of transistor 810. The difference is that an insulating layer 741 covers the edge of the semiconductor layer 742. In an opening formed by selectively removing a portion of the insulating layer 741 overlapping the conductor layer 742, The semiconductor layer 742 and the electrode 744a are electrically connected to each other. In another opening formed by selectively removing a part of the insulating layer 741, the semiconductor layer 742 and The electrode 744b is electrically connected to the insulating layer 741. can function as a channel protection layer.

[0278] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, when the electrode 744a and the electrode 744b are formed, the layer 742 can be prevented from being exposed. In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0279] In addition, the transistor 820 has a larger current flowing between the electrodes 744a and 746 than the transistor 810. The distance between electrodes 744a and 744b and the distance between electrodes 744b and 746 are increased. It is possible to reduce the parasitic capacitance generated between the electrode 744b and the electrode 746. This can reduce the parasitic capacitance occurring between 746.

[0280] FIG. 27C shows a channel-etched transistor, which is one of the bottom-gate transistors. 7 is a cross-sectional view of the transistor 825 in the channel length direction. Therefore, the electrodes 744a and 744b are formed without using the A part of the semiconductor layer 742 that is exposed during the formation of the electrode 744b may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be increased.

[0281] [Top-gate transistor] The transistor 842 illustrated in FIG. 28A is one of the top-gate transistors. The electrodes 744a and 744b are formed through openings formed in the insulating layers 728 and 729. The insulating layer 742 is electrically connected to the semiconductor layer 742 at the portion.

[0282] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the electrode 746 and the remaining insulating layer By introducing impurities into the semiconductor layer 742 using the mask 726, the semiconductor layer 742 The impurity region can be formed in a self-aligned manner. The sintered body 842 has an area where the insulating layer 726 extends beyond the edge of the electrode 746. The impurity concentration in the region of the layer 742 into which the impurity is introduced through the insulating layer 726 is The semiconductor layer 742 is smaller than the region where the impurity is introduced without the insulating layer. A region overlapping the layer 726 but not the electrode 746 is provided with an LDD (Lightly Deposited Diode) layer. A doped drain region is formed.

[0283] The transistor 842 also has an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 via the insulating layer 772. The electrode 723 may be omitted. good.

[0284] Also, as in the case of a transistor 844 shown in FIG. 28B, the insulation of the region that does not overlap with the electrode 746 Layer 726 may be removed entirely. Alternatively, an insulating layer may be used, such as transistor 846 shown in FIG. 28C. An edge layer 726 may be left.

[0285] FIG. 29A is a cross-sectional view of a transistor 810 in the channel width direction, and FIG. 29B is a cross-sectional view of a transistor 84 2 shows a cross-sectional view in the channel width direction of the semiconductor device shown in FIG.

[0286] In the structure shown in FIG. 29A and FIG. 29B, the gate electrode and the back gate electrode are connected to each other. The gate electrode and the back gate electrode have the same potential. The gate electrode is sandwiched between the electrode and the back gate electrode.

[0287] The length of each of the gate electrode and the back gate electrode in the channel width direction is 2 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is The layer is sandwiched between the gate electrode and the back gate electrode.

[0288] With this structure, the semiconductor layer 742 included in the transistor is The gate electrode can be electrically surrounded by the electric field of the gate electrode.

[0289] In this way, the electric field of the gate electrode and the back gate electrode forms a channel formation region. The device structure of the transistor that electrically surrounds the semiconductor layer 742 is called Surrou. This can be called a nded channel (S-channel) structure.

[0290] By adopting an S-channel structure, either one of the gate electrode and the back gate electrode By both, an electric field is effectively applied to the semiconductor layer 742 to induce a channel. This improves the current drive capability of the transistor and makes it possible to obtain high on-current characteristics. In addition, since it is possible to increase the on-current, it is possible to miniaturize transistors. In addition, the S-channel structure makes it possible to mechanically Strength can be increased.

[0291] The gate electrode and the back gate electrode are not connected, and different potentials are supplied to them. For example, a constant potential may be applied to the back gate electrode of the transistor. The threshold voltage of the transistor can be controlled.

[0292] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0293] (Embodiment 4) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproducing device equipped with a recording medium, a mobile phone, Game consoles, including those of the 1990s, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include automatic vending machines. Specific examples of such electronic devices are shown in Figures 30A to 30F.

[0294] FIG. 30A shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 963. , speaker 967, display unit 965, operation keys 966, zoom lever 968, lens 969 The display device of one embodiment of the present invention can be used for the display portion 965.

[0295] FIG. 30B shows a portable data terminal, which includes a housing 911, a display unit 912, a speaker 913, and operation buttons. The display unit 912 has a touch panel function, and a camera 919. The display device according to one embodiment of the present invention is used for the display unit 912. can be done.

[0296] FIG. 30C shows a mobile phone, which includes a housing 951, a display unit 952, an operation button 953, and an external connection The mobile phone has a port 954, a speaker 955, a microphone 956, a camera 957, and the like. The device is provided with a touch sensor on the display unit 952. All operations can be performed by touching the display unit 952 with a finger or a stylus. In addition, the housing 951 and the display unit 952 are flexible and can be folded as shown in the figure. The display device of one embodiment of the present invention can be used for the display portion 952.

[0297] FIG. 30D shows a video camera, which includes a first housing 901, a second housing 902, a display unit 903, and an operation The operation key 904 includes a key 904, a lens 905, a connection portion 906, a speaker 907, etc. The lens 905 is provided in the first housing 901, and the display unit 903 is provided in the second housing 902. The display device of one embodiment of the present invention can be used for the display portion 903.

[0298] FIG. 30E shows a television, which includes a housing 971, a display unit 973, operation buttons 974, and a speaker 97 5, a communication connection terminal 976, an optical sensor 977, etc. The display device of one embodiment of the present invention is provided in the display portion 973, and an input operation can be performed. It can be used.

[0299] FIG. 30F shows a digital signage having a large display unit 922. For example, a large display unit 922 is attached to the side of a pillar 921. The display device according to one embodiment of the present invention can be used.

[0300] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is. [Explanation of symbols]

[0301] 10: pixel, 11: pixel array, 12: pixel, 20: source driver, 30: gate driver 40: circuit, 51: conductive layer, 51a: conductive layer, 51b: conductive layer, 52: conductive layer, 5 2a: conductive layer, 52b: conductive layer, 53: conductive layer, 54: conductive layer, 55: connection wiring, 61: Dielectric layer, 62: dielectric layer, 62a: dielectric layer, 62b: dielectric layer, 63: protective layer, 10 1: transistor, 102: transistor, 103: transistor, 104: transistor 105: transistor, 106: capacitor, 106a: capacitor, 106b: Capacitor, 107: Capacitor, 108: Light emitting device, 109: Transistor, 110 : Liquid crystal device, 121: Wiring, 122: Wiring, 123: Wiring, 124: Wiring, 125: Wiring, 126: Wiring, 127: Wiring, 129: Wiring, 130: Wiring, 131: Wiring, 16 0: opening, 161: opening, 162: opening, 165: opening, 215: display, 22 1a: scanning line driving circuit, 231a: signal line driving circuit, 232a: signal line driving circuit, 241 a: common line driver circuit, 723: electrode, 726: insulating layer, 728: insulating layer, 729: insulating layer , 741: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode , 771: substrate, 772: insulating layer, 810: transistor, 820: transistor, 82 5: transistor, 842: transistor, 844: transistor, 846: transistor 901: housing, 902: housing, 903: display unit, 904: operation keys, 905: lens , 906: connection section, 907: speaker, 911: housing, 912: display section, 913: speaker 914: Operation button, 919: Camera, 921: Pillar, 922: Display unit, 951: Housing 952: display unit, 953: operation buttons, 954: external connection port, 955: speaker, 956: Microphone, 957: Camera, 961: Housing, 962: Shutter button, 963: Microphone, 965: Display, 966: Operation keys, 967: Speaker, 968: Zoom lever , 969: Lens, 971: Housing, 973: Display, 974: Operation button, 975: Spin 976: communication connection terminal, 977: optical sensor, 4001: substrate, 4003: layer, 4 004: layer, 4005: sealant, 4006: substrate, 4008: liquid crystal layer, 4009: composite layer, 4010: transistor, 4011: transistor, 4013: liquid crystal device, 40 14: wiring, 4015: electrode, 4016: light scattering type liquid crystal device, 4017: electrode, 40 18: FPC, 4019: anisotropic conductive layer, 4020: capacitor, 4021: electrode, 40 22: transistor, 4023: transistor, 4030: electrode layer, 4031: electrode layer, 4032: insulating layer, 4033: insulating layer, 4035: spacer, 4041: printed circuit board, 4042: integrated circuit, 4102: insulating layer, 4103: insulating layer, 4104: insulating layer, 411 0: insulating layer, 4111: insulating layer, 4112: insulating layer, 4131: colored layer, 4132: light shielding layer layer, 4133: insulating layer, 4200: input device, 4210: touch panel, 4227: electrode , 4228: electrode, 4237: wiring, 4238: wiring, 4239: wiring, 4263: substrate , 4272b: FPC, 4273b: IC, 4340a: Backlight unit, 434 0b: backlight unit, 4341: light guide plate, 4342: light emitting device, 4344: Lens, 4345: mirror, 4347: printed circuit board, 4348: reflective layer, 4352: expander Scattering plate, 4510: partition wall, 4511: light-emitting layer, 4513: light-emitting device, 4514: filler

Claims

[Claim 1] A pixel includes a first capacitor, a second capacitor, and a display element; the first capacitor and the second capacitor are electrically connected to the display element; the first capacitor has a configuration in which a first conductive layer, a first dielectric layer, and a second conductive layer are laminated in this order; the second capacitor has a configuration in which the second conductive layer, a second dielectric layer, and a third conductive layer are laminated in this order; A display device, wherein the first capacitor and the second capacitor have an overlapping area.

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