Display device

Abstract

To provide a wire whose side surface has different angles precisely at desired parts on one mother glass substrate without increasing the steps.SOLUTION: By using a multiple-gradation mask, a photoresist layer is formed so as to have a tapered shape whose cross-sectional area decreases continuously to a direction away from one mother glass substrate. When one wire is formed, one photomask is used to selectively etch a metal film, so that one wire having different side surface shapes (specifically, angles with respect to substrate main plane) depending on places is obtained.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device having a circuit configured with thin film transistors (hereinafter referred to as TFTs). The present invention relates to a device and a method for manufacturing the same, for example, an electro-optical device such as a liquid crystal display panel, The present invention relates to an electronic device that incorporates a light-emitting display device having a light-emitting element as a component.

[0002] In this specification, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This term refers to devices in general, and electro-optical devices, semiconductor circuits, and electronic equipment are all classified as semiconductor devices. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates with insulating surfaces have been used. The technology of constructing thin film transistors (TFTs) has been attracting attention. It is widely used in electronic devices such as ICs and electro-optical devices, especially in switches for image display devices. Development of this technology as a photonics element is being rushed.

[0004] In particular, a switching element made of a TFT is provided for each display pixel arranged in a matrix. Active matrix display devices (liquid crystal display devices and light-emitting display devices) have been actively developed. is.

[0005] The switching elements of this image display device are designed to be area-efficient in order to obtain high-definition image displays. Therefore, high-precision photolithography technology capable of arranging the electrodes is required.

[0006] In addition, up until now, multiple panels have been cut out from a single mother glass substrate, making mass production more efficient. The size of the mother glass substrate has been increased to 1.5 times that of the 1990s. The first generation was 300 x 400 mm, and in 2000 the fourth generation was 680 x 88 0mm or 730 x 920mm, and multiple display panels can be mounted on a single substrate. In the future, the size of mother glass substrates will become larger. In order to achieve this, it is necessary to support, for example, 10th generation boards that exceed 3m in size.

[0007] In order to obtain a display device that can display high-definition images, a metal film formed on a mother glass substrate is Etching of thin films using resist masks obtained by photolithography technology This forms wiring.

[0008] There are various etching methods, but they can be broadly divided into dry etching and wet etching. The wet etching method is an isotropic etching method, The side of the wiring layer protected by the resist mask is scraped off to a certain extent, which is inappropriate for miniaturization. It is considered to be the direction.

[0009] In addition, the commonly known dry etching method is the RIE dry etching method. Since it is anisotropic etching, isotropic etching is required for miniaturization. This is considered to be advantageous over wet etching methods, which

[0010] In addition, tungsten wiring with a tapered cross section was produced using an ICP etching device. is disclosed in Patent Document 1.

[0011] In addition, an auxiliary pattern having a light intensity reducing function, which is made of a diffraction grating pattern or a semi-transparent film, is provided. The photomask or reticle thus placed is applied to a photolithography process for forming a gate electrode. Such a TFT manufacturing process is disclosed in Patent Document 2.

[0012] In addition, the cross-sectional shape of the wiring can be partially adjusted by adjusting the resist mask width and etching conditions. Patent Document 3 discloses a technique for making the difference.

[0013] In addition, a photomask having an auxiliary pattern with a light intensity reducing function made of a semi-transparent film is used. Patent Document 4 discloses a technique for forming a source electrode or a drain electrode using a semiconductor device. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Patent Publication No. 2001-35808 [Patent Document 2] Patent Publication No. 2002-151523 [Patent Document 3] Patent Publication No. 2006-13461 [Patent Document 4] Patent Publication No. 2007-133371 Summary of the Invention [Problem to be solved by the invention]

[0015] When forming wiring on a single mother glass substrate, the conventional method requires wiring with the same cross-sectional shape. For example, when using the RIE dry etching method, the developed resist The resist shape is changed by heating and melting it, and then etching is performed to change the resist shape. The side of the wiring is tapered to reflect the change in the resist. In addition, the resist area is expanded by dissolving the resist, so the adjacent It is difficult to narrow the spacing between lines. In addition, when forming multi-layer wiring, If there is wiring under the area to be removed, the wiring will also be heated when the resist is melted. Therefore, the resist heating temperature becomes uneven, and the rate at which the resist melts and spreads varies depending on the location. This makes it difficult to obtain a desired wiring shape.

[0016] In addition, when using an ICP etching device, a coil antenna is used, so the antenna is rectangular. However, it is difficult to obtain a uniform discharge over the entire surface of a single mother glass substrate.

[0017] For example, in the pixel section of a transmissive liquid crystal display device, the gate wiring is tapered. A thin semiconductor layer is formed on top of it, but the taper shape increases the wiring width, so the opening In addition, the tapered shape increases the wiring width, which may cause a decrease in the wiring efficiency. If there is another wiring that overlaps with the above via an insulating film, an unnecessary parasitic capacitance is formed. To reduce capacitance, the wiring on each layer is arranged so that the wiring on different layers does not overlap. When the layout is performed, the aperture ratio is reduced.

[0018] In addition, an auxiliary pattern having a light intensity reducing function, which is made of a diffraction grating pattern or a semi-transparent film, is provided. When a photomask having a different shape is used, the cross-sectional shape of the wiring can be selectively varied. In this case, the side of the wiring has two types of cross-sectional shapes: one with two steps and one without. It becomes wiring.

[0019] In the method for manufacturing a semiconductor device, a semiconductor device can be manufactured by forming a semiconductor device on a single mother glass substrate without increasing the number of steps. The object of the present invention is to provide wiring in which the angles of the side surfaces of the wiring are precisely different in each desired portion. do. [Means for solving the problem]

[0020] a light-transmitting substrate capable of transmitting exposure light; and a light-shielding portion formed on the light-transmitting substrate and made of chromium or the like; A light intensity reducer in which lines and spaces made of a light-shielding material are repeatedly formed with a predetermined line width. The exposure mask is formed of lines and spaces. An exposure mask with a semi-transparent portion is also called a gray-tone exposure mask. Such exposure is also called graytone exposure.

[0021] A gray-tone exposure mask has at least one pattern such as slits or dots, and a periphery. The aperture pattern is periodically or non-periodically arranged. Light intensity reduction consisting of spaces between the mask apertures consisting of lines and spaces below the boundary The light intensity of the functional auxiliary pattern can be adjusted within the range of 10 to 70%.

[0022] In addition, the exposure mask has a semi-transmitting portion made of a semi-transmitting film having a function of reducing the light intensity of the exposure light. The exposure mask is also called a half-tone exposure mask, and exposure using this exposure mask is called half-tone exposure. In addition to MoSiN, other semi-transparent films include MoSi, MoSiO, and MoS. iON, CrSi, etc. can be used.

[0023] In this specification, the term "graytone exposure mask" and "halftone exposure mask" are used collectively. For convenience, the mask is called a multi-tone mask.

[0024] By using a multi-tone mask, one photoresist layer is separated from one mother glass substrate. The photoresist layer is formed to have a tapered shape in which the cross-sectional area continuously decreases in the direction. The present invention uses a gray-tone exposure mask or a half-tone exposure mask. By developing one photoresist layer to two different thicknesses, They do not form a single step each.

[0025] In the present invention, when forming one wiring, one photomask is used, and the first region is A gray-tone exposure (or half-tone exposure) is performed, and at the same time, a portion of the second region is Then, development is performed and the metal film is selectively etched to remove the A single wiring is obtained in which the side shape (specifically, the angle with respect to the main surface of the substrate) differs depending on the location. This method allows the side shape of the wiring to be intentionally made different, and it is convenient for the implementer. The desired wiring can be obtained.

[0026] As a result, the width of the side of the wiring in the first region (also called the width of the tapered portion) is The width of the side of the wiring in the first region is wider than the width of the side of the wiring in the first region. The angle of the facet is smaller than that of the second region.

[0027] In one wiring, at least a portion of the first region and a portion of the second region are formed on the main surface of the substrate. It is preferable that the difference in the angle of the side surface with respect to the surface be greater than 10°.

[0028] For example, in a transmissive liquid crystal display device, a region that becomes a gate electrode and overlaps with a semiconductor layer is called a first The area is used to form thin-film transistors with excellent electrical properties, and the gate electrode is placed between the pixel electrodes. The area that will become the wiring is treated as the second area, and the width of the tapered part is narrowed to improve the aperture ratio. In addition, the gate wiring is tapered to reduce the wiring resistance and improve the aperture ratio. It is preferable to narrow the width of the gate electrode. By making the width of the electrode wider than that of the gate, the wiring resistance can be reduced.

[0029] The configuration of the invention disclosed in this specification is a semiconductor layer on a substrate, and wiring that partially overlaps the semiconductor layer. The wiring has a wide region on the wiring side and a narrow region on the wiring side, The wide region at least partially overlaps the semiconductor layer, and the wiring side of the narrow region is arranged The side angle of the cross section in the wiring width direction is smaller by 10° or more than the side angle of the cross section in the wiring width direction. This is a semiconductor device having the following characteristics.

[0030] Specifically, the side angle of the cross section in the width direction of the wiring in the wide region of the wiring side is 10° to 50°. The side angle of the cross section in the wiring width direction in the narrow region of the wiring side is in the range of 60° to 90°. If the side angle of the cross section in the wiring width direction is 90°, the cross section of the wiring is If the cross section of the wiring is rectangular or square and less than 90°, the top side is shorter than the bottom side. It is a shape.

[0031] In the case of an inverted staggered thin-film transistor, the semiconductor layer formed on the gate wiring is approximately 50 Because the gate wiring is so thin (only nm), the side angle of the cross section in the wiring width direction in the wide area on the side of the gate wiring is 10° The part of the semiconductor layer that overlaps with the end or side of the gate wiring is thinned in the range of 50° from the edge of the gate wiring. It is preferable not to do so.

[0032] The present invention solves at least one of the above problems.

[0033] In addition, the wiring is not limited to the gate wiring, and may be a source wiring, a drain wiring, a connection wiring, etc., on the interlayer insulating film. The present invention can also be used when forming any other wiring.

[0034] In addition to forming a wiring having side surfaces at the same angle on both ends of the wiring in cross section, In addition, the angle of one side surface and the other side surface with respect to the main surface of the substrate can be made different. In this case, the cross-sectional shape of the wiring can be said to be a trapezoid with two different interior angles that contact the base.

[0035] In addition, the configuration of another invention includes a first wiring on a substrate, an insulating film covering the first wiring, and a and a second wiring electrically connected to the first wiring via the second wiring. The angle between one side surface and the other side surface of the two ends of the semiconductor device differs from that of the other side surface of the semiconductor device. It is a body device.

[0036] In addition to the above configuration, the transparent conductive film is partially overlapped with the second wiring, and the transparent conductive film is Of the two ends in the cross-sectional shape of the wiring in 2, the one that has a smaller angle with respect to the main plane of the substrate By adopting such a configuration, the transparent electrode overlapping one side surface of the second wiring To ensure reliable electrical connection with a conductive film and reduce disconnection of the transparent conductive film.

[0037] In addition, another aspect of the present invention is a gray-tone exposure mask or a half-tone exposure mask. By using this method, one photoresist layer can be developed to three or more different thicknesses, Two or more steps are formed on both ends of the layer. When the conductive layer is etched, the cross-sectional shape of the resulting wiring has two or more steps on one side. Of course, wiring having this cross-sectional shape can be selectively formed. Therefore, a first wiring and a second wiring having a cross-sectional shape different from that of the first wiring are provided on the same insulating film surface. The cross-sectional shape of the first wiring is rectangular or trapezoidal, while the cross-sectional shape of the second wiring is The first wiring and the second wiring are made of the same material. In the case where the cross section of the wiring is tapered, the taper The position of the end of the groove depends on the etching time. There is a risk of variation in the wiring width of the quartz crystal, and the side surface may become curved and have a skirt shape, resulting in cutting. Although there is a risk of the area decreasing and the wiring resistance increasing, the etching time can be reduced by making it step-shaped. Even if the cross-sectional shape of the second wiring is slightly different, a constant wiring width can be obtained. By using this wiring layer, a sufficient margin for etching conditions can be obtained. By making the end of the wiring in FIG. 2 have two steps in the cross section, the taper angle is less than 50°. Therefore, the same degree of step coverage as that of a wiring having a full tapered shape can be ensured.

[0038] In addition, in one wiring, the cross-sectional shape of the first region is a rectangle or a trapezoid, and the cross-sectional shape of the second region is a The cross-sectional shape may be stepped having two or more steps on one side surface.

[0039] The present invention also relates to a manufacturing method for achieving the above structure, and is characterized in that a conductive layer is formed on a substrate. A multi-tone mask is used to perform one exposure, and the side surface and the main surface of the substrate are clearly visible in the cross section. The first resist mask and the second resist mask, which have different angles, are developed, and the first resist mask is The conductive layer is etched using the first resist mask and the second resist mask to form wiring. The angle of the side cross section of the first resist mask after development and the angle of the side cross section of the second resist mask are The difference between the angles is greater than 10°.

[0040] In addition, the configuration of the invention relating to another manufacturing method is to form a conductive layer on a substrate and then use a multi-tone mask. A first resist pattern is formed by performing a single exposure and forming a first resist pattern having a different angle between the side surface and the main surface of the substrate in a cross section. The first resist mask and the second resist mask are developed to form a The conductive layer is etched using the mask to form a single wiring, and the first resist is The difference between the side cross-sectional angle of the first resist mask and the side cross-sectional angle of the second resist mask is less than 10°. This is a method for manufacturing a large semiconductor device.

[0041] In each of the above-mentioned manufacturing methods, the cross-sectional shape of the first resist mask is rectangular or trapezoidal. The cross-sectional shape of the second resist mask is a trapezoid. The cross-sectional shape of the first resist mask is rectangular or trapezoidal, and the cross-sectional shape of the second resist mask is The surface shape is stepped, with two or more steps on one side.

[0042] These methods mentioned above are not just design matters, but are used to actually form wiring using a multi-tone mask. The invention was made after extensive consideration by the inventors.

[0043] The technique disclosed in Patent Document 1 is to selectively etch the side of the wiring by changing the etching conditions of the ICP etching device. Since the angle of the surface is determined, wiring formed on the same substrate using the same etching process The side shape of the wiring is intended to be uniform for all wiring. This is significantly different from the present invention in which the side shape of the line is made different depending on the location.

[0044] In addition, the techniques disclosed in Patent Documents 2 and 4 have a step-like side of a resist mask, The side of the wiring is also stepped to reflect the shape of the resist mask. The wiring disclosed in Patent Document 4 has one step, which is provided on each end.

[0045] In addition, the technology disclosed in Patent Document 3 is a technology for partially varying the cross-sectional shape of the wiring, The side surface of the wiring formed in the same etching process forms the same angle with the main surface of the substrate.

[0046] In this specification, terms expressing directions such as up, down, side, horizontal, vertical, etc. refer to the top of the substrate surface. This refers to the direction based on the board surface when the device is placed on the board.

[0047] In this specification, a gate electrode is a thin film that overlaps a semiconductor layer via a gate insulating film. The gate wiring refers to the part that forms the channel of the thin film transistor. Note that part of one pattern made of the same conductive material is the gate electrode, and the other part is The remaining portion becomes the gate wiring.

[0048] In the present invention, the semiconductor layer is a semiconductor film mainly composed of silicon or a metal oxide. As a semiconductor film mainly composed of silicon, Using an amorphous semiconductor film, a semiconductor film including a crystalline structure, a compound semiconductor film including an amorphous structure, etc. Specifically, amorphous silicon, microcrystalline silicon, polycrystalline silicon, monocrystalline silicon, Crystalline silicon or the like can be used. In addition, a semiconductor film mainly composed of a metal oxide can be used. For example, zinc oxide (ZnO) and zinc-gallium-indium oxide (In-Ga-Zn-O) are used. O) etc. can be used.

[0049] In addition, the present invention can be applied regardless of the TFT structure or transistor structure. For example, top-gate TFTs, bottom-gate TFTs (inverted staggered TFTs), and forward staggered TFTs. It is possible to use TFTs. Also, it is not limited to single-gate transistors. First, a multi-gate transistor having a plurality of channel forming regions, for example, a double-gate A type transistor may also be used. Effect of the Invention

[0050] Using one mask, the desired area can be printed on one mother glass substrate without increasing the number of processes. It is possible to fabricate wiring with precisely different angles on the side surfaces of the wiring. [Brief description of the drawings]

[0051] [Figure 1] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Diagram 2] FIG. 13 is a photograph showing an example of a cross section of a wiring. [Diagram 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 4] FIG. 13 is a photograph showing an example of a cross section of a wiring. [Diagram 5] 1A, 1C, and 1D are partial top views of a mask, and 1B and 1E are schematic diagrams showing an example of the relationship between light intensity. [Figure 6] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 7] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 9] 1A to 1C are cross-sectional views illustrating a manufacturing method of the present invention. [Figure 10] 1A to 1C are cross-sectional views illustrating a manufacturing method of the present invention. [Figure 11] 1A to 1C are cross-sectional views illustrating a manufacturing method of the present invention. [Figure 12] 1A to 1C are top views illustrating a manufacturing method of the present invention. [Figure 13]FIG. 13 is a diagram showing an example of a time chart illustrating a process of forming a microcrystalline silicon film. [Figure 14] FIG. [Figure 15] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 16] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 17] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 18] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 19] 1A to 1C are cross-sectional views illustrating a manufacturing process of a semiconductor device. [Figure 20] FIG. 1 is a cross-sectional view illustrating an example of a liquid crystal display device. [Figure 21] FIG. 1 is a top view illustrating an example of a liquid crystal display device. [Figure 22] FIG. 1 is a top view illustrating an example of a liquid crystal display device. [Diagram 23] 1 is an equivalent circuit diagram of a pixel of a liquid crystal display device. [Figure 24] FIG. 1 is a diagram illustrating an example of a liquid crystal display device. [Diagram 25] FIG. 1 is a diagram illustrating an example of a liquid crystal display device. [Figure 26] FIG. 2 is a perspective view illustrating a display panel. [Figure 27] 1A and 1B are a top view and a cross-sectional view illustrating a display panel. [Figure 28] FIG. 1 is a perspective view illustrating an electronic device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below.

[0053] (Embodiment 1) In this embodiment, a pixel portion having a thin film transistor and an FPC or the like are connected to an external device. The manufacturing process for forming a terminal part having a connection wiring for connecting the semiconductor device to the semiconductor device on the same substrate is shown in FIG.

[0054] First, a substrate 101 having an insulating surface is prepared. The substrate 101 having an insulating surface is a light-transmitting substrate, such as a glass substrate, a crystallized glass substrate, or a plastic substrate; When the substrate 101 is a mother glass, the size of the substrate is (320mm x 400mm), 2nd generation (400mm x 500mm), 3rd generation (550 mm×650mm), 4th generation (680mm×880mm, or 730mm×920mm m), 5th generation (1000mm x 1200mm or 1100mm x 1250mm), 6th generation (1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation Generation (2160mm x 2460mm), 9th generation (2400mm x 2800mm, 245 10th generation (2950mm x 3400mm), etc. can be used. can.

[0055] In addition, the substrate 101 having an insulating surface is formed such that the outermost layer or film has an insulating surface. For example, a base film made of an insulator, a semiconductor layer, or a conductive film may already be formed.

[0056] Next, a first conductive layer 103 is formed on the substrate 101 having an insulating surface. Layer 103 is made of a high melting point metal such as tungsten, titanium, chromium, tantalum, or molybdenum. The alloy or compound mainly composed of high melting point metals such as tantalum or tantalum nitride is 200 nm thick. The thickness of the wiring is about 600 nm. In order to reduce the resistance of the wiring, the wiring is made of aluminum, gold, and Alternatively, a metal film such as copper and the above-mentioned high melting point metal may be laminated.

[0057] Next, a resist film 403 is applied to the entire surface of the first conductive layer 103, and then, as shown in FIG. Exposure is performed using a mask 400 shown in FIG. 1. Here, a resist film having a thickness of 1.5 μm is applied. The exposure is performed using an exposure machine with a resolution of 1.5 μm. The light used for exposure is i-line (wavelength 365 nm) and the exposure energy is 70 to 140 mJ / cm 2 Select from the range of. Not limited to i-line, but a mixture of i-line, g-line (wavelength 436 nm) and h-line (wavelength 405 nm) Alternatively, light that has been irradiated with light may be used for exposure.

[0058] In this embodiment, the first photomask is an exposure mask having a light intensity reducing function in a part thereof. Auxiliary patterns (gray tones) are installed to provide a pixel area for the thin film transistor. The taper angle of the gate electrode is set in the range of 10° to 50°.

[0059] In FIG. 1A, the exposure mask 400 has a light-shielding portion 401b made of a metal film such as Cr. and a semi-transmitting portion 401 having a slit as an auxiliary pattern having a light intensity reducing function. In the cross-sectional view of the exposure mask 400, the width of the light-shielding portion 401b is t2 The width of the semi-transmitting portion 401a is denoted by t1 and t3. Although an example using a light tone has been shown, a half tone using a semi-permeable film may also be used.

[0060] When the resist film 403 is exposed to light using the exposure mask 400 shown in FIG. Non-exposed regions 403a and 403b and exposed region 403c are formed on the photoresist film 403. 1(A) is caused by the light going around the light-shielding portion 401b or passing through the semi-transparent portion 401a. ) is formed.

[0061] Then, when development is performed, the exposed area 403c is removed, and the image is left as shown in FIG. A first resist mask 404a is applied to the element portion, and a second resist mask 404b is applied to the terminal portion. Each of them is obtained on the first conductive layer 103. By adjusting the exposure conditions such as the exposure energy, Thus, a first resist mask 404a having a tapered shape is obtained, instead of an end portion having a step. The terminal portion exposed to the photomask in the area where the gray tone is not provided can be In the embodiment, a second resist mask having a larger side angle in cross section than the first resist mask 404a is used. A top mask 404b is formed.

[0062] Next, the resist masks 404a and 404b are used as masks to perform dry etching. The first conductive layer 103 is etched by etching. Note that depending on the etching conditions, The substrate 101 having the above structure is also etched, and the thickness of the substrate is partially thinned. The top layer of 101 or on the substrate 101 has an insulating film that may be etched. Etching gases include carbon tetrafluoride (CF4), sulfur fluoride (SF6), and chlorine (C I2) and oxygen (O2). Also, compared to ICP etching equipment, it can process a large area. Use a dry etching device that can easily obtain uniform discharge. The upper electrode is grounded and a 13.56MHz high-frequency power source is connected to the lower electrode. In addition, a 3.2MHz low-frequency power source was connected to the lower electrode. Capacitively Coupled Plasma (CAP) mode etching equipment This etching equipment is suitable for etching a 10th generation 3m wafer as the substrate 101. This also makes it possible to accommodate cases where a substrate larger than this is used.

[0063] After the etching process is completed, the remaining resist mask is removed by ashing or the like. In this way, as shown in FIG. 1C, a first wiring layer 107a and The second wiring layer 107b is formed on each of the first wirings formed in the pixel area. The taper angle θ1 of the layer 107a is set to about 50°, and the taper angle θ2 of the second wiring layer 107b formed in the terminal portion is set to about 50°. The taper angle θ2 is set to about 70°. In a later process, a semiconductor film or a wiring layer is formed on the first wiring layer 107a. Since a line is formed, it is effective to make the taper angle on both sides small to prevent breakage. In addition, the second wiring layer 107b is arranged adjacent to each other and is connected to an FPC or the like. Therefore, the taper angles of both side surfaces are made large so as to prevent short circuits from occurring between adjacent second wiring layers 107b. In addition, it is effective to arrange a plurality of second wiring layers 107b in a narrow area. In this case, the interval between adjacent second wiring layers 107b can be narrowed, so that the tape on both sides can be It is effective to process the angle to a large value.

[0064] The resist film used in the etching process of the first conductive layer 103 is a negative resist. Since it is difficult to apply the method, the pattern configuration of the photomask or reticle for forming the gate electrode is , this is based on the assumption that a positive resist is used.

[0065] Next, a gate electrode made of silicon nitride (dielectric constant 7.0, thickness 300 nm) is formed on the first wiring layer 107a. An insulating film 102 is laminated. The gate insulating film 102 is formed by using a CVD method, a sputtering method, or the like. The insulating film can be formed of a silicon nitride film or a silicon nitride oxide film. A silicon oxide film is a film whose composition contains more nitrogen than oxygen, and has a concentration range of As the atomic percentage of oxygen, 15 to 30 atomic percent, nitrogen, 20 to 35 atomic percent, silicon, 25 to 35 atomic percent, water, This refers to a material that contains 15 to 25 atomic percent of elemental elements.

[0066] Next, after the gate insulating film 102 is formed, the substrate is transported without being exposed to the air, and the gate The amorphous semiconductor film 105 is formed in a vacuum chamber different from the vacuum chamber in which the insulating film is formed. To film.

[0067] Next, after the amorphous semiconductor film 105 is formed, the substrate is transported without being exposed to the air. The semiconductor film 105 is formed in a vacuum chamber different from the vacuum chamber in which the semiconductor film 105 is formed. A semiconductor film containing an impurity is formed.

[0068] A semiconductor film to which an impurity that gives one conductivity type is added is typically doped with phosphorus. It is possible to add an impurity gas such as phosphine gas to silicon hydride. The semiconductor film doped with impurities that impart a type is formed to a thickness of 2 nm to 50 nm. The throughput can be improved by thinning the thickness of the semiconductor film to which the impurity that gives one conductivity type is added. can be improved.

[0069] Next, a resist mask is formed on the semiconductor film to which an impurity that imparts one conductivity type is added. The resist mask is formed by photolithography or an inkjet method. Here, a semiconductor doped with an impurity that gives one conductivity type is patterned using a second photomask. The resist applied on the film is exposed and developed to form a resist mask.

[0070] Next, a semiconductor film to which an impurity imparting one conductivity type is added and a non- The amorphous semiconductor film 105 is etched to form an island-shaped semiconductor layer. Remove the sc.

[0071] Next, a semiconductor film to which an impurity imparting one conductivity type is added and a gate insulating film 102 are covered with The second conductive layer is formed as follows. The second conductive layer is made of aluminum, copper, silicon, Heat-resistant elements such as titanium, neodymium, scandium, and molybdenum, or hillock prevention elements It is preferable that the insulating layer is formed of a single layer or a multilayer of an aluminum alloy to which a blocking element is added. The second conductive layer is a conductive film having a three-layer laminate structure (not shown). The first and third conductive layers are made of molybdenum film, and the second conductive layer is made of aluminum film. The second conductive layer is formed by a sputtering method or a vacuum deposition method.

[0072] Next, as shown in FIG. 1(D), a resist is formed on the second conductive layer using a third photomask. A mask is formed, and a portion of the second conductive layer is etched to form a pair of source electrodes or drain electrodes. The electrodes 109 and 110 are formed. When the second conductive layer is wet-etched, the second conductive layer The end of the source is selectively etched. As a result, the source has an area smaller than that of the resist mask. The source and drain electrodes 109, 110 can be formed.

[0073] Next, a semiconductor film to which an impurity that gives one conductivity type is added is formed using a resist mask. 10 is etched to form a pair of source and drain regions 106, 108. In addition, a part of the amorphous semiconductor film 105 is also etched in this etching process. The process of forming the source region and the drain region and the recess (groove) of the amorphous semiconductor film 105 are performed in the same process. The depth of the recess (groove) in the amorphous semiconductor film 105 can be set to the depth of the amorphous semiconductor film 1 By making the thickness of the thickest region of 05 1 / 2 to 1 / 3, the source region and drain region Since the distance between the source and drain regions can be increased, the leakage current between the source and drain regions can be reduced. After that, the resist mask is removed.

[0074] Next, the source or drain electrodes 109, 110, the source or drain region 1 06, 108, the amorphous semiconductor film 105, and the insulating film 111 that covers the gate insulating film 102. The insulating film 111 can be formed by using the same film formation method as that for the gate insulating film 102. The gate insulating film 102 is resistant to contamination such as organic matter, metal matter, and water vapor suspended in the air. The purpose of the membrane is to prevent the intrusion of dye impurities, and a dense membrane is preferable.

[0075] Through the above steps, a thin film transistor can be formed in the pixel portion.

[0076] Next, the insulating film 111 is selected using a resist mask formed using a fourth photomask. A first contact is selectively etched to expose the source electrode or drain electrode 109 in the pixel area. The contact holes, the insulating film 111 and the gate insulating film 102 are selectively etched to form terminals. A second contact hole is formed in the contact portion to expose the second wiring layer 107b. After the holes are formed, the resist mask is removed.

[0077] Next, after forming a transparent conductive film, a resist mask was formed using a fifth photomask. A part of the transparent conductive film is etched using a 9, and a pixel electrode 112 electrically connected to the second wiring layer 107b at the terminal portion. After the pixel electrode 112 and the connection electrode 113 are formed, a resist is The mask is then removed. The cross-sectional view after completing the steps up to this point is shown in Figure 1(D).

[0078] The transparent conductive film is made of indium oxide containing tungsten oxide, indium oxide containing tungsten oxide, Indium zinc oxide, indium oxide with titanium oxide, indium tin oxide with titanium oxide Indium oxide, indium tin oxide, indium zinc oxide, indium doped with silicon oxide A conductive material having light transmitting properties, such as tin oxide, can be used. The conductive film can be formed using a conductive composition containing a conductive macromolecule (also called a conductive polymer). The pixel electrode 112 formed using the conductive composition has a sheet resistance of 10000 Ω / In the following, it is preferable that the light transmittance at a wavelength of 550 nm is 70% or more. It is preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω·cm or less.

[0079] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0080] In this manner, an element substrate that can be used in a transmission type liquid crystal display device can be formed. .

[0081] In addition, an experiment was performed to measure the cross-section SE of wiring obtained by etching using a gray-tone mask. A photograph is shown in Figure 2.

[0082] The sample was prepared by depositing a silicon oxynitride film with a thickness of 100 nm on a glass substrate, and then depositing a 400 nm A titanium film was formed. A resist film was then formed on the titanium film.

[0083] The resist film was exposed using an exposure device with a resolution of 1.5 μm, and then developed. As the first etching condition, the flow rate of BCl3 gas was set to 40 sccm, and the flow rate of Cl2 gas was set to 100 sccm. After etching for 65 seconds with the flow rate set to 40 sccm, the second etching condition was changed to B Etching was performed with the Cl3 gas flow rate set to 70 sccm and the Cl2 gas flow rate set to 10 sccm. We conducted a survey.

[0084] The cross section of the wiring in the area without gray tones corresponds to Figure 2(A). The width of the light-shielding part is 3 μm. The taper angle of the wiring in FIG. 2(A) is about 50°.

[0085] In addition, exposure was performed using a gray-tone mask with a line width of 0.5 μm and a space width of 0.5 μm. The cross section of the wiring in the shaded area corresponds to Figure 2(B). The width of the light-shielding part is 3 μm. The taper angle of the wiring is approximately 40°.

[0086] In addition, a grating with a line width of 0.5 μm and a space width of 0.5 μm repeated twice was used. The cross section of the wiring in the exposed area using a shading mask corresponds to Figure 2(C). m. The taper angle of the wiring in Figure 2(C) is about 30°.

[0087] Even if the width of the light-shielding part is the same, the width of the lines and spaces in the gray tones can affect the appearance. The resulting wiring width and taper angle can be varied. When experiments were conducted with different spacing widths, the results showed that the wiring shape had a step on the side and a protruding In some cases, the wiring shape may have a recessed portion.

[0088] Here, the experiment was conducted under the above etching conditions, but the conditions are not particularly limited, and the taper may be formed by exposure and development. The resist with different angle can be obtained, and the wiring reflecting the resist shape can be obtained. It is desirable for the operator to appropriately adjust the mask design and etching conditions.

[0089] (Embodiment 2) In this embodiment mode, when forming wiring on an interlayer insulating film covering a thin film transistor, An example of making the cross-sectional shape different from that of the terminal portion will be described with reference to FIG.

[0090] Since the steps up to this point are the same as those in the first embodiment, detailed description thereof will be omitted here. In addition, in Fig. 3, the same reference numerals will be used to denote the same parts as in Fig. 1.

[0091] In this embodiment, a flat insulating film 111 is formed on the insulating film 111 that covers the thin film transistor formed in the first embodiment. This is an example of forming a film.

[0092] First, the steps up to the step of forming the insulating film 111 are carried out according to the first embodiment.

[0093] Next, a planarization film 114 is formed. The planarization film 114 is formed of an organic resin film. Next, The insulating film 111 and the planarizing film 112 are formed using a resist mask formed using the fourth photomask. 114 is selectively etched to expose the source electrode or drain electrode 109 in the pixel portion. A first contact hole is formed, and the gate insulating film 102, the insulating film 111, and the planarizing film are 114 is selectively etched to form a second contact that exposes the second wiring layer 107b at the terminal portion. This creates a hole.

[0094] Next, a third conductive layer 115 is formed on the planarizing film 114. corresponds to FIG. 3(A).

[0095] Next, a resist film is applied to the entire surface of the third conductive layer 115, and then the mask shown in FIG. Exposure is performed using the photoresist 410.

[0096] In this embodiment, a fourth photomask is provided as an exposure mask having a light intensity reducing function. One side of the connection electrode of the terminal part is provided with an auxiliary pattern (gray tone) The taper angle of the face is in the range of 10° to 50°.

[0097] In FIG. 3B, the exposure mask 410 has a light-shielding portion 411a made of a metal film such as Cr. and a semi-transmitting portion 411 having a slit as an auxiliary pattern having a light intensity reducing function. Here, an example is shown in which a gray tone is used as part of the exposure mask. However, a halftone using a semi-permeable membrane may also be used.

[0098] When the resist film is exposed to light using the exposure mask 410 shown in FIG. Non-exposed regions 413a and 413b and exposed region 413c are formed. 3B. Region 413c is formed.

[0099] Then, when development is performed, the exposed region 413c is removed, and a third resist mask is left in the pixel portion. A fourth resist mask is formed on the third conductive layer 115 and a fourth resist mask is formed on the terminal portion. By adjusting the exposure conditions such as light energy, the step is not formed on one side, but on the other side. A fourth resist mask having a tapered surface can be obtained.

[0100] Next, the third resist mask and the fourth resist mask are used as masks to perform dry etching. The third conductive layer 115 is etched by etching. A dry etching device is used, which makes it easier to obtain uniform discharge over a wide area. In such a dry etching device, the upper electrode is grounded and the lower electrode is connected to a 13.56 MH An ECC with a high frequency power supply of 1.0 MHz connected to the lower electrode and a low frequency power supply of 3.2 MHz connected to the lower electrode. P(Enhanced Capacitively Coupled Plasma) In this etching apparatus, for example, the substrate 101 and This makes it possible to accommodate 10th generation substrates exceeding 3m in size.

[0101] The cross-sectional view of the process up to this stage corresponds to FIG. 3(C). The resist mask is also etched when the third conductive layer 115 is etched, so that the first connecting electrode A third resist mask 414a is formed on the electrode 116, and a fourth resist mask 414b is formed on the second connection electrode 117. The mask 414b remains. The second connection electrode 117 is formed by reflecting the shape of the fourth resist mask. Only one side of the glass is tapered. Also, gray tones are provided. In the pixel portion exposed by the photomask in the region where no photoresist is present, the area of ​​the first connection electrode 116 is This can contribute to improving the aperture ratio.

[0102] After the etching process is completed, the remaining resist mask is removed by ashing or the like. Remove.

[0103] Next, after forming a transparent conductive film, a resist mask was formed using a fifth photomask. A part of the transparent conductive film is etched using a a pixel electrode 118 electrically connected to the terminal portion and a third connection electrode 117 electrically connected to the terminal portion; After the pixel electrode 118 and the third connection electrode 119 are formed, a resist The cross-sectional view after the steps up to this point is shown in FIG. 3(D). The connection electrode 119 is arranged so as to overlap the tapered portion of the second connection electrode 117. By providing this, disconnection of the third connection electrode 119 is prevented.

[0104] In this manner, an element substrate that can be used in a transmission type liquid crystal display device can be formed. .

[0105] In addition, an experiment was performed to measure the cross-section SE of wiring obtained by etching using a gray-tone mask. The photograph is shown in Figure 4.

[0106] The sample was prepared by depositing a silicon oxynitride film with a thickness of 100 nm on a glass substrate, and then depositing a 400 nm A titanium film was formed. A resist film was then formed on the titanium film.

[0107] The resist film was exposed using an exposure device with a resolution of 1.5 μm, and then developed. As the first etching condition, the flow rate of BCl3 gas was set to 40 sccm, and the flow rate of Cl2 gas was set to 100 sccm. After etching for 65 seconds with the flow rate set to 40 sccm, the second etching condition was changed to B Etching was performed with the Cl3 gas flow rate set to 70 sccm and the Cl2 gas flow rate set to 10 sccm. We conducted a survey.

[0108] As shown in the photomask in FIG. 3(B), the line width is 0.5 μm and the space is 0.5 μm on only one side. Wiring in the exposed area using a gray-tone mask with two 0.5μm widths The cross section of the axial groove corresponds to FIG. 4(A). One taper angle is about 70°, and the other taper angle is about 10°. is about 35°.

[0109] In addition, a grate with a line width of 0.5 μm and a space width of 0.75 μm on only one side The cross section of the wiring in the region exposed using the laser mask corresponds to FIG. 4(B). The taper angle is about 70°, and the other side is more gentle than the other, resulting in a different taper angle. The other side has a taper angle of about 30° on the side closer to the substrate. The taper angle on the far side is approximately 60°.

[0110] Note that a line width of 0.5 μm and a space width of 0.5 μm are arranged three times on only one side. When the exposure was performed using a gray-tone mask, a wiring shape with a step on the side was obtained. In this way, if the line width and space width are changed, the resulting wiring shape changes significantly. Therefore, the practitioner must select the optimum line width and space width and optimize the etching conditions. It is important to optimize it.

[0111] Also, semi-transparent areas formed of lines and spaces or rectangular patterns and spaces An example of an exposure mask having the above structure will be described with reference to FIG.

[0112] A specific example of a top view of an exposure mask is shown in FIG. An example of the light intensity distribution 214 is shown in FIG. , semi-transmitting portion Q, and transmitting portion R. The semi-transmitting portion Q of the exposure mask shown in FIG. Lines 203, 205, 207 and spaces 201 are arranged in a stripe or slit shape. , 204, 206 are provided repeatedly, and the lines and spaces are arranged at the end 202 of the light-shielding portion P. In this semi-transparent portion, the lines 205 made of light-shielding material are arranged in a parallel direction. The width of the light blocking material is L, and the width of the space 204 between the light blocking material is W2. The line 203 is formed in a rectangular shape. However, it is not limited to this. It is sufficient that the width is constant. For example, It may also have a curved shape.

[0113] In the exposure mask of FIG. 5(A), the width W of the space 204 is smaller than the width W1 of the space 201. 2 is wider, and the width W3 of space 206 is wider than the width W2 of space 204. In addition, in the exposure mask of FIG. 5(A), the line width is the same.

[0114] The exposure mask in FIG. 5(A) is an example, and the light intensity distribution shown in FIG. 5(B) is obtained. For example, as shown in FIG. 5(C), Exposure is performed using an exposure mask having a light-shielding portion 215 with an acute angle at the end, and the result is shown in FIG. In addition, the light intensity distribution is set to be such that the light shielding portion 216 having a plurality of branches as shown in FIG. Using an exposure mask having the above structure, the light intensity distribution shown in FIG. 5(B) is obtained.

[0115] This embodiment mode can be freely combined with the first embodiment mode.

[0116] (Embodiment 3) This embodiment is an example that is partially different from the embodiment 2, and will be described with reference to FIG. Since the figure is the same as in FIG. 3(A), detailed explanations are omitted here, and the same parts are denoted by the same reference numerals. I will use this to explain.

[0117] According to the second embodiment, the steps up to forming the third conductive layer 115 are carried out, and the result is shown in FIG. The same stage.

[0118] Next, the third conductive layer 115 is selectively etched using a photomask different from that in the second embodiment. In this embodiment, the pixel portion has a taper angle on only one side. A first connection electrode 120 is formed, and a second connection electrode having the same taper angle on both ends is formed at the terminal portion. This is an example of forming an electrode 121.

[0119] After the etching process is completed, the remaining resist mask is removed by ashing or the like. Remove.

[0120] Next, after forming a transparent conductive film, a resist mask was formed using a fifth photomask. A part of the transparent conductive film is etched using a The pixel electrode 122 is electrically connected to the terminal portion, and the second connection electrode 121 is electrically connected to the terminal portion. A third connection electrode 123 is formed.

[0121] In this embodiment, the pixel electrode 122 has a tapered shape of the first connection electrode 120. By providing the pixel electrode 122 so as to overlap the portion where the pixel electrode 122 is being cut, a step-disconnection of the pixel electrode 122 is prevented.

[0122] In this manner, an element substrate that can be used in a transmission type liquid crystal display device can be formed. .

[0123] This embodiment mode can be freely combined with the first or second embodiment mode.

[0124] (Embodiment 4) In this embodiment, an auxiliary pattern ( This is an example where a halftone film is used.

[0125] First, as in the first embodiment, a first conductive layer 103 is formed on a substrate 101. Forms a gyrus membrane.

[0126] In FIG. 7A, the exposure mask 420 has a light-shielding portion 421a made of a metal film such as Cr. , 421b, and a semi-transparent film (halftone film) as an auxiliary pattern having a light intensity reducing function. (also referred to as semi-transparent portions 422a and 422b) are provided. In the cross-sectional view of the exposure mask 420, the light-shielding portion 421b and the semi-transmitting portion 422b are shielded. The width of the overlapping area of ​​the light-transmitting portion 421b and the semi-transmitting portion 422b is denoted as t2. In other words, the width of the region of one layer is indicated as t1 and t3 in the semi-transmissive portion 422a. The widths of the regions not overlapping with the portion 421a are denoted as t1 and t3.

[0127] When the resist film is exposed to light using the exposure mask 420 shown in FIG. Non-exposed regions 423a and 423b and exposed region 423c are formed. By passing through the semi-transparent portions 422a and 422b, An exposed region 423c shown in FIG. 7(A) is formed.

[0128] Then, when development is performed, the exposed area 423c is removed, and the substrate is left as shown in FIG. The resist mask 424a has a perforated shape on both sides, and the resist mask 424b has a rectangular cross section. A mask 424b is obtained on the first conductive layer 103.

[0129] Next, using the resist masks 424a and 424b as masks, Then, the first conductive layer 103 is etched.

[0130] After the etching process is completed, the remaining resist mask is removed by ashing or the like. In this way, as shown in FIG. 7C, the first wiring layer 124a and The second wiring layer 124b is formed on the pixel portion. The taper angle of the layer 124a is set to about 60°, and the side surface of the second wiring layer 124b formed in the terminal portion The angle is approximately 90°.

[0131] In the subsequent steps, a thin film transistor is formed according to the first embodiment, and a transmissive liquid crystal display device is manufactured. The present invention provides an element substrate that can be used in the above.

[0132] This embodiment can be freely combined with embodiment 1, embodiment 2, or embodiment 3. It is possible.

[0133] (Embodiment 5) In this embodiment, the wiring has a cross-sectional shape having two steps, a trapezoidal cross-sectional shape, and a This is an example in which three types of cross-sectional shapes having steps are formed using the same mask.

[0134] First, as in the first embodiment, a first conductive layer 103 is formed on a substrate 101. Forms a gyrus membrane.

[0135] Next, the resist film is exposed to light using an exposure mask 430 shown in FIG. When the film is exposed to light, the resist film has non-exposed regions 433a, 433b, and 433d and exposed regions 433c. During exposure, light is absorbed by the light shielding portion 431b and the semi-transmitting portion 431a and 33c. By passing through 431c, an exposed area 433c shown in FIG. 8(A) is formed.

[0136] In this embodiment, the first photomask is an exposure mask having a light intensity reducing function in a part thereof. Auxiliary patterns (gray tones) are installed to provide a pixel area for the thin film transistor. Two steps are formed on both ends of the gate electrode. The first photomask is shown in FIG. The pattern shown in the figure is arranged on both sides of the light-shielding part. By changing the conditions, a light intensity distribution different from that shown in FIG. 5(B), for example, the light intensity distribution shown in FIG. 5(E), can be obtained. The light intensity distribution 217 has two steps. The exposure mask shown in FIG. For example, as shown in FIG. 5C, a light shielding pattern having a sharp edge, rather than a line, may be used. Exposure is performed using an exposure mask having a portion 215, and the light intensity distribution shown in FIG. Also, an exposure mask having a light shielding portion 216 with a plurality of branch portions as shown in FIG. A light intensity distribution shown in FIG. 5(E) may be obtained by using a mask.

[0137] In addition, a step is formed on both ends of the connection electrode of the terminal section. It is formed by using a semi-transparent portion 431c different from the gate electrode.

[0138] Then, when development is performed, the exposed area 433c is removed, and the image is left as shown in FIG. A first resist mask 434a is applied to the elemental portion, and a second resist mask is applied to the gate wiring portion of the pixel portion. A resist mask 434b is formed on the first conductive layer 103, and a third resist mask 434c is formed on the terminal portion. By adjusting the exposure conditions such as the exposure energy, a first step with two steps at the edge can be obtained. A resist mask 434a of 1 can be obtained. In the gate wiring portion of the pixel portion exposed with the photomask, a trapezoidal second resist A mask 434b is formed. A third resist having a step at an end is formed at the terminal portion. Thus, a top mask 434c can be obtained.

[0139] Next, using the resist masks 434a, 434b, and 434c as masks, dry etching is performed. The first conductive layer 103 is etched by etching.

[0140] After the etching process is completed, the remaining resist mask is removed by ashing or the like. In this way, as shown in FIG. 8C, the first wiring layer 125a and A second wiring layer 125b and a third wiring layer 125c are formed. The first wiring layer 125a formed in the above-mentioned manner has two steps at its end, and the gate wiring of the pixel portion is The side of the second wiring layer 125b formed in the terminal portion is trapezoidal, and the side of the third wiring layer 125b formed in the terminal portion is trapezoidal. The line layer 125c has an end portion with one step. When the line layer 125c has a tapered shape, the end of the tapered The position of the part depends on the etching time. In particular, if the taper angle is less than 60°, the total However, by using a stepped wiring layer, the etching Even if the time varies slightly, a constant wiring width can be obtained. In other words, by making the wiring layers stepwise, This allows for a sufficient margin in the etching conditions. By making the end have two steps, the tapered shape has a taper angle of less than 50°. It is possible to ensure the same level of step coverage as the wiring layer. The side angle of the formed second wiring layer 125b is in the range of 60° to 90°.

[0141] In this way, the operator can select the shape of the desired wiring layer by appropriately designing the exposure mask 430. It can be formed in a systematic way.

[0142] In the subsequent steps, a thin film transistor is formed according to the first embodiment, and a transmissive liquid crystal display device is manufactured. The present invention provides an element substrate that can be used in the above.

[0143] This embodiment is the same as the first, second, third, or fourth embodiment. can be freely combined.

[0144] (Embodiment 6) In this embodiment mode, a manufacturing process of a thin film transistor used in a liquid crystal display device will be described with reference to FIG. 9 to 11 show the manufacturing process of a thin film transistor. FIG. 12 is a cross-sectional view of a thin film transistor and a pixel electrode connection region in one pixel. FIG. 13 is a timing chart showing a method for forming a microcrystalline silicon film. FIG. 14 is a cross-sectional view of an etching device used to form electrodes or wiring. be.

[0145] Thin film transistors with microcrystalline semiconductor films have higher mobility in n-type transistors than in p-type transistors. It is more suitable for use in driving circuits. It is desirable to have the same polarity for the n-channel transistors in order to reduce the number of processes. A description will be given using a thin film transistor of this type.

[0146] As shown in FIG. 9A, a gate electrode 51 is formed on a substrate 50. The substrate 50 is a ballast. Borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass It is possible to use non-alkali glass substrates manufactured by the fusion method or float method. If the substrate 50 is a mother glass, the size of the substrate is 1st generation (320 mm x 40 0mm), 2nd generation (400mm x 500mm), 3rd generation (550mm x 650mm) , 4th generation (680mm x 880mm, or 730mm x 920mm), 5th generation (1 000mm x 1200mm or 1100mm x 1250mm), 6th generation 1500mm x 1800mm), 7th generation (1900mm x 2200mm), 8th generation (2160mm) ×2460mm), 9th generation (2400mm×2800mm, 2450mm×3050m m), 10th generation (2950mm x 3400mm), etc. can be used.

[0147] The gate electrode 51 is made of titanium, molybdenum, chromium, tantalum, tungsten, aluminum, or the like. The gate electrode 51 is formed by sputtering. A conductive film is formed on the substrate 50 by a coating method or a vacuum deposition method, and the conductive film shown in the first embodiment is A resist mask is formed using a multi-tone mask, and a conductive film is etched using the mask. In addition, a barrier layer is formed to improve the adhesion of the gate electrode 51 and prevent the gate electrode 51 from diffusing into the underlying layer. As the metal, a nitride film of the above-mentioned metal material may be provided between the substrate 50 and the gate electrode 51. Here, a resist mask formed using a multi-tone photomask is used. The conductive film formed on the substrate 50 is then etched to form a gate electrode 51, and the gate electrode Wiring with different side angles (gate wiring, routing wiring, capacitance wiring, etc.) are also formed at the same time. do.

[0148] In this embodiment, the etching is performed using an etching apparatus shown in FIG.

[0149] In the etching apparatus shown in FIG. 14, the upper electrode 137 is grounded and the lower electrode 135 is connected to a ground potential of 13.5 V. A 6 MHz high frequency power supply 132 is connected, and a 3.2 MHz low frequency power supply is further connected to the lower electrode 135. ECCP (Enhanced Capacitively Coupled) with source 131 This is an etching device that operates in the LED Plasma mode. For example, the substrate 50 can be used in a case where a 10th generation substrate having a size exceeding 3 m is used. It is possible.

[0150] The chamber 130 has an opening on the outer wall thereof for introducing a substrate to be processed. A gate valve 133 is provided at the substrate load chamber or the access point. The chamber 130 is connected to the unloading chamber or the transfer chamber. The pressure in the chamber 130 can be reduced by a vacuum exhaust means such as a pump. It has a pair of parallel plate electrodes consisting of an upper electrode 137 and a lower electrode 135 .

[0151] The upper electrode 137 is a shower head, and an etching gas is introduced into the chamber 130. In addition, the upper electrode 137 has a hollow portion through which an etchant is introduced. The mixing gas is supplied from a gas supply mechanism 139 connected via a gas supply pipe and a valve. In addition, the gas supply mechanism 139 is connected to the gas supply source 138.

[0152] An insulating member 134 is provided on the outer periphery and the upper peripheral edge of the lower electrode 135. However, the lower electrode 135 is provided with an electrostatic chuck or the like for holding the substrate 136 to be processed. The apparatus includes a substrate holding means and a heating or cooling means for adjusting the temperature. The outer electrode 137 may be provided with a heating means or a cooling means for adjusting the temperature.

[0153] A power supply line is electrically connected to the lower electrode 135. The power supply line is connected to a first matching unit 1. 40a is connected to a high-frequency power supply 132. The high-frequency power supply 132 has a frequency of 13.56 MHz. The high frequency power for plasma generation is supplied to the lower electrode. The combiner 140b is connected to a low-frequency power source 131. The low-frequency power source 131 is, for example, A 2MHz high frequency power is supplied to the lower electrode and is superimposed on the high frequency power for plasma generation. It looks like this.

[0154] Moreover, each component of the etching apparatus shown in FIG. 14 is controlled by a process controller. By using this etching equipment, even 10th generation substrates over 3m in size can be used. It is possible to ensure in-plane uniformity.

[0155] Next, gate insulating films 52a, 52b, and 52c are formed in this order on the gate electrode 51. The cross-sectional view after completing the steps up to this point corresponds to FIG.

[0156] The gate insulating films 52a, 52b, and 52c are formed by using a CVD method, a sputtering method, or the like. The insulating film may be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. In order to prevent interlayer shorts caused by pinholes in the gate insulating film, It is preferable to form a multi-layer structure using insulating layers. 2c shows a form in which a silicon nitride film, a silicon oxynitride film, and a silicon nitride film are laminated in this order. vinegar.

[0157] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. The concentration range is 55 to 65 atomic percent for oxygen, 1 to 20 atomic percent for nitrogen, and 25 to 40 atomic percent for silicon. 35 atomic % and hydrogen in the range of 0.1 to 10 atomic %.

[0158] The thickness of the first and second layers of the gate insulating film is set to be greater than 50 nm. The first layer is silicon nitride to prevent the diffusion of impurities (such as alkali metals) from the substrate. The first layer of the gate insulating film is preferably a silicon oxide nitride film. In addition to preventing oxidation, it can also prevent hillocks when aluminum is used for the gate electrode. The third layer of the gate insulating film in contact with the crystalline semiconductor film is thicker than 0 nm and less than 5 nm, preferably The third layer of the gate insulating film is about 1 nm thick to improve adhesion with the microcrystalline semiconductor film. In addition, the third layer of the gate insulating film is made of silicon nitride, which is For example, the oxygen content of the microcrystalline semiconductor film is When heat treatment is performed in a state where a thick insulating film and a microcrystalline semiconductor film are in contact with each other, the microcrystalline semiconductor film is oxidized. There is a risk.

[0159] Furthermore, a gate insulating film was formed using a microwave plasma CVD device with a frequency of 1 GHz. It is preferable to form a silicon oxynitride film or a silicon nitride film using a microwave plasma CVD apparatus. The silicon nitride film has a high withstand voltage and can improve the reliability of the thin film transistor.

[0160] Here, the gate insulating film has a three-layer structure, but it is also used for the switching element of a liquid crystal display device. In this case, since it is driven by AC, only a single layer of silicon nitride film may be used.

[0161] Next, after the gate insulating film is formed, the substrate is transported without being exposed to the air, and the gate insulating film The microcrystalline semiconductor film 53 is formed in a vacuum chamber different from the vacuum chamber in which the is preferred.

[0162] A procedure for forming the microcrystalline semiconductor film 53 will be described below with reference to FIG. The explanation in 13 starts from the stage of evacuating the vacuum chamber from atmospheric pressure to vacuum 200. After that, pre-coating 1201, substrate loading 1202, base pre-treatment 1203, and film formation process are performed. The processes of 1204, 1205 for removing the substrate, and 1206 for cleaning are shown in chronological order. However, it is not limited to evacuation from atmospheric pressure, and it is also possible to maintain a certain degree of vacuum in the vacuum chamber at all times. It is preferable to maintain the same number of nozzles for mass production, or to reduce the ultimate vacuum in a short time. Above is preferred.

[0163] In this embodiment, the degree of vacuum in the vacuum chamber before the substrate is loaded is set to 10 -5 Lower than Pa This stage corresponds to the vacuum evacuation 1200 in FIG. When performing high vacuum evacuation, a cryopump is used in combination with a turbo molecular pump to evacuate the gas. It is also preferable to use a cryopump for vacuum evacuation. It is also effective to connect the tubes in a row and evacuate them. It is preferable to provide a heater and perform a heat treatment to remove gases from the inner wall of the vacuum chamber. The heater for heating the substrate is also operated to stabilize the temperature. The reaction is carried out at a temperature of from 120°C to 300°C, preferably from 120°C to 220°C.

[0164] Next, a precoat 1201 is performed before the substrate is carried in, and a silicon film is formed as an inner wall coating film. As the precoat 1201, hydrogen or a rare gas is introduced to generate plasma and evacuate the vacuum. Gases (atmospheric components such as oxygen and nitrogen, or vacuum chamber components) adhering to the inner walls of the chamber After removing the etching gas used to clean the plate, silane gas is introduced to Silane gas reacts with oxygen and moisture, so it is necessary to flow silane gas and By generating silane plasma in the vacuum chamber, oxygen and moisture can be removed. In addition, by performing the precoat 1201 treatment, the vacuum chamber is formed in the microcrystalline silicon film. This prevents the metal elements of the components that make up the member from being absorbed as impurities. In other words, by covering the inside of the vacuum chamber with silicon, the inside of the vacuum chamber This prevents the silicon from being etched by plasma, and the silicon is included in the microcrystalline silicon film that is formed later. The precoat 1201 is used to coat the inner wall of the vacuum chamber. It involves coating a substrate with the same type of film that is to be deposited on the substrate.

[0165] After pre-coating 1201, the substrate is loaded 1202. A microcrystalline silicon film is deposited. The substrates to be tested are stored in a vacuum-evacuated load chamber. The degree of vacuum in the empty chamber does not deteriorate significantly.

[0166] Next, a base pretreatment 1203 is performed. The base pretreatment 1203 is a process for forming a microcrystalline silicon film. In particular, it is preferable to carry out the above-mentioned treatment when the glass substrate surface is A microcrystalline silicon film is formed on the surface of the insulating film or the surface of the amorphous silicon by a plasma CVD method. When a film is formed by this method, the film becomes amorphous in the early stages of deposition due to factors such as impurities and lattice mismatch. The thickness of this amorphous layer should be reduced as much as possible, and if possible, eliminated. It is preferable to perform a base pretreatment 1203 in order to prevent the formation of a fluorine-containing layer. It is preferable to carry out the treatment by a rare gas plasma, a hydrogen plasma treatment, or a combination of the two. For the Zuma treatment, rare gas elements with large mass numbers such as argon, krypton, and xenon are used. It is preferable to use a spatula to remove impurities such as oxygen, moisture, organic matter, and metal elements from the surface. The hydrogen plasma treatment removes the surface by hydrogen radicals. Removal of the impurities adsorbed on the surface and etching of the insulating film or amorphous silicon film This is effective in forming a clean surface on which a film is to be formed. The use of a plasma treatment in combination helps to promote the formation of microcrystalline nuclei.

[0167] In terms of promoting the generation of fine crystal nuclei, as shown by the dashed line 1207 in FIG. In addition, it is effective to continue supplying a rare gas such as argon in the initial stage of the formation of the microcrystalline silicon film. It is effective.

[0168] Next, a substrate pretreatment 1203 is followed by a film formation process 1204 for forming a microcrystalline silicon film. In this embodiment, the first film formation condition, which has a low film formation rate but good quality, is used to form a gate insulating film interface. A film is formed in the vicinity of the first deposition condition, and then the film is deposited under second deposition conditions with a higher deposition rate.

[0169] There is no particular limitation as long as the film formation rate under the second film formation condition is faster than the film formation rate under the first film formation condition. Therefore, the high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz, or It is formed by a microwave plasma CVD apparatus of 1GHz or more, typically SiH4, Silicon hydride such as Si2H6 can be diluted with hydrogen and plasma generated to form a film. In addition to silicon hydride and hydrogen, helium, argon, krypton, and neon can also be used. A microcrystalline semiconductor film can be formed by diluting with one or more selected rare gas elements. In these cases, the flow rate ratio of hydrogen to silicon hydride is preferably 12 to 1000 times. Preferably, the ratio is 50 to 200 times, more preferably 100 times. Instead, SiH2Cl2, SiHCl3, SiCl4, SiF4, etc. can be used. .

[0170] In addition, when helium is added to the material gas, helium has the highest energy of all gases at 24.5 eV. has a high ionization energy, and is slightly lower than that, about 20 eV Since there is a metastable state at the level of 1, the difference in ionization is about 4 eV during the discharge. Therefore, the discharge starting voltage is the lowest among all gases. Due to its properties, helium can maintain a stable plasma. It also creates a uniform plasma. Therefore, even if the area of ​​the substrate on which the microcrystalline silicon film is deposited becomes large, the plate can be formed without any problems. This has the effect of making the plasma density uniform.

[0171] In addition, carbon hydrides such as CH4, C2H6, GeH4, GeF4, etc. are present in silane gas. By mixing germanium hydrides and germanium fluorides such as these, the energy bandwidth can be increased to 1. It may be adjusted to 5 to 2.4 eV or 0.9 to 1.1 eV. Adding luminium can change the temperature characteristics of the TFT.

[0172] Here, the first film formation condition is that silane is mixed with hydrogen and / or a rare gas at a concentration of 100 times or more and 2000 times or more. The substrate is heated to a temperature of 100°C to 300°C, preferably 120°C to 220°C. The growth surface of the microcrystalline silicon film is inactivated with hydrogen to promote the growth of microcrystalline silicon. To achieve this, it is preferable to perform film formation at a temperature of 120°C to 220°C.

[0173] FIG. 9B shows a cross-sectional view of the gate insulating film 52c after the first film formation condition is completed. Although the deposition rate is low, a microcrystalline semiconductor film 23 having good quality is formed. The quality of the microcrystalline semiconductor film 23 obtained under these conditions is important for increasing the on-current of the TFT to be formed later and To improve the field effect mobility, the oxygen concentration in the film is set to 1×10 17 / cm or less It is important to reduce the oxygen concentration sufficiently so that the oxygen concentration is not increased by the above procedure. Therefore, the concentration of nitrogen and carbon mixed into the microcrystalline semiconductor film can be reduced. Therefore, the microcrystalline semiconductor film can be prevented from becoming n-type.

[0174] Next, the film formation conditions are changed to the second film formation conditions, and the film formation speed is increased to form a microcrystalline semiconductor film 53. The cross-sectional view at this stage corresponds to FIG. The thickness of the insulating film 11 may be set to 0 nm (preferably 100 nm to 250 nm). The deposition time of the microcrystalline semiconductor film 53 is the first deposition period in which the film is deposited under the first deposition condition. and a second deposition period during which deposition is performed under the second deposition condition.

[0175] Here, the second film formation condition is that silane is mixed with hydrogen and / or a rare gas at a ratio of 12 times to 100 times. The heating temperature of the substrate is 100°C to 300°C, preferably 120°C to 220°C. In addition, a capacitively coupled (parallel plate) CVD device was used, and the gap (the distance between the electrode surface and the substrate surface) was The spacing between the plates was set to 20 mm, the vacuum in the vacuum chamber was set to 100 Pa, and the substrate temperature was set to 300°C. Then, 20 W of 60 MHz high-frequency power was applied, and silane gas (flow rate 8 sccm) and hydrogen (flow rate 400sccm) and dilute 50 times to form a microcrystalline silicon film. Then, the flow rate of silane gas was changed to 4 sccm and diluted 100 times to form a microcrystalline silicon film. The deposition rate slows down when the film is formed. By fixing the hydrogen flow rate and increasing the silane flow rate, the deposition rate By decreasing the deposition rate, the crystallinity is improved.

[0176] In this embodiment, a capacitively coupled (parallel plate) CVD apparatus is used, and the gap (between the electrode surface and The first deposition condition was a vacuum of 100P in the vacuum chamber. a, the substrate temperature was 100°C, 30 W of 60 MHz high frequency power was applied, and silane gas (flow The gas flow rate was 200 times diluted with hydrogen (flow rate 400 sccm). The second deposition condition was to increase the deposition rate by changing the flow rate of silane gas at 4 sccm and hydrogen gas (flow rate 4 The film is formed under the condition of diluting the solution 100 times at 0.00 sccm.

[0177] Next, after the formation of the microcrystalline silicon film under the second film formation conditions is completed, materials such as silane and hydrogen are added. The supply of the gas and high frequency power is stopped, and the substrate is removed (1205). When a film formation process is to be performed using the vacuum chamber, the process returns to the stage of substrate loading 1202 and the same process is performed. Cleaning 1206 is performed to remove any coating or powder adhering to the inside of the chamber.

[0178] Cleaning 1206 is a plasma etching process using etching gases such as NF3 and SF6. Etching is performed. Also, etching can be performed without using plasma like ClF3. In the cleaning step 1206, the heater for heating the substrate is turned off. It is preferable to lower the temperature in order to suppress the generation of reaction by-products due to etching. After the cleaning 1206 is completed, the process returns to the pre-coat 1201 and the next substrate is The same process as described above can be carried out. Since NF3 contains nitrogen in its composition, the nitrogen in the deposition chamber In order to reduce the concentration, it is desirable to carry out precoating to sufficiently reduce the nitrogen concentration.

[0179] Next, after the microcrystalline semiconductor film 53 is formed, the substrate is transported without being exposed to the air. The buffer layer 54 is formed in a vacuum chamber different from the vacuum chamber in which the semiconductor film 53 is formed. By separating the buffer layer 54 from the vacuum chamber, the microcrystalline semiconductor The vacuum chamber in which the film 53 is formed is a dedicated chamber that is evacuated to an ultra-high vacuum before the substrate is introduced. This makes it possible to minimize impurity contamination and shorten the time required to reach ultra-high vacuum. When baking is performed to achieve ultra-high vacuum, the temperature of the chamber inner wall drops and becomes stable. This is particularly effective because it takes time for the vacuum chamber to become The frequency of the high frequency power can be varied according to the film quality to be obtained. .

[0180] The buffer layer 54 is formed using an amorphous semiconductor film containing hydrogen or halogen. Hydrogen is introduced at a flow rate of 1 to 10 times, more preferably 1 to 5 times, the flow rate of silicon hydride. By using the above-mentioned silicon hydride, an amorphous semiconductor film containing hydrogen can be formed. Gases containing fluorine, chlorine, bromine, or iodine (F2, Cl2, Br2, I2, HF, H Cl, HBr, HI, etc.) to produce amorphous materials containing fluorine, chlorine, bromine, or iodine. A high-quality semiconductor film can be formed. Instead of silicon hydride, SiH2Cl2, S iHCl3, SiCl4, SiF4, etc. can be used.

[0181] The buffer layer 54 is formed by sparging with hydrogen or a rare gas using an amorphous semiconductor as a target. In addition, the amorphous semiconductor film can be formed by ionizing the fluorine or chlorine in the atmosphere. , bromine, or iodine-containing gases (F2, Cl2, Br2, I2, HF, HCl, HBr , HI, etc.) to produce amorphous semiconductors containing fluorine, chlorine, bromine, or iodine. A body membrane can be formed.

[0182] The buffer layer 54 is preferably formed of an amorphous semiconductor film that does not contain crystal grains. Therefore, high-frequency plasma CVD with frequencies of several tens to several hundreds of MHz or microwave plasma CVD is used. When forming the film using the Zuma CVD method, the film formation conditions are adjusted so that the film becomes an amorphous semiconductor film that does not contain crystal grains. It is preferable to control the condition.

[0183] The buffer layer 54 is partially etched in the subsequent process of forming the source and drain regions. At this time, a part of the buffer layer 54 is removed so that the microcrystalline semiconductor film 53 is not exposed. It is preferable to form the film with a thickness that allows the remaining film to have a thickness of 100 nm or more and 400 nm or less. It is preferable to form the thin film transistor with a thickness of 200 nm or more and 300 nm or less. In display devices where a high voltage is applied to the transistor (for example, about 15 V), typically a liquid crystal display device, In addition, when the thickness of the buffer layer 54 is made thicker as shown in the above range, the breakdown voltage is increased. To prevent the thin film transistor from deteriorating even when a high voltage is applied to the thin film transistor. It is possible.

[0184] The buffer layer 54 is doped with impurities such as phosphorus or boron that impart one conductivity type. The semiconductor film 55 to which the impurity that imparts one conductivity type is added is not The buffer layer 54 functions as a barrier layer to prevent substances from diffusing into the microcrystalline semiconductor film 53. In the case where a buffer layer is not provided, the microcrystalline semiconductor film 53 is doped with an impurity imparting one conductivity type. If the semiconductor film 55 comes into contact with the semiconductor film 55, impurities may be removed by the subsequent etching process or heat treatment. may move, making threshold control difficult.

[0185] Furthermore, a buffer layer 54 is formed on the surface of the microcrystalline semiconductor film 53. It is possible to prevent natural oxidation of the surface of the crystal grains contained in 53. In the area where the matrix and the microcrystal grains come into contact, cracks are easily generated due to local stress. When exposed to heat, the grains are oxidized and silicon oxide is formed.

[0186] The energy gap of the buffer layer 54, which is an amorphous semiconductor film, is larger than that of the microcrystalline semiconductor film 53. (The energy gap of the amorphous semiconductor film is 1.6 eV to 1.8 eV, and the fine The energy gap of the crystalline semiconductor film 53 is 1.1 eV or more and 1.5 eV or less, and the resistance is high. The mobility is low, being 1 / 5 to 1 / 10 of that of the microcrystalline semiconductor film 53. In the thin film transistor to be formed, the source region and the drain region and the microcrystalline semiconductor film 53 The buffer layer formed between the microcrystalline semiconductor film 53 and the channel functions as a high resistance region. This function serves as a region for forming a thin film transistor, thereby reducing the off-current of the thin film transistor. When the thin film transistor is used as a switching element of a display device, The contrast can be improved.

[0187] A buffer layer 54 is formed on the microcrystalline semiconductor film 53 by plasma CVD at 300° C. to 400° C. The deposition temperature is preferably 0.5 to 100° C. Hydrogen is removed from the microcrystalline semiconductor film 5 by this deposition process. 3, the same effect as hydrogenating the microcrystalline semiconductor film 53 can be obtained. That is, By depositing the buffer layer 54 on the microcrystalline semiconductor film 53, the microcrystalline semiconductor film 53 is The element can be diffused to terminate dangling bonds.

[0188] Next, after the buffer layer 54 is formed, the substrate is transported without being exposed to the air, and the buffer layer The impurity that gives one conductivity type is deposited in a vacuum chamber different from the vacuum chamber in which 54 is deposited. It is preferable to form a doped semiconductor film 55. The cross section at this stage is shown in FIG. The buffer layer 54 is formed in a vacuum chamber different from the vacuum chamber in which the buffer layer 54 is formed. By forming a semiconductor film 55 to which an impurity for imparting a shape is added, a uniform structure is formed during the formation of the buffer layer. This can prevent impurities that impart a conductivity type from being mixed in.

[0189] The semiconductor film 55 to which an impurity that imparts one conductivity type is added is an n-channel thin film transistor. When forming a silicon hydride, phosphorus is added as a typical impurity element. Adding impurity gas such as PH3 is sufficient. Also, forming a p-channel thin film transistor In this case, boron can be added as a typical impurity element, and hydrogenated silicon can be added to BH The semiconductor film 5 to which an impurity that gives one conductivity type is added may be formed by adding an impurity gas such as 6. The semiconductor layer 5 can be made of a microcrystalline semiconductor or an amorphous semiconductor. The semiconductor film 55 to which the impurity is added is formed to a thickness of 2 nm to 50 nm. The throughput is improved by thinning the thickness of the semiconductor film to which the impurities that give the impurities are added. It is possible to do so.

[0190] Next, as shown in FIG. 10(A), a semiconductor film 5 to which an impurity that imparts one conductivity type is added is formed. A resist mask 56 is formed on the 5. The resist mask 56 is formed by photolithography. Alternatively, the second photomask is used to form the first conductive film. The resist applied on the semiconductor film 55 to which the impurity that gives the charge type is added is exposed and developed. Then, a resist mask 56 is formed.

[0191] Next, the microcrystalline semiconductor film 53, the buffer layer 54, and the conductive type The semiconductor film 55 doped with the impurity imparting the electric field is etched and separated to obtain the semiconductor film 55 shown in FIG. As shown in FIG. 1, the microcrystalline semiconductor film 61, the buffer layer 62, and the semiconductor layer 63 are doped with an impurity imparting one conductivity type. This forms a semiconductor film 63. After that, the resist mask 56 is removed.

[0192] Since the end side surfaces of the microcrystalline semiconductor film 61 and the buffer layer 62 are inclined, A leakage current is generated between the source region and the drain region formed on the microcrystalline semiconductor film 62 and the microcrystalline semiconductor film 61. In addition, the source electrode and the drain electrode are micro-connected. Therefore, it is possible to prevent the occurrence of leakage current between the microcrystalline semiconductor film 61 and the microcrystalline semiconductor film 62. The inclination angle of the end side surface of the film 61 and the buffer layer 62 is 30° to 90°, preferably 45°. By setting the angle in this range, the source electrode or drain electrode due to the step shape can be prevented from being damaged. This can prevent the inner electrode from breaking.

[0193] Next, as shown in FIG. 10C, a semiconductor film 63 to which an impurity that imparts one conductivity type is added is The conductive films 65a to 65c are formed so as to cover the gate insulating film 52c. 65c is made of aluminum, copper, silicon, titanium, neodymium, scandium, molybdenum, Aluminum alloys containing elements such as ribdenum to improve heat resistance or to prevent hillocks. It is preferable that the semiconductor device is formed of a single layer or a laminate of the above-mentioned. The film in contact with the semiconductor film is made of titanium, tantalum, molybdenum, tungsten, or It is formed by forming nitrides of these elements, and then forming aluminum or an aluminum alloy on top of it. Furthermore, the upper and lower surfaces of the aluminum or aluminum alloy may be laminated. sandwiched between titanium, tantalum, molybdenum, tungsten, or nitrides of these elements. Alternatively, the conductive film may have a laminated structure. In this embodiment, the conductive film is a laminate of three conductive films 65a to 65c. The conductive film 65a and 65c are made of molybdenum films, and the conductive film 65b is made of aluminum films. A laminated conductive film using a titanium film, a titanium film for the conductive film 65a and 65c, and an aluminum film for the conductive film 65b. The conductive films 65a to 65c are formed by sputtering or a pure aluminum film. It is formed by vacuum deposition.

[0194] Next, as shown in FIG. 10(D), a third photomask is used on the conductive films 65a to 65c. A resist mask 66 is formed, and a part of the conductive films 65a to 65c is etched to form a pair of solenoids. The source and drain electrodes 71a to 71c are formed. As a result, the conductive films 65a to 65c are isotropically etched. Therefore, the source and drain electrodes having a smaller area than the resist mask 66 are selectively etched. The electrodes 71a to 71c can be formed.

[0195] Next, as shown in FIG. 11(A), a resist mask 66 is used to remove impurities that impart one conductivity type. The doped semiconductor film 63 is etched to form a pair of source and drain regions 72. Furthermore, in this etching process, a part of the buffer layer 62 is also etched. The buffer layer in which a part is etched and a recess (groove) is formed is designated as buffer layer 73. The source and drain regions are formed in the same process as the recess (trench) in the buffer layer. The depth of the recess (groove) in the buffer layer can be set to the thickness of the buffer layer 73 at its thickest point. By making the area 1 / 2 to 1 / 3 of the area where the source and drain regions are located, the distance between the source and drain regions can be increased. Therefore, the leakage current between the source region and the drain region can be reduced. After that, the resist mask 66 is removed.

[0196] In particular, when exposed to plasma used in dry etching, the resist mask changes in quality and becomes In order to prevent the buffer layer 73 from being completely removed in the etching removal process and leaving residue, the buffer layer 73 is The resist mask 66 is etched by etching a part of the conductive films 65a to 65c. The silicon dioxide is used twice: in the etching process for forming the source and drain regions 72 and in the etching process for forming the source and drain regions 72. In either case, dry etching is likely to leave residues, so it is necessary to remove the residues. The buffer layer 73 may be etched when it is completely removed. In addition, the buffer layer 73 is hardly damaged by plasma during dry etching. It is also possible to prevent the radiation from being applied to the crystalline semiconductor film 61 .

[0197] Next, as shown in FIG. 11(B), the source and drain electrodes 71a to 71c, The drain region 72, the buffer layer 73, the microcrystalline semiconductor film 61, and the gate insulating film 5 An insulating film 76 is formed to cover the gate insulating films 52a, 52b, and 52c. The insulating film 76 can be formed by the same film formation method as that of the insulating film 76. It is used to prevent the intrusion of contaminating impurities such as organic matter, metals, and water vapor, and a dense membrane is preferred. In addition, by using a silicon nitride film for the insulating film 76, the oxygen concentration in the buffer layer 73 can be reduced. 5×10 19 atoms / cm 3 Less than or equal to 1×10 19 atoms / cm 3 below It can be said that:

[0198] As shown in FIG. 11B, the ends of the source and drain electrodes 71a to 71c and the The ends of the source region and the drain region 72 are not aligned but are offset from each other. Since the ends of the drain electrodes 71a to 71c are spaced apart, In addition, the source electrode and the drain electrode 7 can be prevented from leaking current or shorting. The ends of the regions 1a to 71c and the ends of the source and drain regions 72 are not aligned but are shifted. Therefore, the source and drain electrodes 71a to 71c and the source and drain regions The electric field is not concentrated at the ends of the gate electrode 51 and the source and drain electrodes 71a to This prevents leakage current between the MOSFET 71 and 71c. It is possible to fabricate high-voltage thin film transistors.

[0199] Through the above steps, the thin film transistor 74 can be formed.

[0200] The thin film transistor described in this embodiment has a gate insulating film and a microcrystalline semiconductor film over a gate electrode. , a buffer layer, a source region, a drain region, a source electrode, and a drain electrode are laminated; The surface of the microcrystalline semiconductor film functioning as a channel formation region is covered with a buffer layer. A recess (groove) is formed in a part of the layer, and the area other than the recess is the source region and the drain region. That is, the source and drain regions are covered by the recesses formed in the buffer layer. The distance between the source and drain regions is large, which reduces leakage current between the source and drain regions. In addition, the buffer layer can be partially etched to form a recess. In order to remove the etching residues generated in the process of forming the source and drain regions, Therefore, leakage current (parasitic current) can flow through the residue to the source and drain regions. This can prevent the occurrence of a problem such as a channel failure.

[0201] In addition, the microcrystalline semiconductor film serving as a channel formation region and the source and drain regions A buffer layer is formed between the microcrystalline semiconductor film and the insulating film. The high resistance buffer layer is formed between the microcrystalline semiconductor film and the source and drain regions. Since the insulating layer extends between the thin film transistor and the insulating layer, the occurrence of leakage current in the thin film transistor can be reduced. This makes it possible to reduce deterioration caused by application of high voltage. The layer, the microcrystalline semiconductor film, the source region, and the drain region are all overlapped with the gate electrode. Therefore, it can be said that the structure is not affected by the edge shape of the gate electrode. When the electrode has a laminated structure, if aluminum is used as the lower layer, the aluminum on the side of the gate electrode However, the source and drain regions are also exposed, which may cause hillocks. By configuring the gate electrode so that it does not overlap with the edge of the gate electrode, In addition, the surface of the microcrystalline semiconductor film is prevented from being terminated by hydrogen. Since the end of the amorphous semiconductor film is formed as a buffer layer, the oxidation of the microcrystalline semiconductor film is prevented. It is possible to prevent the above-mentioned problems that occur during the process of forming the source and drain regions. It is possible to prevent etching residues from being mixed into the microcrystalline semiconductor film. The thin film transistor has excellent properties and excellent voltage resistance.

[0202] In addition, the channel length of the thin film transistor can be shortened, and the planar surface of the thin film transistor can be reduced. The product can be reduced.

[0203] Next, a resist mask is formed on the insulating film 76 using a fourth photomask. A contact hole is formed by etching a part of 76, and A pixel electrode 77 is formed in contact with the source electrode or drain electrode 71c. 12C) corresponds to a cross-sectional view taken along the dashed line AB in FIG.

[0204] As shown in FIG. 12, the ends of the source and drain regions 72 are connected to the source and drain electrodes. It can be seen that the end of the buffer layer 73 is located outside the end of the source electrode 71c. The source and drain electrodes 71c and the source and drain regions 72 are located outside the ends of the source and drain electrodes 71c and the source and drain regions 72. In addition, one of the source electrode and the drain electrode is connected to the other of the source region and the drain region. The shape is a circle (specifically, U-shaped or C-shaped). Therefore, the area where the carriers move is Since the area can be increased, the amount of current can be increased. In addition, the area of ​​the gate electrode can be reduced. Since the source electrode and the drain electrode are overlapped, the effect of the unevenness of the gate electrode is small. It is possible to reduce the coverage rate and suppress the occurrence of leakage current. One of the drain electrodes also functions as a source wiring or a drain wiring.

[0205] The width of the side of the gate wiring that does not overlap with the microcrystalline semiconductor film is This is narrower than the width of the gate electrode side, which is connected to the pixel. In addition, the angle (taper angle) of the side surface of the gate electrode overlapping the microcrystalline semiconductor film is This is smaller than the side of the gate wiring that does not overlap with the crystalline semiconductor film. This ensures good coating properties of the film that is formed.

[0206] The pixel electrode 77 is made of indium oxide containing tungsten oxide, tungsten oxide Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide Indium tin oxide, indium tin oxide, indium zinc oxide, indium oxide with silicon oxide added A light-transmitting conductive material such as indium tin oxide can be used.

[0207] The pixel electrode 77 is made of a conductive composition containing a conductive polymer. The pixel electrode 77 formed by using a conductive composition can be formed by a sheet. Resistance is 10000Ω / □ or less, and light transmittance at a wavelength of 550nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that:

[0208] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0209] Here, the pixel electrode 77 is formed by forming an indium tin oxide film by a sputtering method. After that, a resist is applied onto the indium tin oxide film. Next, a fifth photomask is used. The resist is exposed and developed using the resist mask to form a resist mask. The indium tin oxide film is then etched to form the pixel electrode 77.

[0210] In this manner, an element substrate that can be used in a display device can be formed.

[0211] This embodiment is the same as embodiment 1, embodiment 2, embodiment 3, embodiment 4 or embodiment It can be freely combined with form 5.

[0212] (Embodiment 7) In this embodiment, hydrogen or a rare gas is introduced to generate plasma before the substrate is carried into the vacuum chamber. The gas (oxygen, nitrogen, and other atmospheric components, or After removing the etching gas used to clean the vacuum chamber, hydrogen and silane were This example shows the introduction of a small amount of phosphine (PH3) gas and a small amount of fluorine gas. Since only the process is different, only the different process will be described in detail below with reference to FIG. In FIG. 15, the same parts as in the second embodiment are designated by the same reference numerals.

[0213] First, a gate electrode is formed on a substrate 350 using a multi-tone mask in the same manner as in the sixth embodiment. Here, a non-alkali glass substrate measuring 600 mm x 720 mm is used. In this example, a display device with a large display screen is manufactured using a large-area substrate. The first conductive layer 351a is made of aluminum having low air resistance. The gate electrode is formed by laminating a second conductive layer 351b made of molybdenum, which has a high heat resistance. The etching apparatus used is an ECCP mode etching apparatus shown in FIG.

[0214] Next, a gate insulating film 352 is formed on the second conductive layer 351b which is the upper layer of the gate electrode. When used as a switching element in a liquid crystal display device, the gate insulation is required to drive the device by AC. The film 352 is preferably a single layer of silicon nitride film. 2. A single-layer silicon nitride film (dielectric constant 7.0, thickness 300 nm) was deposited by plasma CVD. The cross-sectional view after the steps up to this point is shown in FIG.

[0215] Next, after the gate insulating film is formed, the substrate is transported without being exposed to the air, and the gate insulating film The microcrystalline semiconductor film is formed in a vacuum chamber different from the vacuum chamber in which the above film is formed.

[0216] Before the substrate is transferred into the vacuum chamber of the deposition equipment, hydrogen or a rare gas is introduced to generate a plasma. The gas (oxygen, nitrogen, and other atmospheric components, if any) attached to the inner wall of the vacuum chamber is After removing the etching gas (used for cleaning the vacuum chamber), hydrogen and silicon were Silane gas and a small amount of phosphine (PH3) gas are introduced. Silane gas is introduced into the vacuum chamber. The small amount of phosphine gas reacts with the oxygen and moisture in the film. Phosphorus can be contained in the microcrystalline semiconductor film.

[0217] Next, the substrate is carried into a vacuum chamber, and silane gas and After exposure to a small amount of phosphine gas, a microcrystalline semiconductor film is formed. Generally speaking, silicon hydrides such as SiH4 and Si2H6 are diluted with hydrogen to generate plasma. The flow rate of the silane gas is more than 100 times and less than 2000 times. By using hydrogen, a microcrystalline semiconductor film 353 containing phosphorus and hydrogen can be formed. By exposing the semiconductor substrate to the phosphine gas, crystal nucleation is promoted to form a microcrystalline semiconductor film 353. In the microcrystalline semiconductor film 353, the concentration of phosphorus increases with distance from the gate insulating film interface. The concentration profile shows a decreasing concentration as the concentration increases.

[0218] Next, the deposition conditions were changed in the same chamber, with the flow rate of silicon hydride being 1 to 10 times that of the original flow rate. More preferably, hydrogen is used at a flow rate of 1 to 5 times that of hydrogen, and the amorphous silicon containing hydrogen is A buffer layer 54 is then laminated. The cross-sectional view after completing the steps up to this point corresponds to FIG. 15(C). do.

[0219] Next, after the buffer layer 54 is formed, the substrate is transported without being exposed to the air, and the microcrystalline semiconductor The vacuum chamber for forming the solid film 353 and the buffer layer 54 is different from the vacuum chamber for forming the solid film 353 and the buffer layer 54. A semiconductor film 55 is formed by adding impurities that impart a conductivity type. Since this process is the same as that in the sixth embodiment, a detailed description thereof will be omitted here.

[0220] This embodiment includes embodiment 1, embodiment 2, embodiment 3, embodiment 4, and embodiment This can be freely combined with embodiment 5 or embodiment 6.

[0221] (Embodiment 8) A method for manufacturing a thin film transistor different from that in Embodiment 2 will be described with reference to FIGS. Here, the number of photomasks can be reduced compared to the sixth embodiment. The process for manufacturing a thin film transistor will be described.

[0222] As in the case of FIG. 9(A) shown in the sixth embodiment, a conductive film is formed on a substrate 50, and a laser is applied to the conductive film. A resist is applied and formed by a photolithography process using a multi-tone mask. A part of the conductive film is etched using a mask to form a gate electrode 51. Although not shown, gate electrodes or gate wirings having side surfaces with different taper angles are formed as appropriate. Next, gate insulating films 52a, 52b, and 52c are formed in this order on the gate electrode 51. .

[0223] Next, a microcrystalline semiconductor film 53 is formed under the first film formation condition. The film was formed under the film formation condition of 2, and a microcrystalline semiconductor was formed in the same manner as in FIG. 9(C) shown in the sixth embodiment. Next, in the same manner as in FIG. 9(D) shown in the sixth embodiment, the microcrystalline semiconductor film 5 A buffer layer 54 and a semiconductor film 55 doped with an impurity that gives one conductivity type are formed on the substrate 3 in this order. Complete.

[0224] Next, conductive films 65a to 65c are formed on the semiconductor film 55 to which an impurity imparting one conductivity type is added. Next, as shown in FIG. 16A, a resist 80 is applied onto the conductive film 65a. .

[0225] The resist 80 may be a positive resist or a negative resist. , shown using a positive resist.

[0226] Next, the resist 80 is irradiated with light using the multi-tone mask 59 as a second photomask. Then, the resist 80 is exposed.

[0227] After exposure using a multi-tone mask, the film is developed to have a thickness of 100 μm, as shown in FIG. A resist mask 81 having different regions can be formed.

[0228] Next, the microcrystalline semiconductor film 53, the buffer layer 54, and the first conductive layer 55 are formed on the resist mask 81. The semiconductor film 55 to which the impurity that imparts the charge type is added and the conductive films 65a to 65c are etched. As a result, the microcrystalline semiconductor film 61, the buffer layer 62, and the like are separated as shown in FIG. 62, a semiconductor film 63 to which an impurity that imparts one conductivity type is added, and conductive films 85a to 85c can be formed.

[0229] Next, the resist mask 81 is ashed. As a result, the area of ​​the resist is reduced and the thickness At this time, the resist in the thin region (which overlaps a part of the gate electrode 51) The resist mask 86 is then removed to form a separate resist mask 86, as shown in FIG. It is possible.

[0230] Next, the conductive films 85a to 85c are etched and separated using the resist mask 86. As a result, pairs of source and drain electrodes 92a to 92c are formed as shown in FIG. The conductive films 85a to 85c are formed by wet etching using the resist mask 86. When etching is performed, the ends of the conductive films 85a to 85c are selectively etched. Then, source and drain electrodes 92a to 92c having areas smaller than that of the resist mask 86 are formed. It can be achieved.

[0231] Next, a semiconductor film doped with an impurity that imparts one conductivity type is formed using a resist mask 86. 63 is etched to form a pair of source and drain regions 88. In the etching process, a part of the buffer layer 62 is also etched. The buffer layer thus formed is referred to as a buffer layer 87. A recess is formed in the buffer layer 87. The source and drain regions are formed in the same process as the recess (groove) of the buffer layer. In this case, a portion of the buffer layer 87 is smaller than the resist mask 81. The source and drain regions are partially etched away by the resist mask 86, which has a reduced area. The buffer layer 87 is formed to protrude outside the region 88. After that, the resist mask 86 is removed. In addition, the ends of the source and drain electrodes 92a to 92c and the source region and The ends of the drain region 88 are not aligned but are offset, and the source and drain electrodes 92a to 9 Outside the ends of 2c, the ends of source and drain regions 88 are formed.

[0232] As shown in FIG. 17C, the ends of the source and drain electrodes 92a to 92c and the The ends of the source region and the drain region 88 are not aligned but are offset from each other, so that the source electrode and Since the ends of the drain electrodes 92a to 92c are spaced apart, In addition, the source electrode and the drain electrode 9 can be prevented from leaking current or shorting. The ends of the electrodes 2a to 92c and the ends of the source and drain regions 88 are not aligned but are shifted. Therefore, the source and drain electrodes 92a to 92c and the source and drain regions The electric field is not concentrated at the end of the gate electrode 51 and the source and drain electrodes 92a to This makes it possible to prevent leakage current between the terminal 92 and the terminal 92c.

[0233] Through the above steps, a thin film transistor 83 can be formed. A thin film transistor can be formed using a photomask.

[0234] Next, as shown in FIG. 18(A), the source and drain electrodes 92a to 92c, The drain region 88, the buffer layer 87, the microcrystalline semiconductor film 90, and the gate insulating film 5 An insulating film 76 is formed on 2c.

[0235] Next, a part of the insulating film 76 is removed using a resist mask formed using a third photomask. Then, a contact hole is formed by etching. A pixel electrode 77 is formed in contact with the source electrode or drain electrode 71c. As for 77, an indium tin oxide film is formed by sputtering, and then indium A resist is applied onto the tin oxide film. Next, the resist is exposed using a fourth photomask. Then, the resist mask is used to form an indium tin oxide film. The oxide film is then etched to form pixel electrodes 77 .

[0236] As a result, the number of masks can be reduced by using a multi-tone mask, and a device that can be used in a display device can be obtained. A daughter board can be formed.

[0237] This embodiment includes embodiment 1, embodiment 2, embodiment 3, embodiment 4, and embodiment This can be freely combined with embodiment 5, embodiment 6, or embodiment 7.

[0238] (Embodiment 9) In this embodiment, a process of forming a storage capacitor using a multi-tone mask and a process of forming a thin film transistor are performed. The process of forming a contact for a pixel electrode is shown in FIG. The same parts as in embodiment 6 are designated by the same reference numerals.

[0239] According to the sixth embodiment, after the process of forming the insulating film 76 is completed, a multi-tone mask is used to A first interlayer insulating film 84a having openings of different depths is formed. The angle of the side of the wiring is larger than that of the gate electrode, as shown in FIG. 19(A). By using a multi-tone mask to change the angle of the wiring side surface and control the wiring width at each location, The aperture ratio of the elemental portion is improved. The cross-sectional view at this stage corresponds to Figure 19(A).

[0240] As shown in FIG. 19A, an insulating film 76 is formed above the source or drain electrode 71c. The first opening exposes the surface, and the first conductive layer 78a and the second conductive layer 78b are laminated. A second opening having a depth shallower than that of the first opening is provided on the capacitance wiring. The first conductive layer 78a and the second conductive layer 78b are respectively connected to the first conductive layer 51a of the gate electrode. The second conductive layer 51b is formed in the same process as the first conductive layer 51a.

[0241] Next, a portion of the insulating film 76 is selectively etched using the first interlayer insulating film 84a as a mask. 3 to expose a part of the source or drain electrode 71c.

[0242] Next, the first interlayer insulating film 84a is etched until the second opening is expanded to expose the surface of the insulating film 76. At the same time, the first opening is also enlarged, but the size of the opening formed in the insulating film 76 is does not change, a step is formed.

[0243] Next, the pixel electrode 77 is formed. The cross-sectional view at this stage corresponds to FIG. The first interlayer insulating film is reduced to a second interlayer insulating film 84b by the above-mentioned process. 5 uses an insulating film 76 and a gate insulating film 52 as a dielectric, and a capacitance wiring and a pair of electrodes. A pixel electrode 77 is used.

[0244] In this way, the storage capacitor can be formed with a small number of steps using a multi-tone mask.

[0245] This embodiment includes embodiment 1, embodiment 2, embodiment 3, embodiment 4, and embodiment It can be freely combined with embodiment 5, embodiment 6, embodiment 7, or embodiment 8. Cut.

[0246] (Embodiment 10) In this embodiment mode, a display device having the thin film transistor described in Embodiment 6 is used. The liquid crystal display device will be described below.

[0247] First, we will explain the VA (Vertical Alignment) type liquid crystal display device. A VA type LCD is a type of display that controls the alignment of liquid crystal molecules in the LCD panel. In VA type LCD devices, the liquid crystal molecules are aligned relative to the panel surface when no voltage is applied. In this embodiment, the pixels are divided into several regions. (sub-pixels), and each sub-pixel is designed to tilt the molecules in a different direction. In the following explanation, we will refer to multi-domain design. A liquid crystal display device that takes this into consideration will be described.

[0248] 21 and 22 show a pixel electrode and a counter electrode, respectively. FIG. 2 is a plan view of the substrate on which the element electrodes are formed, showing a cross-sectional structure corresponding to the cutting line AB shown in the figure. FIG. 20 shows this. FIG. 22 shows a plan view of the substrate on which the counter electrode is formed. The following description will make reference to these figures.

[0249] FIG. 20 shows a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 630. The substrate 600 on which the counter electrode 640 and the like are formed is overlapped with the counter substrate 601. 4, showing the state after liquid crystal is injected.

[0250] In the position where the spacer 642 is to be formed on the opposing substrate 601, a light-shielding film 632 and a first adhesive A color film 634, a second color film 636, a third color film 638, and a counter electrode 640 are formed. This structure allows the heights of the protrusions 644 and spacers 642 for controlling the alignment of the liquid crystal to be different. An alignment film 648 is formed on the pixel electrode 624, and an alignment film 648 is formed on the counter electrode 640. An alignment film 646 is also formed on the first and second electrodes 642 and 644. A liquid crystal layer 650 is formed between them.

[0251] Although the spacers 642 are shown as columnar spacers here, bead spacers may be dispersed. Furthermore, a spacer 642 is formed on the pixel electrode 624 formed on the substrate 600. Good too.

[0252] On the substrate 600, a TFT 628, a pixel electrode 624 connected thereto, and a storage capacitor 63 are provided. 0 is formed. The pixel electrode 624 covers the TFT 628, the wiring, and the storage capacitor 630. A contact hole 62 penetrates an insulating film 620 and a third insulating film 622 that covers the insulating film. 3, it is connected to the wiring 618. Also, using a multi-tone mask, the wiring 618 and the TFT 628 The source electrode or drain electrode of the wiring 618 is selectively etched, and the side angle of the wiring 618 is set to T The side angle of the source electrode or drain electrode of the FT628 is made larger than that of the FT628, which contributes to improving the aperture ratio. The thin film transistor shown in the embodiment mode 6 can be appropriately used for the TFT 628. The storage capacitor 630 can be connected to the gate wiring 60 of the TFT 628 according to the second embodiment. The first capacitance wiring 604, the gate insulating film 606, and the wiring The first capacitor wiring 617 is formed in the same manner as the first capacitor wiring 616 and the second capacitor wiring 617. The side angle of the wiring 604 is set to be larger than the side angle of the wirings 616 and 618 of the TFT 628. This contributes to improving the aperture ratio.

[0253] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0254] FIG. 21 shows the structure on the substrate 600. The pixel electrode 624 is made of the material shown in the sixth embodiment. The pixel electrode 624 is provided with a slit 625. The slit 625 is formed by controlling the alignment of the liquid crystal. This is to control the

[0255] The TFT 629 and the pixel electrode 626 and storage capacitor 631 connected thereto shown in FIG. The TFT 628, the pixel electrode 624, and the storage capacitor 630 can be formed in the same manner. Both the TFT 628 and the TFT 629 are connected to the wiring 616. A pixel is composed of a pixel electrode 624 and a pixel electrode 626. 624 and the pixel electrode 626 are a sub-pixel.

[0256] 22 shows the structure on the opposing substrate side. An opposing electrode 640 is formed on a light-shielding film 632. The counter electrode 640 is preferably formed using the same material as the pixel electrode 624. A protrusion 644 for controlling the alignment of the liquid crystal is formed on the counter electrode 640. A spacer 642 is formed in accordance with the position of 32.

[0257] The equivalent circuit of this pixel structure is shown in Figure 23. TFT628 and TFT629 are both gate The wiring 602 and the wiring 616 are connected. In this case, the first capacitance wiring 604 and the third capacitance By making the potential of the wiring 605 different, the operation of the liquid crystal element 651 and the liquid crystal element 652 can be made different. That is, the potentials of the first capacitance wiring 604 and the third capacitance wiring 605 can be set individually. By controlling it separately, the orientation of the liquid crystal can be precisely controlled to widen the viewing angle.

[0258] When a voltage is applied to the pixel electrode 624 having the slit 625, The slit 625 and the protrusion on the opposing substrate 601 side cause distortion of the electric field (diagonal electric field). By arranging the 644 in an alternating manner, a diagonal electric field is effectively generated, and the liquid crystal By controlling the orientation, the direction in which the liquid crystal is oriented can be made to differ depending on the location. The viewing angle of the LCD panel is expanded by making it multi-domain.

[0259] Although an example of a VA type liquid crystal display device has been described above, the pixel electrode structure shown in FIG. Not done.

[0260] Next, a configuration of a TN type liquid crystal display device will be described.

[0261] Figures 24 and 25 show the pixel structure of a TN type liquid crystal display device. Figure 25 is a plan view. The cross-sectional structure corresponding to the cutting line AB shown in the figure is shown in FIG. The following description will be given with reference to these two figures. Note that in Figs. 24 and 25, the same parts as in Fig. 20 are uses the same sign.

[0262] The pixel electrode 624 is connected to the TFT 628 through a contact hole 623 and a wiring 618. The wiring 616 functioning as a data line is connected to the TFT 628. Any of the TFTs shown in the second embodiment can be applied to 28.

[0263] The pixel electrode 624 is formed using the pixel electrode 77 shown in the second embodiment.

[0264] On the opposing substrate 601, a light-shielding film 632, a second colored film 636, and an opposing electrode 640 are formed. In addition, a flattening film 637 is formed between the second colored film 636 and the counter electrode 640. The liquid crystal layer 650 is disposed between the pixel electrode 624 and the counter electrode 640. has been formed.

[0265] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a liquid crystal element. It is being done.

[0266] In addition, the substrate 600 or the opposing substrate 601 may have a color filter or a disclination. A shielding film (black matrix) for preventing the above may be formed on the substrate 60. A polarizing plate is attached to the surface opposite to the surface on which the thin film transistor of 0 is formed, and a counter substrate is attached to the surface opposite to the surface on which the thin film transistor of 0 is formed. A polarizing plate is attached to the surface of the plate 601 opposite to the surface on which the counter electrode 640 is formed. .

[0267] Through the above steps, a liquid crystal display device can be manufactured. The off-state current is small, and the thin film transistor with excellent electrical characteristics and high reliability is used. Therefore, the liquid crystal display device has high contrast and high visibility. By adjusting the side angle of the wiring for each location, a liquid crystal display device with a high aperture ratio is realized. In addition, by using a multi-tone mask to adjust the side angle of the wiring for each location, This reduces breaks and short circuits above the

[0268] The present invention can also be applied to a liquid crystal display device of the in-plane switching type. This method applies an electric field horizontally to the liquid crystal molecules inside the display to drive the liquid crystal and express gradation. This method can expand the viewing angle to approximately 180 degrees.

[0269] This embodiment includes embodiment 1, embodiment 2, embodiment 3, embodiment 4, and embodiment It may be freely combined with embodiment 5, embodiment 6, embodiment 7, embodiment 8, or embodiment 9. It is possible to combine them.

[0270] (Embodiment 11) A structure of a display panel, which is one embodiment of a liquid crystal display device of the present invention, will be described below.

[0271] In FIG. 26A, only a signal line driver circuit 6013 is formed separately and is formed on a substrate 6011. The pixel portion 6012 and the scan line 6013 are connected to the display panel. The driver circuit 6014 is formed using a thin film transistor using a microcrystalline semiconductor film. A transistor that has a higher mobility than a thin-film transistor using a crystalline semiconductor film. By forming a driving circuit, it is possible to realize a signal line driving circuit, which requires a higher driving frequency than the scanning line driving circuit. The signal line driver circuit 6013 is made of a single crystal semiconductor. A transistor using a conductor, a thin-film transistor using a polycrystalline semiconductor, or a SOI The pixel portion 6012, the signal line driver circuit 6013, and the driving circuit 6014 may be a transistor using the same. The power supply potential and various signals are respectively supplied to the scanning line driving circuit 6014 via the FPC 6015. are supplied.

[0272] In addition, both the signal line driver circuit and the scanning line driver circuit may be formed on the same substrate as the pixel portion. stomach.

[0273] In addition, when a driver circuit is formed separately, the substrate on which the driver circuit is formed is not necessarily the substrate on which the pixel portion is formed. It is not necessary to attach it to a substrate on which a film is formed. For example, it can be attached to an FPC. In FIG. 26B, only a signal line driver circuit 6023 is formed separately, and A liquid crystal display panel connected to the formed pixel portion 6022 and the scanning line driver circuit 6024 The pixel portion 6022 and the scanning line driver circuit 6024 are formed using a microcrystalline semiconductor film. The signal line driver circuit 6023 is formed using a thin film transistor. The pixel portion 6022 is connected to a signal line driver circuit 6023. The scanning line driver circuit 6024 is connected to the power supply potential and various signals via the FPC 6025. and supplied.

[0274] In addition, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed using a microcrystalline semiconductor film. The thin film transistors that were used in the previous step were formed on the same substrate as the pixel section, and the remaining part was formed separately to form the pixel section. In FIG. 26C, an analog signal line driver circuit may be electrically connected to the The switch 6033a is disposed on the same substrate 6031 as the pixel portion 6032 and the scanning line driver circuit 6034. A shift register 6033b of the signal line driver circuit is formed on a different substrate. The pixel portion 6032 and the scanning line driver circuit are shown in FIG. The signal line driver circuit 6034 is formed using a thin film transistor using a microcrystalline semiconductor film. The shift register 6033b of the circuit is connected to the pixel section 6032 via the FPC 6035. A pixel portion 6032, a signal line driver circuit, and a scanning line driver circuit 6034 are provided. The power supply potential, various signals, etc. are supplied via FPC6035.

[0275] As shown in FIG. 26, the liquid crystal display device has a part or the whole of the driver circuit on the same substrate as the pixel portion. A thin film transistor using a microcrystalline semiconductor film can be formed over the plate.

[0276] The method for connecting the separately formed substrate is not particularly limited, and may be a known COG method. The method for connecting the wiring may be a soldering method, a wire bonding method, or a TAB method. The position of the wiring is not limited to the position shown in FIG. 26, so long as electrical connection is possible. Alternatively, a controller, a CPU, a memory, etc. may be formed separately and connected.

[0277] Note that the signal line driver circuit used in this embodiment mode includes only a shift register and an analog switch. In addition to the shift register and analog switch, the It may have other circuits such as a bell shifter, a source follower, etc. The analog switch does not necessarily have to be provided. For example, a decoder can be used instead of a shift register. Alternatively, a separate circuit such as a rectifier circuit that can select a signal line may be used, or an analog switch may be used instead. Instead, a latch or the like may be used.

[0278] This embodiment includes embodiment 1, embodiment 2, embodiment 3, embodiment 4, and embodiment Embodiment 5, embodiment 6, embodiment 7, embodiment 8, embodiment 9 or embodiment 10 can be freely combined.

[0279] (Embodiment 12) FIG. 27 shows the appearance and cross section of a liquid crystal display panel which corresponds to one embodiment of the display device of the present invention. FIG. 27A shows a microcrystalline semiconductor film formed on a first substrate 4001. A thin film transistor 4010 and a liquid crystal element 4013 are disposed between a second substrate 4006 and FIG. 27(B) is a top view of the panel sealed with the sealant 4005. A) corresponds to a cross-sectional view taken along line A-A'.

[0280] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. A sealant 4005 is provided so as to cover the pixel portion 4002. A second substrate 4006 is provided on the circuit 4004. The scanning line driver circuit 4004 is a circuit board including a first substrate 4001, a sealant 4005, and a second substrate 400. The liquid crystal 4008 is sealed by the sealant 6 on the first substrate 4001. In a region different from the region surrounded by the material 4005, a polycrystalline silicon layer is formed on a separately prepared substrate. A signal line driver circuit 4003 formed of a semiconductor film is mounted. A signal line driver circuit having a thin film transistor using a polycrystalline semiconductor film is formed on the first substrate 40. 01 will be described. In FIG. 27, the signal line driver circuit 4 is formed on the substrate 1 and then bonded to the substrate 1. 40 shows an example of a thin film transistor 4009 formed of a polycrystalline semiconductor film, which is included in the semiconductor device 003 .

[0281] A pixel portion 4002 and a scanning line driver circuit 4004 are provided on a first substrate 4001. In FIG. 27B, the thin film transistor included in the pixel portion 4002 is The thin film transistor 4010 is a microcrystalline semiconductor film. This corresponds to a thin film transistor using

[0282] The pixel electrode 4030 of the liquid crystal element 4013 is a thin The film transistor 4010 is electrically connected to the liquid crystal element 4041. The counter electrode 4031 of the pixel 4013 is formed on the second substrate 4006. The overlapping portion of the liquid crystal element 4013 corresponds to the liquid crystal element 4013. Correct.

[0283] The first substrate 4001 and the second substrate 4006 are made of glass, metal (typically Stainless steel, ceramics, and plastics can be used. is a FRP (Fiberglass-Reinforced Plastics) plate, P VF (polyvinyl fluoride) film, polyester film, or acrylic resin You can also use aluminum foil with a PVF film or polyester film. It is also possible to use a sheet having a structure in which the sheet is sandwiched between two thermoplastic films.

[0284] Also, 4035 is a spherical spacer, which is disposed between the pixel electrode 4030 and the counter electrode 4031. The insulating film is selectively etched to control the distance (cell gap). Alternatively, a spacer obtained by gating may be used.

[0285] A signal line driver circuit 4003 and a scanning line driver circuit 4004 or a pixel section Various signals and potentials are applied to 4002 via wiring 4014 and 4015. Powered by FPC4018.

[0286] In this embodiment, the connection terminal 4016 is connected to the pixel electrode 4030 of the liquid crystal element 4013. The lead wirings 4014 and 4015 are formed from the same conductive film as the wiring 40 It is formed of the same conductive film as 41. As shown in the first embodiment, a multi-tone mask is used. As a result, the side angles of the lead wires 4014 and 4015 are larger than that of the wire 4041. It is effective to process both sides vertically to prevent short circuits between adjacent wiring. It is effective.

[0287] The connection terminal 4016 is connected to a terminal of the FPC 4018 via an anisotropic conductive film 4019. are electrically connected.

[0288] Although not shown, the liquid crystal display device shown in this embodiment has an alignment film and a polarizing plate. It may further comprise a color filter and a shielding film.

[0289] In FIG. 27, a signal line driver circuit 4003 is formed separately and mounted on a first substrate 4001. However, this embodiment is not limited to this configuration. Alternatively, only a part of the signal line driver circuit or a part of the scanning line driver circuit may be formed and mounted. It may be formed separately and mounted.

[0290] This embodiment can be implemented in combination with the configurations described in other embodiment modes. be.

[0291] (Embodiment 13) The display device obtained by the present invention is used to manufacture an active matrix display device module. That is, the present invention can be applied to all electronic devices that incorporate such a display unit. can.

[0292] Such electronic devices include cameras such as video cameras and digital cameras, head-mounted displays (goggle-type displays), car navigation systems, projectors, car Stereos, personal computers, personal digital assistants (mobile computers, mobile phones, etc.) An example of such a device is shown in Figure 28.

[0293] FIG. 28(A) is a television device. The display module is as shown in FIG. Then, the TV set can be completed by installing the FPC in the housing. The display panel mounted on the display unit is also called a display module. 03 is formed, and other accessories include speaker unit 2009 and operation switches. In this manner, the television device is completed.

[0294] As shown in FIG. 28A, a display panel 2002 using a display element is mounted on a housing 2001. The receiver 2005 can receive general television broadcasts, and the modem 2004 can receive the By connecting to a wired or wireless communication network via It is also possible to communicate information one-to-one (between a sender and a receiver, or between receivers) or two-way (between a sender and a receiver, or between receivers themselves). The television set can be operated by a switch built into the housing or by a separate remote control. This can be done by the remote control device 2006, which also displays the information to be output. A display unit 2007 may also be provided.

[0295] In addition to the main screen 2003, the television device also has a sub-screen 2008 for second display. The display may be formed of a panel and may be provided with a configuration for displaying channels, volume, etc. In this embodiment, the main screen 2003 is formed of a liquid crystal display panel having a good viewing angle, and the sub-screen 2008 is formed of a liquid crystal display panel having a good viewing angle. The display may be formed of a light-emitting display panel capable of displaying with low power consumption. In order to achieve this, the main screen 2003 is formed of a light-emitting display panel, and the sub-screen is formed of a light-emitting display panel. and the sub screen may be configured to be able to blink.

[0296] Of course, the present invention is not limited to television devices, and may be used with monitors of personal computers. In addition, it is also used in large-area displays such as information display boards at train stations and airports, and advertising display boards on the street. It can also be used for various purposes as a display medium.

[0297] FIG. 28B shows an example of a mobile phone 2301. This mobile phone 2301 has a display The display unit 2302 includes an operation unit 2303. By applying the display device described in the above embodiment, mass productivity can be improved.

[0298] The portable computer shown in FIG. 28C includes a main body 2401, a display unit 2402, etc. By applying the display device described in the above embodiment to the display portion 2402, , mass productivity can be improved. [Explanation of symbols]

[0299] 101: Substrate 102: Gate insulating film 103: First conductive layer 106: source region and drain region 107a: First wiring layer 107b: second wiring layer 108: source region and drain region 109: source electrode or drain electrode 110: source electrode or drain electrode 111: Insulating film 112: pixel electrode 113: Connection electrode 116: first connection electrode 117: second connection electrode 118: Pixel electrode 119: third connection electrode

Claims

1. A display device including a transistor and a liquid crystal element electrically connected to one of a source and a drain of the transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating layer having a region disposed on the first conductive layer; a semiconductor layer having a region disposed on the first insulating layer and having a channel formation region of the transistor; a first layer having a region disposed on the semiconductor layer and functioning as one of a source and a drain of the transistor; a second layer having a region disposed on the semiconductor layer and functioning as the other of the source and drain of the transistor; a second conductive layer having a region in contact with an upper surface of the first layer and electrically connected to the semiconductor layer via the first layer; a third conductive layer having a region in contact with an upper surface of the second layer and electrically connected to the semiconductor layer via the second layer; a pixel electrode of the liquid crystal element, the pixel electrode having a region disposed on the second conductive layer and electrically connected to the second conductive layer; the second conductive layer has a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer; a side surface of the second conductive layer in the first region has a smaller taper angle than a side surface of the second conductive layer in the second region; Display device.

2. A display device including a transistor and a liquid crystal element electrically connected to one of a source and a drain of the transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating layer having a region disposed on the first conductive layer; a semiconductor layer having a region disposed on the first insulating layer and having a channel formation region of the transistor; a first layer having a region in contact with a top surface of the semiconductor layer and functioning as one of a source and a drain of the transistor; a second layer having a region in contact with an upper surface of the semiconductor layer and functioning as the other of the source and the drain of the transistor; a second conductive layer having a region in contact with an upper surface of the first layer and electrically connected to the semiconductor layer via the first layer; a third conductive layer having a region in contact with an upper surface of the second layer and electrically connected to the semiconductor layer via the second layer; a pixel electrode of the liquid crystal element, the pixel electrode having a region disposed on the second conductive layer and electrically connected to the second conductive layer; the second conductive layer has a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer; a side surface of the second conductive layer in the first region has a smaller taper angle than a side surface of the second conductive layer in the second region; Display device.

3. A display device including a transistor and a liquid crystal element electrically connected to one of a source and a drain of the transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating layer having a region disposed on the first conductive layer; a semiconductor layer having a region disposed on the first insulating layer and having a channel formation region of the transistor; a first layer having a region disposed on the semiconductor layer and functioning as one of a source and a drain of the transistor; a second layer having a region disposed on the semiconductor layer and functioning as the other of the source and drain of the transistor; a second conductive layer having a region in contact with an upper surface of the first layer and electrically connected to the semiconductor layer via the first layer; a third conductive layer having a region in contact with an upper surface of the second layer and electrically connected to the semiconductor layer via the second layer; a second insulating layer having a region disposed on the second conductive layer and having a region disposed on the third conductive layer; a pixel electrode of the liquid crystal element, the pixel electrode having a region disposed on the second insulating layer and electrically connected to the second conductive layer via a contact hole disposed in the second insulating layer; the second conductive layer has a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer; the contact hole has a region overlapping with the second region, a side surface of the second conductive layer in the first region has a smaller taper angle than a side surface of the second conductive layer in the second region; Display device.

4. A display device including a transistor and a liquid crystal element electrically connected to one of a source and a drain of the transistor, a first conductive layer having a function as a gate electrode of the transistor; a first insulating layer having a region disposed on the first conductive layer; a semiconductor layer having a region disposed on the first insulating layer and having a channel formation region of the transistor; a first layer having a region in contact with a top surface of the semiconductor layer and functioning as one of a source and a drain of the transistor; a second layer having a region in contact with an upper surface of the semiconductor layer and functioning as the other of the source and the drain of the transistor; a second conductive layer having a region in contact with an upper surface of the first layer and electrically connected to the semiconductor layer via the first layer; a third conductive layer having a region in contact with an upper surface of the second layer and electrically connected to the semiconductor layer via the second layer; a second insulating layer having a region disposed on the second conductive layer and having a region disposed on the third conductive layer; a pixel electrode of the liquid crystal element, the pixel electrode having a region disposed on the second insulating layer and electrically connected to the second conductive layer via a contact hole disposed in the second insulating layer; the second conductive layer has a first region overlapping with the first conductive layer and a second region not overlapping with the first conductive layer; the contact hole has a region overlapping with the second region, a side surface of the second conductive layer in the first region has a smaller taper angle than a side surface of the second conductive layer in the second region; Display device.

Images