Semiconductor device

Abstract

To provide a semiconductor device having high integration.SOLUTION: A semiconductor device includes a substrate, a prismatic insulator, and a memory cell string having a plurality of transistors connected in series. The prismatic insulator is arranged on the substrate, and the memory cell string is arranged on a lateral face of the prismatic insulator. Each of the plurality of transistors has a gate insulator and a gate electrode. The gate insulator has a first insulator, a second insulator, and a charge storage layer. The charge storage layer is arranged between the first insulator and the second insulator.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to, for example, a semiconductor, a transistor, and a semiconductor device. For example, the present invention relates to a method for manufacturing a semiconductor, a transistor, and a semiconductor device. For example, a semiconductor, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, a processor, , electronic devices. Or, semiconductors, display devices, liquid crystal display devices, light-emitting devices, storage devices, The present invention relates to a method for manufacturing an electronic device, a semiconductor device, a display device, a liquid crystal display device, and a light-emitting device. The present invention relates to a memory device and a method for driving an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. It is about the nature of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. Display devices, light-emitting devices, lighting devices, electro-optical devices, semiconductor circuits, and electronic devices may include a semiconductor device. [Background technology]

[0004] Semiconductor memory devices are attracting attention as large-capacity storage devices for computers and other devices. In particular, the number of wiring and electrodes per memory cell in NAND flash memory is It is known that the number of bits is small and it is easy to increase the degree of integration. In addition, technology such as multi-value processing has been realized, Memory capacity has been increasing year by year. In recent years, high integration has been achieved by arranging memory cells in a planar manner. The technology is reaching its limits and is being replaced by technology that arranges memory cells three-dimensionally (particularly See patent document 1. ). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2011-96340 A Summary of the Invention [Problem to be solved by the invention]

[0006] It is an object of the present invention to provide a semiconductor device with a high degree of integration. Another object of the present invention is to provide a semiconductor device having a semiconductor memory device with a large memory capacity. It is an object of the present invention to provide a semiconductor device having a memory cell with a long retention period. An object of the present invention is to provide a semiconductor device.

[0007] Another object of the present invention is to provide a module including the semiconductor device. It is an object of the present invention to provide a semiconductor device or an electronic device having the module. Another object of the present invention is to provide a novel semiconductor device. One of the objectives is to provide a novel electronic device. do.

[0008] Another object of the present invention is to provide a transistor having normally-off electrical characteristics. Another object of the present invention is to provide a transistor having a small leakage current when off. Alternatively, the object is to provide a transistor with a small subthreshold swing value. Another object of the present invention is to provide a transistor having a small short channel effect. Another object of the present invention is to provide a transistor with excellent electrical characteristics. Another object of the present invention is to provide a highly reliable transistor. An object of the present invention is to provide a transistor having

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0010] (1) One aspect of the present invention is a semiconductor device including a substrate, a prismatic insulator, and a plurality of transistors connected in series. a memory cell string having a prismatic insulator disposed on the substrate; The cell string is a semiconductor device disposed on the side of a prismatic insulator.

[0011] (2) One aspect of the present invention is a semiconductor device comprising a substrate, a prismatic insulator, and a plurality of transistors connected in series. a memory cell string having a transistor; and a prismatic insulator disposed on the substrate. The memory cell strings are arranged on the side surfaces of a rectangular prism-shaped insulator. It is a semiconductor device.

[0012] (3) In one aspect of the present invention, in the configuration (1) or (2), each of the plurality of transistors is a gate a gate insulator and a gate electrode, the gate insulator being made of a first insulator, a second insulator and a and a charge storage layer, the charge storage layer being disposed between a first insulator and a second insulator. It is a semiconductor device.

[0013] (4) According to one embodiment of the present invention, in any one of (1) to (3), the plurality of transistors are The semiconductor device has a nitride semiconductor.

[0014] (5) In one embodiment of the present invention, in the above-described (4), the oxide semiconductor is The semiconductor device comprises a metal oxide (Zn, gallium, yttrium or tin) and zinc.

[0015] (6) According to one aspect of the present invention, in any one of (1) to (5), a second a first transistor and a second transistor, is electrically connected to the first terminal of the memory cell string and is connected to the drain of the second transistor. The IN terminal is a semiconductor device that is electrically connected to the second terminal of the memory cell string. .

[0016] (7) One aspect of the present invention is the semiconductor device according to item (6), wherein the first transistor and the second transistor are The semiconductor device has single crystal silicon. Effect of the Invention

[0017] A semiconductor device having a high degree of integration can be provided. Alternatively, a semiconductor device having a large memory capacity can be provided. Alternatively, a semiconductor device having a memory cell with a long retention period can be provided. can be done.

[0018] Alternatively, a module having the semiconductor device can be provided. Alternatively, a novel semiconductor device or electronic device having the module can be provided. A new module may be provided. Alternatively, a novel electronic device can be provided.

[0019] Alternatively, a transistor having normally-off electrical characteristics can be provided. It is possible to provide a transistor with a small leakage current when it is not conducting. It is possible to provide a transistor with a small threshold swing value. It is possible to provide a transistor with a small channel effect. To provide a highly reliable transistor. Alternatively, a transistor having high frequency characteristics can be provided.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description, This is self-evident from the description in the drawings, claims, etc. It is possible to extract other effects from any of the descriptions. [Brief description of the drawings]

[0021] [Figure 1] 1A and 1B are a cross-sectional view and a circuit diagram of a semiconductor device according to one embodiment of the present invention. [Diagram 2]1A and 1B are a schematic diagram and a cross-sectional view illustrating the operation of a semiconductor device according to one embodiment of the present invention. [Diagram 3] FIG. 1 is a circuit diagram illustrating the operation of a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a circuit diagram illustrating the operation of a semiconductor device according to one embodiment of the present invention. [Diagram 5] FIG. 1 is a circuit diagram illustrating the operation of a semiconductor device according to one embodiment of the present invention. [Figure 6] FIG. 1 is a circuit diagram illustrating the operation of a semiconductor device according to one embodiment of the present invention. [Figure 7] FIG. 1 is a circuit diagram illustrating the operation of a semiconductor device according to one embodiment of the present invention. [Figure 8] FIG. 1 is a circuit diagram illustrating the operation of a semiconductor device according to one embodiment of the present invention. [Figure 9] FIG. 1 is a circuit diagram illustrating the operation of a semiconductor device according to one embodiment of the present invention. [Figure 10] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 13 is a band diagram in the vicinity of a channel formation region of a transistor according to one embodiment of the present invention. [Figure 13] A ternary diagram illustrating the composition of In-M-Zn oxide. [Figure 14] 1A and 1B are diagrams illustrating structural analyses of a CAAC-OS and a single crystal oxide semiconductor by XRD, and diagrams showing selected-area electron diffraction patterns of a CAAC-OS. [Figure 15] Cross-sectional TEM image and planar TEM image of CAAC-OS, and their image analysis images. [Figure 16] Electron diffraction pattern of nc-OS and cross-sectional TEM image of nc-OS. [Figure 17] Cross-sectional TEM image of a-like OS. [Figure 18] FIG. 1 shows the change in the crystal part of an In-Ga-Zn oxide due to electron irradiation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] The present invention will be described in detail with reference to the drawings. The present invention is not limited to the above, and various modifications in form and detail can be easily made by those skilled in the art. It is understood that the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same reference numerals are used in different The hatch pattern is used in common among drawings. In some cases, no particular symbol is attached.

[0023] In the figures, the size, thickness of the film (layer), or area is exaggerated for clarity. There may be cases where

[0024] In this specification, the terms "film" and "layer" are interchangeable. It is possible.

[0025] Also, a voltage is a voltage between a certain potential and a reference potential (such as ground potential (GND) or source potential). Therefore, it is possible to say "voltage" as "potential". In general, potential (voltage) is relative, and the magnitude is measured relative to a reference potential. Therefore, even if it is described as "ground potential", The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." With respect to the potential, a positive potential and a negative potential are defined for .

[0026] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "the first" should not be changed to "the second" or "the third" In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers. and the ordinal numbers used to identify an aspect of the invention may not match.

[0027] The impurities in a semiconductor are, for example, those other than the main components that make up the semiconductor. For example, Elements with a concentration of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of State) in the body and carrier mobility In some cases, the semiconductor may become an oxide semiconductor, or the crystallinity may decrease. In the case of a semiconductor, impurities that change the properties of the semiconductor include, for example, Group 1 elements, Group 2 elements, Elements, Group 14 elements, Group 15 elements, transition metals other than the main component, etc., in particular, for example, Hydrogen (also found in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen In the case of oxide semiconductors, for example, oxygen vacancies are formed due to the inclusion of impurities such as hydrogen. Also, if the semiconductor is silicon, impurities that change the properties of the semiconductor may occur. Examples of the elements include oxygen, elements of Group 1 except hydrogen, elements of Group 2, elements of Group 13, elements of Group 15, Group elements, etc.

[0028] In this specification, when it is stated that A has a shape protruding from B, it is to be understood that the shape is not limited to a top view. or in a cross-sectional view, at least one end of A is outside at least one end of B. Therefore, it may be described as having a shape in which A protrudes more than B. For example, in the top view, one end of A is outside one end of B. It can be read as having.

[0029] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Line" refers to the state in which two straight lines are arranged at an angle between -30° and 30°. "Perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the angle may be between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0030] In addition, in this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. .

[0031] <Semiconductor device> A semiconductor device according to one embodiment of the present invention will be described below.

[0032] In the following, we will assume that the transistor is an n-channel type. However, the transistor may be a p-channel type. In order to apply this to transistors, terms or symbols may be interpreted as appropriate.

[0033] <Structure of Semiconductor Device> A structure of a semiconductor device according to one embodiment of the present invention will be exemplified below.

[0034] FIG. 1A is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 2 is a circuit diagram corresponding to the semiconductor device shown in FIG.

[0035] The semiconductor device shown in FIG. 1A includes a substrate 100, an insulator 120, an insulator 122, and an insulating film. The body 124, the insulator 126, the insulator 128, the insulator 130, the conductor 140, and the conductor Conductor 142, conductor 144, conductor 146, conductor 148, conductor 132, and conductor A conductor 134, a conductor 136, a conductor 138, a transistor Tr_S1, and a transistor a transistor Tr_S2, and a transistor Tr_1 to a transistor Tr_2n (n is an integer of 2 or more). ) and.

[0036] The transistor Tr_S1 and the transistor Tr_S2 are provided on a substrate 100. Specifically, the transistor Tr_S1 is formed by a pair of impurity regions 166 provided in the substrate 100. A channel forming region sandwiched between the impurity regions 166 and a region overlapping the channel forming region are a conductor 154 having a channel forming region and an insulator 162 sandwiched between the conductor 154 and the channel forming region; Here, the conductor 154 functions as a gate electrode, and the insulator 162 functions as a gate electrode. The gate insulator functions as a gate electrode of the transistor Tr_S1. The electric conductor 154 is electrically connected to the wiring SEL_1. The conductor 154 functioning as a gate electrode is electrically connected to the wiring SEL_2. The transistor Tr_S2 is described as having the same structure as the transistor Tr_S1. The transistors Tr_S1 and Tr_S2 may have different structures. The transistor Tr_S2 is isolated by an insulator 120. The isolation method is as follows: STI (Shallow Trench Isolation) method and LOCOS (Loc The Tran Oxidation of Silicon method is one example. The structure of the transistor Tr_S1 and the transistor Tr_S2 is the same as that shown in FIG. The structure is not limited to SOI (Silicon on Insulator) substrate. The transistor may be a transistor provided in the MOSFET or a FIN type transistor.

[0037] An insulator 122 is disposed on the transistor Tr_S1 and the transistor Tr_S2. On the insulator 122, an insulator 130, a conductor 144, a conductor 146, and a conductor 1 The insulator 130 is prism-shaped or wall-shaped, and has a transistor on its side. Transistors Tr_1 to Tr_2n (n is an integer of 2 or more) are arranged. The channel length direction of each of the transistors Tr_1 to Tr_n is The direction is parallel to the vertical direction in which the transistors Tr_n+1 to Tr_2n are arranged. The length direction of each channel is parallel to the vertical direction to the top surface of the substrate. The insulator 30 does not have to be prismatic or wall-shaped, and may be, for example, cylindrical. The transistors Tr_1 to Tr_n are arranged on one side of the transistor 30, and The transistors Tr_n+1 to Tr_2n are arranged in the The density of semiconductor devices increases as n increases. For example, n can be 2, 4, 8, 16, 32, 64, 128, etc. The number can be set as, for example,

[0038] The conductor 132 is connected to the transistors Tr_1 to T The conductor 132 has an area facing the transistors Tr_1 to r_2n. It has a function as a back gate electrode (also called a second gate electrode) of the transistor Tr_2n, It is electrically connected to the wiring BGL.

[0039] For example, the transistor Tr_1 includes an insulator 106a, a semiconductor 106b, and an insulator 106. c, the conductor 116a, the conductor 116b, the insulator 112a, and the charge storage layer 112b. , insulator 112c, and conductor 104. Insulator 106a is adjacent to insulator 130. The semiconductor 106b is disposed along the side surface of the insulator 130 via the insulator 106a. The insulator 106c is disposed along the semiconductor 106b and the insulator 106a. The insulator 112a, the conductor 116a, and the conductor 116b are disposed along the side of the insulator 130. 116b is connected to the insulator 13 via the insulator 106c, the semiconductor 106b, and the insulator 106a. The insulator 112a has a region facing the conductor 116a and the conductor 116b. The charge storage layer 112b is disposed between the insulator 112a, the insulator 106c, and the semiconductor 1 106a and 106b, and has an area facing the insulator 130 through the insulator 106a. c is a charge storage layer 112b, an insulator 112a, an insulator 106c, a semiconductor 106b, and an insulator The conductor 104 has an area facing the insulator 130 through the edge 106a. 2c, the charge storage layer 112b, the insulator 112a, the insulator 106c, the semiconductor 106b and the insulator It has an area facing the insulator 130 via the edge 106a.

[0040] Therefore, in the transistor Tr_1, the semiconductor 106b functions as a channel formation region. The conductor 104 functions as a gate electrode, the insulator 112a, the charge storage layer The conductor 112b and the insulator 112c function as a gate insulator, and the conductor 116a is a solenoid. The conductor 116b functions as a source electrode and the conductor 116c functions as a drain electrode. In addition, the insulator 106a and the insulator 106c have a defect level density at the interface with the semiconductor 106b. The insulator 106a, the semiconductor 106b, and the insulator 106c have a function of reducing the electric field. The combination of materials that can be used will be described later. The conductor 104, which functions as a conductor, is electrically connected to the wiring WL_1. The transistor Tr_1 has a function as a word line. For example, some structures such as the insulator 106a and the insulator 106c may be used. The component may not have any components.

[0041] The transistor Tr_1 has a charge storage layer 112b between the conductor 104 and the semiconductor 106b. Therefore, the transistor Tr_1 detects the polarity and The threshold voltage of the transistor Tr_1 corresponds to the amount of charge stored in the charge storage layer 112b. Since the threshold voltage can be controlled by this, a memory cell that stores data according to the threshold voltage can be formed. (Also referred to as a memory element).

[0042] As shown on the left side of FIG. 2A, for example, no electrons are stored in the charge storage layer 112b. In this state, the threshold voltage of the transistor Tr_1 is a negative value. As shown in FIG. 1, when electrons are accumulated in the charge accumulation layer 112b, the electric field generated by the electrons is struck. In order to erase the charge, the threshold voltage changes and becomes a positive value, as shown on the right side of Figure 2(A). That is, in the transistor Tr_1, electrons are not stored in the charge storage layer 112b. In the state where electrons are stored, the data is "1" because the data is conductive, and in the state where electrons are stored, the data is "da" because the data is not conductive. ta”0”. Here, we have explained the case where the memory cell has two values, but it can also have three or more values ​​( For example, it may be a multi-value memory cell having four values, eight values, sixteen values, and 32 values. The injection of electrons into the charge storage layer 112b will be described later.

[0043] The transistors Tr_2 to Tr_2n have the same configuration as the transistor Tr_1. However, the gates of the transistors Tr_2 to Tr_2n are The electrodes are electrically connected to the wirings WL_2 to WL_2n, respectively. Each of the wirings L_2 to WL_2n functions as a word line.

[0044] In this manner, the transistors Tr_1 to Tr_2n are each a memory cell. The transistors Tr_1 to Tr_2n are connected in series. Because they are connected together, they can be collectively called a memory cell string. The memory cell strings can be arranged in a matrix on the substrate 100, for example. Each memory cell string can be electrically connected to a selection transistor. Specifically, a plurality of straight lines extending in a first direction and a plurality of lines extending in a second direction on the substrate 100 are The memory cell strings may be arranged on the points where the multiple straight lines in the first direction intersect with each other. The angle between the first direction and the second direction may be typically 45° or 90°. For example, 10° to 90°, 30° to 90°, 45° to 90°, or 60° or more The range is 90° or less, and the density increases depending on the shape of the memory cell string. Here, for example, if the wiring SL and the wiring BL are arranged along the first direction, For example, the wiring SL and the wiring BL are provided between the memory cell strings formed along the first direction. However, the arrangement of memory cell strings is limited to a matrix. The wiring SL functions as a source line. It functions as a wire.

[0045] A group of multiple memory cell strings is called a block. For example, there are a × b pieces (a is a natural number) in the first direction and b pieces (b is a natural number) in the second direction. However, in each block, the memory cell strings are The number of blocks may be different. Also, the method of grouping blocks may be determined arbitrarily. In the block, for example, the wiring BGL and the conductor 132 are electrically connected to each other. Between the blocks, the wiring BGL and the conductor 132 may be electrically separated. In the block, for example, wirings WL_1 to WL_2n are arranged along the second direction. Then, the wirings WL_1 to WL_3 are arranged between the memory cell strings formed in the second direction. The wiring WL_1 to the wiring WL_2n can be shared for each block. The wiring may be divided into two or may be shared among blocks arranged along the second direction. A group of memory cells sharing the wirings WL_1 to WL_2n is called a page. The lines BL and the wiring SL can be shared between blocks arranged along the first direction. Cut.

[0046] The transistor Tr_S1 has a source terminal electrically connected to the line SL and a drain terminal The transistor Tr_S is electrically connected to the first terminal of the memory cell string. 2, the drain terminal is electrically connected to the wiring BL, and the source terminal is In this manner, the memory cell string is electrically connected to the second terminal of the Since the transistors Tr_S1 and Tr _S2 can be called the select transistor.

[0047] The data write and read operations for the semiconductor device shown in FIG. He explains.

[0048] <Reset operation> When writing data to each memory cell, the data is erased (data It is recommended to write "1" in the data erase operation. The reset operation is performed for each block. For example, select the block you want to erase. 3A, the wiring BGL electrically connected to the conductor 132 is applied with an erase potential V E (for example, 15 V) is applied to the wirings WL_1 to WL_2n, and a low potential (transistor A potential (e.g., 0V) is applied to the transistors Tr_1 to Tr_2n such that the transistors Tr_1 to Tr_2n are non-conductive. This can be done by making the transistors Tr_S1 and Tr_S2 conductive. When the conductor 132 is not provided, the wiring SL and the wiring BL are applied with the erase potential V E Mark The reset operation can also be performed by applying a reset voltage to the transistor T The electrons stored in the charge storage layers 112b of the transistors r_1 to Tr_2n are It can be pulled out.

[0049] On the other hand, for the blocks in which data is not to be erased, the electrical connection between the conductor 132 and the wiring BGL is The connection is broken and the conductor 132 is applied with the erase potential V E Alternatively, the following can be done: As shown in FIG. 3(B), the wirings WL_1 to WL_2 electrically connect to the blocks from which data is not erased. A potential that turns on the transistors Tr_1 to Tr_2n is applied to the wiring WL_2n. , for example, the erase potential V E That is, the charge storage layer 112b is charged with the electrons. It is sufficient to not apply a potential difference that would cause this.

[0050] Note that the data in memory cells that are not rewritten is stored before the block reset operation. It is preferable to store the information in a separate area.

[0051] <Write operation> Next, the operation of writing data to each memory cell will be explained with reference to Figs. 4, 5 and 6. Reveal.

[0052] The data write operation can be performed for each page as described above. A write potential (for example, 15 V) is applied to the word line of the page to be written, and A positive potential (a potential at which the transistor is conductive, for example, 3 V) is applied to the word line of the As shown in FIG. 4, a write potential is first applied to the wiring WL_1, and then a write potential is applied to the wirings WL_2 through WL_3. A positive potential is applied to the line WL_2n. Then, the transistor T r_S1 is made non-conductive, and the transistor Tr_S2 electrically connected to the wiring BL is made conductive. By doing so, the potential of the wiring BL is applied to the memory cell of the page to be written. Therefore, data according to the potential of the wiring BL is written to the memory cell. Specifically, when the potential of the wiring BL is a low potential (for example, 0 V), When the potential difference between the write potential and the potential stored in the charge storage layer 112b increases, electrons are injected into the charge storage layer 112b. When the potential of the wiring BL is a positive potential, the write signal applied to the wiring WL_1 is The potential difference between the positive and negative potentials is reduced, so that electrons are not injected into the charge storage layer 112b. That is, when a low potential is applied to the wiring BL, data “0” is written to the memory cell. In rare cases, when a positive potential is applied, the memory cell remains at data "1."

[0053] Here, by applying a different potential to the wiring BL for each memory cell string, The data can be written as shown in FIG. 6, the same is done for the wirings WL_2 to WL_2n. Alternatively, data can be written to the entire semiconductor device.

[0054] It is also possible to write data other than data “0” and data “1” to memory cells. For example, the charge accumulation layer 112 can be changed by changing the potential of the wiring BL or the time for applying the potential. The amount of electrons injected into b can be controlled.

[0055] <Read operation> Next, the read operation of the data written in each memory cell will be described with reference to FIGS. This will be explained using the following.

[0056] Data read operations can also be performed page by page. First, the page to be read A low potential (for example, 0V) is applied to the word lines of the pages that are not to be read. A positive potential (a potential at which the transistor is conductive, for example, 3 V) is applied. Here, as shown in FIG. In this manner, a low potential is first applied to the wiring WL_1, and a positive potential is applied to the wirings WL_2 to WL_2n. Then, the transistor Tr_S1 and the wiring SL are electrically connected to each other. The transistor Tr_S2 electrically connected to the line BL is turned on. A read potential (for example, 1 V) is applied, and a low potential (for example, 0 V) ​​is applied to the line SL. At this time, if the memory cell has data “1”, current flows through the memory cell string, and d If ata is “0”, no current flows through the memory cell string. The data in the memory cell is read by detecting the current value or the potential drop of the wiring BL. It can be put out.

[0057] Here, the data of each memory cell string is read out to the wiring BL, so that the data is read out in units of pages. The same data can be read out as shown in Figures 8 and 9. By performing the same process on the wirings WL_2 to WL_2n, the block or semiconductor It is possible to read data from the entire device.

[0058] As described above, the semiconductor device according to one embodiment of the present invention has memory cells arranged three-dimensionally. This allows for a high degree of integration. For example, storage capacity of 1 Tbyte or more, 3 Tbyte or more, or 10 Tbyte or more In addition, since data can be stored for a long period of time, it is a non-volatile or The memory device may also be called a semiconductor device having a substantially nonvolatile memory element.

[0059] A semiconductor device according to one embodiment of the present invention is rewritable, has a large storage capacity, and stores data. Since it is possible to store data for a long period of time, it is suitable for storage devices such as computers. For example, the main memory (or memory and Also called "secondary storage" and "external storage devices" that store data outside of a computer. It can be used for external storage devices such as memory cards. and SSD (Solid State Drive).

[0060] <Modifications of the semiconductor device> The semiconductor device according to one embodiment of the present invention is not limited to the structure shown in FIG. For example, as shown in FIG. 10, the insulator 106c is made of the semiconductor 106b and the insulator 106a. The insulator 112a may be disposed along the insulator 130 via the insulator 112b. 106c, the semiconductor 106b and the insulator 106a are disposed along the insulator 130. The charge storage layer 112b may be formed by combining the insulator 112a, the insulator 106c, and the semiconductor The insulating member 106b and the insulating member 106a may be disposed in a shape along the insulator 130. In addition, the conductor 116a and the conductor 116b shown in FIG. 1A do not necessarily have to be provided.

[0061] Alternatively, as shown in FIG. 11, the transistors Tr_S1 and Tr_S2 It may be a FIN type transistor.

[0062] <Components of Semiconductor Device> The components of the semiconductor device will be described below.

[0063] Insulator 120, insulator 122, insulator 124, insulator 126, insulator 128 and insulator Examples of 130 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, and aluminum. Umium, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zinc Insulators containing lanthanum, neodymium, hafnium or tantalum are used in a single layer or in For example, aluminum oxide, magnesium oxide, silicon oxide, etc. , silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide The silicon oxide nitride film may be made of silicon oxide or tantalum oxide. A silicon nitride oxide film is a film that contains more oxygen than nitrogen. The composition of the silicon nitride oxide film is as follows: This refers to a film that contains more nitrogen than oxygen.

[0064] In addition, the insulators 120, 122, 124, 126, 128, and The insulator 130 may have a function of isolating adjacent elements, wiring, etc. It is preferable to use an insulator with a low dielectric constant. For example, the dielectric constant is 5 or less, preferably 4 or less. More preferably, an insulator having a molecular weight of 3 or less is used. Specifically, an insulator having silicon and oxygen is used. It is preferable to use an insulator having a fluorine content or an insulator having a fluorine content. 120, insulator 122, insulator 124, insulator 126, insulator 128 and insulator 130 One or more of the above may be a space.

[0065] Insulator 120, insulator 122, insulator 124, insulator 126, insulator 128 and insulator 130 has a function of blocking impurities such as hydrogen and oxygen (permeation) It is preferable that the transistors Tr_1 to Tr_2 have an insulator having a thickness of 100 .mu.m or less. An insulator that blocks impurities such as hydrogen and oxygen is placed near Tr_2n. By arranging the transistors Tr_1 to Tr_2n, the electrical characteristics of the transistors Tr_1 to Tr_2n can be It can be stabilized.

[0066] For example, the transistors Tr_1 to Tr_2n may be transistors using an oxide semiconductor. In the case of a transistor, the adjacent insulator 130 and / or insulator 126 may have excess oxygen. The excess oxygen is preferably used to reduce oxygen vacancies in the oxide semiconductor. The excess oxygen is oxygen that is present in an insulator and is bonded to the insulator. This refers to oxygen that is not bonded (free) or that has low bond energy with insulators, etc. .

[0067] Insulators that have excess oxygen are analyzed by thermal desorption spectroscopy (TDS) at temperatures above 100°C. 1×10 in the range of surface temperatures below 700℃ or between 100℃ and 500℃ 18 atom s / cm 3 That's it, 1×10 19 atoms / cm 3 or more than 1×10 20 atoms / cm 3 It may even release more than this amount of oxygen (calculated as the number of oxygen atoms).

[0068] The method for measuring the amount of released oxygen using TDS analysis is described below.

[0069] The total amount of gas released when the measurement sample was subjected to TDS analysis was calculated based on the integral value of the ion intensity of the released gas. By comparison with a standard sample, the total amount of gas released can then be calculated.

[0070] For example, the results of a TDS analysis of a silicon substrate containing a given density of hydrogen as a standard sample, From the TDS analysis results of the measured sample, the amount of oxygen molecules released from the measured sample (N O2 ) is expressed as follows: Here, the gas detected with a mass-to-charge ratio of 32 obtained by TDS analysis is We assume that all of the CH3OH is derived from oxygen molecules. The possibility of this is low, so it is not considered here. The abundance of oxygen atoms and oxygen molecules containing the oxygen atom with mass number 18 in nature is also The rate is so small that it is not taken into consideration.

[0071] N O2 =N H2 / S H2 ×S O2 ×α

[0072] N H2 is the density of hydrogen molecules desorbed from the standard sample. H2 is a standard test The integral value of the ion intensity when the sample is subjected to TDS analysis. Here, the reference value of the standard sample is N H2 / S H2 Let us assume that S O2 is the integral value of the ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ion intensity in TDS analysis. For details, see Japanese Patent Application Laid-Open No. 6-275697. A thermal desorption analyzer EMD-WA1000S / W manufactured by Epson Corporation was used. Measurements are performed using a silicon substrate containing a fixed amount of hydrogen atoms.

[0073] In addition, some of the oxygen is detected as oxygen atoms in the TDS analysis. The ratio of the oxygen molecules can be calculated from the ionization rate of the oxygen molecules. Since the ionization rate of oxygen molecules is included in the calculation, the amount of oxygen atoms released can be calculated by evaluating the amount of oxygen molecules released. It is possible to estimate even if

[0074] In addition, N O2is the amount of oxygen molecules released. The amount of oxygen released in terms of oxygen atoms is This is twice the amount released.

[0075] Alternatively, an insulator that releases oxygen upon heat treatment may contain peroxide radicals. Specifically, the spin density due to the peroxide radical is 5×10 17 spins / cm 3 Insulators containing peroxide radicals can be analyzed by electron spin resonance (ES R: Electron Spin Resonance, g value is near 2.01. It may also have symmetrical signals.

[0076] Here, the transistors Tr_S1 and Tr_S2 are made of single crystal silicon or In the case of transistors using silicon such as polycrystalline silicon, excess oxygen can affect the electrical characteristics. Therefore, the transistors Tr_S1 and In order to prevent excess oxygen from entering the transistor Tr_S2, the insulator 122 is an insulating material with low oxygen permeability. It is preferred to have a body.

[0077] Hydrogen, on the other hand, can be used to terminate dangling bonds of silicon. As a result, the electrical characteristics of the transistors Tr_S1 and Tr_S2 are improved. However, hydrogen can be Since this may cause deterioration of electrical characteristics, the insulator 122 is preferably an insulating material with low hydrogen permeability. It is preferred to have a body.

[0078] Hydrogen has a small atomic radius and therefore easily diffuses through insulators (it has a large diffusion coefficient). For example, For example, a low density insulator has high hydrogen permeability. The low density insulator does not need to have a low density throughout the entire insulator, but only a partial This includes areas where the density is very low. This is because the low density areas provide a path for hydrogen. The density at which light can pass through is not uniquely determined, but a typical value is 2.6 g / cm 3 Examples include: Examples of low density insulators include silicon oxide and silicon oxynitride. Inorganic insulation, as well as polyester, polyolefin, polyamide (nylon, aramid and organic insulators such as polyimide, polycarbonate, and acrylic. Examples of high density insulators include magnesium oxide, aluminum oxide, and germanium oxide. tungsten, gallium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide These include zinc oxide, hafnium oxide, and tantalum oxide. The high-strength insulators are not limited to those mentioned above. For example, these insulators may include boron, Contains one or more elements selected from nitrogen, fluorine, neon, phosphorus, chlorine, or argon. It may be possible.

[0079] Insulators having grain boundaries may have high hydrogen permeability. Insulators that have no grain boundaries (or few grain boundaries) are difficult for hydrogen to permeate. Crystalline insulators (such as amorphous insulators) have lower hydrogen permeability than polycrystalline insulators.

[0080] Insulators with high hydrogen binding energy may have low hydrogen permeability. For example, The insulator that bonds with hydrogen to form hydrogen compounds is heated during the manufacturing process or operation of the device. If the material has a bond energy that is low enough to prevent hydrogen from being released at high temperatures, it can be said to be an insulator with low hydrogen permeability. For example, 200°C to 1000°C, 300°C to 1000°C, or 400°C to 1000°C. Insulators that form hydrogen compounds at temperatures between ℃ and 1000℃ may have low hydrogen permeability. For example, the hydrogen desorption temperature is 200°C or more and 1000°C or less, or 300°C or more and 1000°C or less. Insulators that produce hydrogen compounds at temperatures below 400°C or 1000°C have low hydrogen permeability. On the other hand, the hydrogen desorption temperature is sometimes lower than 20°C or 400°C or lower. Insulators that form hydrogen compounds at temperatures below ℃ or between 20℃ and 200℃ have low hydrogen permeability. In some cases, the amount of hydrogen that is easily released and the amount of free hydrogen are called excess hydrogen. There is.

[0081] The charge storage layer 112b may include, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, etc. Aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium Insulators containing lithium, zirconium, lanthanum, neodymium, hafnium or tantalum , may be used in a single layer or a laminated layer. For example, aluminum oxide, magnesium oxide, Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, oxide Germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, Hafnium oxide or tantalum oxide may be used.

[0082] The insulators 112a and 112c may include, for example, boron, carbon, nitrogen, oxygen, and fluorine. Fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, gel Al, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum An insulator containing aluminum oxide may be used in a single layer or a multilayer structure. magnesium oxide, silicon oxide nitride, silicon nitride oxide, silicon nitride, Gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide , neodymium oxide, hafnium oxide or tantalum oxide may be used.

[0083] The charge storage layer 112b is disposed between the insulator 112a and the insulator 112c. The charge accumulation layer 112b may have any function other than accumulating electrons. For example, Electron traps can be created by adding impurities or by causing damage. In addition, the interface between the charge storage layer 112b and the insulator 112a, Alternatively, there may be electron traps at the interface between the charge storage layer 112b and the insulator 112c. In this case, the charge storage layer 112b and the insulator 112a and the charge storage layer 112b and the insulator 112 It is preferable that the charge storage layer 112b and the insulator 112a are heterojunctions. In the case where an electron trap is present, the insulator 112c may not be provided. When there is an electron trap at the interface between the accumulation layer 112b and the insulator 112c, the insulator 112a In some cases, the charge storage layer 112b may not be provided between adjacent memory cells. Since the charge storage layer 112b is shared, it is preferable that the movement of electrons in the charge storage layer 112b is unlikely to occur. However, when the charge storage layer 112b is separated from the adjacent memory cell, In other words, the charge storage layer 112b may be a semiconductor or a conductor. It may be an electric body.

[0084] In order to inject electrons into the charge storage layer 112b, the insulators 112a and 112c are The thickness must be such that electron tunneling occurs due to the gate voltage or back gate voltage. However, it is preferable to suppress the outflow of electrons while the memory cell is retaining data. Therefore, the tunneling of electrons without the application of gate or back gate voltages However, it is preferable that the thickness is such that electron tunneling does not occur. Therefore, the thickness must be such that electron tunneling does not occur while data can be retained. For example, the thickness of the insulator 112a and the insulator 112c may be 3 nm or more. The thickness is set to 5 nm or less, preferably 4 nm to 10 nm. For this reason, it is preferable to use an insulator with a large energy gap. The energy gap between the body 112a and the insulator 112c is preferably 6 eV or more and 10 eV or less. The energy is preferably 7 eV or more and 10 eV or less, and more preferably 8 eV or more and 10 eV or less. stomach.

[0085] Specifically, the charge storage layer 112b is made of silicon nitride or oxynitride, which has a high density of defect levels. Silicon or hafnium oxide is preferable. As c, silicon oxide or silicon oxynitride is preferable.

[0086] Conductor 154, Conductor 140, Conductor 142, Conductor 144, Conductor 146, Conductor 14 8, conductor 104, conductor 116a, conductor 116b, conductor 132, conductor 134, conductor The conductor 136 and the conductor 138 may be, for example, boron, nitrogen, oxygen, fluorine, silicon, or the like. Ni, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, Gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, sulphur Conductors containing one or more of zinc, tantalum and tungsten are used in a single layer or multilayer. For example, the material may be an alloy or a compound, and may be a conductor containing aluminum, copper, or titanium. Conductors containing tungsten, conductors containing copper and manganese, conductors containing indium, tin and oxygen Conductors, such as conductors containing titanium and nitrogen, may also be used.

[0087] The insulator 106a, the semiconductor 106b, and the insulator 106c will be described below.

[0088] By disposing the insulators 106a and 106c above and below the semiconductor 106b, In some cases, it may be possible to improve the electrical characteristics of the transistor.

[0089] The insulator 106a preferably has a CAAC-OS. The insulator 106c preferably has a CAAC-OS. .

[0090] The semiconductor 106b is, for example, an oxide containing indium. In addition, when indium is contained, the carrier mobility (electron mobility) is increased. It is preferable that b contains the element M. The element M is preferably aluminum, gallium, yttrium, or the like. Thorium or tin. Other elements that can be used for M include boron, Silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum , cerium, neodymium, hafnium, tantalum, tungsten, etc. However, the elements In some cases, M may be a combination of the above elements. The element M may be, for example, an acid. For example, the bond energy with oxygen is Alternatively, the element M may be an element that increases the energy gap of the oxide, for example. The semiconductor 106b preferably contains zinc. Materials may be more prone to crystallization if they contain zinc.

[0091] However, the semiconductor 106b is not limited to an oxide containing indium. , for example, zinc-containing, indium-free, zinc-containing, such as zinc tin oxide and gallium tin oxide. The oxide may be an oxide containing gallium, an oxide containing tin, or the like.

[0092] The semiconductor 106b is made of, for example, an oxide having a large energy gap. The energy gap of b is, for example, 2.5 eV or more and 4.2 eV or less, preferably 2.8 The excitation voltage is preferably from 3 eV to 3.5 eV, and more preferably from 3 eV to 3.8 eV.

[0093] For example, the insulators 106a and 106c are made of a material other than oxygen that constitutes the semiconductor 106b. The oxide is composed of one or more elements. The insulators 106a and 106c are composed of one or more elements other than oxygen. Therefore, the interface between the insulator 106a and the semiconductor 106b and the interface between the semiconductor 106b and the insulator 106a are Defect levels are unlikely to be formed at the interface with the layer 106c.

[0094] The insulator 106a, the semiconductor 106b, and the insulator 106c each contain at least indium. When the insulator 106a is an In-M-Zn oxide, the sum of In and M is preferably When 100 atomic %, In is preferably less than 50 atomic % and M is preferably less than 50 atomic %. More preferably, In is less than 25 atomic % and M is 75 atomic % or more. When the semiconductor 106b is an In-M-Zn oxide, I When the sum of n and M is 100 atomic %, In is preferably 25 atomic %. %, M is less than 75 atomic %, and more preferably In is 34 atomic % The insulator 106c is In-M-Zn In the case of oxides, when the sum of In and M is 100 atomic %, In is preferably 50 atomic %, M is higher than 50 atomic %, and more preferably In is 2 5 atomic % or less, and M is higher than 75 atomic %. However, the same oxide as that of the insulator 106a may be used. In some cases, the insulator 106c does not need to contain indium. For example, The insulating material 106a and / or the insulating material 106c may be gallium oxide. The number of atoms of each element contained in the body 106a, the semiconductor 106b, and the insulator 106c is simply It does not have to be an integer ratio.

[0095] The semiconductor 106b is an oxide having a larger electron affinity than the insulators 106a and 106c. For example, the semiconductor 106b is made of a material selected from the insulators 106a and 106c. The electron affinity is 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV. It is more preferable to use an oxide having a larger molecular weight by 0.15 eV or more and 0.4 eV or less. Electron affinity is the energy difference between the vacuum level and the bottom of the conduction band.

[0096] Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the insulator 106c contains indium gallium oxide. The atomic ratio [Ga / (In+Ga)] is, for example, 70% or more, preferably 80% or more, and Preferably, the ratio is 90% or more.

[0097] At this time, when a gate voltage is applied, the insulator 106a, the semiconductor 106b, and the insulator 106c Of these, a channel is formed in the semiconductor 106b having the larger electron affinity.

[0098] Here, between the insulator 106a and the semiconductor 106b, In addition, between the semiconductor 106b and the insulator 106c, The mixed region may have a semiconductor 106b and an insulator 106c. Therefore, the potential density of the insulator 106a, the semiconductor 106b, and the insulator 106c is reduced. In the laminate, the energy changes continuously near each interface (also called continuous junction). (See FIG. 12.) Note that the insulator 106a, the semiconductor 106b, and In some cases, the interface between the insulating body 106c and the insulator 106b may not be clearly distinguishable.

[0099] At this time, the electrons flow into the semiconductor 106b, not into the insulator 106a and the insulator 106c. The insulators 106a and 106c mainly move through the In the case of a transistor, it can have the properties of a conductor, a semiconductor, or an insulator. Specifically, the insulator 106a and the semiconductor 106b have a region in which a channel is not formed. The channel is formed only near the interface between the insulator 106c and the semiconductor 106b and near the interface between the insulator 106c and the semiconductor 106b. The channel is not formed in the other regions. In this specification, the term "insulator" is used instead of "semiconductor" and "conductor". Here, the insulator 106a, the semiconductor 106b, the insulator 106c, The distinction between semiconductors and insulators is based on the relative differences in physical properties. For example, In the semiconductor 10, an insulator that can be used as the insulator 106a or the insulator 106c is As described above, the insulator 106a and the semiconductor 106b may be used as the The defect level density at the interface with the semiconductor 106b and the interface between the semiconductor 106b and the insulator 106c By lowering the defect state density in the semiconductor 106b, the movement of electrons is inhibited in the semiconductor 106b. This reduces the risk of cracking, and allows the on-state current of the transistor to be increased.

[0100] In addition, the on-current of the transistor is increased as the factors that inhibit the movement of electrons are reduced. For example, if there is no factor that inhibits the movement of electrons, electrons can move efficiently. It is estimated that the electron movement is caused by the large physical unevenness of the channel formation region. is also inhibited.

[0101] In order to increase the on-current of the transistor, for example, The square of the surface (the surface to be formed, here the upper surface of the insulator 106a) in the range of 1 μm×1 μm Root Mean Square (RMS) roughness less than 1 nm, preferably is less than 0.6 nm, more preferably less than 0.5 nm, and even more preferably less than 0.4 nm. In addition, the average surface roughness (also called Ra) in the range of 1 μm × 1 μm is 1n m, preferably less than 0.6 nm, even more preferably less than 0.5 nm, The maximum height difference (PV ) is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, More preferably, it is less than 7 nm. RMS roughness, Ra and PV are - Scanning probe microscope system SPA-500 manufactured by Nano Technology Co., Ltd. It can be measured.

[0102] In addition, in order to increase the on-state current of the transistor, the thickness of the insulator 106c is preferably as small as possible. For example, it is preferably less than 10 nm, more preferably 5 nm or less, and even more preferably 3 nm or less. On the other hand, the insulator 106c may have a channel shape. The semiconductor 106b is formed by adding elements other than oxygen (hydrogen, silicon) that compose the adjacent insulator. The insulator 106c has a function of blocking the intrusion of For example, the thickness is 0.3 nm or more, preferably 1 nm or more. More preferably, the insulator 106c has a region with a thickness of 2 nm or more. The insulator 106c is made of an oxygen-containing material to suppress outward diffusion of oxygen released from other insulators. It is preferable that the compound has a property of blocking the above-mentioned.

[0103] In order to increase reliability, the insulator 106a is preferably thick and the insulator 106c is preferably thin. For example, it is preferably 10 nm or more, more preferably 20 nm or more, and even more preferably 40 nm or more. It is preferable that the insulator 106a has a region having a thickness of 60 nm or more, more preferably 60 nm or more. By increasing the thickness of the insulator 106a, the heat generated from the interface between the insulator 106a and the adjacent insulator is reduced. The distance from the semiconductor 106b where the channel is formed can be increased. Since the productivity of the device may decrease, for example, the thickness is set to 200 nm or less, preferably 120 nm or less. The insulator 106a may have a thickness of 80 nm or less. stomach.

[0104] For example, between the semiconductor 106b and the insulator 106a, for example, secondary ion mass spectrometry (S In IMS (Secondary Ion Mass Spectrometry) , 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 The following is preferably is 1×10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 Below are some more Preferably 1×10 16 atoms / cm 3 More than 2×10 18 atoms / cm 3 The following In addition, a region having a silicon concentration is formed between the semiconductor 106b and the insulator 106c. In MS, 1 × 10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Below Lower, preferably 1×10 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 Below or less, and more preferably 1×10 16 atoms / cm 3 More than 2×10 18 atoms / c m 3 The silicon concentration in the region is as follows:

[0105] The semiconductor 106b has a SIMS resolution of 1×10 16 atoms / cm 3 More than 2× 10 20 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 More than 5× 10 19 atoms / cm 3 Less than or equal to 1×10 16 atoms / cm 3 End 1×10 19 atoms / cm 3 Less than 1×10, more preferably 16 atoms / cm 3 5×10 or more 18 atoms / cm 3 The hydrogen concentration range is as follows: In order to reduce the hydrogen concentration in the insulator 106b, the hydrogen concentrations in the insulators 106a and 106c are Insulators 106a and 106c are preferably formed by SIMS. 1×10 16 atoms / cm 3 More than 2×10 20 atoms / cm 3 Hereinafter, preferably 1×10 16 atoms / cm 3 5×10 or more 19 atoms / cm 3 The following is more preferred: 1×10 16 atoms / cm 3 More than 1×10 19 atoms / cm 3 Further details are below. Preferably 1 x 10 16 atoms / cm 3 5×10 or more 18atoms / cm 3 below The semiconductor 106b has a region with a hydrogen concentration of 1×10 1 5 atoms / cm 3 5×10 or more 19 atoms / cm 3 Less than or equal to 1×10 1 5 atoms / cm 3 5×10 or more 18 atoms / cm 3 Less than or equal to 1×1, more preferably 0 15 atoms / cm 3 More than 1×10 18 atoms / cm 3 More preferably, 1×10 15 atoms / cm 3 5×10 or more 17 atoms / cm 3 With the following nitrogen concentration In order to reduce the nitrogen concentration in the semiconductor 106b, the insulator 106a It is preferable to reduce the nitrogen concentration in the insulator 106a and the insulator 106c. 06c is 1×10 15 atoms / cm 3 5×10 or more 19 ato ms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 5×10 or more 18 ato ms / cm 3 Less than or equal to 1×10 15 atoms / cm 3 More than 1×10 18 a toms / cm 3 Less than 1×10, more preferably 15 atoms / cm 3 5×10 or more 17 atoms / cm 3 The nitrogen concentration ranges as follows:

[0106] The three-layer structure described above is an example. For example, a two-layer structure without the insulator 106a or the insulator 106c Alternatively, the insulating layer 106 may be formed on or under the insulating layer 106a or on the insulating layer 106c. The insulator 106a, the semiconductor 106b, and the insulator 106c are illustrated above and below. Alternatively, a four-layer structure having one of the semiconductors on the insulator 106a may be used. At least two of the following locations: under the insulator 106a, over the insulator 106c, and under the insulator 106c Any of the semiconductors exemplified as the insulator 106a, the semiconductor 106b, and the insulator 106c may be used. Alternatively, it may have an n-layer structure (n is an integer of 5 or more) having one or more layers.

[0107] <Composition> The composition of the In-M-Zn oxide is described below. The element M is aluminum. M is a metal, gallium, yttrium, or tin. Other elements that can be used for M These include boron, silicon, titanium, iron, nickel, germanium, zirconium, and molybdenum. Lithium, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, etc. be.

[0108] FIG. 13 is a triangular diagram in which In, M, or Zn is placed at each vertex. indicates the atomic concentration of In, [M] indicates the atomic concentration of element M, and [Zn] indicates the atomic concentration of Zn. Shows.

[0109] It is known that In-M-Zn oxide crystals have a homologous structure, and InMO3 (ZnO) m (m is a natural number.) It is also possible to replace In with M. Therefore, In 1+α M 1-α O3(ZnO) m It can also be expressed as (-1≦α≦1). This means that [In]:[M]:[Zn]=1+α:1-α:1, [In]:[M]:[Zn ]=1+α:1-α:2, [In]:[M]:[Zn]=1+α:1-α:3, [In] :[M]:[Zn]=1+α:1-α:4, and [In]:[M]:[Zn]=1+α The composition is shown by the dashed line written as α:1-α:5. Note that the thick line above the dashed line indicates, for example, This is a composition that can become a solid solution when the raw oxides are mixed and fired at 1350°C.

[0110] Therefore, by approaching the composition that can become the above-mentioned solid solution, the crystallinity can be increased. When forming an In-M-Zn oxide film by sputtering, the target The composition of the target may differ from the composition of the film. For example, the atomic ratio of the target may be 1:1: 1", "1:1:1.2", "3:1:2", "4:2:4.1", "1:3:2", When the In-M-Zn oxides with the ratios of 1:3:4 and 1:4:5 were used, the atomic ratio of the film was The ratios are "1:1:0.7 (0.5 to 0.9)" and "1:1:0.9 (0.8 to 1 .1), 3:1:1.5 (1 to 1.8), 4:2:3 (2.6 to 3 .6), 1:3:1.5 (1 to 1.8), 1:3:3 (2.5 to 3 Therefore, the desired combination is To obtain a film of this composition, the composition of the target should be selected taking into consideration the change in composition.

[0111] <Structure of oxide semiconductor> The structure of an oxide semiconductor will be described below.

[0112] Oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, c-axis-aligned (CAAC-OS) crystalline oxide semiconductor, polycrystalline oxide Semiconductor, nc-OS (nanocrystalline oxide semiconducting uctor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous-l ike oxide semiconductor and amorphous oxide semiconductor. do.

[0113] From another point of view, the oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. Crystalline oxide semiconductors are classified into single crystal oxide semiconductors, CAAC- Examples of such materials include OS, polycrystalline oxide semiconductors, and nc-OS.

[0114] Amorphous structures are generally isotropic, have no inhomogeneous structure, and are metastable arrangements of atoms. The bond angles are flexible, and the short-range order is not fixed. It is said that...

[0115] That is, the stable oxide semiconductor is transformed into a completely amorphous In addition, it is not isotropic (for example, it does not have a periodic structure in a small region). On the other hand, an oxide semiconductor having an a-li structure cannot be called a completely amorphous oxide semiconductor. The ke OS is not isotropic, but has an unstable structure with voids. In terms of instability, a-like OS is similar in physical properties to amorphous oxide semiconductors. .

[0116] <caac-os> First, let me explain about CAAC-OS.

[0117] CAAC-OS is an oxide semiconductor that has multiple crystal parts (also called pellets) aligned along the c-axis. It is a type of conductor.

[0118] CAAC-OS was analyzed by X-ray diffraction (XRD). For example, the InGaZnO4, which is classified into the space group R-3m, The structure of CAAC-OS with crystals is analyzed by the out-of-plane method. As shown in FIG. 14(A), a peak appears at a diffraction angle (2θ) of about 31°. The peak is attributed to the (009) plane of the InGaZnO4 crystal, so The crystal has a c-axis orientation, and the c-axis is the surface on which the CAAC-OS film is to be formed (also called the surface on which the film is to be formed). It can be seen that the crystal is oriented in a direction perpendicular to the upper surface. In addition to the peaks around 2θ of 36°, a peak may also appear around 2θ of 36°. The peaks near the center are due to the crystal structure classified into the space group Fd-3m. It is preferable that -OS does not show such a peak.

[0119] On the other hand, in-pla, X-rays are incident on the CAAC-OS in a direction parallel to the surface on which the film is to be formed. When the structure is analyzed by the NE method, a peak appears at 2θ of about 56°. This peak is I The lattice constant is the (110) plane of the nGaZnO4 crystal. The 2θ is fixed at around 56°. The analysis (φ scan) is performed while rotating the sample around the axis (φ axis) of the normal vector of the sample surface. Even if the annealing is performed, no clear peak appears as shown in FIG. When φ was scanned with 2θ fixed at around 56° for nO4, the results were as shown in Figure 14(C). As shown in Fig. 1, six peaks are observed that are attributable to crystal planes equivalent to the (110) plane. From the structural analysis using RD, it was found that the orientation of the a-axis and b-axis of CAAC-OS is irregular. It can be confirmed that:

[0120] Next, we will explain the CAAC-OS analyzed by electron diffraction. For CAAC-OS with nO4 crystals, a probe was applied parallel to the CAAC-OS surface. When an electron beam with a diameter of 300 nm is incident, a diffraction pattern (control pattern) as shown in FIG. This is also called the limited-area electron diffraction pattern.) may appear. This diffraction pattern includes In The spots are due to the (009) plane of the GaZnO4 crystal. In some cases, the pellets contained in the CAAC-OS have a c-axis orientation, and the c-axis is aligned with the surface on which the material is formed. On the other hand, for the same sample, the direction of the sample surface is The diffraction pattern when an electron beam with a probe diameter of 300 nm is incident perpendicularly is shown in Fig. 14(E). A ring-shaped diffraction pattern is observed in FIG. 14(E). Electron diffraction using an electron beam with a diameter of 300 nm also revealed that the pellets in the CAAC-OS It can be seen that the a-axis and b-axis of the slit have no orientation. The first ring is due to the (010) and (100) planes of the InGaZnO4 crystal. It is considered that the second ring in Fig. 14(E) is due to the (110) plane, etc. It is possible.

[0121] In addition, a transmission electron microscope (TEM) A combined analysis image of the bright-field image and the diffraction pattern of CAAC-OS was obtained using a microscope. (also called high-resolution TEM image), multiple pellets can be confirmed. On the other hand, even in high-resolution TEM images, the boundaries between pellets, i.e., grain boundaries (grain bows), are not clearly visible. In some cases, it may not be possible to clearly identify the CAAC It can be said that the -OS is less susceptible to the decrease in electron mobility caused by grain boundaries.

[0122] Figure 15(A) shows a high-resolution T The TEM image is shown. For high-resolution TEM imaging, spherical aberration correction is used. The spherical aberration correction function was used. A high-resolution TEM image is specifically called a Cs-corrected high-resolution TEM image. For example, the atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd. It can be observed that.

[0123] From FIG. 15(A), a pellet, which is an area where metal atoms are arranged in layers, can be confirmed. It has been found that the size of a single pellet can be 1 nm or more, or 3 nm or more. Therefore, the pellets are called nanocrystals (nc). CAAC-OS can also be used with CANC (C-Axis Aligned nan The pellets are also called oxide semiconductors with CAAC -OS surface or top surface unevenness, and CAAC-OS surface or top surface unevenness is parallel to the surface.

[0124] In addition, Fig. 15(B) and Fig. 15(C) show CAAC images observed from a direction approximately perpendicular to the sample surface. 15(D) and 15(E) show Cs-corrected high-resolution TEM images of the -OS plane. These are images obtained by processing the images of Fig. 15(B) and Fig. 15(C), respectively. First, the method of converting FIG. 15(B) into a fast Fourier transform (FFT) is Then, the FFT image is obtained by Fourier Transform (FFT) processing. In the FFT image, the origin is used as the reference point, and the distance is 2.8 nm. -1 From 5.0 nm -1 Remaining range between Next, the masked FFT image is subjected to an inverse fast Fourier transform (IFFT: Inverse Fast Fourier Transform (IFFT) processing is used to The image thus obtained is called an FFT filtered image. The filtered image is an image in which periodic components are extracted from a Cs-corrected high-resolution TEM image. The sequence is shown.

[0125] In FIG. 15(D), the area where the lattice arrangement is disturbed is indicated by a dashed line. The area surrounded by the dashed line is The area indicated by the dashed line is the connection between the pellets. The broken line indicates a hexagonal shape, so it can be seen that the pellets are hexagonal. The shape of the dot is not limited to a regular hexagon, and is often a non-regular hexagon.

[0126] In FIG. 15(E), a dotted line separates an area with a uniform lattice arrangement from an area with a different uniform lattice arrangement. Even in the vicinity of the dotted line, no clear grain boundaries can be confirmed. When you connect the neighboring lattice points, you can get a distorted hexagon, pentagon, or / and heptagon. In other words, by distorting the lattice arrangement, the formation of grain boundaries can be suppressed. This is because the atomic arrangement of CAAC-OS is dense in the ab-plane direction. The substitution of metal elements causes changes in the bond distance between atoms. This is believed to be because distortion can be tolerated.

[0127] As described above, the CAAC-OS has a c-axis orientation and multiple crystals in the ab-plane direction. A number of pellets (nanocrystals) are connected to form a distorted crystal structure. AC-OS, CAA crystal(c-axis-aligned ab-pl It can also be called an oxide semiconductor having an ane-anchored crystal. do.

[0128] CAAC-OS is a highly crystalline oxide semiconductor. The crystallinity of oxide semiconductors is improved by the incorporation of impurities. CAAC-OS is a material that can be degraded by impurities and defects ( It can also be said that the oxide semiconductor has few oxygen vacancies.

[0129] The impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metals. For example, oxygen is more abundant than metal elements such as silicon that constitute oxide semiconductors. Elements with strong bonding strength with the oxide semiconductor remove oxygen from the oxide semiconductor, thereby changing the atomic arrangement of the oxide semiconductor. In addition, heavy metals such as iron and nickel, argon, and nitrogen Carbon oxide and other elements have a large atomic radius (or molecular radius), so they can easily arrange the atoms of oxide semiconductors. This causes the crystallinity to decrease.

[0130] When an oxide semiconductor has impurities or defects, its characteristics may change due to light, heat, etc. For example, impurities contained in an oxide semiconductor can become carrier traps or can displace carriers. For example, oxygen vacancies in oxide semiconductors can act as carrier traps. In some cases, the SiO 2 can become a carrier generation source by capturing hydrogen.

[0131] CAAC-OS, which has few impurities and oxygen vacancies, is an oxide semiconductor with low carrier density. Specifically, 8×10 11 pieces / cm 3 Less than 1 x 10 11 / cm 3 less than, More preferably, 1×10 10 pieces / cm 3 Less than 1 x 10 -9 pieces / cm 3 The above Such an oxide semiconductor can be a high-purity intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and is a substantially high-purity intrinsic oxide semiconductor. In other words, it can be said that the oxide semiconductor has stable characteristics.

[0132] <nc-os> Next, we will explain nc-OS.

[0133] The following describes the case where nc-OS is analyzed by XRD. For example, When structural analysis is performed using the out-of-plane method, no peaks indicating orientation appear. That is, the crystals of the nc-OS do not have any orientation.

[0134] For example, an nc-OS having InGaZnO4 crystals was sliced ​​to a thickness of 34 nm. When an electron beam with a probe diameter of 50 nm is incident parallel to the surface to be formed on the region shown in FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown in (A) was observed. In addition, the diffraction pattern (nm) when an electron beam with a probe diameter of 1 nm was incident on the same sample was The electron diffraction pattern (EMD pattern) is shown in FIG. 16(B). From FIG. 16(B), a ring-shaped region Therefore, nc-OS has a probe diameter of 50 nm. Although no order was observed by irradiating the electron beam, the order was observed by irradiating the electron beam with a probe diameter of 1 nm. By projecting the images, order is confirmed.

[0135] In addition, when an electron beam with a probe diameter of 1 nm is incident on an area with a thickness of less than 10 nm, As shown in FIG. 16(C), an electron diffraction pattern was observed in which the spots were arranged in a roughly regular hexagonal shape. Therefore, in the range of thickness less than 10 nm, the nc-OS is ordered. It can be seen that the crystals have highly crystalline regions. Therefore, there are some areas where no regular electron diffraction pattern is observed.

[0136] FIG. 16(D) shows the Cs-corrected high resolution image of the cross section of nc-OS observed from a direction approximately parallel to the surface on which the nc-OS was formed. The nc-OS is shown in the high-resolution TEM image, with the areas indicated by the auxiliary lines. As shown in Fig. 1, there are areas where crystals can be confirmed, and areas where no clear crystals can be confirmed. The crystal part in the nc-OS has a size of 1 nm to 10 nm. In particular, the size of the crystal part is often between 1 nm and 3 nm. An oxide semiconductor having a diameter of more than 0 nm and less than 100 nm is called a microcrystalline oxide semiconductor. It is sometimes called a crystalline oxide semiconductor. For example, in the case of nc-OS, the grain boundaries may not be clearly identified in high-resolution TEM images. It is possible that the nanocrystals originate from the same source as the pellets in CAAC-OS. Therefore, hereinafter, the crystalline parts of the nc-OS may be referred to as pellets.

[0137] In this way, the nc-OS can be used in microscopic regions (e.g., regions of 1 nm to 10 nm, especially The atomic arrangement has periodicity in the region of 1 nm to 3 nm. There is no regularity in the crystal orientation between different pellets. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous OS. It may be difficult to distinguish it from an oxide semiconductor.

[0138] In addition, since the crystal orientation between pellets (nanocrystals) is not regular, nc-OS is Oxide with RANC (Random Aligned nanocrystals) Semiconductor or NANC (Non-Aligned nanocrystals) In other words, the oxide semiconductor can be called an oxide semiconductor.

[0139] The nc-OS is an oxide semiconductor with higher order than an amorphous oxide semiconductor. The nc-OS has a lower density of defect states than the a-like OS and amorphous oxide semiconductors. However, the crystal orientation of nc-OS is not regular among different pellets. , the nc-OS has a higher density of defect states than the CAAC-OS.

[0140] <a-like OS> The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. It is a conductor.

[0141] Figure 17 shows high-resolution cross-sectional TEM images of the a-like OS. This is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. ) is 4.3 × 10 8 e - / nm 2 Electrons (e - ) High a-like OS after irradiation 17(A) and 17(B) show that the a-like OS It can be seen that from the start of electron irradiation, striped bright regions extending in the vertical direction are observed. It can be seen that the shape of the bright regions changes after electron irradiation. It is estimated to be in the degree range.

[0142] Because of the porosity, the a-like OS is an unstable structure. To demonstrate that the OS has a less stable structure compared with CAAC-OS and nc-OS. , shows the change in structure due to electron irradiation.

[0143] The samples prepared were a-like OS, nc-OS, and CAAC-OS. The sample in is also an In-Ga-Zn oxide.

[0144] First, high-resolution cross-sectional TEM images of each sample are obtained. Each of the above has a crystalline portion.

[0145] The unit cell of the InGaZnO4 crystal has three In-O layers and a Ga-Zn- It is known that the structure has a total of nine layers, including six O layers, stacked in layers in the c-axis direction. The spacing between these adjacent layers is the same as the lattice spacing (also called the d value) of the (009) plane. The value is about 0.29 nm, which is determined by crystal structure analysis. In the figure below, the areas where the lattice spacing is between 0.28 nm and 0.30 nm are InGaZn The lattice fringes correspond to the ab plane of the InGaZnO4 crystal. do.

[0146] Figure 18 shows an example of the average size of the crystal parts (22 to 30 places) of each sample. The length of the lattice fringes mentioned above is the size of the crystal part. The crystal part of the OS grows larger according to the cumulative dose of electrons used in obtaining the TEM image. From Figure 18, it can be seen that in the early stages of TEM observation, the size of the particles is about 1.2 nm. The part of the crystal that was a nucleus (also called the initial nucleus) is filled with electrons (e - ) cumulative exposure of 4.2 × 10 8 e - / nm 2 It can be seen that the size of the crystals grows to about 1.9 nm in the nc The cumulative electron dose from the start of electron irradiation was 4.2 × 10 8 e - / nm 2 It can be seen that there is no change in the size of the crystals in the range from The size of the crystalline parts of the nc-OS and CAAC-OS was The results show that the thicknesses are approximately 1.3 nm and 1.8 nm, respectively. A Hitachi transmission electron microscope H-9000NAR was used for the TEM observations. Electron beam irradiation conditions The acceleration voltage was 300 kV and the current density was 6.7 × 10 5 e - / (nm 2 ·s), irradiation area The diameter was set to 230 nm.

[0147] Thus, in a-like OS, the growth of crystals can be observed by electron irradiation. On the other hand, the growth of the crystals in the nc-OS and CAAC-OS was hardly observed by electron irradiation. That is, compared with the nc-OS and CAAC-OS, the a-like OS It is clear that this is an unstable structure.

[0148] In addition, because of the porosity, a-like OS is more resistant to vascular endothelial cell proliferation than nc-OS and CAAC-OS. Specifically, the density of the a-like OS is lower than that of a single crystal of the same composition. The density of nc-OS is 78.6% or more and less than 92.3% of that of CAAC. The density of the -OS is 92.3% or more and less than 100% of the density of a single crystal of the same composition. It is difficult to form a film of an oxide semiconductor having a density of less than 78% of that of the oxide semiconductor.

[0149] For example, in an oxide semiconductor with an atomic ratio of In:Ga:Zn=1:1:1, The density of single crystal InGaZnO4 with a hexagonal crystal structure is 6.357 g / cm 3 That is it. For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, , the density of a-like OS is 5.0g / cm 3 More than 5.9g / cm 3 is less than For example, in an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, The density of nc-OS and that of CAAC-OS are 5.9 g / cm 3 More than 6.3g / cm 3 is less than.

[0150] If single crystals of the same composition do not exist, single crystals of different compositions can be combined in any ratio. By doing so, it is possible to estimate the density equivalent to a single crystal of a desired composition. The density of a single crystal of a desired composition is calculated by the ratio of the single crystals of different compositions. The density can be estimated by using a weighted average. It is preferable to estimate them together.

[0151] As described above, oxide semiconductors have various structures, each of which has various characteristics. The oxide semiconductor may be, for example, an amorphous oxide semiconductor, an a-like OS, an nc-OS, The CAAC-OS may be a laminated film having two or more kinds. [Explanation of symbols]

[0152] 100 Substrates 104 Conductors 106a Insulator 106b Semiconductors 106c Insulator 112a Insulator 112b Charge storage layer 112c Insulator 116a Conductor 116b Conductor 120 Insulator 122 Insulators 124 Insulators 126 Insulators 128 Insulator 130 Insulator 132 Conductors 134 Conductors 136 Conductors 138 Conductors 140 Conductors 142 Conductors 144 Conductors 146 Conductors 148 Conductors 154 Conductors 162 Insulators 166 Impurity region

Claims

[Claim 1] a memory cell string having a substrate, a prismatic insulator, and a plurality of transistors connected in series; The prismatic insulator is disposed on the substrate, the memory cell string is disposed on a side surface of the prismatic insulator; Each of the plurality of transistors has a gate insulator and a gate electrode; the gate insulator comprises a first insulator, a second insulator, and a charge storage layer; the charge storage layer is disposed between the first insulator and the second insulator; the plurality of transistors include an oxide semiconductor; The oxide semiconductor device contains indium, an element M (aluminum, gallium, yttrium or tin), and zinc.

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