Semiconductor device

Abstract

To provide a semiconductor device configured so that damage to a joining member is prevented.SOLUTION: A semiconductor device comprises semiconductor elements 40, a first wiring member 50, a second wiring member 60, conductive spacers 70, and joining members 101. The semiconductor elements 40 have first main electrodes 40D and second main electrodes 40S. The wiring members are electrically connected to the two main electrodes of the semiconductor elements, respectively. The conductive spacers are arranged between the semiconductive elements and one wiring member. The joining member joins the semiconductor elements to the spacers. Comparison results of the plurality of spacers having different yield stresses show that the smaller the yield stress, the smaller distortion of the joining members. Further, a ratio of a difference in distortion between the joining members to a difference in yield stress between the spacers in a state where the yield stress is a predetermined yield stress or lower is larger than a ratio of a difference in distortion between the joining members to a difference in yield stress between the spacers in a state where the yield stress is the predetermined yield stress or higher, where the yield stress of the spacers is smaller than the predetermined yield stress.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The disclosure provided herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 describes a semiconductor device having a semiconductor chip having a front and back surface on which a semiconductor element is formed, and a heat sink block joined to the back surface of the semiconductor chip via solder. The semiconductor chip is a vertical semiconductor element that flows current in the thickness direction of the substrate as a heat generating element, and the back surface of the semiconductor chip is structured such that various pads are formed. The entire back surface of the back surface is a pad connected to the collector or drain of the semiconductor power element. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-229472 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the semiconductor chip and the spacer are deformed by the thermal cycle, stress is concentrated on the bonding material between the semiconductor element and the spacer, which may cause damage to the bonding material.

[0005] An object of the present disclosure is to provide a semiconductor device in which damage to bonding members is suppressed. [Means for solving the problem]

[0006] A semiconductor device according to an aspect of the present disclosure includes: a semiconductor element (40) having a first main electrode (40D) provided on one surface and a second main electrode (40S) provided on a back surface opposite to the one surface in a plate thickness direction; a first wiring member (50) electrically connected to the first main electrode; a second wiring member (60) electrically connected to the second main electrode; a conductive spacer (70) provided between the semiconductor element and the second wiring member; a bonding member (101) provided between the semiconductor element and the spacer and bonding the semiconductor element and the spacer together; When comparing multiple spacers with different yield stresses, The smaller the yield stress of the spacer, the smaller the joining member strain, which is the strain of the joining member, and the ratio of the difference in the joining member strain to the difference in the spacer yield stress below a predetermined yield stress is greater than the ratio of the difference in the joining member strain to the difference in the spacer yield stress above the predetermined yield stress, The spacer has a yield stress less than a predetermined yield stress.

[0007] Even if the semiconductor element (40) and the spacer (70) are deformed by the thermal cycle, the yield stress of the spacer is smaller than the predetermined yield stress, so the distortion of the bonding member (101) is reduced, and therefore damage to the bonding member can be suppressed.

[0008] It should be noted that the reference numbers in parentheses above merely indicate the corresponding relationship with the configurations described in the embodiments described below, and do not in any way limit the technical scope. [Brief description of the drawings]

[0009] [Figure 1] FIG. 2 is an electric circuit diagram illustrating a drive system of the vehicle. [Diagram 2] FIG. 1 is a cross-sectional view of a semiconductor device. [Diagram 3] FIG. 2 is a schematic diagram illustrating a cross section of a semiconductor device. [Figure 4] 13 is a graph showing the relationship between the yield stress of a spacer and the distortion of a second main electrode for each size of a semiconductor element. [Diagram 5] 1 is a graph showing the relationship between yield stress and electrode distortion for a joining member. [Figure 6]1 is a graph showing the relationship between temperature and yield stress in a bonding member and a spacer. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, several embodiments for carrying out the present disclosure will be described with reference to the drawings. In each embodiment, the same reference numerals may be used to designate parts corresponding to matters described in the preceding embodiment, and duplicated descriptions may be omitted. In each embodiment, when only a part of the configuration is described, the other embodiment described previously may be applied to the other parts of the configuration.

[0011] In addition to combinations of parts that are explicitly stated as possible in each embodiment, it is also possible to partially combine embodiments, embodiments and variations, and variations even if not explicitly stated, provided that there are no particular problems with the combination.

[0012] (First embodiment) First, a schematic configuration of a vehicle drive system 1 will be described with reference to FIG.

[0013] <Vehicle drive system> As shown in FIG. 1, a vehicle drive system 1 includes a DC power supply 2, a motor generator 3, and a power conversion device 4.

[0014] The DC power supply 2 is a DC voltage source composed of a chargeable and dischargeable secondary battery. The secondary battery is, for example, a lithium-ion battery or a nickel-metal hydride battery. The motor generator 3 is a three-phase AC rotating electric machine. The motor generator 3 functions as a drive source for the vehicle, that is, an electric motor. The motor generator 3 functions as a generator during regeneration. The power conversion device 4 performs power conversion between the DC power supply 2 and the motor generator 3.

[0015] <Power conversion device> Next, a circuit configuration of the power conversion device 4 will be described with reference to Fig. 1. The power conversion device 4 includes a power conversion circuit. The power conversion device 4 of this embodiment includes a smoothing capacitor 5 and an inverter 6 which is the power conversion circuit.

[0016] The smoothing capacitor 5 mainly smoothes the DC voltage supplied from the DC power supply 2. The smoothing capacitor 5 is connected to a P line 7, which is a power supply line on the high potential side, and an N line 8, which is a power supply line on the low potential side. The P line 7 is connected to the positive electrode of the DC power supply 2, and the N line 8 is connected to the negative electrode of the DC power supply 2. The positive electrode of the smoothing capacitor 5 is connected to the P line 7 between the DC power supply 2 and the inverter 6. The negative electrode of the smoothing capacitor 5 is connected to the N line 8 between the DC power supply 2 and the inverter 6. The smoothing capacitor 5 is connected in parallel to the DC power supply 2. The P line 7 and the N line 8 may be referred to as power supply lines.

[0017] The inverter 6 is a DC-AC conversion circuit. The inverter 6 converts a DC voltage into a three-phase AC voltage in accordance with switching control by a control circuit (not shown) and outputs the voltage to the motor generator 3. This drives the motor generator 3 to generate a predetermined torque. During regenerative braking of the vehicle, the inverter 6 converts the three-phase AC voltage generated by the motor generator 3 upon receiving rotational force from the wheels into a DC voltage in accordance with switching control by the control circuit and outputs the DC voltage to the P line 7. In this way, the inverter 6 performs bidirectional power conversion between the DC power source 2 and the motor generator 3.

[0018] The inverter 6 is configured with upper and lower arm circuits 9 for three phases. The upper and lower arm circuits 9 are sometimes referred to as legs. The upper and lower arm circuits 9 each have an upper arm 9H and a lower arm 9L. The upper arm 9H and the lower arm 9L are connected in series between the P line 7 and the N line 8, with the upper arm 9H on the P line 7 side. A connection point between the upper arm 9H and the lower arm 9L is connected to the winding 3a of the corresponding phase in the motor generator 3 via an output line 10. The inverter 6 has six arms. Each arm is configured with a switching element. At least a part of each of the P line 7, the N line 8, and the output line 10 is configured with a conductive member such as a bus bar.

[0019] In this embodiment, an n-channel MOSFET 11 is used as the switching element constituting the upper and lower arms. The type of the switching element is not limited to a MOSFET. For example, an IGBT may be used. In this embodiment, as an example, a case where a MOSFET 11 is used as the switching element will be described. The number of switching elements constituting the upper and lower arms is not particularly limited. There may be one or more. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0020] As an example, in this embodiment, two MOSFETs 11 are connected in series between the P line 7 and the N line 8. The drain of the MOSFET 11 in the upper arm 9H is connected to the P line 7. The source of the MOSFET 11 in the lower arm 9L is connected to the N line 8.

[0021] A freewheeling diode 12 is connected in anti-parallel to each of the MOSFETs 11. The diode 12 may be a parasitic diode (body diode) of the MOSFET 11, or may be provided separately from the parasitic diode. The anode of the diode 12 is connected to the source of the corresponding MOSFET 11, and the cathode is connected to the drain. The upper and lower arm circuits 9 for one phase are provided by one semiconductor device 20. Details of the semiconductor device 20 will be described later.

[0022] The power conversion device 4 may further include a converter as a power conversion circuit. The converter is a DC-DC conversion circuit that converts a DC voltage into a DC voltage of a different value. The converter is provided between the DC power source 2 and the smoothing capacitor 5. The converter is configured to include, for example, a reactor and the above-mentioned upper and lower arm circuits 9. With this configuration, voltage can be increased and decreased. The power conversion device 4 may include a filter capacitor that removes power supply noise from the DC power source 2. The filter capacitor is provided between the DC power source 2 and the converter.

[0023] The power conversion device 4 may include a drive circuit for a switching element constituting the inverter 6 or the like. The drive circuit supplies a drive voltage to the gate of the MOSFET 11 of the corresponding arm based on a drive command from the control circuit. The drive circuit drives the corresponding MOSFET 11, i.e., turns it on and off, by applying the drive voltage. The drive circuit is sometimes referred to as a driver.

[0024] The power conversion device 4 may include a control circuit for the switching element. The control circuit generates a drive command for operating the MOSFET 11 and outputs it to the drive circuit. The control circuit generates the drive command based on, for example, a torque request input from a higher-level ECU (not shown) and signals detected by various sensors. ECU is an abbreviation for Electronic Control Unit.

[0025] The various sensors include, for example, a current sensor, a rotation angle sensor, and a voltage sensor. The current sensor detects the phase current flowing through the winding 3a of each phase. The rotation angle sensor detects the rotation angle of the rotor of the motor generator 3. The voltage sensor detects the voltage across the smoothing capacitor 5. The control circuit is configured to include, for example, a processor and a memory. The control circuit outputs, for example, a PWM signal as a drive command. PWM is an abbreviation for Pulse Width Modulation.

[0026] <Semiconductor device> Next, the semiconductor device 20 will be described with reference to Figs. 2 to 6. Fig. 2 is a cross-sectional view of the semiconductor device 20. Fig. 3 is a schematic view illustrating a cross-section of the semiconductor device 20. Fig. 4 is a graph showing the relationship between the yield stress of the spacer 70 and the strain of the source electrode 40S for each size of the semiconductor element 40. Fig. 5 is a graph showing the relationship between the yield stress of the spacer 70 and the strain of the source electrode 40S for each of the bonding members 100 to 102. Fig. 6 is a graph showing the relationship between the temperature and the yield stress in the bonding member 101 and the spacer 70.

[0027] In the following, the thickness direction of the semiconductor element 40 (semiconductor substrate) is defined as the Z direction. The arrangement direction of two semiconductor elements 40 arranged side by side, perpendicular to the Z direction, is defined as the X direction. In this embodiment, the arrangement direction of two semiconductor elements 40 connected in series is defined as the X direction. The direction perpendicular to both the Z direction and the X direction is defined as the Y direction. Unless otherwise specified, a shape viewed from the Z direction, in other words a shape along the XY plane defined by the X direction and the Y direction, is defined as a planar shape. The planar view from the Z direction may be simply referred to as a planar view.

[0028] 2, the semiconductor device 20 constitutes one of the above-mentioned upper and lower arm circuits 9, that is, one phase of the upper and lower arm circuits 9. The semiconductor device 20 includes a sealing body 30, a semiconductor element 40, substrates 50 and 60, and a spacer 70. The semiconductor device 20 may be called a semiconductor module, a power card, or the like.

[0029] The encapsulant 30 encapsulates a part of the other elements constituting the semiconductor device 20. The remaining parts of the other elements are exposed to the outside of the encapsulant 30. The encapsulant 30 is made of, for example, a resin. An example of the resin is an epoxy resin. The encapsulant 30 is made of a resin and molded by, for example, a transfer molding method. Such an encapsulant 30 may be called an encapsulating resin body, a molded resin, a resin molded body, or the like. The encapsulant 30 may be formed of, for example, a gel. The gel is filled (placed) in, for example, the opposing regions of the pair of substrates 50, 60.

[0030] The sealing body 30 has a generally rectangular shape in plan view. The sealing body 30 has a lower surface 30a and an upper surface 30b, which is the surface opposite the lower surface 30a in the Z direction, as surfaces forming an outer periphery. The lower surface 30a and the upper surface 30b are, for example, flat surfaces. The sealing body 30 also has a side surface 30c, which is a surface connecting the lower surface 30a and the upper surface 30b.

[0031] The semiconductor element 40 is formed by forming a switching element on a semiconductor substrate made of silicon (Si) or a wide band gap semiconductor with a wider band gap than silicon. Examples of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga2O3), and diamond. The semiconductor element 40 may be called a power element, a semiconductor chip, or the like.

[0032] The semiconductor element 40 of this embodiment is formed by forming the n-channel MOSFET 11 on a semiconductor substrate made of Si. The MOSFET 11 has a vertical structure so that a main current flows in the thickness direction of the semiconductor element 40 (semiconductor substrate), that is, in the Z direction. The semiconductor element 40 has main electrodes of a switching element on both sides in the Z direction, which is the thickness direction of the semiconductor element 40. Specifically, as main electrodes, the semiconductor element 40 has a drain electrode 40D on one side on the lower surface 30a side, and a source electrode 40S on the back side on the upper surface 30b side, which is the opposite side in the Z direction from the one side. The main current flows between the drain electrode 40D and the source electrode 40S.

[0033] When the diode 12 is a parasitic diode, the source electrode 40S also serves as an anode electrode, and the drain electrode 40D also serves as a cathode electrode. The diode 12 may be formed on a chip separate from the MOSFET 11. The drain electrode 40D is a main electrode on the high potential side, and the source electrode 40S is a main electrode on the low potential side.

[0034] The semiconductor element 40 has a generally rectangular shape, for example a square, in plan view. The source electrode 40S is exposed from a protective film (not shown) formed on the rear surface of the semiconductor substrate. The drain electrode 40D is formed on almost the entire surface. The source electrode 40S is formed on a portion of the rear surface of the semiconductor element 40. In plan view, the drain electrode 40D has a larger area than the source electrode 40S. The source electrode 40S corresponds to a first main electrode, and the drain electrode 40D corresponds to a second main electrode.

[0035] The semiconductor device 20 includes a plurality of semiconductor elements 40 having the above-described configuration. The plurality of semiconductor elements 40 includes a semiconductor element 40H constituting the upper arm 9H and a semiconductor element 40L constituting the lower arm 9L. The semiconductor element 40H may be referred to as an upper arm element, and the semiconductor element 40L may be referred to as a lower arm element. The semiconductor element 40 of this embodiment includes one semiconductor element 40H and one semiconductor element 40L.

[0036] In this embodiment, all the semiconductor elements 40 have a common structure. The arrangement of the semiconductor elements 40H and the arrangement of the semiconductor elements 40L have two-fold symmetry around an axis along the Z direction. The semiconductor elements 40H and the semiconductor elements 40L are aligned in the X direction. The semiconductor device 20 has one row of the semiconductor elements 40H and the semiconductor elements 40L aligned in the X direction.

[0037] The semiconductor elements 40 are disposed at approximately the same positions as one another in the Z direction. A drain electrode 40D of each semiconductor element 40 faces the substrate 50. A source electrode 40S of each semiconductor element 40 faces the substrate 60.

[0038] The substrates 50 and 60 are disposed in the Z direction so as to sandwich the semiconductor elements 40H and 40L therebetween. The substrates 50 and 60 are disposed so as to at least partially face each other in the Z direction. The substrates 50 and 60 contain all of the multiple semiconductor elements 40 (40H, 40L) in a plan view.

[0039] The substrate 50 is disposed on the drain electrode 40D side of the semiconductor element 40. The substrate 60 is disposed on the source electrode 40S side of the semiconductor element 40. The substrate 50 is electrically connected to the drain electrode 40D as described below, and provides a wiring function. Similarly, the substrate 60 is electrically connected to the source electrode 40S, and provides a wiring function. For this reason, the substrates 50 and 60 may be referred to as a wiring member, a wiring substrate, etc. The substrate 50 may be referred to as a drain substrate, and the substrate 60 may be referred to as a source substrate.

[0040] The substrates 50 and 60 provide a heat dissipation function for dissipating heat generated by the semiconductor element 40. For this reason, the substrates 50 and 60 are sometimes referred to as heat dissipation members. The substrate 50 corresponds to a first wiring member. The substrate 60 corresponds to a second wiring member electrically connected to the second main electrode.

[0041] The substrate 50 has an opposing surface 50a facing the semiconductor element 40 and an opposing back surface 50b opposite the opposing surface 50a. The substrate 50 includes an insulating base material 51, a front metal body 52, and a back metal body 53. The substrate 60 has an opposing surface 60a facing the semiconductor element 40 and an opposing back surface 60b opposite the opposing surface 60a. The substrate 60 includes an insulating base material 61, a front metal body 62, and a back metal body 63. The substrate 50 is a substrate in which the insulating base material 51 and the metal bodies 52 and 53 are laminated. The substrate 60 is a substrate in which the insulating base material 61 and the metal bodies 62 and 63 are laminated.

[0042] In this embodiment, the opposing back surface 50b is exposed from the lower surface 30a. The opposing back surface 60b is exposed from the upper surface 30b. The opposing back surfaces 50b, 60b are cooled by a cooler (not shown) or by air. This allows heat from the semiconductor element 40 to be dissipated to the outside. In this embodiment, a double-sided heat dissipation structure is adopted in which heat is dissipated from both the opposing back surface 50b and the opposing back surface 60b.

[0043] The insulating substrate 51 electrically separates the front metal body 52 from the back metal body 53. Similarly, the insulating substrate 61 electrically separates the front metal body 62 from the back metal body 63. The insulating substrates 51 and 61 are sometimes called insulating layers. The material of the insulating substrates 51 and 61 is resin or ceramic, which is an inorganic material. For example, epoxy resin or polyimide resin can be used as the resin. For example, Al2O3 (alumina) or Si3N4 (silicon nitride) can be used as the ceramic. When the insulating substrates 51 and 61 are resin, the substrates 50 and 60 are sometimes called metal-resin substrates. When the insulating substrates 51 and 61 are ceramic, the substrates 50 and 60 are sometimes called metal-ceramic substrates.

[0044] The metal bodies 52, 53, 62, 63 are provided as, for example, a metal plate or a metal foil. The metal bodies 52, 53, 62, 63 are formed from a metal material having good electrical and thermal conductivity, such as copper. The front metal body 52 is disposed on the front surface of the insulating substrate 51 in the Z direction. The back metal body 53 is disposed on the back surface of the insulating substrate 51. Similarly, the front metal body 62 is disposed on the front surface of the insulating substrate 61 in the Z direction. The back metal body 63 is disposed on the back surface of the insulating substrate 61.

[0045] The spacer 70 has a substantially rectangular parallelepiped shape having a thickness in the Z direction. The spacer 70 has a first main surface 70a facing the semiconductor element 40 and a second main surface 70b opposite to the first main surface 70a. The spacer 70 is provided, for example, as a metal block. The spacer 70 is formed of a metal material having good electrical conductivity and thermal conductivity, such as copper. For example, C1020-1 / 2H or the like can be used as the spacer 70. In the Z direction, the spacer 70 is provided on the opposite side of the front surface metal body 52 via the semiconductor element 40. The semiconductor element 40 is disposed so as to be sandwiched between the spacer 70 and the front surface metal body 52.

[0046] The drain electrode 40D of the semiconductor element 40 is joined to the surface metal body 52 via a joining member 100. The source electrode 40S of the semiconductor element 40 is joined to the spacer 70 via a joining member 101. The spacer 70 is joined to the surface metal body 62 via a joining member 102. The joining members 100 to 102 are electrically conductive joining members. For example, solder can be used as the joining members 100 to 102. One example of the solder is a multi-element lead-free solder containing Cu, Ni, and the like in addition to Sn. Instead of solder, a sintered joining member such as sintered silver may be used.

[0047] As described above, the semiconductor element 40 is formed from a semiconductor material such as Si. The linear expansion coefficient and Young's modulus are shown below as physical quantities of the semiconductor element 40. The linear expansion coefficient of the semiconductor element 40 is approximately 4 to 5 ppm / K. The Young's modulus of the semiconductor element 40 is approximately 169 GPa. As described above, the spacer 70 is formed from a metal material such as copper. The linear expansion coefficient and Young's modulus are shown below as physical quantities of the spacer 70. The linear expansion coefficient of the spacer 70 is approximately 17.7 ppm / K. The Young's modulus of the spacer 70 is approximately 122 GPa.

[0048] The linear expansion coefficient of the spacer 70 is larger than that of the semiconductor element 40. The Young's modulus of the spacer 70 is smaller than that of the semiconductor element 40. The Young's modulus of the bonding members 100 to 102 is smaller than both the Young's modulus of the spacer 70 and the Young's modulus of the semiconductor element 40.

[0049] As described above, the bonding member 101 is provided between the semiconductor element 40 and the spacer 70. The bonding member 101 is made of a material with a lower Young's modulus than the spacer 70 and the semiconductor element 40, and is therefore the softest of the three and the most susceptible to stress. Since the spacer 70 and the semiconductor element 40 have different linear expansion coefficients, a thermal cycle occurs in the environment in which the semiconductor device 20 is used, and thus a compressive stress is applied to the spacer 70. A tensile stress is applied to the semiconductor element 40. This applies stress to the member sandwiched between the spacer 70 and the semiconductor element 40. In other words, stress is applied to the bonding member 102 sandwiched between the spacer 70 and the semiconductor element 40.

[0050] As described above, the source electrode 40S is provided on the spacer 70 side of the semiconductor element 40. When a thermal cycle occurs in the usage environment of the semiconductor device 20, stress is applied to the bonding member 102 and also to the source electrode 40S. As a result, there is a risk that the bonding member 102 and the source electrode 40S will be damaged.

[0051] Therefore, in this embodiment, the stress applied to the joining member 101 is reduced by lowering the yield stress of the spacer 70. Specifically, the yield stress of the spacer 70 is set lower than a predetermined yield stress by controlling the average crystal grain size of the spacer 70 and the defect density called sub-grain boundary. The predetermined yield stress is, for example, 20 MPa. The predetermined yield stress will be described in detail later.

[0052] In general, the mechanical properties of metals, such as yield stress and hardness, depend on the density of defects in the metal crystals; the lower the defect density, the smaller the mechanical properties. To reduce defect density, the crystal grains should be made as large as possible. Deformation of copper in response to stress is transmitted by the movement of dislocations in the copper crystals. If the defect density in the copper crystals is low, the movement of dislocations due to stress becomes smoother, making deformation easier. Conversely, if the defect density is high, the movement of dislocations is hindered by the defects, making deformation more difficult. In other words, if the yield stress of copper is low, the movement of dislocations due to stress becomes smoother, making deformation easier.

[0053] When a thermal cycle occurs in the semiconductor device 20, the spacer 70 tends to shrink more since the spacer 70 has a larger linear expansion coefficient than the semiconductor element 40. Furthermore, if the spacer 70 has a small yield stress, it tends to deform easily, and tends to deform in accordance with the deformation of the semiconductor element 40. By making the spacer 70 in a state in which the yield stress is small and it is easy to deform, the stress generated by the thermal cycle can be distributed to the deformation of the spacer 70. This can suppress stress concentration on the bonding member 101 and the source electrode 40S. Damage to the bonding member 101 and the source electrode 40S is suppressed.

[0054] FIG. 4 is a graph showing the relationship between the yield stress of the spacer 70 and the strain of the source electrode 40S for each size of the semiconductor element 40. The strain of the source electrode 40S refers to the strain of the source electrode 40S that occurs due to the stress applied to the bonding member 101. Hereinafter, including the drawings, the yield stress of the spacer 70 may be simply referred to as the yield stress. The strain of the source electrode 40S may be simply referred to as the electrode strain. The strain of the source electrode 40S may also be referred to as the second main electrode strain. Graphs relating to the electrode strain and the sizes of two semiconductor elements 40 are shown in FIG. 4.

[0055] Each graph is created by plotting the electrode strain when the yield stress is 200 MPa, 20 MPa, and 10 MPa. 200 MPa corresponds to the default value of the yield stress of the spacer 70. 20 MPa corresponds to a value slightly higher than the yield stress of the joining members 100-102. The yield stress of the joining members 100-102 is about 16 MPa. 10 MPa corresponds to a lower yield stress than the joining members 100-102. In FIG. 4, a plurality of semiconductor devices 20 are used to create the graph. The plurality of semiconductor devices 20 employ spacers 70 each having a different yield stress. The graph is created by plotting the electrode strain corresponding to each spacer 70.

[0056] 4, the electrode distortion is smaller as the yield stress of the spacer 70 is smaller. Regardless of the size of the semiconductor element 40, the electrode distortion when the yield stress is 200 MPa is larger than the electrode distortion when the yield stress is 20 MPa or 10 MPa. Regardless of the size of the semiconductor element 40, the electrode distortion when the yield stress is 10 MPa is smaller than the electrode distortion when the yield stress is 20 MPa or 200 MPa.

[0057] In the range of yield stress from 10 MPa to 200 MPa, the graph value for the larger of the two semiconductor elements 40 is larger than the graph value for the smaller of the two semiconductor elements 40. As an example, the sizes of the two semiconductor elements 40 are 15, 8 mm, and 7 mm in side length.

[0058] In the large-sized semiconductor element 40, the electrode strain when the yield stress is 20 MPa is approximately 4% lower than when the yield stress is 200 MPa. In the large-sized semiconductor element 40, the electrode strain when the yield stress is 10 MPa is approximately 8% lower than when the yield stress is 200 MPa. In the small-sized semiconductor element 40, the electrode strain when the yield stress is 20 MPa is 4% lower than when the yield stress is 200 MPa. In the small-sized semiconductor element 40, the electrode strain when the yield stress is 10 MPa is 12% lower than when the yield stress is 200 MPa.

[0059] Regardless of the size of the semiconductor element 40, the ratio of the difference in electrode strain to the difference in yield stress in the range of 10 MPa to 20 MPa is greater than the ratio of the difference in electrode strain to the difference in yield stress in the range of 20 MPa to 200 MPa. In other words, the slope of the graph in the range of 10 MPa to 20 MPa is greater than the slope of the graph in the range of 20 MPa to 200 MPa. That is, it can be seen that the electrode strain is rapidly reduced when the yield stress is 20 MPa or less, in other words, below a predetermined value. It can be seen that the electrode strain is rapidly reduced when the yield stress is below a predetermined yield stress.

[0060] FIG. 5 is a graph showing the relationship between the yield stress of the spacer 70 and the strain of the bonding members 100-102. FIG. 5 shows a graph for three bonding members 100-102. The bonding member 101 may be referred to as a first bonding member. The bonding member 100 may be referred to as a second bonding member. Each graph is created by plotting the strain of the bonding members 100-102 when the yield stress of the spacer 70 is 200 MPa, 20 MPa, and 10 MPa. In FIG. 5 as well, a plurality of semiconductor devices 20 are used to create the graph. The plurality of semiconductor devices 20 employ spacers 70 each having a different yield stress. The graph is created by plotting the strain of the bonding members 100-102 corresponding to each spacer 70.

[0061] Hereinafter, the strain of the bonding members 100 to 102 may be simply referred to as bonding member strain, including in the drawings. The bonding member strain of the second bonding member 100 hardly changes when the yield stress of the spacer 70 is in the range of 10 MPa to 200 MPa. The bonding member strain of the second bonding member 100 maintains a value of about 0% to 1.0%. The bonding member strain of the bonding members 101 and 102 is smaller as the yield stress of the spacer 70 is smaller. The bonding member strain of the bonding members 101 and 102 is the largest when the yield stress of the spacer 70 is 200 MPa. The bonding member strain of the bonding members 101 and 102 is the smallest when the yield stress of the spacer 70 is 10 MPa. The strain of the bonding member 101 may also be referred to as the first bonding member strain. The strain of the bonding member 100 may also be referred to as the second bonding member strain.

[0062] The ratio of the difference in the strain of the bonding members 101, 102 to the difference in the yield stress in the range of 10 MPa to 20 MPa is larger than the ratio of the difference in the strain of the bonding members 101, 102 to the difference in the yield stress in the range of 20 MPa to 200 MPa. In other words, the slope of the graph in the range of 10 MPa to 20 MPa for the bonding members 101, 102 is larger than the slope of the graph in the range of 20 MPa to 200 MPa for the yield stress. That is, it can be seen that the strain of the bonding members 101, 102 is rapidly reduced when the yield stress of the spacer 70 is 20 MPa or less.

[0063] Fig. 6 is a graph showing the relationship between temperature and yield stress for the joining members 100-102 and the spacer 70. Fig. 6 shows a graph for two spacers 70 with different yield stresses at room temperature, and a graph for the joining members 100-102. The graph for the two spacers 70 was created by plotting the yield stresses at temperatures of room temperature, 100°C, 150°C, and 200°C. Regardless of the magnitude of the yield stress at room temperature, the yield stress decreases as the temperature increases. The yield stress is greatest at room temperature. The yield stress is least at a temperature of 200°C.

[0064] In the temperature range of room temperature to 200 degrees, the value in the graph for the spacer 70 having a yield stress of 20 MPa at room temperature is greater than the value in the graph for the spacer 70 having a yield stress of 10 MPa at room temperature. Also, the yield stress of the joining members 100 to 102 decreases as the temperature increases. The yield stress of the joining members 100 to 102 at room temperature is about 16 MPa. The yield stress of the joining members 100 to 102 at 180 degrees is about 6 MPa. In the temperature range of room temperature to 180 degrees, the yield stress of the spacer 70 having a yield stress of 20 MPa at room temperature is equal to or greater than the yield stress of the joining members 100 to 102. In the temperature range of room temperature to 180 degrees, the yield stress of the spacer 70 having a yield stress of 10 MPa at room temperature is equal to or less than the yield stress of the joining members 100 to 102. It can be seen from FIGS. 4 to 6 that when the yield stress of the spacer 70 is smaller than the yield stress of the joining members 100 to 102, the distortion reduction effect is large.

[0065] <Action and effect> The semiconductor device 20 includes a semiconductor element 40, a substrate 50, a substrate 60, a spacer 70, and bonding members 100 to 102. A drain electrode 40D is provided on one surface of the semiconductor element 40. A source electrode 40S is provided on the back surface of the semiconductor element 40. The substrate 50 is electrically connected to the drain electrode 40D. The substrate 60 is electrically connected to the source electrode 40S. A spacer 70 is provided between the semiconductor element 40 and the substrate 60. A bonding member 101 is provided between the semiconductor element 40 and the spacer 70. The bonding member 101 bonds the spacer 70 and the bonding member 101. When comparing a plurality of spacers 70 with different yield stresses, the bonding member strain of the bonding member 101 is smaller as the yield stress of the spacer 70 is smaller. Furthermore, the ratio of the difference in the bonding member strain to the difference in the yield stress of the spacer 70 below a predetermined yield stress is greater than the ratio of the difference in the bonding member strain to the difference in the yield stress of the spacer 70 above a predetermined yield stress. In the semiconductor device 20 having such a relationship, the yield stress of the spacer 70 of the semiconductor device 20 in this embodiment is smaller than the predetermined yield stress. This reduces the distortion of the bonding material, and the occurrence of damage to the bonding member 101 can be suppressed.

[0066] Moreover, the electrode distortion is smaller as the yield stress of the spacer 70 is smaller. The ratio of the difference in electrode distortion to the difference in yield stress of the spacer 70 below a certain yield stress is greater than the ratio of the difference in electrode distortion to the difference in yield stress of the spacer 70 above the certain yield stress. In the semiconductor device 20 having such a relationship, the yield stress of the spacer 70 of the semiconductor device 20 in this embodiment is smaller than the certain yield stress. According to this, even if stress is concentrated on the source electrode 40S due to the thermal cycle, the same action as above works, so that the stress can be dispersed to the deformation of the spacer 70. As a result, damage to the source electrode 40S can be suppressed.

[0067] Furthermore, the yield stress of the bonding members 100-102 is smaller than a predetermined yield stress. The yield stress of the spacer 70 is smaller than the yield stress of the bonding members 100-102. Since the yield stress of the spacer 70 is smaller than the predetermined yield stress, the bonding material distortion and the electrode distortion are reduced. As a result, damage to the bonding member 101 and the source electrode 40S can be effectively suppressed.

[0068] A bonding member 100 is provided between the substrate 50 and the semiconductor element 40. The bonding member 100 bonds the substrate 50 and the semiconductor element 40. The ratio of the difference in strain in the bonding member 101 to the difference in yield stress of the spacer 70 is greater than the ratio of the difference in strain in the bonding member 100 to the difference in yield stress of the spacer 70. The bonding member 101 is easily affected by stress due to thermal cycles, and stress is easily concentrated on the bonding member 101. In such a semiconductor device 20, reducing the yield stress of the spacer 70 is effective in reducing stress concentration on the bonding member 101. Second embodiment

[0069] In the first embodiment, a double-sided heat dissipation structure in which heat is dissipated from both the opposing back surface 50b and the opposing back surface 60b has been described. However, the heat dissipation structure is not limited to the double-sided heat dissipation structure. In a second embodiment, the semiconductor device 20 may have a single-sided cooling structure in which heat is dissipated to the outside from only one of the opposing back surface 50b and the opposing back surface 60b. Third embodiment

[0070] In the first and second embodiments, the spacer 70 is made of copper. However, the material of the spacer 70 is not limited to copper. The spacer 70 may be a composite material of copper and a metal material having a linear expansion coefficient lower than that of copper. Even in this case, the effects of the above embodiments can be obtained as long as the yield stress of the spacer 70 is equal to or lower than a predetermined yield stress.

[0071] Although the present disclosure has been described based on the embodiment, it is understood that the present disclosure is not limited to the embodiment or structure. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, although various combinations and forms are shown in the present disclosure, other combinations and forms including only one element, more than one, or less than one element are also within the scope and concept of the present disclosure. [Explanation of symbols]

[0072] 100 second bonding member, 101 bonding member, 40 semiconductor element, 40D first main electrode, 40S second main electrode, 50 first wiring member, 60 second wiring member, 70 spacer.

Claims

1. A semiconductor element (40) having a first main electrode (40D) provided on one surface and a second main electrode (40S) provided on a back surface opposite to the one surface in a plate thickness direction; a first wiring member (50) electrically connected to the first main electrode; a second wiring member (60) electrically connected to the second main electrode; a conductive spacer (70) provided between the semiconductor element and the second wiring member; a bonding member (101) provided between the semiconductor element and the spacer and bonding the semiconductor element and the spacer, When comparing a plurality of spacers having different yield stresses, a smaller yield stress of the spacer results in a smaller bonding member strain, which is a strain of the bonding member, and a ratio of a difference in the bonding member strain to a difference in the yield stress of the spacer at or below a predetermined yield stress is greater than a ratio of a difference in the bonding member strain to a difference in the yield stress of the spacer at or above the predetermined yield stress, The semiconductor device, wherein the yield stress of the spacer is less than the predetermined yield stress.

2. 2. The semiconductor device according to claim 1, wherein the smaller the yield stress of the spacer, the smaller the second main electrode distortion, which is the distortion of the second main electrode, and the ratio of the difference in the second main electrode distortion to the difference in the yield stress of the spacer below the specified yield stress is greater than the ratio of the difference in the second main electrode distortion to the difference in the yield stress of the spacer above the specified yield stress.

3. the yield stress of the joining member is smaller than the predetermined yield stress, 3. The semiconductor device according to claim 1, wherein the yield stress of the spacer is smaller than the yield stress of the bonding member.

4. 4. The semiconductor device according to claim 3, wherein the semiconductor element and the spacer have a different linear expansion coefficient.

5. In addition to the first joining member, which is the joining member, a second joining member (100) is further included, the second bonding member is provided between the first wiring member and the semiconductor element and bonds the first wiring member and the semiconductor element; The semiconductor device according to claim 4, wherein a ratio of a first bonding member strain difference, which is the strain of the first bonding member, to the difference in the yield stress of the spacer is greater than a ratio of a second bonding member strain difference, which is the strain of the second bonding member, to the difference in the yield stress of the spacer.

6. 6. The semiconductor device according to claim 5, wherein the spacer is a composite material of copper and a metal material having a linear expansion coefficient lower than that of the copper.

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