Wiring board

Abstract

To provide a wiring board where deterioration of connection reliability is suppressed.SOLUTION: A wiring board of an embodiment comprises: insulation layers 21 to 26 and conductive layers 11 to 18; and via conductor groups 41G to 43G that connect the conductive layers 11 to 18 nipping the insulation layers 21 to 26 so as to penetrate the insulation layers 21 to 26. The via conductor groups 41G to 43G contain a plurality of via conductors 41a to 43a and 41b to 43b that are arranged in a two-dimentional arrangement in a plan view, and a lower part of the via conductors 41a, 42a, 43a, 41b, 42b, and 43b are connected to conductor pads 17a, 11a, 12a, 17b, 11b, and 12b contained in the conductor layers 17, 11, and 12. The via conductor groups 41G to 43G are constructed from inside via conductors 41a to 43a and outside via conductors 41b to 43b. The outside via conductors 41b to 43b contain a dummy via conductor DV that is separated from a wiring for transmitting a signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a wiring board. [Background technology]

[0002] Patent Document 1 discloses a wiring board including insulating layers and conductor layers that are alternately laminated, and a plurality of via conductors that penetrate the insulating layers and connect the conductor layers that sandwich the insulating layers together. The via conductors are arranged in a lattice pattern. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2015-76567 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the wiring board disclosed in Patent Document 1, discoloration may occur at the bottom of the via conductors arranged in the outer region of the via conductor group. A discolored via conductor may have a lower connection reliability with other conductors connected thereto, compared to a non-discolored via conductor. [Means for solving the problem]

[0005] The wiring board of the present invention includes insulating layers and conductor layers that are alternately stacked, and a via conductor group that penetrates the insulating layer to connect the conductor layers sandwiching the insulating layer. The via conductor group includes a plurality of via conductors arranged in a two-dimensional array in a plan view, and lower portions of the plurality of via conductors are connected to a plurality of conductor pads included in the conductor layer. The via conductor group includes inner via conductors arranged in an inner region of the two-dimensional array, and outer via conductors arranged in an outer region of the two-dimensional array and surrounding the inner via conductors. The outer via conductors include dummy via conductors that are separated from wiring that transmits signals and are included in the conductor layer.

[0006] According to the embodiments of the present invention, it is believed that a decrease in connection reliability is suppressed in a wiring board including a group of via conductors arranged in a two-dimensional array. [Brief description of the drawings]

[0007] [Figure 1] FIG. 1 is a cross-sectional view showing an example of a wiring board according to an embodiment of the present invention. [Figure 2A] 2 is a plan view showing an example of a two-dimensional arrangement of via conductor groups in each insulating layer of the wiring board of FIG. 1. [Figure 2B] 1. FIG. 4 is a plan view showing another example of a two-dimensional array of via conductor groups in each insulating layer of the wiring board of FIG. [Diagram 3] An enlarged view of part III in Fig. 1 . [Figure 4A] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 4B] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 4C] 5A to 5C are enlarged cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 4D] 5A to 5C are enlarged cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 4E] 5A to 5C are enlarged cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 4F] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. [Figure 4G] 1A to 1C are cross-sectional views showing an example of a method for manufacturing a wiring board according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] A wiring board according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a wiring board 100, which is an example of a wiring board according to an embodiment. FIG. 2A shows a plan view showing an example of a two-dimensional arrangement of a via conductor group in each insulating layer in the wiring board 100 of FIG. 1, and FIG. 2B shows a plan view showing another example of a two-dimensional arrangement of a via conductor group in each insulating layer in the wiring board 100 of FIG. 1. FIG. 3 shows an enlarged view of part III in FIG. 1. Note that the wiring board 100 is merely an example of the wiring board according to the present embodiment. The laminated structure of the wiring board according to the embodiment, and the number of each of the conductor layers and the insulating layers included in the wiring board 100 are not limited to the laminated structure of the wiring board 100 of FIG. 1, and the number of each of the conductor layers and the insulating layers included in the wiring board 100.

[0009] As shown in FIG. 1, the wiring board 100 includes a core board 3, conductor layers 11-16, and insulating layers 21-26. The core board 3 includes a core insulating layer 30, a conductor layer 17 formed on a first surface 30F of the core insulating layer 30, and a conductor layer 18 formed on a second surface 30B of the core insulating layer 30. On the first surface 30F side of the core insulating layer 30, an insulating layer 21, a conductor layer 11, an insulating layer 22, a conductor layer 12, an insulating layer 23, and a conductor layer 13 are laminated in this order on the core board 3. On the other hand, on the second surface 30B side of the core insulating layer 30, an insulating layer 24, a conductor layer 14, an insulating layer 25, a conductor layer 15, an insulating layer 26, and a conductor layer 16 are laminated in this order on the core board 3. The wiring board of the embodiment may include one or more pairs of two conductor layers facing each other and one or more insulating layers interposed between the two opposing conductor layers.

[0010] A through-hole conductor 33 is formed in the core insulating layer 30 to connect the conductor layer 17 and the conductor layer 18. The through-hole conductor 33 has a cylindrical shape that fits along the inner wall of the through hole 30a of the core insulating layer 30. The through-hole conductor 33 may be formed of, for example, a metal film. The cavity 33a of the through-hole conductor 33 is filled with a resin 4 such as an epoxy resin.

[0011] In the description of the embodiment, the side of the wiring board 100 farther from the core insulating layer 30 in the thickness direction is also referred to as the "outside", "upper side" or "upper", or simply "upper", and the side closer to the core insulating layer 30 is also referred to as the "inside", "lower side" or "lower", or simply "lower". Furthermore, in each conductor layer and the conductor pattern contained in each conductor layer, and in each insulating layer, the surface facing the side opposite the core insulating layer 30 is also referred to as the "upper surface", and the surface facing the core insulating layer 30 is also referred to as the "lower surface". The thickness direction of the wiring board 100 is also referred to as the "Z direction".

[0012] A solder resist 5 is formed on the conductor layer 13 and the insulating layer 23. A solder resist 5 is also formed on the conductor layer 16 and the insulating layer 26. The solder resist 5 has an opening that exposes a part of the conductor layer 13 or a part of the conductor layer 16, respectively.

[0013] The wiring board 100 further includes a plurality of via conductors 41a to 43a, 41b to 43b, 41c to 43c, and 44 to 46. The via conductors 41a, 41b, and 41c each penetrate the insulating layer 21 to connect the conductor layer 17 and the conductor layer 11 that sandwich the insulating layer 21. Similarly, the via conductors 42a, 42b, and 42c each penetrate the insulating layer 22 to connect the conductor layer 12 and the conductor layer 11 that sandwich the insulating layer 22, and the via conductors 43a, 43b, and 43c each penetrate the insulating layer 23 to connect the conductor layer 13 and the conductor layer 12 that sandwich the insulating layer 23. Similarly, the via conductors 44, 45, and 46 each penetrate the insulating layers 24, 25, and 26 to connect the conductor layers 18, 14, and 15 that sandwich the insulating layers 24, 25, and 26 to the conductor layers 14, 15, and 16 that sandwich the insulating layers 24, 25, and 26.

[0014] Each of the insulating layers 21 to 26 has a through hole 6 penetrating the insulating layer, and each via conductor is formed in the through hole 6 penetrating the insulating layer. The through hole 6 penetrating the insulating layer 21 is filled with via conductors 41a, 41b, and 41c, the through hole 6 penetrating the insulating layer 22 is filled with via conductors 42a, 42b, and 42c, and the through hole 6 penetrating the insulating layer 23 is filled with via conductors 43a, 43b, and 43c. Similarly, the through holes 6 penetrating the insulating layers 24, 25, and 26 are filled with via conductors 44, 45, and 46, respectively.

[0015] The via conductors 41a to 43a, 41b to 43b, 41c to 43c, and 44 to 46 each protrude from one of two opposing conductor layers and contact the other. The via conductors 41a, 41b, and 41c are formed integrally with the conductor layer 11. The via conductors 42a, 42b, and 42c are formed integrally with the conductor layer 12. The via conductors 43a, 43b, and 43c are formed integrally with the conductor layer 13. Similarly, the via conductors 44, 45, and 46 are formed integrally with the conductor layers 14, 15, and 16, respectively.

[0016] The core insulating layer 30 and the insulating layers 21 to 26 are formed of any insulating resin. Examples of insulating resins include epoxy resin, bismaleimide triazine resin (BT resin), and phenol resin. In the example of Fig. 1, the core insulating layer 30 includes a core material (reinforcing material) 34 formed of glass fiber, aramid fiber, or the like. Each insulating layer may further include a filler (not shown) made of particles such as silicon dioxide or alumina.

[0017] The conductor layers 11-18, the through-hole conductor 33, and the via conductors 41a-43a, 41b-43b, 41c-43c, and 44-46 may be formed using any metal such as copper or nickel. In the example of Fig. 1, the conductor layers 11-18, and the via conductors 41a-43a, 41b-43b, 41c-43c, and 44-46 each have a two-layer structure including a first metal film 4a (see Figs. 4B, 4F, and 4G) and a second metal film 4b (see Figs. 4B, 4F, and 4G) formed on the first metal film 4a. The first metal film 4a constituting the via conductors 41a-43a, 41b-43b, 41c-43c, and 44-46 is formed directly on the inner wall of the through hole 6.

[0018] The first metal film 4a (see Figs. 4B, 4F, and 4G) is formed by, for example, electroless plating. The second metal film 4b (see Figs. 4B, 4F, and 4G) is, for example, an electrolytic plating film formed by electrolytic plating using the first metal film 4a as a power supply layer. The through-hole conductor 33 also has a two-layer structure including an electroless plating film and an electrolytic plating film. On the other hand, the conductor layer 17 and the conductor layer 18 have a three-layer structure further including a metal foil (see Fig. 4A).

[0019] Each of the conductor layers 11 to 18 includes an arbitrary conductor pattern. In the example of Fig. 1, for example, the conductor layer 11 includes a conductor pattern 110, the conductor layer 12 includes a conductor pattern 120, and the conductor layer 13 includes a conductor pattern 130. The conductor layer 14 includes a conductor pattern 140, the conductor layer 15 includes a conductor pattern 150, and the conductor layer 16 includes a conductor pattern 160. The conductor layer 17 includes a conductor pattern 170, and the conductor layer 18 includes a conductor pattern 180.

[0020] Conductive patterns 110, 120, 130 of conductor layers (upper conductor layers) 11, 12, 13 respectively include conductor pads 11a, 12a, 13a which are so-called via lands (via pads) of via conductors 41a, 42a, 43a, conductor pads 11b, 12b, 13b which are via lands of via conductors 41b, 42b, 43b, and conductor pads 11c, 12c, 13c which are via lands of via conductors 41c, 42c, 43c. Conductive patterns 170, 110, 120 of the conductor layers (lower conductor layers) 17, 11, 12 respectively include conductor pads 17a, 11a, 12a which are so-called receiving pads for via conductors 41a, 42a, 43a, conductor pads 17b, 11b, 12b which are receiving pads for via conductors 41b, 42b, 43b, and conductor pads 17c, 11c, 12c which are receiving pads for via conductors 41c, 42c, 43c.

[0021] The conductor pad 13a may also be a connection pad. An electrode Ea of an electronic component E may be connected to the conductor pad 13a. The electronic component E may be, for example, an active component such as a semiconductor integrated circuit device or a transistor, or a passive component such as an electric resistor.

[0022] 1, 2A, and 2B, in a wiring board 100 according to an example of an embodiment, the multiple via conductors include via conductor groups 41G, 42G, and 43G arranged in a two-dimensional array in a plan view in each of insulating layers 21, 22, and 23. Here, "plan view" refers to a view of the wiring board 100 along the Z direction. In addition, in FIGS. 2A and 2B, any one of the via conductor groups 41G, 42G, and 43G is shown as "via conductor group 40G."

[0023] As shown in Fig. 1, Fig. 2A, and Fig. 2B, the via conductor groups 41G, 42G, and 43G are each composed of an inner via conductor arranged in an inner region A1 of the two-dimensional arrangement in the insulating layers 21, 22, and 23, and an outer via conductor arranged in an outer region A2 of the two-dimensional arrangement and surrounding the inner via conductor. Specifically, the via conductor group 41G is composed of an inner via conductor 41a arranged in the inner region A1 of the two-dimensional arrangement, and an outer via conductor 41b arranged in the outer region A2 of the two-dimensional arrangement. Similarly, the via conductor group 42G is composed of an inner via conductor 42a and an outer via conductor 42b, and the via conductor group 43G is composed of an inner via conductor 43a and an outer via conductor 43b. In Fig. 2A and Fig. 2B, the inner via conductor constituting the "via conductor group 40G" is shown as the "inner via conductor 40a", and the outer via conductor constituting the "via conductor group 40G" is shown as the "outer via conductor 40b".

[0024] Here, the two-dimensional array refers to an array of a group of via conductors arranged in two dimensions in one insulating layer in a denser state than other via conductors. As shown in FIG. 2A and FIG. 2B, a two-dimensional array is typically an array of a group of via conductors arranged in two dimensions at regular intervals. In the example of FIG. 2A, the via conductors 40a, 40b constituting the via conductor group 40G are arranged in a lattice (specifically, a lattice of 6 rows x 6 columns). In the example of FIG. 2B, the via conductors 40a, 40b constituting the via conductor group 40G are arranged in a staggered pattern (specifically, a staggered pattern in which seven via conductors arranged in the row direction and six via conductors arranged in the row direction are alternately arranged in seven rows in the column direction). When the via conductors 40a, 40b are arranged in a regular two-dimensional array such as a lattice or staggered pattern, it may be easier to arrange the via conductors 40a, 40b densely.

[0025] 2A and 2B, the via conductor group 40G may be arranged in any pattern other than a lattice pattern or a staggered pattern, as long as the inner via conductors 40a and the outer via conductors 40b can be defined. For example, the two-dimensional arrangement of the via conductor group 40G may be an arrangement of a group of via conductors 40a, 40b that are irregularly arranged in two dimensions, rather than regularly.

[0026] As shown in Fig. 3, in the via conductor groups 41G, 42G, and 43G having such a two-dimensional arrangement, discolored portions 4c may occur at the bottom of the outer via conductors 41b, 42b, and 43b (the via conductor group 43G and the outer via conductor 43b are not shown in Fig. 3). In particular, when the via conductors constituting each via conductor group are arranged at high density, for example, when the center-to-center distance G (see Figs. 2A and 2B) of the via conductors constituting each via conductor group is 150 μm or less, it is assumed that the discolored portions 4c are likely to occur. The discolored portions 4c may increase the connection resistance between the outer via conductors 41b, 42b, and 43b and the conductor pads 17b, 11b, and 12b (the conductor pad 12b is not shown in Fig. 3), which are receiving pads for the outer via conductors, and may reduce the connection reliability between the outer via conductors 41b, 42b, and 43b and the conductor pads 17b, 11b, and 12b.

[0027] As shown in Fig. 3, the discolored portion 4c is considered to be formed at the connection portion (lower portion) of the outer via conductors 41b, 42b, 43b (the outer via conductor 43b is not shown in Fig. 3) with the conductor pads 17b, 11b, 12b when the outer via conductors 41b, 42b, 43b are formed. Specifically, when the first metal film 4a constituting the lower portion of the outer via conductors 41b, 42b, 43b is formed by electroless plating, the discolored portion 4c is considered to be formed at the connection portion (lower portion) of the first metal film 4a with the conductor pads 17b, 11b, 12b (the conductor pad 12b is not shown in Fig. 3) when the first metal film 4a is formed by electroless plating. On the other hand, the discolored portion 4c is unlikely to be formed in the inner via conductors 41a, 42a, 43a (the inner via conductor 43a is not shown in Fig. 3). Considering the locations where discolored portion 4c occurs, it is assumed that discolored portion 4c is formed in locations where the density of the surrounding via conductors changes suddenly, for example, due to an excess or deficiency of the constituent material of the via conductor (the reactive species that precipitate copper when the first metal film 4a is formed of copper by electroless plating).

[0028] As shown in FIG. 1, in the wiring board 100 of the embodiment, the outer via conductors 41b, 42b, and 43b include dummy via conductors DV that are separated from the wiring (hereinafter, also referred to as "signal wiring") that transmits signals and is included in the conductor layers 11 to 18. That is, the dummy via conductors DV are not connected to the signal wiring. In the example of FIG. 1, the outer via conductors 41b, 42b, and 43b at the left and right ends of each of the via conductor groups 41G, 42G, and 43G arranged in six rows on the paper are all dummy via conductors DV that are separated from the signal wiring. If the dummy via conductors DV are separated from the signal wiring, the dummy via conductors DV, which are concerned about a decrease in connection reliability due to the formation of the discolored portion 4c, are not involved in the connection of the signal wiring, and therefore the decrease in connection reliability of the signal wiring is suppressed. Furthermore, when the dummy via conductor DV is separated from the signal wiring, the dummy via conductor DV, which is a concern as it may increase the connection resistance due to the formation of discolored portion 4c, does not contribute to the conductivity of the signal wiring, and it is therefore believed that voltage drops and transmission delays in the signals transmitted by the signal wiring are suppressed.

[0029] In the example of FIG. 1, the via conductor groups 41G, 42G, and 43G overlap with the component mounting area AE on which the electronic component E is mounted in a plan view. When the via conductor groups 41G, 42G, and 43G overlap with the component mounting area AE in a plan view, the conductor layers 11, 12, 13, and 17 and the electronic component E can be easily connected via the conductor pad 13a in the shortest distance. The inner area A1 of the via conductor groups 41G, 42G, and 43G may be substantially the same as the component mounting area AE in a plan view. When the inner area A1 of the via conductor groups 41G, 42G, and 43G is substantially the same as the component mounting area AE in a plan view, for example, by designing the inner via conductors 41a, 42a, and 43a, which are unlikely to form discolored portions 4c (see FIG. 3), as signal wiring, the inner via conductors 41a, 42a, and 43a constituting the signal wiring and the electronic component E can be easily connected via the conductor pad 13a in the shortest distance. It is believed that when the electronic component E is connected to the inner via conductors 41a, 42a, and 43a as signal wirings at the shortest distance, the occurrence of voltage drops and transmission delays in signals transmitted by the signal wirings is further suppressed.

[0030] The dummy via conductors DV included in the outer via conductors 41b, 42b, and 43b are preferably also separated from the wiring to which a ground potential is applied (hereinafter also referred to as "ground wiring") and the wiring to which a power supply potential is applied (hereinafter also referred to as "power supply wiring") included in the conductor layers 11 to 18. That is, the dummy via conductors DV are not connected to the ground wiring and the power supply wiring. Here, the "ground potential" is a constant potential that serves as a reference in the electronic component E connected to the wiring board 100, and the "power supply potential" is a constant potential different from the ground potential that is applied to drive the electronic component E connected to the wiring board 100. In the example of FIG. 1, the outer via conductors 41b, 42b, and 43b at the left and right ends of the via conductor groups 41G, 42G, and 43G arranged in six rows on the paper are all dummy via conductors DV that are also separated from the ground wiring and the power supply wiring. If the dummy via conductor DV is also separated from the ground wiring and the power wiring, the dummy via conductor DV is not involved in the connection of the ground wiring and the power wiring, and therefore it is considered that the decrease in the connection reliability of the ground wiring and the power wiring is suppressed. In addition, if the dummy via conductor DV is also separated from the ground wiring and the power wiring, the dummy via conductor DV, which is concerned about an increase in connection resistance due to the formation of the discolored portion 4c, is not involved in the conductivity of the ground wiring and the power wiring, and therefore it is considered that the ground potential and the power potential in the wiring board 100 are prevented from becoming unstable due to a change in the connection resistance. As a result, it is considered that the driving of the electronic component E is also prevented from becoming unstable.

[0031] As shown in Fig. 2A and Fig. 2B, the boundary between the inner region A1 and the outer region A2 of the two-dimensional array in the via conductor group 40G can be appropriately changed in response to the change in the outer region A2 where discoloration 4c (see Fig. 3) is likely to occur due to the arrangement of the two-dimensional array of the via conductor group 40G and / or the density of the two-dimensional array. For example, in the example of Fig. 2A, the region inside the virtual line LA1 may be the inner region A1 of the two-dimensional array, and the region inside the virtual line LA2 may be the inner region A1 of the two-dimensional array. When the region inside the virtual line LA1 is the inner region A1 of the two-dimensional array, the region between the virtual line LA1 and the virtual line LA3 becomes the outer region A2 of the two-dimensional array. That is, in this case, the outer region A2 is the region of the two outer circumferences of the two-dimensional array, and the regions of the two outer columns in the column direction and the two outer rows in the row direction of the two-dimensional array. When the area inside the virtual line LA2 is the inner area A1 of the two-dimensional array, the area between the virtual lines LA2 and LA3 is the outer area A2 of the two-dimensional array. That is, in this case, the outer area A2 is the outermost area of ​​the two-dimensional array, and is the area of ​​one column on both outer sides in the column direction and one row on both outer sides in the row direction of the two-dimensional array.

[0032] Similarly, in the example of Fig. 2B, the area inside the virtual line LB1 may be the inner area A1 of the two-dimensional array, the area between the virtual line LB1 and the virtual line LB3 may be the outer area A2 of the two-dimensional array, and the area inside the virtual line LB2 may be the inner area A1 of the two-dimensional array, and the area between the virtual line LB2 and the virtual line LB3 may be the outer area A2 of the two-dimensional array. When the area inside the virtual line LB1 is the inner area A1 of the two-dimensional array, the outer area A2 is the area of ​​both outer two columns in the column direction and both outer one row in the row direction of the two-dimensional array, and when the area inside the virtual line LB2 is the inner area A1 of the two-dimensional array, the outer area A2 is the outermost area of ​​the two-dimensional array, and is the area of ​​both outer one column in the column direction and both outer one row in the row direction of the two-dimensional array.

[0033] As an example, the number of the nearest via conductors of the outer via conductor 40b may be defined to be less than the number of the nearest via conductors of the inner via conductor 40a. Specifically, in the example of FIG. 2A, the region inside the virtual line LA2 is the inner region A1 of the two-dimensional array, and the via conductors in that region are the inner via conductors 40a (the number of nearest conductor pads is four). In this case, the region between the virtual line LA2 and the virtual line LA3 is the outer region A2 of the two-dimensional array, and the via conductors in that region are the outer via conductors 40b (the number of nearest conductor pads is two or three). Also, in the example of FIG. 2B, the region inside the virtual line LB1 is the inner region A1 of the two-dimensional array, and the via conductors in that region are the inner via conductors 40a (the number of nearest conductor pads is six). In this case, the region between the imaginary lines LB1 and LB3 is the outer region A2 of the two-dimensional array, and the via conductors in that region are the outer via conductors 40b (the number of nearest conductor pads is five, three, or two).

[0034] The dummy via conductors DV may be all the outer via conductors 40b in the outer region A2, or may be some of the outer via conductors 40b in the outer region A2. As described above, the discolored portion 4c (see FIG. 3) that may occur in the outer via conductors 40b is likely to occur at a location where the density of the surrounding via conductors changes abruptly. Therefore, as shown in FIG. 2A and FIG. 2B, it is preferable that the dummy via conductors DV include at least the outer via conductors 40b arranged at the corners of the outer region A2, which are the locations where the density of the via conductors changes most abruptly. If the dummy via conductors DV include the outer via conductors 40b at the corners of the outer region A2, it is likely to prevent the formation of the discolored portion 4c from causing a decrease in the connection reliability of signal wiring and the like.

[0035] As shown in FIG. 1, in the wiring board 100 of the embodiment, the inner via conductor 41a, the inner via conductor 42a, and the inner via conductor 43a are stacked in the Z direction and overlap each other in a plan view. That is, the inner via conductor 41a, the inner via conductor 42a, and the inner via conductor 43a form a stacked via conductor. Similarly, the outer via conductor 41b, the outer via conductor 42b, and the outer via conductor 43b form a stacked via conductor. That is, in the wiring board 100 of the embodiment, the two-dimensional arrangement of the via conductor groups 41G, 42G, and 43G is the same, and the positions of the inner via conductors 41a, 42a, and 43a and the outer via conductors 41b, 42b, and 43b forming the via conductor groups 41G, 42G, and 43G in the insulating layers 21, 22, and 23 are also the same. The two-dimensional arrangements of the via conductor groups 41G, 42G, and 43G may not be the same, and may be different from each other.

[0036] 3, the dummy via conductors DV (outer via conductor 43b is not shown), which are outer via conductors 41b, 42b, 43b in which discoloration portion 4c may occur, may be formed as a group of via conductors (stacked via conductors in the example of FIG. 3) connected to each other in the Z direction. When the dummy via conductors DV are formed as a group of via conductors, the positions of the dummy via conductors DV that are not involved in the connection of signal wiring or the like in the insulating layers 21, 22, 23 are different in each of the insulating layers 21, 22, 23, which is considered to suppress an increase in the occupied area of ​​each of the via conductor groups 41G, 42G, 43G in the insulating layers 21, 22, 23.

[0037] Next, a method for manufacturing a wiring board according to an embodiment will be described with reference to Figures 4A to 4G using the wiring board 100 of Figure 1 as an example. Each component formed in the manufacturing method described below can be formed using a material exemplified as the material of the corresponding component in the description of the wiring board 100 of Figure 1, unless otherwise specified.

[0038] As shown in Fig. 4A, a core substrate 3 is prepared. In preparing the core substrate 3, first, a substrate (starting substrate) including a core insulating layer 30 and metal foils 1a laminated on both sides of the core insulating layer 30 is prepared. The core insulating layer 30 is formed of any insulating resin such as epoxy resin, BT resin, or phenol resin. In the illustrated example, the core insulating layer 30 includes a core material 34. For example, a double-sided copper-clad laminate may be prepared as the starting substrate.

[0039] Next, a through hole 30a penetrating the core insulating layer 30 and the metal foil 1a is formed by laser processing or the like. After that, a first metal film 1b is formed on the entire surface of the metal foil 1a opposite to the core insulating layer 30, the end face exposed toward the through hole 30a, and the inner wall of the through hole 30a. The first metal film 1b is formed, for example, of an electroless plating film and an electrolytic plating film.

[0040] By forming the first metal film 1b, a through-hole conductor 33 is formed in the through hole 30a, the through-hole conductor 33 being made of the first metal film 1b and having a cavity 33a in the center. The metal foil 1a and the first metal film 1b are laminated in order on the first surface 30F and the second surface 30B of the core insulating layer 30, respectively. After the resin 4 is filled in the cavity 33a and solidified, the second metal film 1c is formed on the entire surface of the first surface 30F side and the second surface 30B side of the core insulating layer 30. The second metal film 1c may be formed of an electroless plating film and an electrolytic plating film, similar to the first metal film 1b.

[0041] Next, unnecessary portions of the metal foil 1a, the first metal film 1b, and the second metal film 1c are removed, for example, by etching. As a result, a core substrate 3 is obtained that includes the conductor layers 17 and 18, which include the conductor patterns 170 and 180, respectively. The conductor layers 17 and 18 include conductor pads 17d and 18d that close the cavity 33a, respectively. The conductor layer 17 also includes conductor pads 17a and 17b to be connected to the inner via conductor 41a and the outer via conductor 41b (see FIG. 4B) included in the via conductor group 41G, respectively, and a conductor pad 17c to be connected to the via conductor 41c. In the illustrated example, the conductor pad 17b is formed without being connected to the other conductor patterns 170 and the through-hole conductor 33 included in the conductor layer 17.

[0042] As shown in FIG. 4B, an insulating layer 21 is formed on the core substrate 3 on the first surface 30F side of the core insulating layer 30, and an insulating layer 24 is formed on the core substrate 3 on the second surface 30B side of the core insulating layer 30. Thereafter, a conductor layer 11 including a conductor pattern 110 is formed on the insulating layer 21, and an inner via conductor 41a, an outer via conductor 41b, and a via conductor 41c are formed in the insulating layer 21. A conductor layer 14 including a conductor pattern 140 is formed on the insulating layer 24, and a via conductor 44 is formed in the insulating layer 24. The conductor layer 11, the inner via conductor 41a, the outer via conductor 41b, and the via conductor 41c, as well as the conductor layer 14 and the via conductor 44 are formed using any metal such as copper or nickel by a semi-additive method, as described below.

[0043] As shown in Fig. 4B, an inner via conductor 41a connected to a conductor pad 17a of the conductor layer 17 is formed integrally with a conductor pad (via pad) 11a, and an outer via conductor 41b connected to a conductor pad 17b of the conductor layer 17 is formed integrally with a conductor pad (via pad) 11b. In the example of Fig. 4B, the conductor pad 11b is formed without being connected to other conductor patterns 110 included in the conductor layer 11. That is, the outer via conductor 41b formed integrally with the conductor pad 11b is formed as a dummy via conductor DV. Similar to the inner via conductor 41a and the outer via conductor 41b, another via conductor 41c connected to a conductor pad 17c of the conductor layer 17 is formed integrally with a conductor pad 11c (via pad).

[0044] Details of the manufacturing process shown in Fig. 4B are shown in Fig. 4C to Fig. 4E, which are enlarged views of part IV in Fig. 4B. Note that Fig. 4C to Fig. 4E show the formation of insulating layer 21 on the first surface 30F side of core insulating layer 30 and the formation of conductor layer 11 on insulating layer 21, but do not show the formation of insulating layer 24 on the second surface 30B side of core insulating layer 30 and the formation of conductor layer 14 on insulating layer 24.

[0045] First, as shown in FIG. 4C, the insulating layer 21 is formed. In forming the insulating layer 21, for example, a film-like epoxy resin is laminated on the core substrate 3 on the first surface 30F side of the core insulating layer 30, and heated and pressurized. As a result, the insulating layer 21 is formed. In the insulating layer 21, the through holes 6a and 6b for forming the inner via conductors 41a and the outer via conductors 41b (see FIG. 4B) included in the via conductor group 41G are formed by, for example, irradiation with a carbon dioxide laser beam. After the through holes 6a and 6b are formed, a desmearing process may be performed to remove resin residues (smears) generated by the formation of the through holes 6a and 6b. For example, the smears in 6a and 6b are removed by exposing the inner walls of 6a and 6b to a treatment liquid such as an alkaline permanganate solution.

[0046] Next, as shown in Fig. 4D, a first metal film 4a is formed by electroless plating on the surface of the insulating layer 21 and the inner walls of the through holes 6a, 6b. At that time, a discolored portion 4c may occur in the lower portion of the first metal film 4a that becomes the outer via conductor 41b (see Fig. 4B) connected to the conductor pad 17b.

[0047] Next, as shown in FIG. 4E, a plating resist R having openings corresponding to the formation regions of the conductor patterns 110 to be included in the conductor layer 11, such as the conductor pads 11a and 11b (see FIG. 4B), is provided on the first metal film 4a on the insulating layer 21. Then, a second metal film 4b is formed in the through holes 6a and 6b by electrolytic plating using the first metal film 4a as a power supply layer. After the plating resist R is removed, unnecessary parts of the first metal film 4a exposed by removing the plating resist R are removed by, for example, etching. As a result, as shown in FIG. 4B, the conductor layer 11 including the conductor patterns 110, such as the conductor pads 11a and 11b, is formed. An inner via conductor 41a and an outer via conductor 41b are formed in the through holes 6a and 6b.

[0048] In a similar manner to that described with reference to Figures 4C to 4E, on the second surface 30B side of the core insulating layer 30, an insulating layer 24 is formed on the core substrate 3, a conductor layer 14 including a conductor pattern 140 is formed on the insulating layer 24, and a via conductor 44 is formed within the insulating layer 24 (see Figure 4B).

[0049] Thereafter, as shown in Fig. 4F, an insulating layer 22 is formed on the insulating layer 21 and the conductor layer 11 in the same manner as described with reference to Figs. 4C to 4E, and a conductor layer 12 including a conductor pattern 120 such as conductor pads 12a, 12b, and 12c is formed on the insulating layer 22. When the conductor layer 12 is formed, an inner via conductor 42a, an outer via conductor 42b, and a via conductor 42c are formed integrally with the conductor pads 12a, 12b, and 12c, respectively, in the insulating layer 22. Although not shown in Fig. 4F, a discolored portion 4c (see Figs. 4D and 4E) may occur under the first metal film 4a of the outer via conductor 42b when the outer via conductor 42b is formed, so that the outer via conductor 42b is formed as the above-mentioned dummy via conductor DV. In addition, an insulating layer 25 is formed on the insulating layer 24 and the conductor layer 14, a conductor layer 15 including a conductor pattern 150 is formed on the insulating layer 25, and a via conductor 45 is formed within the insulating layer 25.

[0050] Thereafter, as shown in Fig. 4G, an insulating layer 23 is formed on the insulating layer 22 and the conductor layer 12 in the same manner as described with reference to Figs. 4C to 4E, and a conductor layer 13 including a conductor pattern 130 such as conductor pads 13a, 13b, and 13c is formed on the insulating layer 23. When the conductor layer 13 is formed, an inner via conductor 43a, an outer via conductor 43b, and a via conductor 43c are formed integrally with the conductor pads 13a, 13b, and 13c, respectively, in the insulating layer 23. Although not shown in Fig. 4G, a discolored portion 4c (see Figs. 4D and 4E) may occur under the first metal film 4a of the outer via conductor 43b when the outer via conductor 43b is formed, so that the outer via conductor 43b is formed as the above-mentioned dummy via conductor DV. In addition, an insulating layer 26 is formed on the insulating layer 25 and the conductor layer 15, and a conductor layer 16 including a conductor pattern 160 is formed on the insulating layer 26, and a via conductor 46 is formed in the insulating layer 26.

[0051] Thereafter, solder resist 5 (see FIG. 1) is formed on insulating layer 23 and conductor layer 13, and solder resist 5 (see FIG. 1) is also formed on insulating layer 26 and conductor layer 16. For example, the solder resist 5 is formed by supplying a photosensitive epoxy resin or polyimide resin to the surface of wiring board 100 in the process by spraying, laminating, printing, or the like. Openings are formed in the solder resist 5 by, for example, exposure and development using a mask having an appropriate opening pattern. By going through the above steps, the wiring board 100 of the example in FIG. 1 is completed.

[0052] According to the manufacturing method of the wiring board 100 of the embodiment, in the manufacturing process of the outer via conductors 41b, 42b, 43b, the outer via conductors 41b, 42b, 43b that may include the discolored portion 4c (see FIG. 4D and FIG. 4E) are formed as dummy via conductors DV separated from any of the other conductor patterns 110-180 of the conductor layers 11-18. Therefore, the outer via conductors 41b, 42b, 43b, which are concerned about the connection reliability with the other conductor patterns 110-180, are not used as signal wiring, and it is considered that the occurrence of signal voltage drop and transmission delay due to an increase in connection resistance, etc. is suppressed. In addition, according to the manufacturing method of the wiring board 100 of the illustrated example, the outer via conductors 41b, 42b, 43b are not used for ground wiring and power wiring, and it is considered that the driving of the electronic component E is also prevented from becoming unstable due to the ground potential and power potential of the electronic component E connected to the wiring board 100 becoming unstable.

[0053] The wiring board of the embodiment is not limited to those having the structure illustrated in each drawing, and the structure, shape, and material illustrated in this specification. As described above, the wiring board of the embodiment may have any laminated structure. The wiring board of the embodiment may include any number of conductor layers and insulating layers. For example, the wiring board of the embodiment may be a so-called coreless board that does not include a core substrate. In addition, in the wiring board of the embodiment, the inner via conductor and the outer via conductor constituting the via conductor group included in the different conductor layers may not be laminated so as to overlap in a plan view. Furthermore, in the wiring board of the embodiment, the via conductor group may be formed in the insulating layer on the second surface side of the core insulating layer. [Explanation of symbols]

[0054] 100 Wiring board 11~18 Conductor layers 11a to 13a, 17a, 11b to 13b, 17b Conductor pads 21~26 Insulation layer 40a~43a Inner via conductor 40b~43b Outer via conductor 41G~43G Via conductor group 4c Discolored area A1 inner area A2 outer area AE component mounting area DV Dummy via conductor E Electronic components

Claims

1. Alternately stacked insulating layers and conductive layers; a via conductor group that penetrates the insulating layer and connects the conductor layers sandwiching the insulating layer; A wiring board comprising: the via conductor group includes a plurality of via conductors arranged in a two-dimensional array in a plan view, the lower portions of the via conductors are connected to the respective conductive pads included in the conductive layer; The via conductor group includes: an inner via conductor disposed in an inner region of the two-dimensional array; an outer via conductor disposed in an outer region of the two-dimensional array and surrounding the inner via conductor; It is composed of The outer via conductors include dummy via conductors that are separated from wiring that transmits signals and are included in the conductor layer.

2. 2. The wiring board according to claim 1, The dummy via conductor is separated from wiring to which a ground potential is applied and wiring to which a power supply potential is applied, both of which are included in the conductor layer.

3. 2. The wiring board according to claim 1, Each of the lower portions of the plurality of via conductors includes an electroless plating film layer and is connected to the conductive pad by the electroless plating film layer.

4. 2. The wiring board according to claim 1, The number of nearest via conductors of the outer via conductor is smaller than the number of nearest via conductors of the inner via conductor.

5. 2. The wiring board according to claim 1, The dummy via conductors are disposed at the corners of the outer region.

6. 2. The wiring board according to claim 1, The via conductor group overlaps with the component mounting region in a plan view.

7. 2. The wiring board according to claim 1, The center-to-center distance of the plurality of via conductors is 150 μm or less.

8. 2. The wiring board according to claim 1, The plurality of via conductors are arranged in a lattice pattern.

9. 2. The wiring board according to claim 1, The plurality of via conductors are arranged in a staggered pattern.

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