Image-capturing unit and image-capturing device

Abstract

To provide a method expanding dynamic range of an image-capturing unit.SOLUTION: An image-capturing unit includes: a plurality of pixels; first control wiring connected to at least a first pixel within a plurality of pixels, to which a first control signal to read a signal from the first pixel is output; second control wiring connected to at least a second pixel within the plurality of pixels, to which a second control signal to read a signal from the second pixel is output; a first arithmetic circuit for performing arithmetic processing using the signal read from the first pixel; a second arithmetic circuit performing arithmetic processing using the signal read from the second pixel; and a drive control section causing outputting the first control signal and the second control signal to the first control wiring and the second control wiring so that the different arithmetic processing are performed in the first arithmetic circuit and the second arithmetic circuit.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to an imaging element and an imaging apparatus. [Background technology]

[0002] An imaging unit is known in which a back-illuminated imaging chip and a signal processing chip are connected via microbumps for each cell unit that groups together multiple pixels. [Prior art document] [Patent documents] [Patent Document 1] JP 2006-49361 A Summary of the Invention [Problem to be solved by the invention]

[0003] If the charge accumulation time is shortened to accommodate the strong incident light and large amount of converted charge, the signal read from the area where the incident light is weak will be small. Conversely, if the charge accumulation time is lengthened to accommodate the area where the incident light is weak, the signal read from the area where the incident light is strong will be saturated. For this reason, the dynamic range of the imaging unit is limited to a narrow range. [Means for solving the problem]

[0004] An imaging element in a first aspect of the present invention comprises a plurality of pixels, a first control wiring connected to at least a first pixel of the plurality of pixels and outputting a first control signal for reading out a signal from the first pixel, a second control wiring connected to at least a second pixel of the plurality of pixels and outputting a second control signal for reading out a signal from the second pixel, a first arithmetic circuit that performs arithmetic processing using the signal read out from the first pixel, a second arithmetic circuit that performs arithmetic processing using the signal read out from the second pixel, and a drive control unit that outputs the first control signal and the second control signal to the first control wiring and the second control wiring, respectively, so that different arithmetic processing is performed in the first arithmetic circuit and the second arithmetic circuit.

[0005] An imaging device according to a second aspect of the present invention includes the imaging element described above, and a control unit that controls the imaging element.

[0006] The above summary of the invention does not list all of the necessary features of the present invention. Also, subcombinations of these features may also be inventions. [Brief description of the drawings]

[0007] [Figure 1] 1 is a cross-sectional view of a back-illuminated MOS type imaging element according to an embodiment of the present invention. [Diagram 2] 1 is a diagram illustrating a pixel array and unit groups of an imaging chip. [Diagram 3] FIG. 2 is a circuit diagram corresponding to a unit group of the imaging chip. [Figure 4] FIG. 2 is a block diagram showing a functional configuration of an imaging element. [Diagram 5] FIG. 2 is a block diagram mainly showing a specific configuration of a signal processing chip. [Figure 6] 1 is a block diagram showing a configuration of an imaging device according to an embodiment of the present invention. [Figure 7] FIG. 1 is a diagram illustrating an example of a scene and region division. [Figure 8] FIG. 13 is a diagram illustrating charge accumulation control for each divided region. [Figure 9] FIG. 4 is a flow chart showing processing of a photographing operation. [Figure 10] 13A and 13B are diagrams illustrating another charge accumulation control for each divided region. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0009] 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment. The image sensor 100 includes an image sensor chip 113 that outputs pixel signals corresponding to incident light, a signal processing chip 111 that processes the pixel signals, and a memory chip 112 that stores the pixel signals. The image sensor chip 113, the signal processing chip 111, and the memory chip 112 are stacked and electrically connected to each other by conductive bumps 109 made of Cu or the like.

[0010] As shown in the figure, the incident light is mainly incident in the Z-axis positive direction indicated by the white arrow. In this embodiment, the surface of the imaging chip 113 on which the incident light is incident is referred to as the back surface. Also, as shown in the coordinate axes, the left direction on the paper surface perpendicular to the Z-axis is the X-axis positive direction, and the front direction on the paper surface perpendicular to the Z-axis and the X-axis is the Y-axis positive direction. In the following figures, the coordinate axes are displayed so that the orientation of each figure can be understood based on the coordinate axes in FIG. 1.

[0011] An example of the imaging chip 113 is a back-illuminated MOS image sensor. The PD layer 106 is disposed on the back side of the wiring layer 108. The PD layer 106 has a plurality of PDs (photodiodes) 104 arranged two-dimensionally and transistors 105 provided corresponding to the PDs 104.

[0012] A color filter 102 is provided on the incident side of the PD layer 106 where the incident light is incident, with a passivation film 103 interposed therebetween. The color filters 102 are of a plurality of types that transmit different wavelength regions, and have a specific arrangement corresponding to each of the PDs 104. The arrangement of the color filters 102 will be described later. A set of the color filter 102, the PD 104, and the transistor 105 forms one pixel.

[0013] A microlens 101 is provided corresponding to each pixel on the incident light side of the color filter 102. The microlens 101 condenses the incident light toward the corresponding PD 104.

[0014] The wiring layer 108 has wiring 107 that transmits pixel signals from the PD layer 106 to the signal processing chip 111. The wiring 107 may be multi-layered, and may include passive and active elements.

[0015] A plurality of bumps 109 are arranged on the surface of the wiring layer 108. The plurality of bumps 109 are aligned with a plurality of bumps 109 provided on the opposing surface of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed, etc., so that the aligned bumps 109 are joined and electrically connected to each other.

[0016] Similarly, a plurality of bumps 109 are arranged on the opposing surfaces of the signal processing chip 111 and the memory chip 112. These bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressed together, etc., so that the aligned bumps 109 are bonded to each other and electrically connected.

[0017] The bonding between the bumps 109 is not limited to Cu bump bonding by solid-phase diffusion, and micro-bump bonding by solder melting may be used. Also, it is sufficient to provide one bump 109 for each pixel group described below. Therefore, the size of the bump 109 may be larger than the pitch of the PD 104. Also, in a peripheral area other than the pixel area where the pixels are arranged, a bump larger than the bump 109 corresponding to the pixel area may be provided.

[0018] The signal processing chip 111 has TSVs (Through Silicon Vias) 110 that connect the circuits provided on the front and back surfaces of the chip to each other. The TSVs 110 are preferably provided in the peripheral region. The TSVs 110 may also be provided in the peripheral region of the imaging chip 113 and the memory chip 112.

[0019] 2 is a diagram for explaining the pixel arrangement of the imaging chip 113 and the unit group 131. In particular, the imaging chip 113 is shown as observed from the back side. More than 20 million pixels are arranged in a matrix in the pixel region. In this embodiment, adjacent 4 pixels x 4 pixels, or 16 pixels, form one group. The grid lines in the figure show the concept of forming the unit group 131 by grouping adjacent pixels.

[0020] As shown in the partially enlarged view of the pixel region, the unit group 131 includes four so-called Bayer arrays, each consisting of four pixels: green pixels Gb, Gr, blue pixel B, and red pixel R, arranged vertically and horizontally. The green pixels are pixels having a green filter as the color filter 102 and receive light in the green wavelength band of the incident light. Similarly, the blue pixels are pixels having a blue filter as the color filter 102 and receive light in the blue wavelength band, and the red pixels are pixels having a red filter as the color filter 102 and receive light in the red wavelength band.

[0021] 3 is a circuit diagram corresponding to the unit group 131 of the imaging chip 113. In the figure, a rectangle surrounded by a dotted line representatively represents a circuit corresponding to one pixel. Note that at least a part of each transistor described below corresponds to the transistor 105 in FIG.

[0022] As described above, the unit group 131 is formed of 16 pixels. The 16 PDs 104 corresponding to the respective pixels are connected to the transfer transistors 302, and each gate of the transfer transistors 302 is connected to the TX wiring 307 to which a transfer pulse is supplied. In this embodiment, the TX wiring 307 is commonly connected to the 16 transfer transistors 302.

[0023] The drain of each transfer transistor 302 is connected to the source of the corresponding reset transistor 303, and a so-called floating diffusion FD between the drain of the transfer transistor 302 and the source of the reset transistor 303 is connected to the gate of the amplification transistor 304. The drain of the reset transistor 303 is connected to a Vdd wiring 310 to which a power supply voltage is supplied, and the gate of the reset transistor 303 is connected to a reset wiring 306 to which a reset pulse is supplied. In this embodiment, the reset wiring 306 is commonly connected to the 16 reset transistors 303.

[0024] The drain of each of the amplification transistors 304 is connected to a Vdd wiring 310 to which a power supply voltage is supplied. In addition, the source of each of the amplification transistors 304 is connected to the drain of each of the corresponding selection transistors 305. Each gate of the selection transistor is connected to a decoder wiring 308 to which a selection pulse is supplied. In this embodiment, the decoder wiring 308 is provided independently for each of the 16 selection transistors 305. Then, the source of each selection transistor 305 is connected to a common output wiring 309. The load current source 311 supplies a current to the output wiring 309. That is, the output wiring 309 for the selection transistor 305 is formed by a source follower. The load current source 311 may be provided on the imaging chip 113 side or on the signal processing chip 111 side.

[0025] Here, the flow from the start of charge accumulation to pixel output after accumulation is completed will be described. When a reset pulse is applied to the reset transistor 303 via the reset wiring 306 and at the same time a transfer pulse is applied to the transfer transistor 302 via the TX wiring 307, the potentials of the PD 104 and the floating diffusion FD are reset.

[0026] When the application of the transfer pulse is released, the PD 104 converts the received incident light into electric charges and accumulates them. After that, when the transfer pulse is applied again without the reset pulse being applied, the accumulated electric charges are transferred to the floating diffusion FD, and the potential of the floating diffusion FD changes from the reset potential to the signal potential after the electric charges are accumulated. Then, when a selection pulse is applied to the selection transistor 305 through the decoder wiring 308, the fluctuation of the signal potential of the floating diffusion FD is transmitted to the output wiring 309 through the amplification transistor 304 and the selection transistor 305. As a result, a pixel signal corresponding to the reset potential and the signal potential is output from the unit pixel to the output wiring 309.

[0027] As shown in the figure, in this embodiment, the reset wiring 306 and the TX wiring 307 are common to the 16 pixels forming the unit group 131. That is, the reset pulse and the transfer pulse are each applied simultaneously to all 16 pixels. Therefore, all the pixels forming the unit group 131 start charge accumulation at the same timing, and end charge accumulation at the same timing. However, pixel signals corresponding to the accumulated charges are sequentially applied to the respective selection transistors 305 by a selection pulse, and are selectively output to the output wiring 309.

[0028] In this way, by configuring the circuit based on the unit group 131, the charge accumulation time can be controlled for each unit group 131. Since the charge accumulation time can be controlled for each unit group, adjacent unit groups 131 can output pixel signals with different charge accumulation times. Furthermore, a common charge accumulation time can be set for all unit groups 131, and a certain unit group 131 can be controlled to perform one charge accumulation and pixel signal output, and an adjacent unit group 131 can be controlled to repeat two charge accumulations and pixel signal outputs. The latter repeated control of charge accumulation and pixel signal output with a common unit time is called unit time control. In addition, when performing unit time control, if the start and end points of charge accumulation are synchronized for all unit groups 131, the reset wiring 306 may be commonly connected to all reset transistors 303 on the imaging chip 113.

[0029] In this embodiment, the unit time control will be described in detail, in particular, the control for making the number of times charge accumulation and pixel signal output are repeated differently for each unit group 131 in response to a single image capture instruction will be described.

[0030] 4 is a block diagram showing the functional configuration of the image sensor 100. In particular, the flow of pixel signals will be explained here.

[0031] The analog multiplexer 411 sequentially selects the 16 PDs 104 forming the unit group 131, and outputs the respective pixel signals to the output wiring 309. The multiplexer 411 is formed in the imaging chip 113 together with the PDs 104.

[0032] The pixel signals output via the multiplexer 411 undergo correlated double sampling (CDS) and analog-to-digital (A / D) conversion by a signal processing circuit 412 formed in the signal processing chip 111, which performs CDS and A / D conversion. The A / D conversion converts the input analog pixel signals into 12-bit digital pixel signals. The A / D converted pixel signals are passed to an arithmetic circuit 415 also formed in the signal processing chip 111. The arithmetic circuit 415 performs integration processing, which will be described later, on the received pixel signals and passes them to the demultiplexer 413.

[0033] The demultiplexer 413 stores the received pixel signals in pixel memories 414 corresponding to the respective pixels. Each of the pixel memories 414 has a capacity capable of storing pixel signals after an integration process described below is executed. The demultiplexer 413 and the pixel memories 414 are formed in the memory chip 112.

[0034] The arithmetic circuit 415 reads out the corresponding pixel signal to be used in the integration process from the pixel memory 414 via the demultiplexer 413. Alternatively, in response to a transfer request from the outside, the arithmetic circuit 415 transfers the pixel signal read out from the pixel memory 414 via the demultiplexer 413 to a downstream image processing unit. The arithmetic circuit 415 may be provided in the memory chip 112.

[0035] Also, while the figure shows the flow of pixel signals for one group, in reality, these exist for each group and operate in parallel. However, a calculation circuit 415 does not have to exist for each group, and for example, one calculation circuit 415 may process sequentially while referring to the values ​​of the pixel memories 414 corresponding to each group in order.

[0036] Next, a description will be given of an example of a specific configuration of mainly the signal processing chip 111. FIG.

[0037] The signal processing chip 111 includes a sensor control unit 441, a block control unit 442, a synchronization control unit 443, and a signal control unit 444 as distributed control functions, and a drive control unit 420 that controls these control units. The drive control unit 420 converts instructions from a system control unit 501 that is responsible for integrated control of the entire imaging device into control signals that can be executed by each control unit, and passes them on to each unit.

[0038] The sensor control unit 441 is responsible for controlling the transmission of control pulses related to charge accumulation and charge readout of each pixel, which are transmitted to the imaging chip 113. Specifically, the sensor control unit 441 controls the start and end of charge accumulation by transmitting a reset pulse and a transfer pulse to the target pixel, and outputs a pixel signal to the output wiring 309 by transmitting a selection pulse to the readout pixel.

[0039] The block control unit 442 executes transmission of a specific pulse to be transmitted to the imaging chip 113 to specify the unit group 131 to be controlled. As described later, the system control unit 501 divides the pixel area of ​​the imaging chip 113 into a plurality of blocks, each including one or more unit groups 131, according to the characteristics of the scene, which is the subject scene. The pixels included in the same block are subjected to the same unit time control. That is, the pixels included in the same block repeat the same number of charge accumulations and pixel signal outputs in response to one imaging instruction. Therefore, the block control unit 442 plays a role of dividing the unit groups 131 into blocks by transmitting a specific pulse to the target unit group 131 based on the designation from the drive control unit 420. The transfer pulse and reset pulse that each pixel receives via the TX wiring 307 and the reset wiring 306 are the logical product of each pulse transmitted by the sensor control unit 441 and the specific pulse transmitted by the block control unit 442. The specific designation of the block from the drive control unit 420 will be described in detail later.

[0040] The synchronization control unit 443 sends a synchronization signal to the imaging chip 113. Each pulse becomes active in the imaging chip 113 in synchronization with the synchronization signal. For example, by adjusting the synchronization signal, random control, thinning control, and the like that control only specific pixels of pixels belonging to the same unit group 131 are realized.

[0041] The signal control unit 444 is mainly responsible for timing control of the A / D converter 412b. The pixel signals output via the output wiring 309 are input to the CDS circuit 412a and the A / D converter 412b via the multiplexer 411. The A / D converter 412b is controlled by the signal control unit 444 to convert the input pixel signals into digital signals. The pixel signals converted into digital signals are passed to the arithmetic circuit 415, where they are subjected to integration processing and the like, which will be described later. The pixel signals subjected to integration processing and the like are passed to the demultiplexer 413 of the memory chip 112, and are stored as digital data pixel values ​​in the pixel memories 414 corresponding to the respective pixels.

[0042] The signal processing chip 111 has a timing memory 430 as an accumulation control memory that stores block division information about which unit groups 131 are to be combined to form a block, and accumulation count information about how many times each of the formed blocks repeats charge accumulation and pixel signal output. The timing memory 430 is formed of, for example, a flash RAM.

[0043] As described later, which unit groups are to be combined to form blocks is determined by the system control unit 501, for example, based on the detection result of scene luminance distribution detection executed prior to a series of shooting sequences. The determined blocks are divided, for example, into a first block, a second block, ..., and each block is defined by which unit group 131 it includes. The drive control unit 420 receives this block division information from the system control unit 501 and stores it in the timing memory 430.

[0044] The system control unit 501 determines how many times each block should repeat charge accumulation and pixel signal output based on, for example, the detection result of the luminance distribution. The drive control unit 420 receives this repetition number information from the system control unit 501 and stores it in the timing memory 430 in a pair with the corresponding block division information. By storing the block division information and the repetition number information in the timing memory 430 in this manner, the drive control unit 420 can independently execute a series of charge accumulation controls by sequentially referring to the timing memory 430. In other words, once the drive control unit 420 receives an image capture instruction signal from the system control unit 501 in the control of acquiring one image, it can complete the accumulation control without receiving an instruction from the system control unit 501 each time for the control of each pixel.

[0045] The drive control unit 420 receives the block division information and the repetition count information to be updated from the system control unit 501, and appropriately updates the stored contents of the timing memory 430. For example, the drive control unit 420 updates the timing memory 430 in synchronization with an imaging preparation instruction or an imaging instruction. This configuration realizes faster charge accumulation control, and while the drive control unit 420 is executing charge accumulation control, the system control unit 501 can execute other processes in parallel.

[0046] The drive control unit 420 not only controls the charge accumulation of the imaging chip 113, but also refers to the timing memory 430 when executing read control. For example, the drive control unit 420 refers to the number of repetitions information for each block, reads out pixel signals already stored in the pixel memory 414, and passes them to the arithmetic circuit 415. Furthermore, the pixel signals that have been subjected to arithmetic processing by the arithmetic circuit 415 are stored again in the pixel memory 414. In other words, the pixel signals in the pixel memory 414 are updated.

[0047] Furthermore, the drive control unit 420 reads out the target pixel signal from the pixel memory 414 via the arithmetic circuit 415 and the demultiplexer 413 in accordance with a delivery request from the system control unit 501, and delivers the signal to the image processing unit 511 provided in the imaging device. The pixel memory 414 is provided with a data transfer interface that transmits the pixel signal in accordance with the delivery request. The data transfer interface is connected to a data transfer line that is connected to the image processing unit 511. The data transfer line is, for example, constituted by a data bus among the bus lines. In this case, the delivery request from the system control unit 501 to the drive control unit 420 is executed by address designation using the address bus.

[0048] The transmission of pixel signals by the data transfer interface is not limited to the addressing method, and various other methods may be adopted. For example, a double data rate method may be adopted, which uses both the rising and falling edges of the clock signal used to synchronize each circuit when transferring data. A burst transfer method may also be adopted, which transfers data all at once by omitting some steps such as addressing, thereby increasing speed. A bus method using lines that connect the control unit, memory unit, and input / output unit in parallel, and a serial method that transfers data one bit at a time in series may also be adopted in combination.

[0049] With this configuration, the image processing unit 511 can receive only the necessary pixel signals, and can complete image processing at high speed, especially when forming an image with low resolution. Also, when the arithmetic circuit 415 is made to perform accumulation processing, the image processing unit 511 does not need to perform accumulation processing, and therefore, the image processing can be speeded up by sharing functions and parallel processing.

[0050] 6 is a block diagram showing the configuration of the imaging device according to this embodiment. The imaging device 500 includes a photographing lens 520 as an imaging optical system, which guides a subject light flux incident along an optical axis O to the imaging element 100. The photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging device 500. The imaging device 500 mainly includes the imaging element 100, a system control unit 501, a photometry unit 503, a work memory 504, a recording unit 505, and a display unit 506. The system control unit 501 functions as an imaging instruction unit that receives an instruction from a user and generates an imaging instruction to be transmitted to the imaging element 100.

[0051] The photographing lens 520 is composed of a group of optical lenses, and focuses the subject light beam from the scene near its focal plane. Note that in Fig. 6, it is represented by a virtual single lens arranged near the pupil. As described above, the drive control unit 420 of the image sensor 100 is a control circuit that performs charge accumulation control such as timing control and area control of the image sensor 100 according to instructions from the system control unit 501.

[0052] The image sensor 100 transfers the pixel signal to an image processor 511 of the system controller 501. The image processor 511 performs various image processes using the work memory 504 as a workspace to generate image data. For example, when generating image data in a JPEG file format, compression is performed after white balance processing, gamma processing, etc. are performed. The generated image data is recorded in a recording unit 505, and is also converted into a display signal and displayed on a display unit 506 for a preset time. The image processor 511 may be configured as an ASIC independent of the system controller 501.

[0053] The photometry unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences for generating image data. The photometry unit 503 includes, for example, an AE sensor with about one million pixels. The calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance of each area of ​​the scene. The calculation unit 512 determines the above-mentioned unit time, aperture value, and ISO sensitivity according to the calculated luminance distribution. In this embodiment, the calculation unit 512 further determines how many times charge accumulation and pixel signal output are to be repeated for which pixel group area of ​​the imaging chip 113 according to the determined unit time. The calculation unit 512 also calculates the time until the charge accumulation of the pixel group area to which the maximum number of repetitions is assigned ends, and determines the timing of opening and closing the shutter. The calculation unit 512 also executes various calculations for operating the imaging device 500.

[0054] FIG. 7 is a diagram for explaining an example of a scene and region division. FIG. 7(a) shows a scene captured by the pixel region of the imaging chip 113. Specifically, it is a scene in which a shadow object 601 and an intermediate object 602 included in an indoor environment and a highlight object 603 in an outdoor environment observed inside a window frame 604 are simultaneously captured. When capturing such a scene with a large difference in brightness from a highlight part to a shadow part, if a conventional imaging element is used, black crush occurs in the shadow part when charge accumulation is performed based on the highlight part, and white blowout occurs in the highlight part when charge accumulation is performed based on the shadow part. In other words, it can be said that the dynamic range of the photodiode is insufficient for a scene with a large difference in brightness in order to output an image signal by uniformly accumulating charge in both the highlight part and the shadow part at one time. Therefore, in this embodiment, the scene is divided into partial regions such as a highlight part and a shadow part, and the number of times that charge accumulation and pixel signal reading are repeated in the photodiode corresponding to each region are made different from each other, thereby substantially expanding the dynamic range.

[0055] FIG. 7(b) shows the division of the pixel region of the imaging chip 113. The calculation unit 512 analyzes the scene of FIG. 7(a) captured by the photometry unit 503 and divides the pixel region based on the luminance. For example, the system control unit 501 causes the photometry unit 503 to capture the scene multiple times while changing the exposure time, and the calculation unit 512 determines the dividing line of the pixel region by referring to the change in the distribution of the blown-out highlight region and the crushed shadow region. In the example of FIG. 7(b), the calculation unit 512 divides the pixel region into three regions: a shadow region 611, a middle region 612, and a highlight region 613.

[0056] The division lines are defined along the boundaries of the unit groups 131. That is, each divided area includes an integer number of unit groups 131. The pixels of each group included in the same area perform charge accumulation and pixel signal output the same number of times in the unit time determined by the calculation unit 512. If the pixels belong to different areas, they perform charge accumulation and pixel signal output different numbers of times.

[0057] Fig. 8 is a diagram illustrating unit control for each divided region in the example of Fig. 7. Here, a case will be described in which the calculation unit 512 receives the output of the photometry unit 503 and calculates that the difference between the EV value of the intermediate region 612 and the EV value of the highlight region 613 is about one step, and that the difference between the EV value of the shadow region 611 and the EV value of the intermediate region 612 is also about one step.

[0058] When the calculation unit 512 receives a shooting preparation instruction from the user, the calculation unit 512 calculates a common unit time T 0 Here, the unit time T 0 is determined from the EV value of the highlight region 613 so that the pixels in the highlight region 613 are not saturated by a single charge accumulation. For example, in the pixel corresponding to the brightest part of the highlight region 613, based on the assumption that 80 to 90 percent of the charge that can be accumulated in one charge accumulation operation, the unit time T 0At this time, the ISO sensitivity, which correlates with the amplification rate of the output pixel signal, and the aperture value of the aperture provided in the photographing lens 520 are determined by the calculation unit 512 in accordance with the unit time T 0 The ISO sensitivity is calculated so as to provide appropriate exposure for the highlighted region 613. The ISO sensitivity is set commonly for all pixels.

[0059] The calculation unit 512 refers to the difference between the calculated EV value of the highlight region 613 and the EV value of the intermediate region 612 and sets the number of repetitions of the intermediate region 612 to two. 0 The charge accumulation and pixel signal readout by the charge accumulation are repeated twice. Similarly, the calculation unit 512 refers to the difference between the calculated EV value of the highlight region 613 and the EV value of the shadow region 611 and sets the charge accumulation count for the shadow region 611 to four. That is, 0 The charge accumulation and pixel signal readout due to the charge accumulation are repeated four times. As described later, the pixel signals that are repeatedly read out are sequentially added together by the arithmetic circuit 415 and stored in the pixel memory 414.

[0060] When an image capture instruction is received from the user at time t=0, the drive control unit 420 applies a reset pulse and a transfer pulse to the pixels of the groups belonging to any of the regions. This application serves as a trigger for all the pixels to start accumulating electric charges.

[0061] Time t=T 0When this occurs, the drive control unit 420 applies a transfer pulse to all pixels. Then, it sequentially applies a selection pulse to the pixels in each group to output each pixel signal to the output wiring 309. The drive control unit 420 converts each pixel signal into a digital signal by the A / D converter 412b, passes it through the arithmetic circuit 415, and stores it in the corresponding pixel memory 414. This process completes the first unit control. Then, the process for the pixels of the group belonging to the highlight region 613 is completed. At this point, the image generated from the pixel signals stored in the pixel memory 414 corresponding to the pixels of the highlight region 613 can be expected to be an image with proper exposure that uses the entire dynamic range of the PD 104 with almost no blown out highlights or crushed shadows.

[0062] After outputting the pixel signals of all the pixels, the drive control unit 420 outputs the pixel signals of the groups belonging to the intermediate region 612 and the shadow region 611 at time t=T 0 At this timing, a reset pulse and a transfer pulse are applied again to start the second charge accumulation. Note that since it takes time to selectively output pixel signals, a time lag occurs between the end of the first charge accumulation and the start of the second charge accumulation. If this time lag cannot be practically ignored, then the start of the second charge accumulation can be delayed by that time.

[0063] Time t=2T 0When the pixel signals are equal to or larger than the pixel signals in the intermediate region 612 and the shadow region 611, the drive control unit 420 applies a transfer pulse to the pixels in the groups belonging to the intermediate region 612 and the shadow region 611. Then, the drive control unit 420 sequentially applies a selection pulse to the pixels in these groups to output the pixel signals to the output wiring 309. The drive control unit 420 converts the pixel signals into digital signals using the A / D converter 412b. In parallel with this, the drive control unit 420 reads out the first pixel signals already stored in the corresponding pixel memories 414. Then, the drive control unit 420 causes the arithmetic circuit 415 to execute an integration process of adding together the first pixel signals and the newly acquired second pixel signals. The drive control unit 420 stores the pixel signals newly generated by the integration process in the corresponding pixel memories 414. As a result, the pixel memories 414 are updated to the pixel signals obtained by the integration process from the first pixel signals. This process completes the second unit control. Then, the process for the pixels in the group belonging to the intermediate region 612 is completed.

[0064] At this point, the image generated from the pixel signals stored in the pixel memory 414 corresponding to the pixels in the intermediate region 612 is expected to be an image with proper exposure that utilizes the entire bit width of the image data and has almost no whiteout or blackout. In other words, if one unit control does not have enough charge accumulation time, an underexposed image that is prone to blackout is created. However, by performing integration processing across two unit controls, it is possible to achieve a substantially 2T 0 It is possible to obtain a proper image equivalent to that obtained by accumulating charges for a period of 2T. Furthermore, by dividing the charge accumulation into two, 0 It is also expected that random noise will be reduced compared to an image obtained by accumulating a single charge over a period of time.

[0065] After outputting the pixel signals of the pixels in the groups belonging to the intermediate region 612 and the shadow region 611, the drive control unit 420 outputs the pixel signals of the pixels in the group belonging to the shadow region 611 at time t=2T 0 At this timing, a reset pulse and a transfer pulse are applied again to start the third charge accumulation.

[0066] Time t=3T 0 When the pixel count reaches 1, the drive control unit 420 applies a transfer pulse to the group of pixels belonging to the shadow region 611. Then, the drive control unit 420 sequentially applies a selection pulse to the pixels in this group to output each pixel signal to the output wiring 309. The drive control unit 420 converts each pixel signal into a digital signal using the A / D converter 412b. In parallel with this, the drive control unit 420 reads out the corresponding pixel signals already stored in the pixel memories 414. Then, the drive control unit 420 causes the arithmetic circuit 415 to execute an integration process of adding together the read-out pixel signals and the newly acquired third pixel signal. The drive control unit 420 stores the pixel signals newly generated by the integration process in the corresponding pixel memories 414. As a result, each pixel memory 414 is updated to the pixel signal newly integrated. This process completes the third unit control.

[0067] Next, the drive control unit 420 performs the following operation on the pixels of the group that belongs to the shadow region 611 at time t=3T 0 At this timing, a reset pulse and a transfer pulse are applied again to start the fourth charge accumulation.

[0068] Time t=4T 0 When the pixel count reaches 1, the drive control unit 420 applies a transfer pulse to the group of pixels belonging to the shadow region 611. Then, the drive control unit 420 sequentially applies a selection pulse to the pixels in this group to output each pixel signal to the output wiring 309. The drive control unit 420 converts each pixel signal into a digital signal by the A / D converter 412b. In parallel with this, the drive control unit 420 reads out the corresponding pixel signals already stored in the pixel memory 414. Then, the drive control unit 420 causes the arithmetic circuit 415 to execute an integration process of adding together the read pixel signals and the newly acquired fourth pixel signal. The drive control unit 420 stores the pixel signals newly generated by the integration process in the corresponding pixel memory 414. As a result, each pixel memory 414 is updated to the pixel signal newly integrated. This process completes the fourth unit control. Then, the process for the pixels in the group belonging to the shadow region 611 is completed.

[0069] At this point, the image generated from the pixel signals stored in the pixel memory 414 corresponding to the pixels in the shadow region 611 is expected to be an image with proper exposure that utilizes the entire bit width of the image data and has almost no whiteout or blackout. In other words, if the charge accumulation time is insufficient in one unit control, an underexposed image that is prone to blackout will be obtained. However, by performing the integration process over four unit controls, the image can be effectively 4T 0 It is possible to obtain a proper image equivalent to that obtained by accumulating charges for a period of 4T. 0 It is also expected that random noise will be reduced compared to an image obtained by accumulating a single charge over a period of time.

[0070] The system control unit 501 detects when the fourth charge accumulation is completed (t=4T 0 The shutter is closed at timing 0. The image processor 511 processes and joins together the pixel signals from each region processed as described above to generate image data with a high dynamic range.

[0071] In the process described above, when a predetermined number of unit controls are completed in a certain region, the drive control unit 420 does not execute charge accumulation for that region even if the unit controls are continuing in other regions. However, charge accumulation may be executed thereafter in accordance with the unit controls of the other regions. In this case, it is sufficient not to output pixel signals by applying transfer pulses and selection pulses. Alternatively, even if pixel signals are output, it is sufficient to discard the pixel signals at any stage, such as conversion to a digital signal by the A / D converter 412b, integration processing by the arithmetic circuit 415, or storage in the pixel memory 414.

[0072] Next, a series of photographing operation processes will be described. Fig. 9 is a flow diagram showing the photographing operation processes. The flow starts when the power supply of the imaging device 500 is turned on.

[0073] In step S101, the system control unit 501 waits until the shutter switch SW1 is pressed down, which is an instruction to prepare for image capture. When the system control unit 501 detects that the shutter switch SW1 has been pressed down, the process proceeds to step S102.

[0074] In step S102, the system control unit 501 executes photometry processing. Specifically, the output of the photometry unit 503 is obtained, and the calculation unit 512 calculates the luminance distribution of the scene. Then, the process proceeds to step S103, where the unit time, area division, number of repetitions, etc. are determined as described above. The determined information is sent from the system control unit 501 to the drive control unit 420 and stored in the timing memory 430.

[0075] When the image capture preparation operation is completed, the process proceeds to step S104, and the process waits until the user presses down the shutter switch SW2, which is an image capture instruction. At this time, if the elapsed time exceeds a predetermined time Tw (YES in step S105), the process returns to step S101. If the pressing down of the switch SW2 is detected before Tw is exceeded (NO in step S105), the process proceeds to step S106.

[0076] In step S106, the drive control unit 420 executes charge accumulation by all pixels as a first unit control, and then executes pixel signal output and A / D conversion after a unit time has elapsed (step S107), and stores the converted digital pixel signal in the pixel memory 414 (step S108).

[0077] Next, drive control section 420 proceeds to step S109, and determines the target region for executing the second unit control by referring to the region division information in timing memory 430. Then, charge accumulation is executed in the target region (step S110).

[0078] After the unit time has elapsed, the drive control unit 420 executes pixel signal output and A / D conversion by the second charge accumulation (step S111). In parallel with this, or before or after this, the drive control unit 420 reads out the pixel signal stored by the first unit control from the pixel memory 414 (step S112). Then, the drive control unit 420 causes the arithmetic circuit 415 to execute an integration process of integrating the pixel signal A / D converted in step S111 and the pixel signal read out in step S112 (step S113). The result of the integration by the arithmetic circuit 415 updates the value of the pixel memory 414 read out in step S112 as a new pixel signal and is stored (step S114).

[0079] The drive control unit 420 proceeds to step S115, where it determines whether the number of repetitions determined in step S103 has been reached by referring to the number of repetitions information in the timing memory 430. If it determines that the number of repetitions has not been reached, it proceeds to step S109, where it executes the third, fourth, and so on unit controls (steps S109 to S114). If it determines that the number of repetitions has been reached, it proceeds to step S116.

[0080] In step S116, the drive control unit 420 reports the completion of unit control to the system control unit 501, and in response to this, the system control unit 501 causes the drive control unit 420 to transmit the pixel signal stored in the pixel memory 414 to the image processing unit 511. The image processing unit 511 executes image processing to generate image data such as JPEG. The system control unit 501 executes recording processing to record the generated image data in the recording unit 505.

[0081] When the recording process is completed, the process proceeds to step S117, where it is determined whether or not the power supply to the imaging device 500 has been turned off. If it is determined that the power supply has not been turned off, the process returns to step S101, and if it is determined that the power supply has been turned off, the series of shooting operation processes ends.

[0082] In the above-described process, the drive control unit 420 0is determined as the time at which the pixels in the highlight region 613 are not saturated. Since the highlight region 613 is determined based on the photometry result of the photometry unit 503, the drive control unit 420 determines the unit time T 0 However, the unit time T 0 Instead of dynamically changing for each shooting, a predetermined fixed value can be used.

[0083] For example, a fixed value of T 0 8 when = 1 / 256 seconds is adopted. Assume that the system control unit 501 calculates, as the photometry results, a charge accumulation time for proper exposure of the highlight region 613 to be 1 / 64 seconds, a charge accumulation time for proper exposure of the intermediate region 612 to be 1 / 32 seconds, and a charge accumulation time for proper exposure of the shadow region 611 to be 1 / 16 seconds. In this case, it is sufficient to determine the number of repetitions as follows: (1 / 64)÷(1 / 256)=4 times for the highlight region 613, (1 / 32)÷(1 / 256)=8 times for the intermediate region 612, and (1 / 16)÷(1 / 256)=16 times for the shadow region 611.

[0084] Here, the unit time T is a fixed value. 0 Therefore, it is preferable to set the unit time T to a relatively short time so that unit time control can be performed even for bright scenes. However, in this embodiment, since the integration process is performed using digital pixel signals after A / D conversion, the unit time T 0 The number of quantization bits of the A / D converter 412b should be increased so that the charge accumulation will result in a value of 1 or more even in the shadow area. In this case, the storage size of the pixel memory 414 is also set according to the number of quantization bits. Here, if the number of bits processed by the image processing unit 511 and the number of bits of the pixel signal stored in the pixel memory 414 differ, the pixel signal may be delivered to the image processing unit 511 after bit conversion is performed by the arithmetic circuit 415 in synchronization with a delivery request from the system control unit 501.

[0085] Furthermore, unit control can be performed without using the photometry results of the photometry unit 503. Specifically, pixel signals are read from the pixel memory 414, and the average value for each unit group, or the average value for each group (for example, 5×5=25 groups in length and width) including adjacent unit groups is calculated one by one, and whether or not further unit control is performed is determined depending on whether or not the average value exceeds a threshold value. That is, in an area where the image is considered to have become bright as a result of repeating the unit control, further unit control is not performed, and in an area where the image is considered to still be dark, further unit control is continued. By performing such average value determination, the image of each area can be made to be an image close to the proper exposure. In this case, when the pixel signals stored in the pixel memory 414 are handed over to the image processing unit 511, normalization can be performed by the number of repetitions. Specifically, for example, each pixel signal can be divided by the number of repetitions. The value to be used for determining whether or not the threshold value has been exceeded is not limited to the average value, and values ​​calculated by various statistical processes can be used.

[0086] According to the configuration of the imaging device 500 of this embodiment, not only is it possible to execute unit control to obtain appropriate exposure for each region, but it is also possible to execute unit control in relation to various image effects. For example, in a unit time T 0 is set to a relatively short time at which camera shake is unlikely to occur, and unit control can be repeated until the image shift exceeds the allowable amount. In this case, the detection result of the motion detection unit can be used to detect the amount of image shift. The motion detection unit can be the photometry unit 503 if the output of a photometry sensor is used, for example, or another motion detection sensor provided separately. With this type of unit time control, an image with less image shake can be obtained. Note that the lack of brightness due to not reaching the scheduled charge accumulation time can be adjusted by amplifying the pixel signal.

[0087] Also, unit control can be exclusively performed for each region. For example, in the example of FIG. 8, the first unit control can be performed only for the highlight region 613, the second and third unit controls can be performed only for the intermediate region 612, and the fourth to seventh unit controls can be performed only for the shadow region 611. By exclusively performing unit control for each region in this way, it is possible to obtain a variety of images in which optical conditions such as aperture value are changed for each region. More specifically, the aperture can be narrowed to repeat unit control more times for the region where the waterfall flows, and the aperture can be opened to perform fewer unit controls for the region of trees around it. According to this type of control, images with different shutter speeds can coexist in one image, so that an image that has not been seen before can be obtained by a single imaging instruction. It should be noted that, for example, if an instruction is received in advance from the user through a live view image, it is possible to determine in advance how many times unit control is to be repeated for which region of the scene.

[0088] Although the above-described embodiments have been described on the assumption that still images are to be captured, it is of course possible to generate moving images by performing similar unit control for each frame. Furthermore, the above-described processing can be performed not only on dedicated digital cameras, but also on camera units incorporated in electronic devices such as mobile phones, information terminals, and PCs.

[0089] Further variations will be described. Fig. 10 is a diagram for explaining charge accumulation control for each divided region as another embodiment. Here, a case will be described in which, similar to the example of Fig. 8, the calculation unit 512 receives the output of the photometry unit 503 and calculates that the difference between the EV value of the intermediate region 612 and the EV value of the highlight region 613 is about one step, and that the difference between the EV value of the shadow region 611 and the EV value of the intermediate region 612 is also about one step. When the calculation unit 512 receives a shooting preparation instruction from the user, similar to the example of Fig. 8, it calculates a common unit time T 0 Determine.

[0090] The calculation unit 512 references the calculated difference between the EV value of the highlight region 613 and the EV value of the intermediate region 612 and determines that the number of charge accumulations required in the intermediate region 612 is two. Similarly, the calculation unit 512 references the calculated difference between the EV value of the highlight region 613 and the EV value of the shadow region 611 and determines that the number of charge accumulations required in the shadow region 611 is four. Here, in this embodiment, the number of charge accumulations determined in the shadow region 611, i.e., the maximum number of charge accumulations determined as necessary, which is four, is set as the number of charge accumulations in all regions. In other words, in all regions, the highlight region 613, the intermediate region 612, and the shadow region 611, the number of charge accumulations required in the unit time T 0 The charge accumulation and pixel signal readout due to this charge accumulation are repeated four times.

[0091] When an image capture instruction is received from the user at time t=0, the drive control unit 420 applies a reset pulse and a transfer pulse to the pixels of the groups belonging to any of the regions. This application serves as a trigger for all the pixels to start accumulating electric charges.

[0092] Time t=T 0 When this occurs, the drive control unit 420 applies a transfer pulse to all pixels. Then, it sequentially applies a selection pulse to the pixels in each group to output each pixel signal to the output wiring 309. The drive control unit 420 converts each pixel signal into a digital signal using the A / D converter 412b, passes the signal through the arithmetic circuit 415, and stores the digital signal in the corresponding pixel memory 414. This process completes the first unit control.

[0093] After outputting the pixel signals of all the pixels, the drive control unit 420 again outputs the pixel signals of all the pixels in the entire region at time t=T 0 At this timing, a reset pulse and a transfer pulse are applied again to start the second charge accumulation. Note that since it takes time to selectively output pixel signals, a time lag occurs between the end of the first charge accumulation and the start of the second charge accumulation. If this time lag cannot be practically ignored, then the start of the second charge accumulation can be delayed by that time.

[0094] Time t=2T 0 When this is the case, the drive control unit 420 applies a transfer pulse to all pixels. Then, the drive control unit 420 sequentially applies a selection pulse to the pixels in each group to output each pixel signal to the output wiring 309. The drive control unit 420 converts each pixel signal into a digital signal by the A / D converter 412b. In parallel with this, the drive control unit 420 reads out the first pixel signals already stored in the corresponding pixel memories 414. Then, the drive control unit 420 causes the arithmetic circuit 415 to execute an integration process of adding together the first pixel signal and the newly acquired second pixel signal. The drive control unit 420 stores the pixel signal newly generated by the integration process in the corresponding pixel memory 414. As a result, each pixel memory 414 is updated to the pixel signal obtained by the integration process from the first pixel signal. This process completes the second unit control.

[0095] Similarly, at time t=2T 0 From 3T 0 The third charge accumulation and pixel signal readout are performed during t=3T 0 From 4T 0 The fourth charge accumulation and pixel signal readout are performed during the unit time T 0 As described above, since is set based on the standard that 80 to 90 percent of the charge that can be accumulated in one charge accumulation operation is accumulated in the pixels corresponding to the brightest parts of the highlight region 613, there is no saturation in each charge accumulation. Therefore, the image of the highlight region 613 obtained by reducing the value of the integrated pixel signal to 1 / 4 can be expected to be a properly exposed image that makes full use of the dynamic range of the PD 104 with almost no blown out highlights or crushed shadows.

[0096] Similarly, when the fourth integration process is completed, because two charge accumulations are sufficient in the intermediate region 612, four integrations are performed, and the integrated pixel signal values ​​are halved. The image of the intermediate region 612 obtained by halving the integrated pixel signal values ​​is expected to be an image with proper exposure that makes full use of the bit width of the image data, with almost no blown out highlights or crushed shadows.

[0097] In addition, the image of the shadow region 611 obtained from the pixel signal that has been integrated four times is expected to be an image with proper exposure that utilizes the entire bit width of the image data and has almost no white blowout or black crush. In other words, if a single unit control is performed, the charge accumulation time is insufficient, resulting in an underexposed image that is prone to black crush. However, by performing integration processing over four unit controls, it is possible to achieve a substantially 4T 0 It is possible to obtain a proper image equivalent to that obtained by accumulating charges for a period of 100 s.

[0098] When such charge accumulation control is performed in this embodiment, 4T 0 Even if the subject moves across the regions during this period, the subject image does not become discontinuous at the boundary between the regions, resulting in an unnatural image. For example, even when photographing a moving car with sunlight shining on part of the car body, the trajectory of the bright spot in the photographed image does not become disconnected between the regions.

[0099] In the above control, after all integration processes are completed, a calculation is performed to reduce the pixels in the highlight region 613 to 1 / 4 and the pixels in the intermediate region 612 to 1 / 2. However, at the stage of converting each pixel signal into a digital signal and storing it in the corresponding pixel memory 414, the calculation circuit 415 may also perform a calculation to reduce the pixels in the highlight region 613 to 1 / 4 and the pixels in the intermediate region 612 to 1 / 2. In other words, a reduction calculation may be performed for each region in each pixel signal readout process. Processing in this manner will also produce the same effects as above.

[0100] Another variation will be described. In the embodiment described with reference to FIG. 8, the system control unit 501 calculates the luminance distribution of the scene from the output of the photometry unit 503 and calculates the luminance distribution of the scene in a unit time T 0 However, these can be determined without obtaining the output result of the photometry unit 503.

[0101] For example, the system control unit 501 may detect a unit time T 0 is determined. At this time, it is preferable to set the time shorter than the shutter speed for acquiring a live view image so that the highlight portion does not become overexposed. Then, when the user presses down the shutter switch SW2, which is an image capture instruction, the system control unit 501 first performs the first charge accumulation and pixel signal readout. Then, the system control unit 501 analyzes the level of the pixel signal obtained here, divides the region, and determines the number of times charge accumulation is repeated for each divided region. Specifically, for example, a region in which pixels having 50% or more of the charge that can be accumulated occupy the majority is determined as a region in which one accumulation control is completed, a region in which pixels having 25% or more but less than 50% of the charge accumulated occupy the majority is determined as a region in which two accumulation controls are completed, and a region in which pixels having less than 25% of the charge accumulated occupy the majority is determined as a region in which four accumulation controls are completed. Then, the second and subsequent charge accumulations and pixel signal readouts are continuously executed. If the control is performed in this way, it is not necessary to provide an independent photometry unit 503. Alternatively, the control using the output of the photometry unit 503 and such control can be switched according to the characteristics of the shooting mode.

[0102] Alternatively, the system control unit 501 can control the system to execute up to region division in the first charge accumulation and pixel signal readout, and determine whether or not to execute the next charge accumulation and pixel signal readout for each region after each signal readout. That is, when m (natural number) charge accumulations and pixel signal readouts are completed in a certain region, if the pixel signal value after the integration process is within a predetermined range, the system control unit 501 ends the process without executing the m+1th charge accumulation, and if not, executes the m+1th charge accumulation. Also, when n (natural number) charge accumulations and pixel signal readouts are completed in another region, if the pixel signal value after the integration process is within a predetermined range, the system control unit 501 ends the process without executing the n+1th charge accumulation, and if not, executes the n+1th charge accumulation.

[0103] In the above description, an example has been described in which the average value or the like for each unit group is calculated one by one without using the photometry results of the photometry unit 503, and whether or not further unit control is performed is determined depending on whether or not this exceeds a threshold value, but the threshold value in this control may be changed according to the number of accumulations. Specifically, the threshold value is gradually decreased as the number of accumulations increases. By gradually decreasing the threshold value, a natural image can be generated in which the brightness of the shadow area and the highlight area is not reversed.

[0104] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the description of the claims that such modifications and improvements can also be included in the technical scope of the present invention.

[0105] It should be noted that the order of execution of each process, such as operations, procedures, steps, and stages, in the devices, systems, programs, and methods shown in the claims, specifications, and drawings is not specifically stated as "before," "prior to," etc., and may be realized in any order unless the output of a previous process is used in a later process. Even if the operational flow in the claims, specifications, and drawings is explained using "first," "next," etc. for convenience, it does not mean that it is essential to perform the process in this order. [Explanation of symbols]

[0106] 100 imaging element, 101 microlens, 102 color filter, 103 passivation film, 104 PD, 105 transistor, 106 PD layer, 107 wiring, 108 wiring layer, 109 bump, 110 TSV, 111 signal processing chip, 112 memory chip, 113 imaging chip, 131 unit group, 302 transfer transistor, 303 reset transistor, 304 amplification transistor, 305 selection transistor, 306 reset wiring, 307 TX wiring, 308 decoder wiring, 309 output wiring, 310 Vdd wiring, 311 load current source, 411 multiplexer, 412 signal processing circuit, 412a CDS circuit, 412b A / D converter, 413 demultiplexer, 414 pixel memory, 415 arithmetic circuit, 420 drive control unit, 430 Timing memory, 441 sensor control unit, 442 block control unit, 443 synchronization control unit, 444 signal control unit, 500 imaging device, 501 system control unit, 503 photometry unit, 504 work memory, 505 recording unit, 506 display unit, 511 image processing unit, 512 calculation unit, 520 photographing lens, 601 shadow subject, 602 intermediate subject, 603 highlight subject, 604 window frame, 611 shadow area, 612 intermediate area, 613 highlight area

Claims

[Claim 1] A first semiconductor substrate having a first photoelectric conversion unit that converts light into electric charges and a second photoelectric conversion unit that converts light into electric charges; a second semiconductor substrate which is stacked together with the first semiconductor substrate and has a drive control unit which controls a number of times that the electric charge converted by the first photoelectric conversion unit is stored and a number of times that the electric charge converted by the second photoelectric conversion unit is stored to be different from each other; An imaging element comprising:

Images