Display device

Abstract

To provide a display device capable of increasing image quality.SOLUTION: A storage node is provided in each pixel, and the storage node can keep first data. To the first data, second data is added by capacitive coupling, and the data can be supplied to a display element. Therefore, a corrected image can be displayed on a display device. A reference potential for performing a capacitive coupling operation is supplied through a power source line or the like, thus, the first data and the second data can be supplied through a common signal line.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one aspect relates to an article, a method, or a manufacturing method. One aspect of the present invention is a process, machine, manufacture, or composition. Therefore, the present invention more specifically disclosed herein The technical field of one embodiment of the present invention is a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, device, power storage device, storage device, imaging device, driving method thereof, or manufacturing method thereof One example can be mentioned.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are one embodiment of a semiconductor device. A display device, an imaging device, or an electronic device may include a semiconductor device. [Background technology]

[0004] Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors. As another material, oxide semiconductors have been attracting attention. Examples of oxide semiconductors include: Not only oxides of single-component metals such as indium oxide and zinc oxide, but also oxides of multi-component metals It is known that In-Ga-Zn oxide (hereinafter referred to as IG) is a multi-component metal oxide. There is a lot of research being done on ZO.

[0005] Research on IGZO has revealed that, among oxide semiconductors, CAA is neither single-crystalline nor amorphous. C (c-axis aligned crystalline) structure and nc (nan A crystalline structure was found (see Non-Patent Documents 1 to 3). In Non-Patent Documents 1 and 2, a transistor is formed using an oxide semiconductor having a CAAC structure. The technology for fabricating a transistor is also disclosed. Even oxide semiconductors with low crystallinity have been shown to have minute crystals, as reported in Non-Patent Document 4 and Non-Patent Document 5. This is shown in reference 5.

[0006] Furthermore, transistors using IGZO as the active layer have extremely low off-state current (non-unique 6), and LSIs and displays that utilize these properties have been reported (Non-Patent Document 1). See patent document 7 and non-patent document 8).

[0007] In addition, a memory device using a transistor with extremely low off-state current as a memory cell is disclosed in the patent document This is disclosed in JP 2003-203363 A. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] JP 2011-119674 A [Non-patent literature]

[0009] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p.151-154 [Non-Patent Document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, p.Q3012-Q3022 [Non-Patent Document 5] S. Yamazaki, “ECS Transactions”,2014, volume 64, issue 10, p.155-164 [Non-Patent Document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p.021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p.T216-T217 [Non-Patent Document 8] S. Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, p.626-629 Summary of the Invention [Problem to be solved by the invention]

[0010] Display devices are becoming increasingly high-resolution, with 8K4K (pixel count: 7680 x 4320) resolution or Hardware capable of displaying at even higher resolutions is being developed. The introduction of HDR (High Dynamic Range) display technology, which improves image quality through adjustments, is also progressing. There is.

[0011] In order to display the image properly on a display device, it is necessary to match the image data to the resolution of the display device. For example, if the resolution of the display device is 8K4K and the image data is 4K2K (number of pixels: 3 840 x 2160), the amount of data must be converted to four times the original size to display full screen. Conversely, if the resolution of the display device is 4K2K and the image data is for 8K4K, In some cases, the data number must be converted to 1 / 4.

[0012] In addition, dedicated circuits are required to generate image data and convert the amount of data used for HDR processing. However, this also increases power consumption. At least the original image data is not converted and is displayed on the display device. It is preferable that the input signal can be input to the pixels of the input signal.

[0013] Therefore, one aspect of the present invention is to provide a display device capable of improving image quality. One of the purposes is to provide a display device that can display image data appropriately without converting the image data. One of the objectives is to provide a display device capable of HDR display. One of the purposes is to provide a display device capable of up-conversion. Another object of the present invention is to provide a display device capable of increasing the luminance of a displayed image. One of the objectives of the present invention is to provide a display device capable of displaying two images in an overlapping manner. One of the purposes of this organization is to provide

[0014] Another object is to provide a display device with low power consumption. One of the objectives is to provide a display device that is easy to use. Another objective is to provide a novel display device, etc. Another object of the present invention is to provide a method for driving the display device. Another object is to provide a novel semiconductor device or the like.

[0015] The description of these problems does not preclude the existence of other problems. It is not necessary for the embodiment to solve all of these problems. The above will become apparent from the description in the specification, drawings, claims, etc. It is possible to extract other issues from the descriptions in the patent, claims, etc. [Means for solving the problem]

[0016] One aspect of the present invention relates to a display device capable of improving image quality. The present invention relates to a display device capable of performing the above.

[0017] One embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a third transistor. a display device having a first capacitance element, a circuit block, a first wiring, and a second wiring, A device, wherein one of the source and drain of a first transistor is connected to a second transistor. and a source or drain of the second transistor. One of the drains is electrically connected to one of the electrodes of the first capacitor. the other electrode is electrically connected to one of the source and the drain of a third transistor; One of the source and the drain of the third transistor is electrically connected to the circuit block. The other of the source and the drain of the first transistor is electrically connected to a first wiring. The other of the source and the drain of the third transistor is electrically connected to the first wiring. The gate of the second transistor is electrically connected to the second wiring, and the gate of the third transistor is electrically connected to the second wiring. The gate of the display element is electrically connected to a second wiring, and the circuit block is a display device having a display element. It is located.

[0018] Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, and a first circuit. A display device having a first circuit, a second circuit, a first wiring, and a second wiring, Each of the first circuit and the second circuit includes a third transistor, a first capacitance element, and a circuit a first capacitance block, and one of the source and drain of the third transistor is connected to the first capacitance block. One electrode of the first capacitance element is electrically connected to the circuit block. The other electrode of the first capacitance element is electrically connected to the source or one of the source and drain of the first transistor is electrically connected to the other of the drain of the first transistor is electrically connected to one of the source and drain of the second transistor, and is connected to the first circuit The other of the source and the drain of the third transistor is electrically connected to the first wiring. The other of the source and the drain of the first transistor is electrically connected to the first wiring. The gate of the third transistor in the first circuit is electrically connected to the second wiring. The gate of the third transistor in the second circuit is electrically connected to the second wiring. The gate of the second transistor is electrically connected to the second wiring, and the circuit block is The display device has a display element.

[0019] The circuit block includes a fourth transistor, a fifth transistor, a second capacitance element, and a surface The display element has an organic EL element, and one electrode of the organic EL element is connected to a fifth transistor. the source or drain of the fifth transistor; The other of the drains is electrically connected to one electrode of the second capacitance element. One electrode of the first transistor is electrically connected to one of the source and drain of the fourth transistor. The gate of the fourth transistor is electrically connected to the other electrode of the second capacitor. The other electrode of the second capacitor element is electrically connected to one electrode of the first capacitor element. It is possible.

[0020] In the above configuration, the other of the source and the drain of the fourth transistor is connected to the second transistor. The source or drain of the transistor can be electrically connected to the other of the source or drain of the transistor.

[0021] The circuit block also includes a sixth transistor, a third capacitor, and a liquid crystal display as a display element. one electrode of the liquid crystal element is electrically connected to one electrode of the third capacitor element. One electrode of the third capacitor is connected to one of the source and drain of the sixth transistor. The other of the source and drain of the sixth transistor is electrically connected to the first capacitor. The capacitance element may be electrically connected to one of the electrodes of the capacitance element.

[0022] In the above structure, the other electrode of the third capacitor element is connected to the source or It can be electrically connected to the other of the drains.

[0023] The third transistor has a metal oxide in a channel formation region, and the metal oxide includes In and Zn and M (where M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd or Hf) It is preferred that Effect of the Invention

[0024] To provide a display device capable of improving image quality by using one embodiment of the present invention. Alternatively, a display device that can display image data appropriately without converting the image data can be provided. It is also possible to provide a display device capable of performing HDR display. Alternatively, a display device capable of up-conversion can be provided. It is possible to provide a display device that can enhance the brightness of an image. It is possible to provide a display device that allows overlapping displays.

[0025] Alternatively, a display device with low power consumption can be provided. Alternatively, a novel display device or the like can be provided. It is also possible to provide a method for driving the display device. It can be provided. [Brief description of the drawings]

[0026] [Figure 1] FIG. 2 is a diagram illustrating a pixel circuit. [Diagram 2] 4 is a timing chart illustrating the operation of the pixel circuit. [Diagram 3] 5A to 5C are diagrams for explaining image data correction and image synthesis. [Figure 4] FIG. 2 is a diagram for explaining a circuit block. [Diagram 5] FIG. 2 is a diagram for explaining a circuit block. [Figure 6] FIG. 2 is a diagram illustrating a pixel circuit. [Figure 7] FIG. 2 is a diagram for explaining a pixel array. [Figure 8] 4 is a timing chart illustrating the operation of the pixel array. [Figure 9] FIG. 1 is a block diagram illustrating a display device. [Figure 10] FIG. 1 is a diagram for explaining an example of the configuration of a neural network. [Figure 11] FIG. 4 is a diagram for explaining the configuration of a pixel array used in a simulation. [Figure 12] FIG. 13 is a diagram for explaining the results of a simulation. [Figure 13] FIG. 13 is a diagram for explaining the results of a simulation. [Figure 14] FIG. 13 is a diagram for explaining the results of a simulation. [Figure 15] FIG. 2 is a diagram illustrating a pixel configuration. [Figure 16] 1A and 1B are diagrams illustrating a display device. [Figure 17] FIG. 2 is a diagram illustrating a touch panel. [Figure 18] 1A and 1B are diagrams illustrating a display device. [Figure 19] 1A to 1C are diagrams illustrating transistors. [Figure 20] 1A to 1C are diagrams illustrating transistors. [Figure 21] 1A to 1C are diagrams illustrating transistors. [Figure 22] 1A to 1C are diagrams illustrating transistors. [Diagram 23] 1A to 1C are diagrams illustrating electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0027] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details thereof without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that the present invention can be modified in various ways. The present invention is not limited to the above-mentioned embodiments. In the drawings, the same reference numerals are used to designate the same parts or parts having similar functions. In addition, the same elements constituting the figures are used in the same way, and their repeated explanations may be omitted. In some cases, the patterns may be omitted or changed as appropriate between different drawings.

[0028] (Embodiment 1) In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0029] One embodiment of the present invention is a display device having a function of correcting image data in each pixel. A storage node is provided in the first data storage unit, and the first data can be stored in the storage node. The first data is added to the second data by capacitive coupling and can be supplied to the display element. Alternatively, the first data can be capacitively coupled to the storage node after the second data is written to the storage node. It can also be added with

[0030] Therefore, the display device can display a corrected image. It is possible to up-convert the image or to convert a part or the whole of the display. The image can be corrected and displayed in HDR. By using the same image data as the input data, the brightness of the displayed image can be significantly improved. Alternatively, by using different image data as the first data and the second data, Any images can be displayed in a superimposed order.

[0031] In addition, by using one embodiment of the present invention, two image data for high resolution and low resolution can be obtained. To display the image appropriately without up-conversion or down-conversion. In the case of displaying at high resolution, the first transistor of each pixel is routed to each Provides individual data to each pixel. When displaying at low resolution, multiple pixels are electrically connected. The same data is supplied to the plurality of pixels via a second transistor that corresponds to the first transistor.

[0032] Here, high-resolution image data is, for example, 8K4K (pixel count: 7680 x 4320 ) In addition, low-resolution image data corresponds to, for example, 4K2K (Number of pixels: 3840 x 2160) The ratio of the number of effective data (corresponding to the number of effective pixels) between the image data and the low-resolution image data is 4: It is assumed that the value is 1.

[0033] In addition, if the ratio of the number of data (number of pixels) is 4:1, it is not limited to the above example, and can be used for high resolution images. The image data is 4K2K, and the image data for low resolution is FullHD (number of pixels It may be data corresponding to a resolution of 1920 x 1080. Alternatively, it may be data corresponding to a resolution of 1920 x 1080. The data corresponds to 16K8K (pixel count: 15360 x 8640), and the image data corresponds to low resolution. The image data may be data corresponding to 8K4K.

[0034] FIG. 1 illustrates a pixel 10 that can be used in a display device of one embodiment of the present invention. The pixel 10 includes a transistor 101, a transistor 102, a transistor 103, and a capacitor. The circuit block 110 includes a transistor, The display element may include a capacitance element and a display element, and will be described in detail later.

[0035] The source or drain of the transistor 101 is connected to the source or drain of the transistor 102. The source or drain of the transistor 102 is electrically connected to one of the drains. One of the electrodes is electrically connected to one of the electrodes of the capacitor 104. The electrode is electrically connected to one of the source and drain of the transistor 103. Either the source or the drain of the transistor 103 is electrically connected to the circuit block 110. do.

[0036] Here, one of the source and drain of the transistor 103 and the other of the capacitor 104 The pole and the wiring to which the circuit block 110 is connected are called nodes NM. The element of the circuit block 110 that connects to the node NM can be floated. do.

[0037] The gate of the transistor 101 is electrically connected to the wiring 122. The gate of the transistor 102 and the gate of the transistor 103 are electrically connected to a wiring 121. The other of the source or drain of the transistor 101 and the other of the source or drain of the transistor 103 The other of the drains is electrically connected to the wiring 123. The other end of the drain is electrically connected to a wiring that can supply a specific potential “Vref”. To be continued.

[0038] The wirings 121 and 122 function as signal lines for controlling the operation of the transistors. The wiring 123 can be used as a signal line for supplying the first data or the second data. The wiring that can supply "Vref" is, for example, For example, a power supply line electrically connected to the elements of the circuit block 110 can be used.

[0039] In order to perform the capacitive coupling operation described later, the pixel is supplied with “Vref” and the first data ( For example, correction data) must be supplied during the same period. When supplying from a line, at least the signal line that supplies the first data and the "Vref" Alternatively, a signal line for supplying second data (eg, image data) is required.

[0040] On the other hand, in the display device of one embodiment of the present invention, “Vref” is supplied from a power supply line or the like. By switching the timing, the first data supply or the second data supply can be This can be done from the signal line (wiring 123). In other words, it can be configured with a small number of wirings. can.

[0041] The node NM is a storage node. When the transistor 103 is turned on, The supplied data can be written to the node NM. Also, the transistor 103 is turned off. By making the transistor 10 conductive, the data can be held in the node NM. 3. By using a transistor with extremely low off-state current, the potential of the node NM can be maintained for a long time. In the transistor, for example, a metal oxide is used as a channel forming region. The transistors used in the above-mentioned embodiment (hereinafter referred to as OS transistors) can be used.

[0042] In addition to the transistor 103, the OS transistor is also used for other transistors constituting the pixel. In addition, the transistor 103 may have a Si channel region. Alternatively, an OS transistor may be used. Alternatively, both a silicon transistor and a silicon transistor may be used. , amorphous silicon transistors, crystalline silicon (typically low-temperature polysilicon Examples include transistors using silicon (polysilicon, single crystal silicon).

[0043] The semiconductor material used for the OS transistor is preferably a material having an energy gap of 2 eV or more. Alternatively, a metal oxide having a polarization of 2.5 eV or more, more preferably 3 eV or more, can be used. A typical example is an oxide semiconductor containing indium. -OS or CAC-OS can be used. CAAC-OS forms a crystal. The atoms are stable, making it suitable for transistors where reliability is important. Since it exhibits high mobility characteristics, it is suitable for use in transistors that operate at high speed.

[0044] Since the OS transistor has a large energy gap, it exhibits extremely low off-state current characteristics. In addition, OS transistors have the following drawbacks: impact ionization, avalanche breakdown, and short-channel Unlike silicon transistors, it has characteristics such as no effect on the semiconductor, and can form highly reliable circuits. It can be achieved.

[0045] The semiconductor layer of the OS transistor is made of, for example, indium, zinc, and M (aluminum). , titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium In-M-Zn oxides containing metals such as tin, neodymium, or hafnium The membrane can be made of a material having a thickness of 100 nm or less.

[0046] When the oxide semiconductor constituting the semiconductor layer is an In-M-Zn oxide, the In-M-Zn oxide The atomic ratio of metal elements in the sputtering target used to deposit a film is In≧M It is preferable that Zn≧M is satisfied. The atomic ratios are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In :M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4. 1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5: The atomic ratio of the semiconductor layers to be formed is preferably 1:8 or the like. This includes a ±40% variation in the atomic ratio of metal elements contained in the ring target.

[0047] The semiconductor layer is made of an oxide semiconductor having a low carrier density. Carrier density is 1×10 17 / cm 3 Less than or equal to 1×10 15 / cm 3 Further details are below. Preferably 1 x 10 13 / cm 3 Less than or equal to 1×10 11 / cm 3 The following is further Preferably 1 x 10 10 / cm 3 Less than 1 x 10 -9 / cm 3 More than career secrets Such an oxide semiconductor can be a high-purity intrinsic or The oxide semiconductor is called a substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and It can be said that the oxide semiconductor has stable characteristics.

[0048] In addition, the semiconductor characteristics and electrical characteristics (field effect) of the required transistors are not limited to these. It is sufficient to use a material with an appropriate composition according to the required properties (e.g., the resultant mobility, threshold voltage, etc.). In order to obtain the semiconductor characteristics of a transistor, the carrier density, impurity concentration, and defect density of the semiconductor layer are determined. It is preferable to appropriately set the density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. stomach.

[0049] In the oxide semiconductor that constitutes the semiconductor layer, silicon and carbon, which are group 14 elements, If oxygen is included, oxygen vacancies increase and the semiconductor layer becomes n-type. The concentrations of cations and carbon (obtained by secondary ion mass spectrometry) were calculated using a ratio of 2×10 18 atom s / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0050] In addition, alkali metals and alkaline earth metals generate carriers when bonded to oxide semiconductors. This may result in an increase in the off-state current of the transistor. The concentration of alkali metals or alkaline earth metals in the conductor layer (measured by secondary ion mass spectrometry) The concentration that can be obtained is 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 a toms / cm 3 To the following:

[0051] In addition, when the oxide semiconductor constituting the semiconductor layer contains nitrogen, the electrons that serve as carriers This increases the carrier density and makes it easier to become n-type. Transistors using conductors tend to be normally-on. The nitrogen concentration (obtained by secondary ion mass spectrometry) was 5×10 18 atoms / cm 3 It is preferable to do the following:

[0052] The semiconductor layer may also have a non-single crystal structure. The non-single crystal structure may have a c-axis oriented structure. CAAC-OS (C-Axis Aligned Crystalline ne Oxide Semiconductor), polycrystalline, microcrystalline, or non-crystalline Among non-single crystal structures, the amorphous structure has the highest defect level density and CAA C-OS has the lowest density of defect states.

[0053] An oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and does not contain a crystalline component. Alternatively, the oxide film having an amorphous structure is, for example, a completely amorphous structure having no crystal parts. stomach.

[0054] In addition, the semiconductor layer may have an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC structure region, or a crystalline structure region. The film may be a mixed film having two or more of the -OS region and the single crystal structure region. The film may have a single layer structure including two or more of the above-mentioned regions, or a laminate structure. It may have a structure.

[0055] In the following, we will discuss a CAC (Cloud-Aligned Crystalline) semiconductor layer, which is one form of a non-single crystal semiconductor layer. This article explains the configuration of the omposite OS.

[0056] CAC-OS is, for example, an oxide semiconductor in which the elements constituting the oxide semiconductor are 0.5 nm to 10 nm. Preferably, the material is unevenly distributed in a size range of 1 nm to 2 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are present in the oxide semiconductor. The region having the metal element is unevenly distributed and has a size of 0.5 nm to 10 nm, preferably 1 nm A mixture of particles with sizes of 2 nm or more or less, or close to that size, in a mosaic or patch pattern It is also called.

[0057] Note that the oxide semiconductor preferably contains at least indium. In addition to these, aluminum, gallium, yttrium, and zinc are preferably contained. Thorium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Contains one or more of the following: tantalum, tungsten, or magnesium. It may be included.

[0058] For example, CAC-OS made of In-Ga-Zn oxide (In-Ga-Zn oxide is one of the CAC-OS) a-Zn oxide may be specifically referred to as CAC-IGZO. (Hereinafter, InO X1 (X1 is a real number greater than 0.) or indium zinc oxide In X2 Zinc Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) ) and gallium oxide (GaO X3 (X3 is a real number greater than 0) . ) or gallium zinc oxide (Ga X4 Zinc Y4 O Z4 (X4, Y4, and Z4 is a real number greater than 0.) The material is separated into a mosaic shape. Mosaic InO X1 , or In X2 Zinc Y2 O Z2 was distributed uniformly in the film. This is a cloud-like configuration.

[0059] In other words, CAC-OS isX3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 A composite oxide semiconductor having a structure in which a region in which In this specification, for example, the atomic ratio of In to the element M in the first region is is greater than the atomic ratio of In to the element M in the second region. Assume that the In concentration is higher than in region 2.

[0060] IGZO is a common name and refers to a compound made of In, Ga, Zn, and O. A typical example is InGaO 3 (ZnO) m1 (m1 is a natural number), or In ( 1+x0) Ga (1-x0) O 3 (ZnO) m0 (-1≦x0≦1, m0 is an arbitrary number) Examples of the crystalline compounds include those which are

[0061] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a structure in which multiple IGZO nanocrystals have a c-axis orientation and are aligned in the ab plane. is a non-oriented connected crystal structure.

[0062] On the other hand, CAC-OS refers to the material composition of oxide semiconductors. In a material composition containing a, Zn, and O, some of the nanoparticles are observed to be mainly composed of Ga. The regions where the In nanoparticles are observed are the same as those where the In nanoparticles are observed as the main component. This refers to a structure in which the pixels are randomly distributed in a mosaic pattern. The crystal structure is a secondary factor.

[0063] It should be noted that the CAC-OS does not include a laminated structure of two or more films having different compositions. For example, a structure consisting of two layers, a film mainly made of In and a film mainly made of Ga, is not included. do not have.

[0064] In addition, GaO X3 The region where In is the main component and X2 Zinc Y2 O Z2 , or InO X1 but In some cases, a clear boundary between the region of the main component and the region of the main component may not be observed.

[0065] Instead of gallium, aluminum, yttrium, copper, vanadium, and beryllium can be used. , boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum , lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium If one or more selected types of sodium, etc. are included, CAC-OS will The region observed is a nanoparticle of the metal element as the main component, and the region observed is a nanoparticle of In as the main component. The nanoparticle-like regions are randomly distributed in a mosaic pattern. say.

[0066] CAC-OS is formed by sputtering without intentionally heating the substrate. In addition, when the CAC-OS is formed by a sputtering method, the deposition gas and The gas is selected from an inert gas (typically argon), oxygen gas, and nitrogen gas. One or more of these may be used. The lower the flow rate ratio of the gas, the more preferable. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%. Or, it is preferable to set it to 0% or more and 10% or less.

[0067] CAC-OS is a type of X-ray diffraction (XRD) measurement method. When measured using the θ / 2θ scan by the out-of-plane method, In other words, no clear peaks are observed from the X-ray diffraction measurement. It can be seen that the orientation of the regions in the ab plane direction and the c-axis direction is not observed.

[0068] In addition, CAC-OS uses an electron beam with a probe diameter of 1 nm (also called a nanobeam electron beam). In the electron beam diffraction pattern obtained by irradiating the sample, a ring-shaped region of high brightness and the corresponding Several bright spots are observed in the ring region. Therefore, the electron diffraction pattern indicates that the CAC- The crystal structure of OS has no orientation in the planar and cross-sectional directions. It can be seen that the crystalline structure is o-crystal.

[0069] For example, in the CAC-OS of In-Ga-Zn oxide, the energy dispersive X Energy Dispersive X-ray spectroscopy (EDX) The EDX mapping obtained using scopy revealed that GaO X3 The area where is the main component And, In X2 Zinc Y2 O Z2 , or InO X1 The areas where the main component is It can be confirmed that the compound has a structure similar to that shown in FIG.

[0070] CAC-OS has a structure different from that of IGZO compounds in which metal elements are uniformly distributed. It has different properties from ZO compounds. That is, CAC-OS is GaO X3 The main ingredients are In a certain area,X2 Zinc Y2 O Z2 , or InO X1 The region where is the main component and The phase is separated into two layers, and the regions each containing one element as a main component are arranged in a mosaic pattern.

[0071] Here, In X2 Zinc Y2 O Z2 , or InO X1 The area where GaO is the main component X3 This region has a higher electrical conductivity than the region where In is the main component. X2 Zinc Y 2 O Z2 , or InO X1 The carriers flow through the area where the main component is oxidized. Therefore, the In X2 Zinc Y2 O Z2 , or In O X1 The region in which the main component is distributed in a cloud-like shape in the oxide semiconductor is a region in which a high electric field Effective mobility (μ) can be achieved.

[0072] On the other hand, GaO X3 The region where the main components are In X2 Zinc Y2 O Z2 , or InO X 1 This region has higher insulating properties than the region where GaO is the main component. X3 etc. The distribution of the main component in the oxide semiconductor suppresses leakage current and provides good switching performance. Switching operation can be achieved.

[0073] Therefore, when CAC-OS is used in a semiconductor device, GaO X3 Insulation caused by And, InX2 Zinc Y2 O Z2 , or InO X1 The conductivity caused by the This results in a high on-state current (I on ) and high field-effect mobility (μ This can be done.

[0074] In addition, semiconductor devices using CAC-OS have high reliability. , and is suitable as a constituent material for various semiconductor devices.

[0075] Correction data is added to image data using the timing charts shown in Figures 2(A) and 2(B). In the following description, a high potential is referred to as “H” and Low potential is represented by "L". Correction data is represented by "Vp", image data is represented by "Vs", and specific potential is represented by "Vp". The reference voltage is designated as "Vref". "Vref" can be, for example, 0V, GND potential, or a specific A reference potential can be used. Note that "Vp" is an arbitrary first data, and "Vs" is an arbitrary It can also be said to be the second data.

[0076] First, the operation of writing the correction data "Vp" to the node NM will be described with reference to FIG. In addition, in the distribution, coupling, or loss of potential, the circuit configuration, operation timing, etc. The detailed changes due to capacitive coupling are not taken into account. However, for clarity, the capacitance of node NM is assumed to be sufficiently small. Assume that.

[0077] At time T1, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When "Vp" is selected, the transistor 102 is turned on, and the potential of one electrode of the capacitor 104 is This operation is a reset for the later correction operation (capacitive coupling operation). It is an action.

[0078] In addition, the transistor 103 is turned on, and the potential of the wiring 123 (correction data “Vp ") is written.

[0079] At time T2, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", the potential of the wiring 123 is set to "L", When the transistor 102 and the transistor 103 are turned off, the node The compensation data "Vp" is stored in the NM. Also, the capacitance element 104 stores "Vp-Vref " is retained.

[0080] This is the write operation of the correction data "Vp". If correction is not performed, In the above operation, the same potential as "Vref" may be supplied as the correction data "Vp".

[0081] Next, referring to FIG. 2B, the correction operation of the image data “Vs” and the circuit block 110 The display operation of the display element included in the liquid crystal display device will be described.

[0082] The operations in FIG. 2(A) and (B) can be performed consecutively within one horizontal period. The action in (A) is performed in the kth frame (k is a natural number), and the action in (B) in Fig. 2 is performed in the k+1th frame. Alternatively, after the operation in FIG. 2(A), the operation in FIG. 2(B) may be performed multiple times. This is also fine.

[0083] At time T11, the potential of the wiring 121 is set to “L”, the potential of the wiring 122 is set to “H”, and the potential of the wiring 123 is set to “L”. When Vs is set as "Vs", the transistor 101 becomes conductive, and the capacitance of the capacitance element 104 causes a The potential "Vs" of the wiring 123 is added to the potential of the node NM. is "Vp-Vref+Vs", and if "Vref"=0, the potential of the node NM is The result is “Vp+Vs”.

[0084] At time T12, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When the potential of the node NM is set to "L", the transistor 103 is turned off and the potential of the node NM is set to "Vp+ Vs”.

[0085] Thereafter, in the display element of the circuit block 110, a display according to the potential of the node NM is Depending on the configuration of the circuit block, the display may start from time T1 or time T11. Sometimes an action is performed.

[0086] Here, the image data correction operation will be described with reference to FIG.

[0087] The diagram shown in FIG. 3A shows four pixels (P1 to P4) in the horizontal and vertical directions. The input image data (Vs1, Vs2, Vs3), the input correction data (+Vp1, V p0, -Vp1) are the corrected image data to be generated. In a display element, when the potential of the image data is relatively high, the display is high brightness, and when it is low, the display is low brightness. This can be done.

[0088] For example, in the pixel P1, positive correction data “+Vp When "1" is applied, the image data becomes "Vs1+Vp1" and the luminance increases. 2 and P3, the correction data “ When "Vp0" is applied, the image data becomes "Vs2+Vp0=Vs1" and the brightness does not change. At pixel P4, negative correction data “-V When "Vs1-Vp1" is applied, the image data becomes "Vs1-Vp1", and the luminance decreases.

[0089] In this combination of image data and correction data, R display, correction of display irregularities inherent to the display device, compensation of the threshold voltage of the transistors in the pixels It is possible to carry out such operations.

[0090] In an up-conversion operation, for example, the same image data is supplied to all four pixels. For example, the number of pixels for 8K4K can be For a specific pixel of a display device having 4K2K pixels, It is possible to input data used in the image processing and display it at improved resolution.

[0091] In a broad sense, it is a correction of image data, but it is also possible to display different images by overlaying them. FIG. 3(B) shows the image on the entire display unit, with the image data “Vs” being the a first image composed of correction data “Vp”; a second image composed of the first image and the second image is the composite image.

[0092] In such a combination of image data and correction data, different images can be synthesized and displayed. In addition, it is possible to improve the brightness of the entire displayed image. For example, it is possible to insert characters or AR (A This technology can be applied to 3D immersive reality (3D immersive reality) displays, etc.

[0093] 4A to 4C are applicable to the circuit block 110 and include an EL element as a display element. This is an example of a configuration that includes:

[0094] The structure shown in FIG. 4A includes a transistor 111, a capacitor 113, and an EL element 114. One of the source and drain of the transistor 111 is connected to one of the EL elements 114. One electrode of the EL element 114 is electrically connected to one electrode of the capacitor 113. The other electrode of the capacitor 113 is electrically connected to the gate of the transistor 111. The gate of the transistor 111 is electrically connected to a node NM. do.

[0095] The other of the source and the drain of the transistor 111 is electrically connected to the wiring 128. The other electrode of the EL element 114 is electrically connected to a wiring 129. For example, the wiring 128 can supply high potential power. In addition, the wiring 129 can supply a low potential power source.

[0096] Here, the source or drain of the transistor 103 for supplying “Vref” shown in FIG. The other drain can be electrically connected to the wiring 128. “Vref” is 0V, Since it is preferable that the potential is GND or a low potential, the wiring 128 is at least one of these potentials. The wiring 128 also has a function of supplying either one of the following: At the timing when the EL element 114 emits light, a high potential is supplied. All you have to do is provide power.

[0097] In the configuration shown in FIG. 4A, the potential of the node NM is equal to or higher than the threshold voltage of the transistor 111. When this occurs, a current flows through the EL element 114. In some cases, the EL element 114 may start emitting light at time T1 in the timing chart, and this may limit the applications. This can sometimes happen.

[0098] FIG. 4B shows a configuration in which a transistor 112 is added to the configuration of FIG. One of the source or drain of the transistor 112 is connected to the source or drain of the transistor 111. The other of the source and drain of the transistor 112 is electrically connected to The gate of the transistor 112 is electrically connected to the wiring 126. The wiring 126 serves as a signal line for controlling the conduction of the transistor 112. It can have a function.

[0099] In this configuration, the potential of the node NM is equal to or higher than the threshold voltage of the transistor 111. When the transistor 112 is conductive, a current flows through the EL element 114. The EL element 114 starts emitting light after time T12 in the timing chart shown in FIG. This makes it suitable for operations involving correction.

[0100] FIG. 4C shows a configuration in which a transistor 115 is added to the configuration of FIG. 4B. One of the source or drain of the transistor 115 is connected to the source or drain of the transistor 111. The other of the source and drain of the transistor 115 is electrically connected to The gate of the transistor 115 is electrically connected to the wiring 131. The wiring 131 functions as a signal line for controlling the conduction of the transistor 115. Note that the gate of the transistor 115 is electrically connected to the wiring 122. This may continue.

[0101] The wiring 130 can be electrically connected to a source of a particular potential, such as a reference potential. A specific potential is applied to either the source or drain of the transistor 111 from the line 130. This also makes it possible to stabilize the writing of image data.

[0102] In addition, the wiring 130 can be connected to the circuit 120 and has a function as a monitor line. The circuit 120 controls the specific potential sources and the electrical characteristics of the transistor 111. The correction data generating unit may have one or more of the functions of acquiring and generating correction data.

[0103] When the wiring 130 is made to function as a monitor line, the above-mentioned correction data “Vp” is A potential for correcting the threshold voltage of the transistor 111 can be generated by the circuit 120 .

[0104] 5A to 5C are applicable to the circuit block 110 and include a liquid crystal element as a display element. This is an example of a configuration that includes:

[0105] The structure shown in FIG. 5A includes a capacitor 116 and a liquid crystal element 117. One electrode of the capacitor 7 is electrically connected to one electrode of the capacitor 116. One electrode of the transistor is electrically connected to a node NM.

[0106] The other electrode of the capacitor 116 is electrically connected to the wiring 132. One electrode is electrically connected to a wiring 133. The wirings 132 and 133 serve to supply power. For example, the wirings 132 and 133 can be connected to a reference potential such as GND or 0V or an arbitrary potential. can be supplied.

[0107] Here, the source or drain of the transistor 103 for supplying “Vref” shown in FIG. The other drain can be electrically connected to the wiring 132 .

[0108] In this configuration, when the potential of the node NM becomes equal to or higher than the threshold voltage for operating the liquid crystal element 117, the liquid crystal element The operation of the crystal element 117 is started. Therefore, in the timing chart shown in FIG. The display operation may start at time T1, and the usage may be limited. However, In the case of a transmissive liquid crystal display device, the backlight is turned off until time T12 shown in FIG. 2(B). By using these actions in combination, it is possible to suppress the visibility of unnecessary display actions. do.

[0109] FIG. 5B shows a configuration in which a transistor 118 is added to the configuration of FIG. 5A. One of the source and drain of the transistor 118 is electrically connected to one electrode of the capacitor element 116. The other of the source and drain of the transistor 118 is electrically connected to the node NM. The gate of the transistor 118 is electrically connected to the wiring 126. 26 can function as a signal line for controlling the conduction of the transistor 118. .

[0110] In this configuration, when the transistor 118 is turned on, the potential of the node NM is applied to the liquid crystal element 117. Therefore, the liquid crystal display 100 changes from the time T12 onward in the timing chart shown in FIG. The operation of the element can be started and is suitable for operation with correction.

[0111] When the transistor 118 is off, the capacitance element 116 and the liquid crystal element 117 are not supplied with Since the supplied potential is held, the capacitor elements 116 and It is preferable to reset the potential supplied to the liquid crystal element 117. For example, a reset potential is supplied to the wiring 123, and the transistors 103 and 118 are turned on. are simultaneously brought into conduction.

[0112] FIG. 5C shows a configuration in which a transistor 119 is added to the configuration of FIG. 5B. One of the source and drain of the transistor 119 is electrically connected to one electrode of the liquid crystal element 117. The other of the source and the drain of the transistor 119 is electrically connected to a wiring 130. The gate of the transistor 119 is electrically connected to the wiring 131. The reference numeral 31 can function as a signal line for controlling the conduction of the transistor 119 . Note that the gate of the transistor 119 may be electrically connected to the wiring 122.

[0113] The circuit 120 electrically connected to the wiring 130 is similar to that described above with reference to FIG. In addition, the potential supplied to the capacitor element 116 and the liquid crystal element 117 is reset. It may be possible.

[0114] In addition, although Figures 4 and 5 show examples where "Vref" is supplied from the power supply line, it can also be supplied from the scan line. For example, as shown in FIG. 6A, “Vref” can be supplied from the wiring 122. As shown in FIG. 6A, when the correction data is written (the transistor 103 When the line 122 is turned on, a potential corresponding to "L" is supplied to the line 122. ef" can be used.

[0115] As shown in FIG. 6B and FIG. 6C, the transistors 101, 102, and 103 are back-coupled. FIG. 6B shows a structure in which a back gate is electrically connected to the front gate. FIG. 6(C) shows a structure in which the transistors are electrically connected to each other, which has the effect of increasing the on-state current. The gate is electrically connected to a wiring 134 that can supply a constant potential. The threshold voltage of the transistor can be controlled. The transistors included in the circuit blocks 110 shown in FIGS. may be provided.

[0116] FIG. 7 shows a part (four pixels) of a pixel array having a pixel 11 to which the basic configuration of pixel 10 is applied. The pixel 11 includes a transistor 103, a capacitor 104, and a circuit block. In addition, the n and m in the parentheses attached to the reference numerals indicate a specific row, and the i indicates a specific column. (n, m, and i are natural numbers).

[0117] The pixels 11 are arranged in a matrix, and the pixels in the nth row and the ith column, the nth row and the (i+x)th column (x is natural number), they can be placed in the (n+1)th row, i-th column and the (n+1)th row, (i+x)th column. In addition, FIG. 7 shows the arrangement when x=1.

[0118] The pixel array also includes a transistor 101 electrically connected to four pixels 11, Transistor 102a and transistor 102b are provided. 02b has the function of the transistor 102 in the pixel 10.

[0119] The transistor 101 is an element of each pixel 11 and is shared by four pixels. The transistor 102a is connected to the pixel 11[n,i] and the pixel 11[n,i+1]. The transistor 102b is an element of the pixel 102 and is shared by the two pixels. 11[n+1,i] and pixel 11[n+1,i+1], which are common to both pixels. In other words, the transistors 101, 102a, and 102b each have one of the following characteristics. They may be distributed over the pixel region.

[0120] In each pixel 11, one of the source and drain of the transistor 103 is connected to a capacitance element 1 One electrode of the capacitor 104 is electrically connected to one electrode of the capacitor 104. The other electrode of the capacitor 104 is electrically connected to the source electrode 110 of the transistor 101. The source or drain of the transistor 101 is electrically connected to One of the drains is electrically connected to one of the source and drain of the transistor 102a. In addition, one of the source and drain of the transistor 101 is connected to the transistor 102. b is electrically connected to either the source or drain of b.

[0121] In this pixel array, the number of wirings and It is possible to perform some of the same operations with a smaller number of transistors.

[0122] In addition, even if the resolution of the display device and the image data are different, the image data and the correction data can be By switching the input path of the data, it is possible to up-convert or down-convert the signal. Appropriate display can be provided without any problem.

[0123] Using the timing charts shown in (A1) and (A2) of FIG. 8, different An example of the operation of writing data for a pixel count of 8K4K will be described. When inputting high resolution image data (8K4K data), Although the description will be given for one pixel 11, the other pixels 11 operate in the same manner. can be applied.

[0124] In the following explanation, high potential is referred to as “H”, low potential is referred to as “L”, and a specific potential between high potential and low potential is referred to as “L”. The potential is represented by "M". Note that "M" is a reference potential such as 0V or GND. However, other potentials are also acceptable. ", and the correction data for high resolution is "Vp1". Note that "Vp1" is an arbitrary first data The data "VsH" can also be considered as an arbitrary second data.

[0125] First, the operation of writing image data "VsH" to the node NM will be described with reference to FIG. In addition, the distribution, coupling, or loss of potential is affected by the circuit configuration and operation timing. Detailed changes due to factors such as the above are not taken into account.

[0126] At time T1, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When the voltage is set to “VsH”, the transistor 102 is turned on, and the potential of the other electrode of the capacitor 104 This operation is a reset for the subsequent correction operation (capacitive coupling operation). This is a fast operation.

[0127] In addition, the transistor 103 is turned on, and the potential of the wiring 123 (image data “Vs H”) is written.

[0128] At time T2, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", the potential of the wiring 123 is set to "L", When the transistor 102 and the transistor 103 are turned off, the The image data "VsH" is stored in the node NM. ef” is retained.

[0129] This is the write operation of the image data "VsH". Next, using FIG. 8(A2), , the correction operation of the image data “VsH” and the display on the display element of the circuit block 110 The operation will be described.

[0130] The operations of (A1) and (A2) in FIG. 8 can be performed continuously within one horizontal period. The operation of FIG. 8(A1) is performed in the kth frame (k is a natural number), and the operation of FIG. 8(A2) is performed in the kth frame. It may be performed in the +1 frame. Or, after the operation of FIG. 8(A1), the operation of FIG. 8(A2) may be performed. may be performed multiple times.

[0131] At time T11, the potential of the wiring 121 is set to “L”, the potential of the wiring 122 is set to “H”, and the potential of the wiring 123 is set to “L”. When Vp1 is set as "Vp1", the transistor 101 becomes conductive, and the capacitance of the capacitance element 104 The potential "Vp1" of the wiring 123 is added to the potential of the node NM. The potential is “VsH-Vref+Vp1”, and if “Vref”=0, then the The potential is "VsH+Vp1". If no correction is made, the above operation is as follows: The same potential as "Vref" may be supplied as the correction data "Vp1".

[0132] At time T12, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When the potential of the node NM is set to "M", the transistor 101 is turned off and the potential of the node NM is set to "VsH+ Vp1”.

[0133] Thereafter, in the display element of the circuit block 110, a display according to the potential of the node NM is Depending on the configuration of the circuit block, the display may start from time T1 or time T11. Sometimes an action is performed.

[0134] By performing correction using selected pixels in this way, HDR display and the like can be achieved. The correction data "Vp1" has the same value for all four pixels, but to achieve the visual effect of light and dark, In addition, when no correction is performed, the potential of the wiring 123 is set to " Alternatively, the potential of the wiring 122 may be set to "L" to keep the transistor 101 should not be conductive.

[0135] Next, using the timing charts shown in FIG. 8(B1) and (B2), the four pixels 11 are simultaneously This operation is for example for a pixel count of 8K4K. A display device that is suitable for inputting low-resolution image data (4K2K data). do.

[0136] First, the operation of writing the correction data “Vp2” to the node NM will be described with reference to FIG. In the following, the image data for low resolution is called "VsL" and the correction data for low resolution is called "Vp 2". Note that "Vp2" is any first data, and "VsL" is any second data. It is also possible to say that.

[0137] At time T1, the potential of the wiring 121 is set to "H", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When “Vp2” is selected, the transistor 102 is turned on, and the potential of the other electrode of the capacitor 104 This operation is a reset for the subsequent correction operation (capacitive coupling operation). This is a fast operation.

[0138] In addition, the transistor 103 is turned on, and the potential of the wiring 123 (correction data “Vp 2") is written.

[0139] At time T2, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", the potential of the wiring 123 is set to "L", When the transistor 102 and the transistor 103 are turned off, the node The correction data "Vp2" is stored in the NM. ef” is retained.

[0140] This is the write operation of the correction data "Vp2". If correction is not performed, In the above operation, the same potential as "Vref" should be supplied as the correction data "Vp2". .

[0141] Next, referring to FIG. 8(B2), the correction operation of the image data “VsL” and the circuit block 1 The display operation of the display element 10 will now be described.

[0142] The operations of (B1) and (B2) in FIG. 8 can be performed continuously within one horizontal period. 8(B1) is performed in the kth frame, and the operation of FIG. 8(B2) is performed in the k+1th frame. Alternatively, after the operation of FIG. 8(B1), the operation of FIG. 8(B2) may be performed multiple times. good.

[0143] At time T11, the potential of the wiring 121 is set to “L”, the potential of the wiring 122 is set to “H”, and the potential of the wiring 123 is set to “L”. When the potential VsL is set to "VsL", the transistor 101 becomes conductive, and the capacitance of the capacitance element 104 The potential of the wiring 123, “VsL”, is added to the potential of the node NM. The potential is “Vp2-Vref+VsL”. If “Vref”=0, then the potential of node NM The potential becomes "Vp2+VsL."

[0144] At time T12, the potential of the wiring 121 is set to "L", the potential of the wiring 122 is set to "L", and the potential of the wiring 123 is set to "L". When the potential of the node NM is set to "Vp2+ VsL”.

[0145] Thereafter, in the display element of the circuit block 110, a display according to the potential of the node NM is Depending on the configuration of the circuit block, the display operation may start from time T11. There are also.

[0146] As the correction data “Vp2”, a different value can be input to each pixel 11. Even if the image data "VsL" is the same, each pixel 11 can display different images. In other words, up-conversion is possible. Note that if no correction is performed, the same image is produced using four pixels. is displayed.

[0147] By operating as described above, the original image data can be displayed on the display without being up-converted. The image can be input to the device and displayed appropriately. It is possible to do the right thing.

[0148] FIG. 9A is an example of a block diagram of a display device of one embodiment of the present invention. A pixel array 12 in which pixels 11 are arranged in a matrix, a row driver 13, and a column driver The driver 14, the circuit 15, and the selection circuit 16 are included. The transistor 102a and the transistor 102b are represented as one block, and a potential "Vref" is provided. The connection form with the wiring that supplies the power is omitted.

[0149] The row driver 13 is, for example, a combination of a shift register 20 and a buffer circuit 21. By controlling the conduction of the buffer circuit 21, the wiring 121 Alternatively, data can be output to wiring 122.

[0150] The column driver 14 is, for example, a combination of a shift register 22 and a buffer circuit 23. By controlling the conduction of the buffer circuit 23, the wiring 12 3 can output data.

[0151] The circuit 15 has a function of generating correction data. It can also be considered an external device for

[0152] The row driver 13 controls the conduction of the transistor 101 and the transistors 102a and 102b. The column driver 14 controls the wiring 123 to transmit correction data or image data. The data can be supplied.

[0153] The circuit 15 receives image data “VsH” for high resolution (for example, 8K4K data) or Image data for resolution "VsL" (for example, 4K2K data) is input. Image data When "VsH" is input, correction data "Vp1" is generated, and image data "VsL" is input, correction data "Vp2" is generated.

[0154] The selection circuit 16 selects the correction data “Vp1” and “Vp2” generated by the circuit 15 as well as the external Correction data "Vp1", "Vp2" or image data "VsH", "VsL" generated by can be output to the column driver 14.

[0155] In the configuration shown in FIG. 9A, for example, when performing a display operation without correction at a low resolution, each driver This allows the number of output stages of the amplifier to be halved, thereby reducing power consumption.

[0156] The circuit 15 may include a neural network. For example, By using a deep neural network trained as the data, highly accurate correction data can be obtained. Data can be generated.

[0157] As shown in Fig. 10(A), the neural network NN has an input layer IL, an output layer OL, and a middle layer OL. It can be composed of an input layer IL, an output layer OL, and an intermediate layer H Each L has one or more neurons (units). It may be a single layer or two or more layers. The network can also be called a DNN (deep neural network), Learning using neural networks can also be called deep learning.

[0158] Input data is input to each neuron in the input layer IL, and previous data is input to each neuron in the hidden layer HL. The output signal of the neurons in the layer OL or the next layer is input, and each neuron in the output layer OL receives the output signal of the neurons in the previous layer. The output signal of the neuron is input. Each neuron is connected to all the neurons in the previous and next layers. A neuron may be connected to all neurons (full connection) or may be connected to only a portion of neurons.

[0159] FIG. 10(B) shows an example of a computation by a neuron. Here, we consider a neuron N and The figure shows two neurons in the front layer that output signals to neuron N. Neuron N has a The output of the neuron x 1 and the output of the previous layer neuron x 2 is entered. Then, At Ron N, the output x 1 and weight w 1 The multiplication result (x 1 w 1 ) and output x 2 and weight w 2 to the power of Calculation result(x 2 w 2 ) x 1 w 1 +x 2 w 2 After is calculated, the bias b is added, the value a=x 1 w 1 +x 2 w 2 +b is obtained. Then, the value a is applied to the activation function h. Thus, the neuron N outputs the output signal y=h(a).

[0160] In this way, the operation of a neuron involves adding up the products of the outputs of the neurons in the previous layer and the weights. This includes operations that multiply and add together (the x 1 w 1 +x 2 w 2 ). This multiply-and-accumulate operation is This may be done on software using a program, or on hardware. When the multiplication and accumulation is performed by hardware, a multiplication and accumulation circuit can be used. The multiplication and accumulation circuit may be a digital circuit or an analog circuit. Good too.

[0161] The multiply-and-accumulate circuit may be constructed using Si transistors or OS transistors. In particular, since the off-state current of the OS transistor is extremely small, The Si transistor is suitable for use as a transistor for forming an analog memory of a semiconductor device. A product-sum circuit may be configured using both the LTC3111 and OS transistors.

[0162] The correction data can be generated not only by the circuit 15 but also by the circuit 120 described above ( (See FIG. 9(B)). Also, a grayscale display is performed on the display unit, and the brightness of the display is Generate correction data based on the data read by the meter or the data read from the photo of the display. Also, a sensor 24 capable of detecting the brightness of the display may be provided to detect and compensate for deterioration of the display element. A circuit 25 capable of generating correct data may be provided (see FIG. 9(C)).

[0163] Next, a configuration in which the circuit block shown in FIG. 4(A) is applied to the pixel array shown in FIG. 7 (see FIG. 11) will be described. The simulation results of the above are explained. The parameters are as follows: The size is L / W=6μm / 6μm (transistor 111), L / W=4μm / 4μm (other other transistors), the capacitance of the capacitance element 104 is 150 fF, the capacitance of the capacitance element 113 is 5 0fF, EL element 114 is an FN diode model, and wiring 128 is an anode potential of +1 0V, +1V as “Vref”, wire 129 is -5V as cathode potential, image data The minimum and maximum values ​​of the compensation data were set to +1V and +8V, respectively. The simulation software used was SPICE.

[0164] 12(A) to (C) show the simulation results verifying high resolution display (without correction). FIG. 12(A) is a timing chart used for the verification. By turning on the transistor 103 at times T1 and T2, the image In addition, during the time period T3 to T4, the image data “Vs” (s[n]) is written. At this time, the wiring 128 is connected to the anode This will be ranked 1st.

[0165] FIG. 12B shows the current (I LED )of This is the result of a simulation. Figure 12(B) shows a simulation for one pixel. As a result, it was confirmed that any pixel (pix1 to pix4) can display gradation. It is being done.

[0166] FIG. 12C shows the potential “V NM Changes in " The simulation results show that the potential of the node NM in each pixel is “V NM " is a painting It has been confirmed that it is proportional to the image data “Vs”.

[0167] That is, it is possible to display the high resolution image data "Vs" supplied from the wiring 123. Confirmed.

[0168] 13(A) to 13(D) show the simulation results for verifying low-resolution display (without correction). The results are shown in Fig. 13(A) and (B) which are timing charts used in the verification. The potential of the line 123 is set to the minimum value (+1V) at all times T1 to T4 in FIG. At this time, the wiring 128 is at a potential “V Since the potential is set to ref'' (+1 V), the differential potential held in the capacitor 104 is 0. That is, no correction is made.

[0169] After that, during the period from time T1 to time T2 shown in FIG. 13B, the transistor 101 is turned on. As a result, image data “Vs” (s[m]) is written from the wiring 123.

[0170] FIG. 13C shows the current (I LED )of The results are shown in Fig. 13(C). The results show that any pixel (pix1 to pix4) can display gradations. It has been done.

[0171] FIG. 13D shows the potential “V NM Changes in " The simulation results show that the potential of the node NM in each pixel is “V NM " is a painting It has been confirmed that it is proportional to the image data “Vs”.

[0172] That is, it is possible to display the low-resolution image data "Vs" supplied from the wiring 123. Confirmed.

[0173] 14(A) to (D) show the results of a simulation verifying a low-resolution display (with correction). The results are shown in Fig. 14 (A) and (B) which are timing charts used in the verification. The desired correction data "Vp" is supplied to the line 123, and the time from T1 to T2 in FIG. At time T3 to T4, the correction data “Vp” (p[n]) is written. At this time, the wiring 128 is at the potential “Vre f” (+1V), the differential potential held in the capacitance element 104 is “Vp-1”. be.

[0174] After that, during the period from time T1 to time T2 shown in FIG. 14B, the transistor 101 is turned on. By this, image data "Vs" is written from the wiring 123, and the correction data is added to the image data. At this time, the wiring 128 is set to an anode potential.

[0175] FIG. 14C shows the current (I LED )of This is the result of a simulation for each compensation data. Compensation data “Vp” is set to 1V to 8V. In either case, gradation can be displayed by writing V and combining it with image data "Vs". It has been confirmed that.

[0176] FIG. 14D shows the potential “V NM Changes in " This is the result of simulating the correction data “Vp” for each correction data “Vp”. In any case where 1V to 8V is written and combined with the image data "Vs", The potential of the node NM, “V NM It has been confirmed that there is a proportional trend.

[0177] That is, the correction data “Vp” and the low-resolution image data “ It was confirmed that a valid display could be obtained by combining Vs”.

[0178] FIG. 15 shows an example in which a pixel according to an embodiment of the present invention is applied to an EL display device capable of performing color display. Here is an example. Generally, the pixels of a display device that can display color are R (red), G (green), and B (blue). In FIG. 15, the sub-pixels arranged in the horizontal direction are The pixel 10R, the sub-pixel 10G, and the sub-pixel 10B are each made up of three sub-pixels of different colors. These represent four pixels in the horizontal and vertical directions. a and transistor 102b are represented as one block.

[0179] As described above, in one embodiment of the present invention, the transistors 101 are arranged in a matrix. The four pixels (corresponding to four sub-pixels emitting the same color in this case) are given correction data "Vp1" or Image data "VsL" can be input. In addition, the transistors 102a and 102b A potential is applied to two pixels (corresponding to two sub-pixels emitting the same color) arranged in the horizontal direction via “Vref” can be supplied.

[0180] In the stripe arrangement, it is preferable that the sub-pixels are arranged at equal intervals. When wiring or transistors are shared among elements, the spacing between each subpixel (elements with the same function) It may be difficult to keep the interval constant.

[0181] Therefore, the pixel electrodes connected to the subpixels 10R, 10G, and 10B are , electrodes 26R, 26G, and 26B, as shown in FIG. It is preferable to arrange the pixel electrodes 6B at equal intervals. It is possible to say that the two are separate elements, but for clarity of explanation, they are treated as separate elements. This is effective for a mission-type EL display device or a reflective-type liquid crystal display device.

[0182] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0183] (Embodiment 2) In this embodiment, a configuration example of a display device using a liquid crystal element and a configuration example of a display device using an EL element are described. A configuration example will be described. In this embodiment, the display device described in the first embodiment will be Descriptions of the elements, operations and functions of the device are omitted.

[0184] 16A to 16C show the structure of a display device in which one embodiment of the present invention can be used. FIG.

[0185] In FIG. 16A, a display portion 215 provided on a first substrate 4001 is surrounded by a A sealant 4005 is provided, and the display unit 215 is disposed between the sealant 4005 and the second substrate 4. Sealed by 006.

[0186] The display unit 215 can be provided with the pixel array shown in FIG. The scanning line driving circuit described below corresponds to a row driver, and the signal line driving circuit corresponds to a column driver. Correct.

[0187] In FIG. 16A, a scanning line driving circuit 221a, a signal line driving circuit 231a, and a signal line driving circuit 232a and the common line driver circuit 241a are provided on a printed circuit board 4041. The integrated circuits 4042 are made of a single crystal semiconductor or a polycrystalline The signal line driving circuit 231a and the signal line driving circuit 232a are formed of semiconductors. The scanning line driving circuit 221a has the function of the column driver shown in the first embodiment. The common line driver circuit 241a has the function of the row driver shown in the first embodiment. It has the function of supplying a specified potential to the wiring that supplies the power supply and the wiring that supplies Vref shown in do.

[0188] A scanning line driving circuit 221a, a common line driving circuit 241a, a signal line driving circuit 231a, and a signal Various signals and potentials are applied to the line driver circuit 232a via a flexible printed circuit (FPC). The signal is supplied via a digital signal processor (DPC) 4018.

[0189] The integrated circuit 4042 included in the scanning line driver circuit 221a and the common line driver circuit 241a is The signal line driver circuit 231a and the signal line driver The integrated circuit 4042 of the drive circuit 232a has a function of supplying image data to the display unit 215. The integrated circuit 4042 is surrounded by a sealant 4005 on the first substrate 4001. The device is implemented in a different area than the area in which it is installed.

[0190] The method of connecting the integrated circuit 4042 is not particularly limited, and may be wire bonding. COG (Chip On Glass) method, TCP (Tape Carrier Package method, COF (Chip On Film) method, etc. can be used. .

[0191] FIG. 16B shows an integrated circuit included in the signal line driver circuit 231a and the signal line driver circuit 232a. The circuit 4042 is implemented by the COG method. The display unit 215 and the display unit 216 can be integrally formed on the same substrate to form a system on panel. Cut.

[0192] In FIG. 16B, the scanning line driving circuit 221a and the common line driving circuit 241a are In this example, the driving circuit is formed on the same substrate as the pixel circuit in the display unit 215. By forming the parts at the same time, the number of parts can be reduced, which increases productivity. can.

[0193] In FIG. 16B, the display portion 215 provided on the first substrate 4001 and the scanning line driver A sealant 4005 is provided to surround the drive circuit 221a and the common line drive circuit 241a. A display unit 215, a scanning line driving circuit 221a, and a common line driving circuit A second substrate 4006 is provided on the display unit 215 and the scanning line driver 241a. The driving circuit 221a and the common line driving circuit 241a are disposed between the first substrate 4001 and the sealing material 40. The display element is sealed by the second substrate 4005 and the second substrate 4006 .

[0194] In addition, in FIG. 16B, a signal line driver circuit 231a and a signal line driver circuit 232a are separately 4001 and mounted on the first substrate 4001, but the present invention is not limited to this configuration. The scanning line driver circuit may be formed separately and mounted, or may be mounted as a part of the signal line driver circuit or the scanning line driver circuit. A part of the driver circuit may be formed separately and mounted. The signal line driving circuit 231a and the signal line driving circuit 232a are formed on the same substrate as the display unit 215. This is also fine.

[0195] The display device includes a panel in which a display element is sealed, and a controller for the panel. The term "IC" may also refer to a module in which an IC or the like including the above is mounted.

[0196] The display portion and the scanning line driver circuit provided on the first substrate have a plurality of transistors. The transistor described in the above embodiment may be used as the transistor. can be done.

[0197] The structure of the transistors in the peripheral driver circuits and the pixel circuits in the display area is The transistors in the peripheral driver circuit are all the same or different. The transistors may have the same structure, or may have two or more types of transistor structures. Similarly, the transistors in the pixel circuit may all have the same structure. Alternatively, the semiconductor device may have transistors with two or more different structures.

[0198] In addition, an input device 4200 can be provided on the second substrate 4006. The display device provided with the input device 4200 can function as a touch panel. .

[0199] There is no limitation on a detection element (also referred to as a sensor element) included in a touch panel of one embodiment of the present invention. We offer a variety of sensors that can detect the proximity or contact of a finger, stylus, or other object. , can be applied as a sensing element.

[0200] The sensor type may be, for example, a capacitance type, a resistive film type, a surface acoustic wave type, or an infrared type. Various methods can be used, such as a pressure-sensitive method, an optical method, or a pressure-sensitive method.

[0201] In this embodiment, a touch panel having a capacitance type sensing element will be described as an example. .

[0202] The capacitive touch sensor includes a surface capacitive touch sensor and a projected capacitive touch sensor. The electrostatic capacitance type includes the self-capacitance type and the mutual capacitance type. This is preferable because it enables simultaneous multi-point detection.

[0203] The touch panel according to one embodiment of the present invention is formed by bonding a display device and a sensing element that are separately manufactured. A detector element is provided on one or both of a substrate supporting a display element and an opposing substrate. Various configurations can be applied, such as a configuration in which electrodes or the like are provided.

[0204] 17(A) and (B) show an example of a touch panel. FIG. 17(A) shows a touch panel 4 FIG. 17B is a perspective view of the input device 4200. For clarity, only representative components are shown.

[0205] The touch panel 4210 is constructed by bonding a display device and a sensing element that are separately manufactured. be.

[0206] The touch panel 4210 includes an input device 4200 and a display device, which are stacked on top of each other. It is being done.

[0207] The input device 4200 includes a substrate 4263, an electrode 4227, an electrode 4228, and a plurality of wirings 4237. , a plurality of wirings 4238 and a plurality of wirings 4239. For example, the electrode 4227 is The electrode 4228 can be electrically connected to the wiring 4237 or the wiring 4239. The FPC 4272b can be electrically connected to the wires 4239. and electrically connects to each of the plurality of wirings 4238. 3b may be provided.

[0208] Alternatively, a touch sensor may be provided between the first substrate 4001 and the second substrate 4006 of the display device. In the case where a touch sensor is provided between the first substrate 4001 and the second substrate 4006, In addition to capacitive touch sensors, optical touch sensors using photoelectric conversion elements are also used. may be applied.

[0209] FIG. 18(A) and FIG. 18(B) show the structure of the region indicated by the dashed line N1-N2 in FIG. 16(B). The display device shown in FIG. 18(A) and FIG. 18(B) has an electrode 4015. The electrode 4015 is electrically connected to a terminal of the FPC 4018 via an anisotropic conductive layer 4019. 18(A) and 18(B), the electrode 4015 is Wiring is provided in openings formed in the insulating layers 4112, 4111, and 4110. It is electrically connected to 4014.

[0210] The electrode 4015 is formed from the same conductive layer as the first electrode layer 4030. The source and drain electrodes of the transistor 4010 and the transistor 4011 are the same. The conductive layer is made of the same material.

[0211] The display unit 215 and the scanning line driver circuit 221a provided on the first substrate 4001 are In FIG. 18(A) and FIG. 18(B), the display unit 215 The transistor 4010 included in the scanning line driver circuit 221a 18(A) and 18(B), the transistor 4 010 and a bottom-gate transistor is illustrated as a transistor 4011. However, it may be a top-gate transistor.

[0212] In FIG. 18(A) and FIG. 18(B), a transistor 4010 and a transistor 401 18B, an insulating layer 4112 is provided on the insulating layer 4112. A partition wall 4510 is formed.

[0213] The transistor 4010 and the transistor 4011 are provided over an insulating layer 4102. The transistor 4010 and the transistor 4011 are formed by insulating layers 4111. The semiconductor device has an electrode 4017 formed thereon. The electrode 4017 functions as a back gate electrode. It is possible.

[0214] 18A and 18B further includes a capacitor 4020. The display device shown in FIG. The capacitor 4020 has an electrode 4 formed in the same process as the gate electrode of the transistor 4010. 021, and electrodes formed in the same process as the source electrode and the drain electrode. The electrodes overlap with each other with an insulating layer 4103 interposed therebetween.

[0215] In general, the capacitance of a capacitor provided in a pixel portion of a display device is determined by the capacitance of a transistor disposed in the pixel portion. The capacitance is set so that the charge can be held for a predetermined period of time, taking into consideration the leakage current of the capacitor. The capacitance of the capacitance element may be set in consideration of the off-state current of the transistor and the like.

[0216] The transistor 4010 provided in the display portion 215 is electrically connected to a display element. FIG. 18(A) is an example of a liquid crystal display device using a liquid crystal element as a display element. In the liquid crystal display device, a liquid crystal element 4013 serving as a display element includes a first electrode layer 4030 and a second electrode layer 40 31, and a liquid crystal layer 4008. The liquid crystal layer 4008 is sandwiched between the alignment films 31 and 32. The second electrode layer 4031 is provided with an insulating layer 4032 and an insulating layer 4033 which function as a A first electrode layer 4030 and a second electrode layer 4031 are provided on the second substrate 4006 side. Overlapping via layer 4008.

[0217] The spacer 4035 is a columnar spacer obtained by selectively etching an insulating layer. The distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031 is controlled. A spherical spacer may also be used.

[0218] If necessary, a black matrix (light-shielding layer), a colored layer (color filter), a polarizing Optical members (optical substrates) such as a member, a phase difference member, and an anti-reflection member may be provided as appropriate. For example, circularly polarized light produced by a polarizing substrate and a retardation substrate may be used. In addition, the above-mentioned backlight and sidelight may be used. Micro LEDs or the like may be used as the light.

[0219] In the display device shown in FIG. 18A, between the second substrate 4006 and the second electrode layer 4031, A light blocking layer 4132, a colored layer 4131, and an insulating layer 4133 are provided.

[0220] Materials that can be used for the light-shielding layer include carbon black, titanium black, gold, etc. Examples of the material for the light-shielding layer include metals, metal oxides, and composite oxides including solid solutions of multiple metal oxides. The film may be a film containing a resin material, or may be a thin film of an inorganic material such as a metal. In addition, a laminated film of a film containing the material of the colored layer may be used for the light-shielding layer. A film containing a material for a colored layer that transmits light of a certain color and a material for a colored layer that transmits light of a different color are used. By using the same material for the colored layer and the light-shielding layer, This is preferable because it allows the equipment to be standardized and the process to be simplified.

[0221] Materials that can be used for the coloring layer include metal materials, resin materials, pigments, or dyes. The light-shielding layer and the colored layer are formed by, for example, an ink-jet method. The electrode can be formed using:

[0222] In addition, the display device shown in FIG. 18(A) and FIG. 18(B) includes an insulating layer 4111 and an insulating layer 41 The insulating layer 4111 and the insulating layer 4104 are made of insulating material that is difficult for impurity elements to penetrate. By sandwiching the semiconductor layer of the transistor between the insulating layer 4111 and the insulating layer 4104, It is possible to prevent impurities from entering from the outside.

[0223] In addition, a light-emitting element that utilizes electroluminescence is used as a display element included in the display device. An EL element can be applied. An EL element is a light-emitting compound placed between a pair of electrodes. A layer including a voltage lower than the threshold voltage of the EL element is provided between a pair of electrodes. When a large potential difference is generated, holes are injected into the EL layer from the anode side and electrons are injected into the EL layer from the cathode side. The injected electrons and holes recombine in the EL layer, forming luminescent The compound emits light.

[0224] EL elements are also classified according to whether the luminescent material is an organic compound or an inorganic compound. In general, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0225] When a voltage is applied to an organic EL element, electrons are emitted from one electrode and holes are emitted from the other electrode. are injected into the EL layer. Then, the carriers (electrons and holes) recombine. This causes the light-emitting organic compound to form an excited state, which then returns to the ground state. Due to this mechanism, this type of light-emitting element is called a current-excited light-emitting element. is called a child.

[0226] In addition to the light-emitting compound, the EL layer may be formed by using a material having a high hole-injecting property and a material having a high hole-transporting property. , hole blocking material, material with high electron transporting ability, material with high electron injecting ability, or bipolar The insulating layer may include a material having high electron-transporting and hole-transporting properties.

[0227] The EL layer can be formed by a variety of methods, including deposition (including vacuum deposition), transfer, printing, inkjet, and coating. It can be formed in any way.

[0228] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements according to their element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor reaction that utilizes the donor and acceptor levels. Thin-film inorganic EL elements are made by sandwiching a light-emitting layer between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner shell electron transition of metal ions. In this example, the light-emitting element is an organic EL element. do.

[0229] In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes must be transparent. A transistor and a light emitting element are formed on the substrate, and light is emitted from the opposite side of the substrate. Top emission structure, which emits light from the top surface of the substrate, and bottom emission structure, which emits light from the bottom surface of the substrate. (bottom emission) structure and dual emission (double emission) structure that emits light from both sides There are light emitting elements having a light-emitting (emission) structure, and light emitting elements having any of the emission structures can be applied.

[0230] FIG. 18(B) shows a light-emitting display device (also called an "EL display device") that uses light-emitting elements as display elements. The light-emitting element 4513, which is a display element, is provided in the display portion 215. The light-emitting element 4513 is electrically connected to the transistor 4010. This is a laminated structure of an electrode layer 4030, a light-emitting layer 4511, and a second electrode layer 4031. The light emitting element 4513 may be arranged in accordance with the direction of light to be extracted from the light emitting element 4513. The configuration of 13 can be changed as appropriate.

[0231] The partition 4510 is formed using an organic insulating material or an inorganic insulating material. An opening is formed on the first electrode layer 4030 using a resin material, and the side of the opening is continuous. It is preferable to form the inclined surface so as to have a curvature.

[0232] The light-emitting layer 4511 may be composed of a single layer or a plurality of layers may be laminated. Either way is fine.

[0233] The color of light emitted by the light-emitting element 4513 can be white, red, green, or blue depending on the material that constitutes the light-emitting layer 4511. , cyan, magenta, or yellow, etc.

[0234] As a method for realizing color display, a light-emitting element 4513 that emits white light is combined with a colored layer. There are two methods: one is to combine the two and the other is to provide a light-emitting element 4513 with a different light-emitting color for each pixel. The first method has higher productivity than the latter method. On the other hand, the latter method requires a light-emitting layer 4511 for each pixel. However, the latter method is less productive than the former method because it requires separate production of In addition to the latter method, it is possible to obtain a luminescent color with higher color purity than the former method. By adding a microcavity structure to element 4513, color purity can be further improved. can be done.

[0235] The light-emitting layer 4511 may contain an inorganic compound such as quantum dots. The child dots can be used in a light-emitting layer to function as a light-emitting material.

[0236] In order to prevent oxygen, hydrogen, moisture, carbon dioxide, and the like from entering the light-emitting element 4513, the second electrode layer A protective layer may be formed on the insulating layer 4031 and the partition wall 4510. The protective layer may be silicon nitride. Silicon oxide nitride, aluminum oxide, aluminum nitride, aluminum oxynitride, Forming aluminum oxide nitride, DLC (Diamond Like Carbon), etc. In addition, the first substrate 4001, the second substrate 4006, and the sealant 4 The space sealed by 005 is sealed with a filler 4514. In addition, a protective film (lamination film) that is highly airtight and has little outgassing is used to prevent exposure to the outside air. It is preferable to package (enclose) the product in a protective film (film, ultraviolet curing resin film, etc.) or a cover material. I wish.

[0237] Filler 4514 can be inert gas such as nitrogen or argon, or ultraviolet curing resin or Thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic resins, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Also, filler 4514 may contain a desiccant.

[0238] The sealing material 4005 is made of glass materials such as glass frit, or two-liquid mixed resin. Resin materials such as heat-curable resin, photocurable resin, and thermosetting resin can be used. Also, the sealant 4005 may contain a desiccant.

[0239] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is placed on the light-emitting surface of the light-emitting element. Optical films such as retardation plates (λ / 4 plates, λ / 2 plates), color filters, etc. may be installed as appropriate. In addition, the polarizing plate or the circular polarizing plate may be provided with an anti-reflection film. Anti-glare treatment can be applied to further diffuse reflected light and reduce glare.

[0240] In addition, by making the light-emitting element a microcavity structure, it is possible to extract light with high color purity. In addition, by combining a microcavity structure with a color filter, This reduces congestion and improves visibility of the displayed image.

[0241] A first electrode layer and a second electrode layer (a pixel electrode layer, a common electrode layer, In the case of the counter electrode layer, the direction of the light to be extracted, the location of the electrode layer, and The light transmitting property or the reflecting property can be selected depending on the pattern structure of the electrode layer.

[0242] The first electrode layer 4030 and the second electrode layer 4031 are made of indium oxide containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide, indium tin oxide containing titanium oxide, indium zinc oxide In addition, a conductive material having light transmitting properties, such as indium tin oxide doped with silicon oxide, is used. This can be done.

[0243] The first electrode layer 4030 and the second electrode layer 4031 are made of tungsten (W) or molybdenum. (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (N b) Tantalum (Ta), Chromium (Cr), Cobalt (Co), Nickel (Ni), Titanium Metals such as titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), and silver (Ag) or an alloy thereof, or a metal nitride thereof. .

[0244] The first electrode layer 4030 and the second electrode layer 4031 are made of a conductive polymer (conductive polymer). The conductive polymer may be a conductive composition containing a conductive polymer. For example, a so-called π-electron conjugated conductive polymer can be used. or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives or a copolymer of two or more of aniline, pyrrole and thiophene, Its derivatives are also included.

[0245] In addition, since transistors are easily damaged by static electricity, etc., a protection circuit for protecting the driver circuit is also required. It is preferable that the protection circuit is configured using a non-linear element.

[0246] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0247] (Embodiment 3) In this embodiment mode, the transistors described in the above embodiment modes can be replaced with An example of a transistor that can be used will be described with reference to the drawings.

[0248] The display device of one embodiment of the present invention includes a bottom-gate transistor or a top-gate transistor. The present invention can be fabricated using various types of transistors, such as transistors. The semiconductor layer materials and transistor structures used can be easily replaced to suit the production line. It is possible.

[0249] [Bottom-gate transistor] FIG. 19(A1) shows a channel-protected transistor, which is a type of bottom-gate transistor. 19A is a cross-sectional view of a transistor 810 in the channel length direction. The transistor 810 is formed on the substrate 771. An electrode 746 is provided with an insulating layer 772 interposed therebetween. The semiconductor layer 742 is an insulating layer that can function as a gate electrode. It can function as a gate insulating layer.

[0250] In addition, an insulating layer 741 is provided on a channel formation region of the semiconductor layer 742. 42, and has an electrode 744a and an electrode 744b on the insulating layer 726. Electrode 744a can function as either a source electrode or a drain electrode. A part of the electrode 744a and the electrode 744b can function as the other of the source electrode and the drain electrode. A portion of the pole 744 b is formed on the insulating layer 741 .

[0251] The insulating layer 741 can function as a channel protection layer. By providing the electrode 744a and the electrode 744b, the exposure of the semiconductor layer 742 that occurs during the formation of the electrode 744a and the electrode 744b is suppressed. Therefore, when the electrodes 744a and 744b are formed, the semiconductor layer This can prevent the channel formation region 742 from being etched. According to this, a transistor having good electrical characteristics can be realized.

[0252] The transistor 810 includes an insulating layer 741 and an electrode 744a. A layer 728 is provided, and an insulating layer 729 is provided on the insulating layer 728 .

[0253] When an oxide semiconductor is used for the semiconductor layer 742, at least At least in the portion in contact with the semiconductor layer 742, oxygen is taken from a portion of the semiconductor layer 742, and oxygen vacancies are formed. It is preferable to use a material capable of generating oxygen vacancies in the semiconductor layer 742. The resulting region has an increased carrier concentration, which makes it n-type, and the region is called an n-type region (n + layer). Therefore, the region can function as a source region or a drain region. When an oxide semiconductor is used for the conductor layer 742, oxygen is taken from the semiconductor layer 742 to fill the oxygen vacancies. Examples of materials that can produce this include tungsten and titanium. do.

[0254] The source region and the drain region are formed in the semiconductor layer 742, whereby the electrode 744a In addition, the contact resistance between the electrode 744b and the semiconductor layer 742 can be reduced. The electrical characteristics of the transistor, such as the effective mobility and threshold voltage, can be improved. can.

[0255] When a semiconductor such as silicon is used for the semiconductor layer 742, the semiconductor layer 742 and the electrode 744a between the semiconductor layer 742 and the electrode 744b, and between the semiconductor layer 742 and the electrode 744b, It is preferable to provide a layer that functions as an n-type semiconductor or a p-type semiconductor. It can function as a source or drain region of a transistor.

[0256] The insulating layer 729 has a function of preventing or reducing diffusion of impurities from the outside into the transistor. It is preferable to form the insulating layer 729 using a material having the above structure. It is also possible.

[0257] The transistor 811 shown in FIG. 19A2 has an insulating layer 729 over which a back gate electrode is formed. The transistor 810 differs from the transistor 810 in that it has a functioning electrode 723. It can be formed from the same materials and by the same method as 746.

[0258] In general, the back gate electrode is formed of a conductive layer, and the gate electrode and the back gate electrode form a semiconductor. The back gate electrode is disposed so as to sandwich the channel forming region of the layer. The back gate electrode can function in the same manner as the gate electrode. Alternatively, the potential may be set to ground potential (GND potential) or any other potential. By changing the potential of the gate electrode independently of the potential of the back electrode, the transistor threshold The voltage can be varied.

[0259] Both the electrode 746 and the electrode 723 can function as a gate electrode. The insulating layer 726, the insulating layer 728, and the insulating layer 729 each serve as a gate insulating layer. The electrode 723 can function as a gate insulating layer. This is also fine.

[0260] When one of the electrodes 746 and 723 is referred to as a "gate electrode," the other is referred to as a "back electrode." For example, in the transistor 811, the electrode 723 is called a "gate electrode." When the term "electrode" is used, the electrode 746 is referred to as the "back gate electrode." When the transistor 811 is used as a top gate electrode, In addition, either the electrode 746 or the electrode 723 can be considered as a "first The first gate electrode is sometimes referred to as the "first gate electrode" and the other as the "second gate electrode."

[0261] By providing the electrode 746 and the electrode 723 with the semiconductor layer 742 interposed therebetween, 6 and the electrode 723 are set to the same potential, the region in which carriers flow in the semiconductor layer 742 The area becomes larger in the film thickness direction, so the amount of carrier movement increases. As the on-current of the transistor 811 increases, the field effect mobility increases.

[0262] Therefore, the transistor 811 is a transistor having a large on-current relative to its occupancy area. That is, the area occupied by the transistor 811 is set to a desired on-current. According to one aspect of the present invention, the area occupied by a transistor can be reduced. Therefore, according to one embodiment of the present invention, a highly integrated semiconductor device can be realized. It is possible.

[0263] In addition, since the gate electrode and the back gate electrode are formed of a conductive layer, they can be electrically connected to the outside of the transistor. The function of preventing the electric field generated from acting on the semiconductor layer in which the channel is formed (especially static electricity The back gate electrode is larger than the semiconductor layer. By forming a back gate electrode and covering the semiconductor layer with the back gate electrode, the electric field shielding function can be improved. .

[0264] In addition, by forming the back gate electrode using a conductive film having a light-shielding property, This can prevent light from entering the semiconductor layer from the side. This prevents the semiconductor layer from being deteriorated by light. This can prevent degradation of electrical characteristics, such as a shift in the threshold voltage of a transistor. .

[0265] According to one embodiment of the present invention, a transistor with high reliability can be provided. A highly reliable semiconductor device can be realized.

[0266] FIG. 19B1 shows a channel protection transistor 82 having a different structure from that shown in FIG. 19A1. 8 is a cross-sectional view of the transistor 820 in the channel length direction. It has a similar structure, but differs in that an insulating layer 741 covers the edge of a semiconductor layer 742. In addition, an opening is formed by selectively removing a part of the insulating layer 741 that overlaps the semiconductor layer 742. In the portion, the semiconductor layer 742 and the electrode 744a are electrically connected to each other. In another opening formed by selectively removing a portion of the insulating layer 741 overlapping with the semiconductor layer 42, The insulating layer 741 is electrically connected to the electrode 744b. The overlapping region can function as a channel protection layer.

[0267] The transistor 821 shown in FIG. 19B2 has a back gate electrode over the insulating layer 729. It differs from transistor 820 in that it has a functioning electrode 723 .

[0268] By providing the insulating layer 741, the semiconductor generated when the electrodes 744a and 744b are formed can be prevented. Therefore, when the electrode 744a and the electrode 744b are formed, the layer 742 can be prevented from being exposed. In addition, the semiconductor layer 742 can be prevented from becoming thin.

[0269] In addition, the transistors 820 and 821 are the same as the transistors 810 and The distance between the electrodes 744a and 746 and the distance between the electrodes 744b and 746 are smaller than the distance between the electrodes 744a and 746 and the distance between the electrodes 744b and 746. Therefore, the distance between the electrodes 744a and 746 is increased. In addition, the parasitic capacitance between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present invention, a transistor with favorable electrical characteristics can be realized. Cut.

[0270] FIG. 19(C1) shows a channel-etched type transistor, which is one of the bottom-gate type transistors. 1 is a cross-sectional view in the channel length direction of a transistor 825. The transistor 825 has an insulating layer 7 Electrodes 744a and 744b are formed without using 41. In addition, a part of the semiconductor layer 742 that is exposed during the formation of the electrode 744b may be etched. On the other hand, since the insulating layer 741 is not provided, productivity of the transistor can be increased.

[0271] A transistor 826 shown in FIG. 19C2 has an insulating layer 729 over which a back gate electrode is formed. It differs from transistor 825 in that it has a functioning electrode 723 .

[0272] In FIG. 20(A1) to (C2), transistors 810, 811, 820, 821, 825, 826 are cross-sectional views in the channel width direction.

[0273] In the structures shown in FIGS. 20(B2) and (C2), the gate electrode and the back gate electrode are connected. The gate electrode and the back gate electrode have the same potential. The gate electrode is sandwiched between the gate electrode and the back gate electrode.

[0274] The length of each of the gate electrode and the back gate electrode in the channel width direction is 2 in the channel width direction, and the entire channel width direction of the semiconductor layer 742 is 726, 741, 728, and 729 are sandwiched between the gate electrode or the back gate electrode. This is a structure.

[0275] With this structure, the semiconductor layer 742 included in the transistor is The gate electrode can be electrically surrounded by the electric field of the gate electrode.

[0276] Like the transistor 821 or the transistor 826, the gate electrode and the back gate The electric field of the electrode electrically surrounds the semiconductor layer 742 in which the channel formation region is to be formed. The device structure of a transistor is called the Surrounded channel (S-channel el) structure.

[0277] By adopting an S-channel structure, either one of the gate electrode and the back gate electrode By both, an electric field is effectively applied to the semiconductor layer 742 to induce a channel. This improves the current drive capability of the transistor and makes it possible to obtain high on-current characteristics. In addition, since it is possible to increase the on-current, it is possible to miniaturize transistors. In addition, the S-channel structure makes it possible to mechanically Strength can be increased.

[0278] [Top-gate transistor] The transistor 842 illustrated in FIG. 21A1 is a top-gate transistor. The electrode 744a and the electrode 744b are formed on the insulating layer 728 and the insulating layer 729. The insulating layer 742 is electrically connected to the semiconductor layer 742 in the opening.

[0279] In addition, a part of the insulating layer 726 that does not overlap with the electrode 746 is removed, and the electrode 746 and the remaining insulating layer The semiconductor layer 742 is doped with impurities 755 using the mask 726. In the semiconductor device 742, an impurity region can be formed in a self-aligned manner. Transistor 842 has an area where insulating layer 726 extends beyond the end of electrode 746 . The impurity concentration in the region of the semiconductor layer 742 into which the impurity 755 is introduced via the insulating layer 726 is The area is smaller than the area where the impurity 755 is introduced without the insulating layer 726. The layer 742 is doped with lightly doped dopant (LDD) in a region that does not overlap with the electrode 746. A rain area is formed.

[0280] The transistor 843 shown in FIG. 21A2 has an electrode 723. 2. The transistor 843 has an electrode 723 formed on a substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. can function as a back gate electrode.

[0281] In addition, the transistor 844 shown in FIG. 21B1 and the transistor shown in FIG. As in the case of the electrode 845, the insulating layer 726 may be entirely removed from areas that do not overlap with the electrode 746. In addition, the transistor 846 shown in FIG. 21C1 and the transistor shown in FIG. Insulating layer 726 may be left behind, as may layer 847.

[0282] After forming the electrode 746, the transistors 842 to 847 are also As a result, the semiconductor layer 742 is doped with impurities 755 using the mask. According to one aspect of the present invention, an impurity region can be formed in a self-aligned manner. According to one aspect of the present invention, a transistor having good integration properties can be realized. Therefore, a highly reliable semiconductor device can be realized.

[0283] In FIG. 22(A1) to (C2), transistors 842, 843, 844, 845, 846, 847 are cross-sectional views in the channel width direction.

[0284] The transistors 843, 845, and 847 are The S-channel structure described above is the same as that described above. However, the present invention is not limited to this. 3. The transistors 845 and 847 are not of S-channel structure. This is also fine.

[0285] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible.

[0286] (Embodiment 4) Examples of electronic devices that can use the display device according to one embodiment of the present invention include display devices, personal computers, and the like. a personal computer, an image storage device or image reproducing device equipped with a recording medium, a mobile phone, Game consoles, including those of the 1990s, portable data terminals, e-book terminals, video cameras, digital still cameras Cameras such as cameras, goggle-type displays (head-mounted displays), navigation systems, audio playback devices (car audio, digital audio players, etc.), machines, fax machines, printers, printer-combined machines, automated teller machines (ATMs), Examples of such electronic devices include vending machines. Specific examples of such electronic devices are shown in Figure 23.

[0287] FIG. 23A shows a digital camera, which includes a housing 961, a shutter button 962, and a microphone 9 63, speaker 967, display unit 965, operation keys 966, zoom lever 968, lens 9 By using the display device of one embodiment of the present invention for the display portion 965, various images can be displayed. The following display can be made.

[0288] FIG. 23B shows a digital signage with a large display unit 922. By using the display device of one embodiment of the present invention for the display portion 922, A variety of images can be displayed.

[0289] FIG. 23C shows a mobile phone, which includes a housing 951, a display unit 952, an operation button 953, and an external The mobile phone has a connection port 954, a speaker 955, a microphone 956, a camera 957, etc. The telephone has a touch sensor on the display unit 952. All operations such as the above can be performed by touching the display unit 952 with a finger or a stylus. In addition, the housing 951 and the display unit 952 are flexible and can be folded as shown in the figure. By using the display device of one embodiment of the present invention for the display portion 952, various It is possible to display a suitable image.

[0290] FIG. 23D shows a portable data terminal, which includes a housing 911, a display portion 912, a speaker 913, and a camera. The display unit 912 has a touch panel function for inputting and outputting information. By using the display device of one embodiment of the present invention for the display portion 912, various images can be displayed. The following display can be made.

[0291] FIG. 23E shows a television set, which includes a housing 971, a display unit 973, operation keys 974, and a speaker 9 The display unit 973 has a touch sensor 975, a communication connection terminal 976, an optical sensor 977, etc. The display device of one embodiment of the present invention is provided in the display portion 973. By using this, various images can be displayed.

[0292] FIG. 23F shows an information processing terminal, which includes a housing 901, a display unit 902, a display unit 903, and a sensor. The display unit 902 and the display unit 903 are each made of a single display panel, and are flexible. The housing 901 is also flexible and can be folded as shown in the figure. It can also be used in a flat shape like a tablet. 4 can sense the shape of the housing 901, for example, when the housing is bent. The display of the display unit 902 and the display unit 903 can be switched. 03. By using the display device of one embodiment of the present invention, various images can be displayed. .

[0293] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is possible. [Explanation of symbols]

[0294] 10 pixels 10B Subpixel 10G subpixel 10R subpixel 11 pixels 12 Pixel Array 13 Low Driver 14 Column Driver 15 Circuit 16 Selection circuit 20 Shift Registers 21 Buffer circuit 22 Shift Register 23 Buffer circuit 24 Sensors 25 Circuit 26B electrode 26G electrode 26R electrode 101 Transistor 102 Transistor 102a Transistor 102b Transistor 103 Transistor 104 Capacitive element 110 Circuit Block 111 Transistor 112 Transistor 113 Capacitive element 114 EL element 115 Transistor 116 Capacitive element 117 Liquid crystal element 118 Transistor 119 Transistor 120 circuits 121 Wiring 122 Wiring 123 Wiring 126 Wiring 128 Wiring 129 Wiring 130 Wiring 131 Wiring 132 Wiring 133 Wiring 134 Wiring 215 Display section 221a Scanning line driving circuit 231a Signal line driver circuit 232a Signal line driver circuit 241a Common line driver circuit 723 Electrode 726 Insulating Layer 728 Insulating Layer 729 Insulation Layer 741 Insulation Layer 742 Semiconductor layer 744a electrode 744b electrode 746 Electrode 755 Impurities 771 Circuit Board 772 Insulation Layer 810 Transistor 811 Transistor 820 Transistor 821 Transistor 825 Transistor 826 Transistor 842 Transistor 843 Transistor 844 Transistor 845 Transistor 846 Transistor 847 Transistor 901 Case 902 Display section 903 Display section 904 Sensors 911 Case 912 Display section 913 Speaker 919 Camera 921 Pillar 922 Display section 951 Case 952 Display section 953 Operation button 954 External connection port 955 Speaker 956 Mike 957 Camera 961 Case 962 Shutter button 963 Mike 965 Display section 966 Operation Key 967 Speaker 968 Zoom Lever 969 Lens 971 Case 973 Display section 974 Operation Key 975 Speaker 976 Communication connection terminal 977 Optical Sensor 4001 Substrate 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4014 Wiring 4015 Electrode 4017 Electrode 4018 FPC 4019 Anisotropic conductive layer 4020 Capacitive element 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4041 Printed circuit board 4042 Integrated Circuits 4102 Insulating layer 4103 Insulating layer 4104 Insulating layer 4110 Insulating layer 4111 Insulating layer 4112 Insulating layer 4131 Colored layer 4132 Light blocking layer 4133 Insulation layer 4200 Input Device 4210 Touch Panel 4227 Electrode 4228 Electrode 4237 Wiring 4238 Wiring 4239 Wiring 4263 Substrate 4272b FPC 4273b IC 4510 Bulkhead 4511 Light-emitting layer 4513 Light emitting element 4514 Filling material

Claims

[Claim 1] A first transistor; A second transistor; and a first circuit and a second circuit; A first wiring; A display device having a second wiring, each of the first circuit and the second circuit includes a third transistor, a first capacitive element, and a circuit block; one of a source and a drain of the third transistor is electrically connected to one electrode of the first capacitance element; one electrode of the first capacitance element is electrically connected to the circuit block; the other electrode of the first capacitance element is electrically connected to one of the source and the drain of the first transistor; one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor; the other of the source and the drain of the third transistor included in the first circuit is electrically connected to the first wiring; the other of the source and the drain of the first transistor is electrically connected to the first wiring; a gate of the third transistor included in the first circuit is electrically connected to the second wiring; a gate of the third transistor included in the second circuit is electrically connected to the second wiring; a gate of the second transistor electrically connected to the second wiring, and the circuit block includes a display element.

Images