Semiconductor device

Abstract

To improve reliability of an operation of an output element by limiting a large current operation under a high temperature in an over-current state.SOLUTION: A semiconductor device 10 has an output element M0, a temperature detection circuit 11, a current limit circuit 12, and an over-current detection circuit 13. The output element M0 is a power semiconductor element that drives a load L0, and operates the load L0 by switching by being connected to the load L0. The temperature detection circuit 11 detects a temperature at an operation of the output element M0. The over-current detection circuit 13 detects an over-current state of the output element M0. The current limit circuit 12 sets a gate voltage of the output element M0 to a voltage lower than that at the time of turn-on of the output element M0 before the temperature exceeds a setting temperature in the case where the over-current state is detected and the temperature exceeds the setting temperature, and limits a current flowing to the output element M0, and also performs an operation for increasing the gate voltage as the temperature becomes lower than the setting temperature.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] In recent years, there has been progress in the development of semiconductor devices that integrate an output element using a power semiconductor element, a drive circuit for the output element, and a peripheral protection circuit, etc., into a single package. Such semiconductor devices are widely used in vehicle electrical systems, such as transmissions, engines, and brakes, and there is a demand for products that meet the requirements of miniaturization, high performance, and high reliability.

[0003] Related techniques include a technique for switching the overcurrent detection threshold by a threshold control unit of an internal circuit (Patent Document 1), and a technique for controlling the on / off time during hiccup operation after detecting an overcurrent state based on a temperature detection signal (Patent Document 2).

[0004] Furthermore, a technology has been proposed that includes a plurality of voltage comparators that output a comparison result signal based on the comparison result between the charging voltage of a capacitor and a comparison voltage generated by a comparison voltage generation circuit (Patent Document 3).Also, a voltage detection circuit has been proposed that includes an RS flip-flop that has a hysteresis characteristic in the detection voltage and turns on / off depending on the input voltage level relative to the threshold voltage (Patent Document 4).

[0005] Furthermore, a technology has been proposed in which an AND circuit to which the output signal from the oscillator and an end-of-life signal are inputted is connected to the set section of an RS flip-flop, and a NOT circuit to which the output signal is inputted is connected to the reset section (Patent Document 5). Also, a technology has been proposed that includes a switch circuit that is connected to the gate of a main MOS transistor and switches the gate current in a power switching element by controlling the on / off of the main MOS transistor (Patent Document 6). Still further, a gate drive circuit has been proposed in which multiple gate charge extraction circuits with different resistances are arranged in parallel (Patent Document 7). [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2021 / 125269 [Patent Document 2] JP 2019-205300 A [Patent Document 3] JP 2013-62725 A [Patent Document 4] Japanese Patent Application Publication No. 1-316668 [Patent Document 5] Japanese Patent Application Publication No. 8-98432 [Patent Document 6] JP 2015-195700 A [Patent Document 7] Patent Publication No. 2021-103849 Summary of the Invention [Problem to be solved by the invention]

[0007] The present invention aims to improve the reliability of the output element's operation by limiting large current operation at high temperatures by limiting the current flowing through the output element when the load is short-circuited based on temperature information of the output element in an overcurrent state. [Means for solving the problem]

[0008] In order to solve the above problem, a semiconductor device is provided, which includes an output element connected to an output terminal connected to a load and a power supply terminal connected to a power supply, an overcurrent detection circuit for detecting an overcurrent state of the output element, a temperature detection circuit for detecting the temperature of the output element during operation, and a current limiting circuit for limiting a current flowing through the output element by setting a gate voltage of the output element to a voltage lower than that at the time of turn-on of the output element when the overcurrent state is detected and the temperature exceeds a set temperature, and increasing the gate voltage as the temperature decreases to a reference temperature lower than the set temperature. Effect of the Invention

[0009] According to one aspect, it is possible to improve the reliability of the operation of the output element by limiting large current operation at high temperatures in an overcurrent state. [Brief description of the drawings]

[0010] [Figure 1] 1A to 1C are diagrams illustrating an example of a configuration and operation of a semiconductor device. [Diagram 2] FIG. 1 is a diagram illustrating an example of a configuration of a semiconductor device. [Diagram 3] FIG. 2 is a diagram illustrating an example of a configuration of a temperature detection circuit. [Figure 4] FIG. 2 is a diagram illustrating an example of a configuration of a current limiting circuit. [Diagram 5] 4 is a time chart showing an example of an operation of the current limiting circuit. [Figure 6] FIG. 2 is a diagram illustrating an example of a configuration of a current limiting circuit. [Figure 7] FIG. 2 is a diagram illustrating an example of a configuration of a temperature detection circuit. [Figure 8] FIG. 2 is a diagram illustrating an example of a configuration of a current limiting circuit. [Figure 9] 4 is a time chart showing an example of an operation of the current limiting circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the present embodiment will be described with reference to the drawings. In this specification and the drawings, elements having substantially the same functions are denoted by the same reference numerals, and redundant description may be omitted.

[0012] Figure 1 is a diagram for explaining an example of the configuration and operation of a semiconductor device. The configuration of a semiconductor device 10 will be explained with reference to Figure 1(A). The semiconductor device 10 has an output element M0, a temperature detection circuit 11, a current limiting circuit 12, and an overcurrent detection circuit 13. The output element M0 is a power semiconductor switching element that drives a load L0, and is connected to the load L0 to operate the load L0 by switching.

[0013] A voltage-controlled switching element can be used as the output element M0. For example, an N-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is used as shown in FIG. 1A. Also, an IGBT (Insulated Gate Bipolar Transistor) may be used instead of a MOS transistor.

[0014] The temperature detection circuit 11 detects the temperature of the output element M0 during operation. The overcurrent detection circuit 13 detects an overcurrent state of the output element M0. When an overcurrent state is detected and the temperature exceeds the set temperature, the current limiting circuit 12 sets the gate voltage of the output element M0 to a voltage lower than when the temperature does not exceed the set temperature, thereby limiting the current flowing through the output element M0. Also, the current limiting circuit 12 operates to increase the gate voltage as the temperature drops below the set temperature.

[0015] 1B, the operation of the semiconductor device 10 will be described. In this figure, it is assumed that a short circuit has occurred in the load L0, resulting in an overcurrent state. [Period pd1] An H-level control signal is input to the gate of the output element M0, turning it on. At this time, the gate voltage of the output element M0 is the voltage Vg1 when it is turned on, and the current flowing through the output element M0 (output element current: drain current) is the current Id1.

[0016] [Period pd2] After the output element M0 is turned off at the end of period pd1, an H-level control signal is input and the output element M0 is turned on. As described above, it is assumed that a short circuit has occurred in the load L0, resulting in an overcurrent state, and that the temperature of the output element M0 exceeds the set temperature during period pd2.

[0017] In this case, the current limiting circuit 12 sets the gate voltage of the output element M0 to a voltage Vg2 lower than the voltage Vg1 at the time of turn-on of the output element M0 (Vg2 < Vg1). For this reason, the current flowing through the output element M0 becomes a current Id2 that is decreased from the current Id1 (Id2 < Id1).

[0018] 〔Period pd3〕After the output element M0 turns off at the end of the period pd2, a control signal of the H level is input and the output element M0 turns on. Although an overcurrent state has occurred because a short circuit of the load L0 has continuously occurred, it is assumed that the temperature of the output element M0 has become lower than the set temperature.

[0019] In this case, the current limiting circuit 12 raises the gate voltage of the output element M0 and sets it to a voltage Vg3 (Vg2 < Vg3 < Vg1). For this reason, the current flowing through the output element M0 increases from the current Id2 and becomes a current Id3 (Id2 < Id3 < Id1).

[0020] Here, as a requirement for the reliability of the output element, a technique is required in which it does not fail even if the state where the driven load is in a short-circuit state continues (for example, a test for continuous operation in a short-circuit state is defined in the reliability standard AEC-Q-100 for automotive products). Further, when the temperature of the output element rises due to a large current continuously flowing due to a short circuit, even if the overcurrent is cut off or limited in the circuit operation, there is a possibility of leading to reliability problems such as electromigration.

[0021] Conventionally, when the load is in a short-circuit state, the overcurrent detection circuit operates, the current of the output element is cut off or limited by the overcurrent detection circuit, and when the overcurrent state is repeated, the temperature of the output element rises. Therefore, the overheat protection circuit operates and an operation to cut off the current of the output element is performed. However, when an overcurrent due to a short circuit flows during the operation near the temperature at which the overheat protection circuit operates, the output element continuously receives stress of high temperature and large current, which may cause the phenomenon of electromigration.

[0022] To cope with such a situation, as described above, in the semiconductor device 10 of the present invention, when an overcurrent state of the output element is detected and the temperature exceeds a set temperature, the gate voltage of the output element is set to a voltage lower than the turn-on voltage, and as the temperature drops below the set temperature, the gate voltage is increased, thereby limiting the current flowing to the output element.

[0023] As a result, when an overcurrent detection state is entered, the current is limited based on the temperature detection result of the output element, so the current limiting operation continues until the temperature drops even if the load is short-circuited. This makes it possible to improve the reliability of the output element's operation by limiting large current operation at high temperatures in an overcurrent state. Furthermore, it becomes possible to avoid the occurrence of the phenomenon of electromigration.

[0024] Next, the configuration and operation of the semiconductor device 10 will be described in detail. Fig. 2 is a diagram showing an example of the configuration of the semiconductor device. The semiconductor device 10 is a device that is applied to, for example, a high-side IPS (Intelligent Power Switch), and includes an input terminal IN, an output terminal OUT, a power supply terminal VT, and a ground terminal GND.

[0025] A microcomputer 5 (higher-level control unit) is connected to the input terminal IN, and a pulse-like control signal s0 output from the microcomputer 5 is input. A load L0 is connected to the output terminal OUT. The load L0 is, for example, an inductive load such as a solenoid valve that is widely used in automobiles, or a resistive load such as a heater. A power supply voltage VCC such as a battery is connected to the power supply terminal VT, and GND is connected to the ground terminal GND.

[0026] The semiconductor device 10 also includes an output element M0, a temperature detection circuit 11, a current limiting circuit 12, an overcurrent detection circuit 13, an overheat protection circuit 14, a logic circuit 15, and a gate driver 16. The logic circuit 15 receives a control signal s0 transmitted from the microcomputer 5 via an input terminal IN, and generates a logic signal that turns the output element M0 on or off.

[0027] For example, when the logic circuit 15 receives an H-level control signal s0 input via the input terminal IN, it outputs a logic signal for turning on the output element M0. The gate driver 16 generates a voltage for turning on the output element M0 based on the logic signal output from the logic circuit 15 and applies the voltage to the gate to turn on the output element M0.

[0028] Furthermore, when the logic circuit 15 receives an L-level control signal s0 transmitted from the microcomputer 5 through the input terminal IN, it outputs a logic signal for turning off the output element M0. The gate driver 16 generates a signal of a level for turning off the output element M0 based on the logic signal output from the logic circuit 15, and applies the signal to the gate of the output element M0 to turn off the output element M0.

[0029] The overcurrent detection circuit 13 detects an overcurrent state of the output element M0. In this case, when the output element M0 is turned on, if it detects that an abnormally large current flowing through the output element M0 is larger than the rated current, it transmits an overcurrent detection signal s1 to the logic circuit 15.

[0030] When the logic circuit 15 receives the overcurrent detection signal s1 transmitted from the overcurrent detection circuit 13, it outputs a logic signal for turning off the output element M0, and the gate driver 16 turns off the output element M0 based on the logic signal output from the logic circuit 15. However, all operations of the present invention are performed before the output element M0 is turned off.

[0031] The overheat protection circuit 14 detects an overheat state of the output element M0. In this case, a potential generated by a constant current flowing through a temperature detection diode (not shown) arranged near the output element M0 is input to the overheat protection circuit 14 as an overheat temperature detection voltage.

[0032] The overheat protection circuit 14 detects an overheated temperature state of the output element M0 based on the overheat temperature detection voltage, and outputs an overheat detection signal s2 when it detects that the output element M0 is in an overheated state. When the logic circuit 15 receives the overheat detection signal s2 transmitted from the overheat protection circuit 14, it outputs a logic signal for turning off the output element M0, and the gate driver 16 turns off the output element M0 based on the logic signal output from the logic circuit 15.

[0033] The temperature detection circuit 11 detects the temperature state of the output element M0. In this case, n temperature detection signals are output for n (n is a natural number) stages of temperature. When the output element M0 is in an overcurrent state, the current limiting circuit 12 adjusts and limits the current flowing through the output element M0 based on the temperature state (n temperature detection signals) detected by the temperature detection circuit 11.

[0034] FIG. 3 is a diagram showing an example of the configuration of the temperature detection circuit. The temperature detection circuit 11 includes a constant current source 11a (constant current source for temperature detection), a reference voltage generating section 11b, a detection circuit 11c, and a comparison circuit 11d. The constant current source 11a includes a constant current element 11a1 (first constant current element) and a constant current element 11a2 (second constant current element), and the reference voltage generating section 11b includes resistors R1, . . . , R4. The resistors R1, . . . , R4 correspond to the first resistor to the fourth resistor, respectively. In addition, the following description is an example in which there are four resistors and four comparators, which will be described later, but the number of resistors and comparators is not limited to four and can be any number.

[0035] The detection circuit 11c includes temperature sense diodes D1, . . . , D4, whose temperature detection voltage based on the current from the constant current source 11a decreases with an increase in temperature. The comparison circuit 11d includes comparators cmp1, . . . , cmp4, which correspond to the first to fourth comparators, respectively.

[0036] In the connection relationship of the components, the input terminal of the constant current element 11a1 is connected to the input terminal of the constant current element 11a2 and the power supply unit. The output terminal of the constant current element 11a1 is connected to the anode of the temperature sensing diode D1, the inverting input terminal (-) of the comparator cmp1, the inverting input terminal (-) of the comparator cmp2, ​​the inverting input terminal (-) of the comparator cmp3, and the inverting input terminal (-) of the comparator cmp4.

[0037] The cathode of the temperature sense diode D1 is connected to the anode of the temperature sense diode D2, the cathode of the temperature sense diode D2 is connected to the anode of the temperature sense diode D3, and the cathode of the temperature sense diode D3 is connected to the anode of the temperature sense diode D4. Note that the number of temperature sense diodes D1, ..., D4 connected in series is not limited to four and can be any number.

[0038] The output terminal of the constant current element 11a2 is connected to the non-inverting input terminal (+) of the comparator cmp1 and one terminal of the resistor R1. The other terminal of the resistor R1 is connected to one terminal of the resistor R2 and the non-inverting input terminal (+) of the comparator cmp2.

[0039] The other end of the resistor R2 is connected to one end of a resistor R3 and the non-inverting input terminal (+) of a comparator cmp3. The other end of the resistor R3 is connected to one end of a resistor R4 and the non-inverting input terminal (+) of a comparator cmp4. The other end of the resistor R4 is connected to the cathode of a temperature sensing diode D4 and GND.

[0040] Here, the current i1 flowing from the constant current element 11a1 to the temperature sense diodes D1,...,D4 is a forward current for the temperature sense diodes D1,...,D4, so the voltage (temperature detection voltage) at the node n1 is the sum of the forward voltages (hereinafter referred to as forward voltages Vf) of the temperature sense diodes D1,...,D4. For example, if the forward voltages Vf of the temperature sense diodes D1,...,D4 are each 0.8V, the temperature detection voltage at the node n1 is 3.2(=0.8×4)V.

[0041] In addition, the temperature sensing diodes D1, . . . , D4 have temperature characteristics, and the forward voltage Vf changes with temperature. For example, when the temperature rises by 1°C, the forward voltage Vf decreases by about 2 mV.

[0042] Therefore, for example, when the temperature rises from 25°C to 50°C, the drop in the forward voltage Vf of one temperature sense diode is 0.05 (=0.002×25) V.

[0043] Therefore, if the forward voltage Vf is 0.8 V at a temperature of 25°C and the temperature rises to 50°C, the total decrease in the forward voltage Vf of the temperature sensing diodes D1, ..., D4 will be 0.2 (= 0.05 x 4) V, and the temperature detection voltage at node n1 will be 3.0 (3.2 - 0.2) V.

[0044] In this way, the temperature detection voltage at node n1 is 3.2V when the temperature is 25°C and 3.0V when the temperature is 50°C, and so changes with temperature changes and decreases as the temperature increases.

[0045] On the other hand, if a current i2 is output from constant current element 11a2 (currents i1 and i2 may be equal or different) and the voltage applied to node n2 is voltage Vr1, a reference voltage Vr1 is input to the non-inverting input terminal (+) of comparator cmp1.

[0046] In addition, the reference voltage Vr2 input to the non-inverting input terminal (+) of the comparator cmp2 is Vr2 = (R2 + R3 + R4) · Vr1 / (R1 + R2 + R3 + R4) due to resistor division.

[0047] Furthermore, the reference voltage Vr3 input to the non-inverting input terminal (+) of the comparator cmp3 is Vr3=(R3+R4)·Vr1 / (R1+R2+R3+R4) due to resistor division.

[0048] Furthermore, the reference voltage Vr4 input to the non-inverting input terminal (+) of the comparator cmp4 is given by Vr4 = R4·Vr1 / (R1 + R2 + R3 + R4) due to resistor voltage division. Note that the magnitude relationship of the reference voltages Vr1, ···, Vr4 is Vr4 < Vr3 < Vr2 < Vr1.

[0049] Here, assuming there are a total of four temperatures T to be detected, let them be Tj1, ···, Tj4 (where Tj1 < Tj2 < Tj3 < Tj4). Also, let the temperature detection voltage at node n1 in the case of temperature Tj1 be the temperature detection voltage Vt1, and the temperature detection voltage at node n1 in the case of temperature Tj2 be the temperature detection voltage Vt2.

[0050] Furthermore, let the temperature detection voltage at node n1 in the case of temperature Tj3 be the temperature detection voltage Vt3, and the temperature detection voltage at node n1 in the case of temperature Tj4 be the temperature detection voltage Vt4. Note that the magnitude relationship of the temperature detection voltages Vt1, ···, Vt4 is Vt4 < Vt3 < Vt2 < Vt1.

[0051] In the temperature detection circuit 11, when the temperature T of the output element M0 to be temperature-detected during operation is T < Tj1, the comparator cmp1, cmp2, cmp3, cmp4 respectively output L-level temperature detection signals A, B, C, D.

[0052] Also, when the temperature T is Tj1 ≤ T < Tj2, the temperature detection voltage Vt1 becomes lower than the reference voltage Vr1 and higher than the reference voltages Vr2, Vr3, Vr4. The comparator cmp1 outputs an H-level temperature detection signal A, and the comparators cmp2, cmp3, cmp4 respectively output L-level temperature detection signals B, C, D.

[0053] Also, when the temperature rises to Tj2 ≤ T < Tj3, the temperature detection voltage Vt2 becomes lower than the reference voltages Vr1, Vr2 and higher than the reference voltages Vr3, Vr4. The comparators cmp1, cmp2 respectively output H-level temperature detection signals A, B, and the comparators cmp3, cmp4 respectively output L-level temperature detection signals C, D.

[0054] Furthermore, when the temperature rises and Tj3 ≤ T < Tj4, the temperature detection voltage Vt3 is lower than the reference voltages Vr1, Vr2, and Vr3 and higher than the reference voltage Vr4. High-level temperature detection signals A, B, and C are respectively output from the comparators cmp1, cmp2, and cmp3, and a low-level temperature detection signal D is output from the comparator cmp4.

[0055] Moreover, when the temperature rises and Tj4 ≤ T, the temperature detection voltage Vt4 is lower than the reference voltages Vr1, Vr2, Vr3, and Vr4, and high-level temperature detection signals A, B, C, and D are respectively output from the comparators cmp1, cmp2, cmp3, and cmp4.

[0056] Thus, in the temperature detection circuit 11 described above, as the temperature rises, high-level (predetermined level) temperature detection signals are gradually output from the comparators cmp1, ···, cmp4. Regarding the outputs of the comparators cmp1, ···, cmp4 as digital logic outputs (high level is 1, low level is 0) and denoting the outputs of the comparators cmp1, ···, cmp4 as (A, B, C, D), when the temperature T of the output element M0 to be temperature-detected is T < Tj1, (A, B, C, D) = (0, 0, 0, 0).

[0057] Also, when the temperature T is Tj1 ≤ T < Tj2, (A, B, C, D) = (1, 0, 0, 0), and when the temperature T is Tj2 ≤ T < Tj3, (A, B, C, D) = (1, 1, 0, 0). Furthermore, when the temperature T is Tj3 ≤ T < Tj4, (A, B, C, D) = (1, 1, 1, 0), and when the temperature T is Tj4 ≤ T, (A, B, C, D) = (1, 1, 1, 1).

[0058] Thus, the temperature detection circuit 11 outputs n (n is a natural number) temperature detection signals for n levels of temperature. In the above example where n = 4, since there are four detected temperatures, four temperature detection signals A, B, C, and D are output.

[0059] Furthermore, the reference voltage generating unit 11b generates n reference voltages based on the current from the constant current source 11a, and generates reference voltages whose voltage values ​​decrease from the first to the kth (1≦k≦n) of the n reference voltages.

[0060] In the above example of n=4, a first reference voltage Vr1, a second reference voltage Vr2, a third reference voltage Vr3, and a fourth reference voltage Vr4 are generated (Vr4 <Vr3<Vr2<Vr1)。

[0061] Furthermore, the comparison circuit 11d compares the kth (1≦k≦n) of n reference voltages with the temperature detection voltage, and when the kth reference voltage is higher than the temperature detection voltage, outputs a temperature detection signal equal to or lower than the kth.

[0062] In the above example where n=4, the first of the four reference voltages Vr1 is compared with the temperature detection voltage, and if the first reference voltage is higher than the temperature detection voltage, the first temperature detection signal A (H-level temperature detection signal A) is output. Also, the second of the four reference voltages Vr2 is compared with the temperature detection voltage, and if the second reference voltage Vr2 is higher than the temperature detection voltage, the second and subsequent (first and second) temperature detection signals A and B (H-level temperature detection signals A and B) are output.

[0063] Furthermore, the third of the four reference voltages Vr3 is compared with the temperature detection voltage, and if the third reference voltage Vr3 is higher than the temperature detection voltage, the third and lower (first, second, third) temperature detection signals A, B, C (H-level temperature detection signals A, B, C) are output. Furthermore, the fourth of the four reference voltages Vr4 is compared with the temperature detection voltage, and if the fourth reference voltage Vr4 is higher than the temperature detection voltage, the fourth and lower (first, second, third, fourth) temperature detection signals A, B, C, D (H-level temperature detection signals A, B, C, D) are output.

[0064] 4 is a diagram showing an example of the configuration of a current limiting circuit. The current limiting circuit 12 includes state-holding circuits 12a1 and 12a2 and gate voltage limiting circuits 12b1 and 12b2. The state-holding circuit 12a1 (first state-holding circuit) includes two-input, one-output negative AND circuits (hereinafter, NAND circuits) ic11 and ic12 and a three-input, one-output NAND circuit ic13. The state-holding circuit 12a2 (second state-holding circuit) includes two-input, one-output NAND circuits ic21 and ic22 and a three-input, one-output NAND circuit ic23.

[0065] The gate voltage limiting circuit 12b1 (first gate voltage limiting circuit) includes a constant current source ir1 and a switch sw1 (first switch), and the gate voltage limiting circuit 12b2 (second gate voltage limiting circuit) includes a constant current source ir2 and a switch sw2 (second switch). The switches sw1 and sw2 are configured with NMOS transistors.

[0066] Regarding the connection relationship of each component, an overcurrent detection signal s1 is input to a first input terminal of the NAND circuit ic11, and a temperature detection signal D is input to a second input terminal of the NAND circuit ic11. The output terminal of the NAND circuit ic11 is connected to a first input terminal of the NAND circuit ic12.

[0067] A second input terminal of the NAND circuit ic12 is connected to an output terminal of the NAND circuit ic13, and an output terminal of the NAND circuit ic12 is connected to the gate of the switch sw1 and a first input terminal of the NAND circuit ic13. An input terminal of the constant current source ir1 is connected to the output terminal of the gate driver 16, the gate of the output element M0, and an input terminal of the constant current source ir2, and an output terminal of the constant current source ir1 is connected to the drain of the switch sw1.

[0068] The source of the switch sw1 is connected to the source of the switch sw2, the source of the output element M0, and the output terminal OUT. The temperature detection signal C is input to a second input terminal of the NAND circuit ic13, and the reset signal rst is input to a third input terminal of the NAND circuit ic13.

[0069] Further, an overcurrent detection signal s1 is input to the first input terminal of the NAND circuit ic21, and a temperature detection signal D is input to the second input terminal of the NAND circuit ic21. The output terminal of the NAND circuit ic21 is connected to the first input terminal of the NAND circuit ic22.

[0070] The second input terminal of the NAND circuit ic22 is connected to the output terminal of the NAND circuit ic23, and the output terminal of the NAND circuit ic22 is connected to the gate of the switch sw2 and the first input terminal of the NAND circuit ic23. The output terminal of the constant current source ir2 is connected to the drain of the switch sw2. A temperature detection signal B is input to the second input terminal of the NAND circuit ic23, and a reset signal rst is input to the third input terminal of the NAND circuit ic13.

[0071] In the current limiting circuit 12 configured as described above, when the output element M0 is in an overcurrent state, the gate voltage applied to the gate of the output element M0 is adjusted in response to the temperature detection signal from the temperature detection circuit 11, and the current flowing through the output element M0 is variably limited. In the configuration of FIG. 4, it is assumed that current limiting is performed for the temperature T detected by the temperature detection circuit 11 when the temperature T is equal to or higher than Tj2, and the temperature detection signals D, C, and B are input (the temperature detection signal A is not used).

[0072] Next, the operation of the current limiting circuit 12 in response to temperature changes will be described. As temperature changes, the cases of Tj4≦T, Tj3≦T<Tj4, Tj2≦T<Tj3, and Tj1≦T<Tj2 described above are shown, and the current limiting when the temperature T gradually decreases will be described. In the current limiting circuit 12, the higher the operating temperature of the output element M0 in the overcurrent state, the stronger the current limiting, and the current limiting is weakened as the temperature decreases.

[0073] Note that Tj4 corresponds to the set temperature, Tj3 corresponds to the first temperature, Tj2 corresponds to the second temperature, and Tj1 corresponds to the third temperature. Also, Tj4≦T corresponds to the first temperature range, Tj3≦T<Tj4 corresponds to the second temperature range, Tj2≦T<Tj3 corresponds to the third temperature range, and Tj1≦T<Tj2 corresponds to the fourth temperature range. Further, the temperature detection signal D at the H level corresponds to the first temperature detection signal, the temperature detection signal C at the H level corresponds to the second temperature detection signal, the temperature detection signal B at the H level corresponds to the third temperature detection signal, and the temperature detection signal A at the H level corresponds to the fourth temperature detection signal.

[0074] Assume that when the load L0 is in a short - circuit state, an over - current state is detected in a high - temperature state (temperature state of Tj4≦T) near the over - heat protection. In this case, an over - current detection signal s1 at the H level is output from the over - current detection circuit 13, and the over - current detection signal s1 at the H level is input to the current - limiting circuit 12. Also, temperature detection signals D, C, B, and A at the H level are output from the temperature detection circuit 11, and among them, the temperature detection signals D, C, and B at the H level are input to the current - limiting circuit 12.

[0075] At this time, in the state - holding circuit 12a1, since the output of the NAND circuit ic11 becomes the L level, a gate - charge extraction signal sg1 at the H level (the first gate - charge extraction signal) is output from the output terminal Q1 (the output terminal of the NAND circuit ic12) of the state - holding circuit 12a1. Also, in the state - holding circuit 12a2, since the output of the NAND circuit ic21 becomes the L level, a gate - charge extraction signal sg2 at the H level (the second gate - charge extraction signal) is output from the output terminal Q2 (the output terminal of the NAND circuit ic22) of the state - holding circuit 12a2.

[0076] Therefore, when the gate - charge extraction signal sg1 at the H level is input to the gate of the switch sw1, the switch sw1 turns on. Thus, the gate of the output element M0 is conducted to the output terminal OUT via the gate - voltage limiting circuit 12b1, and gate charge is extracted from the gate of the output element M0 based on the output current of the constant - current source ir1.

[0077] Also, since the switch sw2 is turned on when the gate charge extraction signal sg2 at the H level is input to the gate of the switch sw2, the gate of the output element M0 is conducted to the output terminal OUT via the gate voltage limiting circuit 12b2, and the gate charge is extracted from the gate of the output element M0 based on the output current of the constant current source ir2.

[0078] In this way, when the output element M0 is in an overcurrent state and the temperature state is Tj4 ≦ T, the two gate voltage limiting circuits 12b1 and 12b2 are driven by the gate charge extraction signals sg1 and sg2, and the gate charge is extracted from the gate of the output element M0.

[0079] Therefore, assuming that the current flowing between the drain and source when the output element M0 is on before the gate charge is extracted is Id1, and the current after the two gate voltage limiting circuits 12b1 and 12b2 are driven to extract the gate charge from the gate of the output element M0 is Id2, then Id2 < Id1, and the current flowing through the output element M0 in the high-temperature state can be limited.

[0080] Note that the reset signal rst in the figure is the power-on reset signal of the semiconductor device 10, and is generated inside the semiconductor device 10 or transmitted from the microcomputer 5, for example. The reset signal rst is a pulse at the L level at the start of operation of the semiconductor device 10, and is a signal at the H level during operation.

[0081] Therefore, when the reset signal rst at the L level pulse is input to the state holding circuits 12a1 and 12a2 at the start of operation, the output terminals Q1 and Q2 of the state holding circuits 12a1 and 12a2 respectively become the L level, and the state holding is reset. As a result, the operation of extracting the gate charge from the gate of the output element M0 is stopped.

[0082] When [Tj3 ≤ T < Tj4], although the output element M0 is in an overcurrent state, it is assumed that the operating temperature T of the output element M0 has decreased until it falls within the range of Tj3 ≤ T < Tj4. In this case, an H-level overcurrent detection signal s1 is output from the overcurrent detection circuit 13, and the H-level overcurrent detection signal s1 is input to the current limiting circuit 12. Also, an L-level temperature detection signal D is output from the temperature detection circuit 11, and H-level temperature detection signals C, B, and A are output. Therefore, the L-level temperature detection signal D and the H-level temperature detection signals C and B are input to the current limiting circuit 12.

[0083] At this time, in the state holding circuit 12a1, the output of the NAND circuit ic11 becomes H-level. Also, since the output of the NAND circuit ic13 becomes L-level, an H-level gate charge extraction signal sg1 is output from the output terminal Q1 (the output terminal of the NAND circuit ic12) of the state holding circuit 12a1.

[0084] On the other hand, in the state holding circuit 12a2, the output of the NAND circuit ic21 becomes H-level. Also, since the output of the NAND circuit ic23 becomes L-level, an H-level gate charge extraction signal sg2 is output from the output terminal Q2 (the output terminal of the NAND circuit ic22) of the state holding circuit 12a2. Therefore, even when the output element M0 is in an overcurrent state and the temperature state is Tj3 ≤ T < Tj4, the two gate voltage limiting circuits 12b1 and 12b2 are driven and gate charge extraction signals sg1 and sg2 are output. Thus, gate charge is extracted from the gate of the output element M0, and the current flowing through the output element M0 is restricted.

[0085] When [Tj2 ≤ T < Tj3], although the output element M0 is in an overcurrent state, it is assumed that the operating temperature T of the output element M0 has decreased until it falls within the range of Tj2 ≤ T < Tj3. In this case, an H-level overcurrent detection signal s1 is output from the overcurrent detection circuit 13, and the H-level overcurrent detection signal s1 is input to the current limiting circuit 12. Also, L-level temperature detection signals D and C are output from the temperature detection circuit 11, and H-level temperature detection signals B and A are output. Therefore, the L-level temperature detection signals D and C and the H-level temperature detection signal B are input to the current limiting circuit 12.

[0086] At this time, in the state holding circuit 12a1, the output of the NAND circuit ic11 becomes the H level. Also, since the output of the NAND circuit ic13 becomes the H level, a gate charge extraction signal sg1 of the L level is output from the output terminal Q1 (the output terminal of the NAND circuit ic12) of the state holding circuit 12a1.

[0087] On the other hand, in the state holding circuit 12a2, the output of the NAND circuit ic21 becomes the H level. Also, since the output of the NAND circuit ic23 becomes the L level, a gate charge extraction signal sg2 of the H level is output from the output terminal Q2 (the output terminal of the NAND circuit ic22) of the state holding circuit 12a2.

[0088] Therefore, when the gate charge extraction signal sg1 of the L level is input to the gate of the switch sw1, the switch sw1 turns off, but when the gate charge extraction signal sg2 of the H level is input to the gate of the switch sw2, the switch sw2 turns on, so that the gate charge is extracted from the gate of the output element M0.

[0089] Therefore, assuming that the current after the gate charge is extracted from the gate of the output element M0 by driving one gate voltage limiting circuit 12b2 is Id3, then Id3 < Id1, and it is possible to limit the current flowing through the output element M0 in the high temperature state. Note that since the gate charge is only extracted from the gate voltage limiting circuit 12b2, Id2 < Id3, and the current limit is weakened compared to the cases where the temperature state is Tj4 ≤ T and Tj3 ≤ T < Tj4.

[0090] When [Tj1 ≤ T < Tj2], although the output element M0 is in an overcurrent state, it is assumed that the operating temperature T of the output element M0 has decreased until it falls within the range of Tj1 ≤ T < Tj2. In this case, an H-level overcurrent detection signal s1 is output from the overcurrent detection circuit 13, and the H-level overcurrent detection signal s1 is input to the current limit circuit 12. Also, L-level temperature detection signals D, C, and B are output from the temperature detection circuit 11, and an H-level temperature detection signal A is output. However, the L-level temperature detection signals D, C, and B are input to the current limit circuit 12.

[0091] At this time, in the state holding circuit 12a1, the output of the NAND circuit ic11 becomes H-level. Also, since the output of the NAND circuit ic13 becomes H-level, an L-level gate charge extraction signal sg1 is output from the output terminal Q1 (the output terminal of the NAND circuit ic12) of the state holding circuit 12a1.

[0092] On the other hand, in the state holding circuit 12a2, the output of the NAND circuit ic21 becomes H-level. Also, since the output of the NAND circuit ic23 becomes H-level, an L-level gate charge extraction signal sg2 is output from the output terminal Q2 (the output terminal of the NAND circuit ic22) of the state holding circuit 12a2.

[0093] Therefore, when the L-level gate charge extraction signal sg1 is input to the gate of the switch sw1, the switch sw1 turns off, and when the L-level gate charge extraction signal sg2 is input to the gate of the switch sw2, the switch sw2 turns off. Thus, gate charge is not extracted from the gate of the output element M0. Therefore, in the configuration of FIG. 4, when the output element M0 is in an overcurrent state and the temperature state is Tj1 ≤ T < Tj2, current limiting is not performed.

[0094] FIG. 5 is a time chart showing an example of the operation of the current limit circuit. Note that the illustration of the temperature detection signal A is omitted. [Period pd11] When an H-level control signal s0 is input to the input terminal IN, the output element M0 is turned on. In addition, a load short circuit occurs, causing an overcurrent state, and the overcurrent detection circuit 13 outputs an H-level overcurrent detection signal s1.

[0095] Furthermore, depending on the temperature T of the output element M0, an L-level temperature detection signal D and H-level temperature detection signals C and B are output, but before the temperature T reaches the set temperature, the control signal s0 becomes L level and the output element M0 is turned off, so no current limiting operation is performed.

[0096] As a result, the gate voltage of the output device M0 becomes the voltage level Vg11 of the turn-on instruction signal output from the gate driver 16 because no gate charge is extracted, and a current (output device current) Id11 flows between the drain and source of the output device M0.

[0097] [Period pd12] After an L-level control signal s0 is input to the input terminal IN to turn off the output element M0, an H-level control signal s0 is input to the input terminal IN to turn on the output element M0. Since the load is continuously short-circuited, an overcurrent state occurs, and the overcurrent detection circuit 13 outputs an H-level overcurrent detection signal s1.

[0098] Furthermore, assume that the temperature T of the output element M0 has risen from that during period pd11 and is, for example, in the range of Tj4≦T. Therefore, the temperature detection circuit 11 outputs H-level temperature detection signals D, C, and B. As a result, as described above, the state holding circuit 12a1 outputs an H-level gate charge extraction signal sg1, and the state holding circuit 12a2 outputs an H-level gate charge extraction signal sg2.

[0099] Therefore, the gate voltage of the output element M0 transitions to a voltage level Vg12 lower than the voltage level Vg11 (Vg12 < Vg11) as gate charge is withdrawn through two paths of the gate charge withdrawal signals sg1 and sg2, and a current Id12 smaller than the current Id11 flows between the drain and source of the output element M0 (Id12 < Id11).

[0100] 〔Period pd13〕After a control signal s0 of L level is input to the input terminal IN and the output element M0 is turned off, a control signal s0 of H level is input to the input terminal IN and the output element M0 is turned on. Since a load short circuit is continuously occurring, an overcurrent state exists, and an overcurrent detection signal s1 of H level is output from the overcurrent detection circuit 13.

[0101] On the other hand, the temperature T of the output element M0 decreases during the OFF period, for example, to a range of Tj2 ≤ T < Tj3, in addition to the current limit based on the gate charge withdrawal control being performed during the period pd12. Therefore, a temperature detection signal D, C of L level and a temperature detection signal B of H level are output from the temperature detection circuit 11. Thus, as described above, a gate charge withdrawal signal sg1 of L level is output from the state holding circuit 12a1, and a gate charge withdrawal signal sg2 of H level is output from the state holding circuit 12a2.

[0102] For this reason, the gate voltage of the output element M0 transitions to a voltage level Vg13 that is lower than the voltage level Vg11 but higher than the voltage level Vg12 (Vg12 < Vg13 < Vg11) as gate charge is withdrawn through one path of the gate charge withdrawal signal sg2. Therefore, a current Id13 that is smaller than the current Id11 but larger than the current Id12 flows between the drain and source of the output element M0 (Id12 < Id13 < Id11).

[0103] FIG. 6 is a diagram showing an example of the configuration of a current limiting circuit. The current limiting circuit 12-1 shown in FIG. 6 has a circuit configuration that allows the temperature state to be detected by the temperature detection signal A. The current limiting circuit 12-1 includes state-holding circuits 12a1, 12a2, and 12a3 and gate voltage limiting circuits 12b1, 12b2, and 12b3. The state-holding circuit 12a3 (third state-holding circuit) includes two-input, one-output NAND circuits ic31 and ic32 and a three-input, one-output NAND circuit ic33. The gate voltage limiting circuit 12b3 (third gate voltage limiting circuit) includes a constant current source ir3 and a switch sw3 (third switch). The switch sw3 is configured by an NMOS transistor.

[0104] The overcurrent detection signal s1 is input to a first input terminal of the NAND circuit ic31, and the temperature detection signal D is input to a second input terminal of the NAND circuit ic31. The output terminal of the NAND circuit ic31 is connected to a first input terminal of the NAND circuit ic32.

[0105] A second input terminal of the NAND circuit ic32 is connected to an output terminal of the NAND circuit ic33, and an output terminal of the NAND circuit ic32 is connected to the gate of the switch sw3 and a first input terminal of the NAND circuit ic33. An input terminal of the constant current source ir3 is connected to the output terminal of the gate driver 16, the gate of the output element M0, and the input terminals of the constant current sources ir1 and ir2, and an output terminal of the constant current source ir3 is connected to the drain of the switch sw3.

[0106] The source of the switch sw3 is connected to the source of the output element M0, the sources of the switches sw1 and sw2, and the output terminal OUT. The temperature detection signal A is input to the second input terminal of the NAND circuit ic33, and the reset signal rst is input to the third input terminal of the NAND circuit ic33. The other configurations are the same as those in FIG.

[0107] In the current limiting circuit 12-1 configured as described above, when the temperature T of the output element M0 in the overcurrent state satisfies Tj4 ≤ T, the temperature detection signals D, C, B, and A are at the H level, and the gate charge extraction signals sg1, sg2, and the gate charge extraction signal sg3 (the third gate charge extraction signal) are at the H level. Therefore, the switches sw1, sw2, and sw3 are turned on, and the gate charge is extracted from the gate of the output element M0 through three paths.

[0108] Also, when the temperature T of the output element M0 in the overcurrent state satisfies Tj3 ≤ T < Tj4, the temperature detection signal D is at the L level, the temperature detection signals C, B, and A are at the H level, and the gate charge extraction signals sg1, sg2, and sg3 are at the H level. Therefore, the switches sw1, sw2, and sw3 are turned on, and the gate charge is extracted from the gate of the output element M0 through three paths.

[0109] Furthermore, when the temperature T of the output element M0 in the overcurrent state satisfies Tj2 ≤ T < Tj3, the temperature detection signals D and C are at the L level, the temperature detection signals B and A are at the H level, the gate charge extraction signal sg1 is at the L level, and the gate charge extraction signals sg2 and sg3 are at the H level. Therefore, the switch sw1 is turned off, and the switches sw2 and sw3 are turned on, so the gate charge is extracted from the gate of the output element M0 through two paths.

[0110] Moreover, when the temperature T of the output element M0 in the overcurrent state satisfies Tj1 ≤ T < Tj2, the temperature detection signals D, C, and B are at the L level, the temperature detection signal A is at the H level, the gate charge extraction signals sg1 and sg2 are at the L level, and the gate charge extraction signal sg3 is at the H level. Therefore, the switches sw1 and sw2 are turned off, and the switch sw3 is turned on, so the gate charge is extracted from the gate of the output element M0 through one path.

[0111] When the temperature T of the output element M0 in the overcurrent state satisfies T < Tj1, the temperature detection signals D, C, B, and A are at the L level, the gate charge extraction signals sg1, sg2, and sg3 are at the L level, and the switches sw1, sw2, and sw3 are turned off. Therefore, no gate charge is extracted from the gate of the output element M0.

[0112] Note that in this embodiment, the number of temperature detection signals is four, and the number of state holding circuits and gate voltage limiting circuits is three each. However, the number of temperature detection signals, the number of state holding circuits, and the number of gate voltage limiting circuits are not limited to this.

[0113] As a second embodiment, the inputs to the inverting input terminals and non-inverting input terminals of each comparator of the comparison circuit 11d in FIG. 3 may be reversed, and the output of the node n1 may be input to the non-inverting input terminal, and the reference voltages Vr1 to Vr4 generated by the reference voltage generation unit may be input to the inverting input terminals. The configuration of the temperature detection circuit 11-1 in this case is shown in FIG. 7.

[0114] Also, the configuration of the current limiting circuit 12-2 in the second embodiment is shown in FIG. 8. All the NAND circuits ic11 to ic23 become NOR circuits id11 to id23, the overcurrent detection signal s1 becomes the inverted overcurrent detection signal s1´, and NOT circuits in1 and in2 are connected to the outputs of the NOR circuits id12 and id22. The other configurations are the same as those in FIGS. 3 and 4.

[0115] Next, the configuration of the modification will be described. FIG. 7 is a diagram showing an example of the configuration of a temperature detection circuit. The temperature detection circuit 11-1 includes a constant current source 11a (constant current source for temperature detection), a reference voltage generation unit 11b, a detection circuit 11c, and a comparison circuit 11d. The constant current source 11a includes a constant current element 11a1 (first constant current element) and a constant current element 11a2 (second constant current element), and the reference voltage generation unit 11b includes resistors R1, ···, R4.

[0116] The detection circuit 11c includes temperature sense diodes D1, . . . , D4, whose temperature detection voltage based on the current from the constant current source 11a decreases with an increase in temperature. The comparison circuit 11d includes comparators cmp1, . . . , cmp4, which correspond to the first to fourth comparators, respectively.

[0117] Here, the difference from the configuration in FIG. 3 is that the non-inverting input terminals (+) of the comparators cmp1, . . . , cmp4 are connected to a node n1 between the output terminal of the constant current source 11a1 and the anode of the temperature sensing diode D1.

[0118] Furthermore, the inverting input terminal (-) of the comparator cmp1 is connected to a node n2 between the output terminal of the constant current source 11a2 and one end of the resistor R1, and the inverting input terminal (-) of the comparator cmp2 is connected between the other end of the resistor R1 of the constant current source 11a2 and one end of the resistor R2.

[0119] Furthermore, the inverting input terminal (-) of the comparator cmp3 is connected between the other end of the resistor R2 of the constant current source 11a2 and one end of the resistor R3, and the inverting input terminal (-) of the comparator cmp4 is connected between the other end of the resistor R3 of the constant current source 11a2 and one end of the resistor R4. The other configurations are the same as those in FIG.

[0120] 3 outputs a temperature detection signal of a predetermined level (H level) when the reference voltage is higher than the temperature detection voltage. In contrast, the temperature detection circuit 11-1 of the modified example outputs a temperature detection signal of a predetermined level (L level) when the reference voltage is lower than the temperature detection voltage.

[0121] Fig. 8 is a diagram showing an example of the configuration of a current limiting circuit. A current limiting circuit 12-2 of a modified example has a circuit configuration that performs current limiting in response to an overcurrent detection signal s1 that goes to L level when an overcurrent is detected and temperature detection signals A, B, C, and D output from the temperature detection circuit 11-1 shown in Fig. 7. The current limiting circuit 12-2 includes state holding circuits 12a4, 12a5, and 12a6 and gate voltage limiting circuits 12b1, 12b2, and 12b3.

[0122] The state holding circuit 12a4 includes two-input, one-output NOR circuits (hereinafter, NOR circuits) ic41 and ic42, a three-input, one-output NOR circuit ic43, and an inverter circuit ic44. The state holding circuit 12a5 includes two-input, one-output NOR circuits ic51 and ic52, a three-input, one-output NOR circuit ic53, and an inverter circuit ic54. The state holding circuit 12a6 includes two-input, one-output NOR circuits ic61 and ic62, a three-input, one-output NOR circuit ic63, and an inverter circuit ic64. The gate voltage limiting circuits 12b1, 12b2, and 12b3 have the same configuration as in FIG. 6.

[0123] The connection relationship of each component element different from that in Fig. 6 will be described. An overcurrent detection signal s1 (overcurrent detection at L level) is input to a first input terminal of the NOR circuit ic41, and a temperature detection signal D is input to a second input terminal of the NOR circuit ic41. The output terminal of the NOR circuit ic41 is connected to a first input terminal of the NOR circuit ic42.

[0124] A second input terminal of the NOR circuit ic42 is connected to an output terminal of the NOR circuit ic43, and an output terminal of the NOR circuit ic42 is connected to an input terminal of the inverter circuit ic44 and a first input terminal of the NOR circuit ic43. An output terminal of the inverter circuit ic44 is connected to the gate of the switch element sw1. A temperature detection signal C is input to a second input terminal of the NOR circuit ic43, and a reset signal rst (the signal is inverted from that in FIG. 4 and FIG. 6) is input to a third input terminal of the NOR circuit ic43.

[0125] An overcurrent detection signal s1 (overcurrent detection at L level) is input to a first input terminal of the NOR circuit ic51, and a temperature detection signal D is input to a second input terminal of the NOR circuit ic51. The output terminal of the NOR circuit ic51 is connected to a first input terminal of the NOR circuit ic52.

[0126] A second input terminal of the NOR circuit ic52 is connected to an output terminal of the NOR circuit ic53, and an output terminal of the NOR circuit ic52 is connected to an input terminal of the inverter circuit ic54 and a first input terminal of the NOR circuit ic53. An output terminal of the inverter circuit ic54 is connected to the gate of the switch element sw2. A temperature detection signal B is input to a second input terminal of the NOR circuit ic53, and a reset signal rst (the signal is inverted from that in FIG. 4 and FIG. 6) is input to a third input terminal of the NOR circuit ic53.

[0127] Furthermore, an overcurrent detection signal s1 (overcurrent detected at L level) is input to a first input terminal of the NOR circuit ic61, and a temperature detection signal D is input to a second input terminal of the NOR circuit ic61. The output terminal of the NOR circuit ic61 is connected to a first input terminal of the NOR circuit ic62.

[0128] A second input terminal of the NOR circuit ic62 is connected to an output terminal of the NOR circuit ic63, and an output terminal of the NOR circuit ic62 is connected to an input terminal of the inverter circuit ic64 and a first input terminal of the NOR circuit ic63. An output terminal of the inverter circuit ic64 is connected to the gate of the switch element sw3. A temperature detection signal A is input to a second input terminal of the NOR circuit ic63, and a reset signal rst (the signal is inverted from that in FIG. 4 and FIG. 6) is input to a third input terminal of the NOR circuit ic63.

[0129] In the above current limiting circuit 12-2, an inverted input signal is input, so by configuring the NAND circuit in the internal configuration of the state retention circuit with a NOR circuit and inserting an inverter circuit at the output terminal, a function similar to that in FIG. 6 can be achieved.

[0130] 9 is a time chart showing an example of the operation of the current limiting circuit, which shows an example of the operation when the temperature detection signals D, C, and B are used in the current limiting circuit 12-2 shown in FIG.

[0131] [Period pd21] When an H-level control signal s0 is input to the input terminal IN, the output element M0 is turned on. In addition, a load short circuit occurs, causing an overcurrent state, and the overcurrent detection circuit 13 outputs an L-level overcurrent detection signal s1.

[0132] Furthermore, depending on the temperature T of the output element M0, an H-level temperature detection signal D and L-level temperature detection signals C and B are output, but before the temperature T reaches the set temperature, the control signal s0 becomes L level and the output element M0 is turned off, so no current limiting operation is performed.

[0133] As a result, the gate voltage of the output device M0 becomes the voltage level Vg11 of the turn-on instruction signal output from the gate driver 16 because no gate charge is extracted, and a current (output device current) Id11 flows between the drain and source of the output device M0.

[0134] [Period pd22] After an L-level control signal s0 is input to the input terminal IN to turn off the output element M0, an H-level control signal s0 is input to the input terminal IN to turn on the output element M0. Since the load short circuit continues, an overcurrent state occurs, and the overcurrent detection circuit 13 outputs an L-level overcurrent detection signal s1.

[0135] Furthermore, assume that the temperature T of the output element M0 has risen from that in period pd21 and is, for example, in the range of Tj4≦T. Therefore, the temperature detection circuit 11-1 outputs L-level temperature detection signals D, C, and B. Therefore, the state holding circuit 12a4 outputs an H-level gate charge extraction signal sg1, and the state holding circuit 12a5 outputs an H-level gate charge extraction signal sg2.

[0136] Therefore, the gate voltage of the output element M0 transitions to a voltage level Vg12 lower than the voltage level Vg11 (Vg12 < Vg11) as gate charge is withdrawn through two paths of the gate charge withdrawal signals sg1 and sg2, and a current Id12 smaller than the current Id11 flows between the drain and source of the output element M0 (Id12 < Id11).

[0137] 〔Period pd23〕After a control signal s0 of L level is input to the input terminal IN and the output element M0 is turned off, a control signal s0 of H level is input to the input terminal IN and the output element M0 is turned on. Since a load short circuit continuously occurs and the overcurrent state is present, an overcurrent detection signal s1 of L level is output from the overcurrent detection circuit 13.

[0138] On the other hand, the temperature T of the output element M0 decreases during the OFF period in addition to the current limiting based on the gate charge withdrawal control being performed in the period pd22, and it is assumed that the temperature drops to a range of, for example, Tj2 ≤ T < Tj3. Therefore, the temperature detection circuit 11-1 outputs a temperature detection signal D, C of H level and a temperature detection signal B of L level. Accordingly, a gate charge withdrawal signal sg1 of L level is output from the state holding circuit 12a4, and a gate charge withdrawal signal sg2 of H level is output from the state holding circuit 12a5.

[0139] Therefore, the gate voltage of the output element M0 transitions to a voltage level Vg13 that is lower than the voltage level Vg11 but higher than the voltage level Vg12 (Vg12 < Vg13 < Vg11) as gate charge is withdrawn through one path of the gate charge withdrawal signal sg2. Thus, a current Id13 that is smaller than the current Id11 but larger than the current Id12 flows between the drain and source of the output element M0 (Id12 < Id13 < Id11).

[0140] As described above, according to the present invention, when the output element enters an overcurrent state, the current flowing through the output element is limited based on the temperature detection result by the temperature detection circuit. As a result, even if the load is short-circuited, the current limiting control continues until the operating temperature of the output element drops to a certain temperature value, so that the large current operation of the output element at high temperatures can be limited and the reliability of the output element's operation can be improved. In addition, by suppressing the temperature rise and limiting the current, it is possible to avoid the occurrence of electromigration, which can cause deformation of conductors and circuit failures.

[0141] Although the embodiments have been described above, the configurations of the parts shown in the embodiments can be replaced with other configurations having similar functions. Any other components or steps may be added. Furthermore, any two or more configurations (features) of the above-described embodiments may be combined. [Explanation of symbols]

[0142] 10 Semiconductor device 11 Temperature detection circuit 12 Current limiting circuit 13 Overcurrent detection circuit M0 output element L0 load pd1, pd2, pd3 period Vg1, Vg2, Vg3 Gate voltages Id1, Id2, Id3 Output element current

Claims

1. an output element connected to an output terminal connected to a load and a power supply terminal connected to a power supply; an overcurrent detection circuit for detecting an overcurrent state of the output element; a temperature detection circuit for detecting a temperature during operation of the output element; a current limiting circuit that, when the overcurrent state is detected and the temperature exceeds a set temperature, sets a gate voltage of the output element to a voltage lower than that at which the output element is turned on when the set temperature is not exceeded, and increases the gate voltage as the temperature decreases to a reference temperature lower than the set temperature, thereby limiting the current flowing through the output element; A semiconductor device having the above structure.

2. The reference temperatures are a total of n-1 temperatures from a first temperature to an n-1th temperature (n is a natural number of 3 or more), the temperature detection circuit outputs a total of n temperature detection signals corresponding to a total of n stages of the set temperature and the reference temperature, and the current limiting circuit limits a current flowing through the output element based on the n temperature detection signals. The semiconductor device according to claim 1.

3. the temperature detection signal group is a collection of the temperature detection signals, The current limiting circuit includes: generating p gate charge extraction signals (p being a natural number less than n) when the temperature detection signal indicating that the temperature exceeds the set temperature is received, and extracting charges from the gates of the output elements by the p gate charge extraction signals; generating q (q is a natural number) gate charge extraction signals, which is less than p, when the group of temperature detection signals indicating that the temperature has fallen below the reference temperature after exceeding the set temperature, and extracting gate charge from the gate by the q gate charge extraction signals; 3. The semiconductor device according to claim 2.

4. The temperature detection circuit includes: A constant current source for detecting temperature; a detection circuit including a temperature sense diode, the temperature detection voltage of which is based on a current from the constant current source for temperature detection and decreases with an increase in temperature; a reference voltage generating unit that generates a reference voltage based on a current from the temperature detection constant current source; a comparison circuit that compares the reference voltage with the temperature detection voltage and outputs the temperature detection signal of a predetermined level when the reference voltage is higher than the temperature detection voltage; 3. The semiconductor device according to claim 2, further comprising:

5. the reference voltage generating unit generates n reference voltages whose voltage values ​​decrease from 1 to n based on a current from the temperature detection constant current source, the comparator circuit compares a kth (1≦k≦n) of the n reference voltages with the temperature detection voltage, and when the kth reference voltage is higher than the temperature detection voltage, outputs the temperature detection signal at a predetermined level equal to or lower than the kth reference voltage.

5. The semiconductor device according to claim 4.

6. the temperature detection constant current source includes a first constant current source and a second constant current source; the reference voltage generating unit includes a total of n resistors connected in series from a first resistor to an n-th resistor in order from a high potential side to a low potential side, and the comparison circuit includes a total of n comparators from a first comparator to an n-th comparator, an input terminal of the first constant current source is connected to an input terminal of the second constant current source and a power supply unit; an output terminal of the first constant current source is connected to an anode of the temperature sensing diode and inverting input terminals of a total of n comparators from the first comparator to the nth comparator; an output terminal of the second constant current source is connected to a non-inverting input terminal of the first comparator and one terminal of the first resistor, and a first temperature detection signal having a first predetermined level is output from an output terminal of the first comparator; A non-inverting input terminal of the kth comparator is directly connected to the high potential end of the kth resistor, and a kth temperature detection signal of a predetermined level is output from an output terminal of the kth comparator (1≦k≦n); the other end of the nth resistor is connected to the cathode of the temperature sensing diode and to ground; 5. The semiconductor device according to claim 4.

7. the reference temperatures are a first temperature to an n-1th temperature, The current limiting circuit includes: when receiving the group of temperature detection signals indicating that the temperature is in a first temperature range equal to or higher than the set temperature, or that the temperature is in a second temperature range equal to or higher than the first temperature but lower than the set temperature after the temperature has reached or exceeded the set temperature, generating all gate charge extraction signals from a first gate charge extraction signal to an (n-1)th gate charge extraction signal, and extracting gate charge from the gate via (n-1) paths; when the temperature detection signal group indicating that the temperature is in an r+1th temperature range that is equal to or higher than an r-th temperature that is lower than the r-1th temperature and lower than the r-1th temperature is received after the temperature has reached the set temperature, generate the r-th gate charge extraction signal to the n-1th gate charge extraction signal out of the first gate charge extraction signal to the n-1th gate charge extraction signal, and extract the gate charge from the gate via n-r paths (2≦r≦n-1); 4. The semiconductor device according to claim 3.

8. The temperature detection circuit includes: In a k-th temperature range, outputting a k-th temperature detection signal having a predetermined level to an n-th temperature detection signal having a predetermined level; The current limiting circuit includes: The first state holding circuit to the (n-1)th state holding circuit are included, the qth gate voltage control circuit includes a qth state holding circuit which outputs the qth gate charge extraction signal after receiving a first temperature detection signal of a predetermined level when receiving an overcurrent detection signal output from the overcurrent detection circuit when the overcurrent state is detected, until the qth temperature detection signal of the predetermined level is no longer received, and a qth switch which makes the gate conductive to an output terminal of the device by switching based on the qth gate charge extraction signal; 8. The semiconductor device according to claim 7.

9. The temperature detection circuit includes: A constant current source for detecting temperature; a detection circuit including a temperature sense diode, the temperature detection voltage of which is based on a current from the constant current source for temperature detection and decreases with an increase in temperature; a reference voltage generating unit that generates a reference voltage based on a current from the temperature detection constant current source; a comparison circuit that compares the reference voltage with the temperature detection voltage and outputs the temperature detection signal at a predetermined level when the reference voltage is lower than the temperature detection voltage; 3. The semiconductor device according to claim 2, further comprising:

10. the reference voltage generating unit generates n reference voltages whose voltage values ​​decrease from 1 to n based on a current from the temperature detection constant current source, the comparator circuit compares the kth (1≦k≦n) reference voltage out of n with the temperature detection voltage, and when the kth reference voltage is lower than the temperature detection voltage, outputs the temperature detection signal at a predetermined level equal to or lower than the kth reference voltage. The semiconductor device according to claim 9.

11. the temperature detection constant current source includes a first constant current source and a second constant current source; the reference voltage generating unit includes a total of n resistors connected in series from a first resistor to an n-th resistor in order from a high potential side to a low potential side, and the comparison circuit includes a total of n comparators from a first comparator to an n-th comparator, an input terminal of the first constant current source is connected to an input terminal of the second constant current source and a power supply unit; an output terminal of the first constant current source is connected to an anode of the temperature sensing diode and non-inverting input terminals of a total of n comparators from the first comparator to the nth comparator; an output terminal of the second constant current source is connected to an inverting input terminal of the first comparator and one terminal of the first resistor, and a first temperature detection signal having a first predetermined level is output from an output terminal of the first comparator; The inverting input terminal of the kth comparator is directly connected to the high potential end of the kth resistor, and a kth temperature detection signal of a predetermined level is output from the output terminal of the kth comparator (1≦k≦n); the other end of the nth resistor is connected to the cathode of the temperature sensing diode and to ground; The semiconductor device according to claim 9.

12. The temperature detection circuit includes: In a k-th temperature range, outputting a first temperature detection signal having a predetermined level to the k-1-th temperature detection signal having a predetermined level; The current limiting circuit includes: The first state holding circuit to the (n-1)th state holding circuit are included, the qth gate voltage control circuit includes a qth state holding circuit which outputs the qth gate charge extraction signal after the first temperature detection signal of a predetermined level is no longer received when the overcurrent detection signal output from the overcurrent detection circuit is received when the overcurrent state is detected, until the qth temperature detection signal of a predetermined level is received, and a qth switch which makes the gate conductive to an output terminal of the device by switching based on the qth gate charge extraction signal.

8. The semiconductor device according to claim 7.

13. an output element connected to an output terminal connected to a load and a power supply terminal connected to a power supply; an overcurrent detection circuit for detecting an overcurrent state of the output element; a temperature detection circuit for detecting a temperature during operation of the output element; a current limiting circuit that, when the overcurrent state is detected and the temperature exceeds a set temperature, limits a current flowing through the output element by setting a gate voltage of the output element to a voltage lower than that at which the output element is turned on when the set temperature is not exceeded, and increases the gate voltage to the voltage when the set temperature is not exceeded when the temperature drops to a reference temperature lower than the set temperature; A semiconductor device having the above structure.

14. the temperature detection circuit outputs two temperature detection signals corresponding to the set temperature and the reference temperature, and the current limiting circuit limits a current flowing through the output element based on the two temperature detection signals. The semiconductor device according to claim 13.

15. the temperature detection signal group is a collection of the temperature detection signals, The current limiting circuit includes: generating a gate charge extraction signal to extract charge from the gate of the output element when the temperature detection signal is received indicating that the temperature exceeds the set temperature; when receiving the group of temperature detection signals indicating that the temperature has fallen below the reference temperature after the temperature has exceeded the set temperature, stopping the gate charge extraction signal to stop gate charge extraction; The semiconductor device according to claim 14.

16. The temperature detection circuit includes: A constant current source for detecting temperature; a detection circuit including a temperature sense diode, the temperature detection voltage of which is based on a current from the constant current source for temperature detection and decreases with an increase in temperature; a reference voltage generating unit that generates a reference voltage based on a current from the temperature detection constant current source; a comparison circuit that compares the reference voltage with the temperature detection voltage and outputs the temperature detection signal of a predetermined level when the reference voltage is higher than the temperature detection voltage; The semiconductor device according to claim 14, comprising:

17. the reference voltage generating unit generates a first higher reference voltage and a second lower reference voltage based on a current from the temperature detection constant current source; the comparator circuit compares a first reference voltage with the temperature detection voltage, and when the first reference voltage is higher than the temperature detection voltage, outputs the temperature detection signal at a first predetermined level, and compares a second reference voltage with the temperature detection voltage, and when the second reference voltage is higher than the temperature detection voltage, outputs the temperature detection signals at the first and second predetermined levels.

17. The semiconductor device according to claim 16.

18. the temperature detection constant current source includes a first constant current source and a second constant current source; the reference voltage generating unit includes a first resistor and a second resistor connected in series in this order from a high potential side to a low potential side, and the comparison circuit includes a first comparator and a second comparator, an input terminal of the first constant current source is connected to an input terminal of the second constant current source and a power supply unit; an output terminal of the first constant current source is connected to the anode of the temperature sensing diode and the inverting input terminals of the first and second comparators; an output terminal of the second constant current source is connected to a non-inverting input terminal of the first comparator and one terminal of the first resistor, and a first temperature detection signal having a first predetermined level is output from an output terminal of the first comparator; a non-inverting input terminal of the second comparator is directly connected to a high potential end of a second resistor, and a second temperature detection signal having a predetermined level is output from an output terminal of the second comparator; the other end of the second resistor is connected to the cathode of the temperature sensing diode and to ground; 17. The semiconductor device according to claim 16.

19. The current limiting circuit includes: generating a gate charge extraction signal to extract a gate charge from the gate when the temperature detection signal group is received indicating that the temperature is in a first temperature range equal to or higher than the set temperature, or that the temperature is in a second temperature range equal to or higher than the reference temperature and lower than the set temperature after the temperature has reached or exceeded the set temperature, and when the temperature detection signal group indicating that the temperature is in a third temperature range less than the reference temperature is received after the temperature has reached the set temperature or higher, the gate charge extraction signal is stopped to stop the extraction of the gate charge from the gate.

16. The semiconductor device according to claim 15.

20. The temperature detection circuit includes: outputting a first temperature detection signal having a predetermined level to a second temperature detection signal having a predetermined level within the first temperature range; outputting the second temperature detection signal at a predetermined level in the second temperature range; In the third temperature range, the temperature detection signal is not output at a predetermined level, The current limiting circuit includes: a state holding circuit which outputs the gate charge extraction signal after receiving the first temperature detection signal of a predetermined level when the overcurrent detection signal is output from the overcurrent detection circuit when the overcurrent state is detected, until the second temperature detection signal of the predetermined level is no longer received, and a switch which makes the gate conductive to an output terminal of a device by switching based on the gate charge extraction signal.

20. The semiconductor device according to claim 19.

21. The temperature detection circuit includes: A constant current source for detecting temperature; a detection circuit including a temperature sense diode, the temperature detection voltage of which is based on a current from the constant current source for temperature detection and decreases with an increase in temperature; a reference voltage generating unit that generates a reference voltage based on a current from the temperature detection constant current source; a comparison circuit that compares the reference voltage with the temperature detection voltage and outputs the temperature detection signal at a predetermined level when the reference voltage is lower than the temperature detection voltage; The semiconductor device according to claim 14, comprising:

22. the reference voltage generating unit generates a first higher reference voltage and a second lower reference voltage based on a current from the temperature detection constant current source; the comparator circuit compares a first reference voltage with the temperature detection voltage, and when the first reference voltage is lower than the temperature detection voltage, outputs the temperature detection signal at a first predetermined level, and compares a second reference voltage with the temperature detection voltage, and when the second reference voltage is lower than the temperature detection voltage, outputs the temperature detection signals at the first and second predetermined levels.

22. The semiconductor device according to claim 21.

23. the temperature detection constant current source includes a first constant current source and a second constant current source; the reference voltage generating unit includes a first resistor and a second resistor connected in series in this order from a high potential side to a low potential side, and the comparison circuit includes a first comparator and a second comparator, an input terminal of the first constant current source is connected to an input terminal of the second constant current source and a power supply unit; an output terminal of the first constant current source is connected to the anode of the temperature sensing diode and the non-inverting input terminals of the first and second comparators; an output terminal of the second constant current source is connected to an inverting input terminal of the first comparator and one terminal of the first resistor, and a first temperature detection signal having a first predetermined level is output from an output terminal of the first comparator; an inverting input terminal of a second comparator is directly connected to the high potential end of a second resistor, and a second temperature detection signal having a predetermined level is output from an output terminal of the second comparator; the other end of the second resistor is connected to the cathode of the temperature sensing diode and to ground; 22. The semiconductor device according to claim 21.

24. The temperature detection circuit includes: In the first temperature range, the temperature detection signal is not output at a predetermined level, outputting a second temperature detection signal having a predetermined level in the second temperature range; In the third temperature range, a first temperature detection signal having a predetermined level to a second temperature detection signal having a predetermined level are outputted; The current limiting circuit includes: a state holding circuit which outputs the gate charge extraction signal when the first temperature detection signal of a predetermined level is not received and until the second temperature detection signal of a predetermined level is received when the overcurrent state is detected and the first temperature detection signal of a predetermined level is not received, and a switch which makes the gate conductive to an output terminal of a device by switching based on the gate charge extraction signal.

20. The semiconductor device according to claim 19.

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