Semiconductor device

Abstract

To provide a semiconductor device with a high-side circuit region having a plurality of high-side circuits operated at a plurality of power source voltages different from each other, without enlarging the device.SOLUTION: In a semiconductor device 101, an N-type diffusion layer 31a is provided in a first high-side circuit region RH1, and an N-type diffusion layer 32a is provided in a second high-side circuit region RH2. Components for the first and second high-side circuits CH1 and CH2 are provided in the N-type diffusion layers 31a and 32a, respectively. A separation trench 70 is provided between the N-type diffusion layer 31a and the N-type diffusion layer 32a. A deepest portion of the separation trench 70 reaches a P-type substrate region of a P-type substrate 10. The N-type diffusion layer 31a and the N-type diffusion layer 32a are electrically separated from each other by the separation trench 70 internally having an embedded insulation film 78.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device having a high-side circuit region and a low-side circuit region. [Background technology]

[0002] A power control HVIC (High Voltage Integrated Circuit) that is mainly used to drive the gates of power semiconductor devices generally comprises a low-side circuit that operates with the ground (GND) potential as a reference potential, a high-side circuit that operates with a potential different from the GND potential, such as a floating potential, as a reference potential, and a level shift circuit that transmits signals between the low-side circuit and the high-side circuit.

[0003] An example of a conventional HVIC is the semiconductor device disclosed in Patent Document 1. In the semiconductor device having the HVIC configuration disclosed in Patent Document 1, a high-voltage termination structure in a high-side circuit region in which a high-side circuit is provided and a high-voltage level shift element are electrically isolated by trench isolation. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 7001050 Summary of the Invention [Problem to be solved by the invention]

[0005] In conventional semiconductor devices with an HVIC configuration, the high-voltage termination structure and high-voltage level shift in the high-side circuit area can be separated, but the internal configuration of the high-side circuit area is generally configured such that elements are provided in the same N-type diffusion area, so the power supply voltage for the high-side circuit area is a single power supply voltage. Even when multiple high-side circuits that operate on different power supply voltages are provided in the high-side circuit area, it is necessary to design the element withstand voltage to be the withstand voltage of the maximum voltage in the circuit, which causes a problem of the device becoming larger.

[0006] As described above, conventional semiconductor devices having an HVIC configuration have a problem in that it is not possible to provide a plurality of high side circuits that operate at different power supply voltages within a high side circuit area without increasing the size of the device.

[0007] The present disclosure has been made to solve the above-mentioned problems, and has an object to obtain a semiconductor device including a high side circuit area having a plurality of high side circuits that operate at a plurality of different power supply voltages, without increasing the size of the device. [Means for solving the problem]

[0008] A semiconductor device according to the present disclosure includes a semiconductor substrate, a low-side circuit region provided in the semiconductor substrate and receiving a first reference potential, a high-side circuit region provided in the semiconductor substrate and receiving a second reference potential different from the first reference potential, and a first isolation region electrically isolating the low-side circuit region and the high-side circuit region, the semiconductor substrate having a circuit base region in which the low-side circuit region and the high-side circuit region are not provided, the high-side circuit region includes first and second high-side circuit regions, a first high-side circuit is provided in the first high-side circuit region and a second high-side circuit is provided in the second high-side circuit region, the first high-side circuit operates on a first power supply voltage based on the second reference potential and the second high-side circuit operates on a second power supply voltage based on the second reference potential, the first and second power supply voltages having different voltage values, and the semiconductor device further includes a second isolation region electrically isolating the first high-side circuit region and the second high-side circuit region. Effect of the Invention

[0009] Since the semiconductor device disclosed herein has a second isolation region that electrically isolates the first and second high side circuit regions, there is no problem even if the first high side circuit provided in the first high side circuit region is operated at a first power supply voltage and the second high side circuit provided in the second high side circuit region is operated at a second power supply voltage different from the first power supply voltage.

[0010] Therefore, in the semiconductor device of the present disclosure, the first and second high side circuit regions having the first and second high side circuits can be provided in the high side circuit region in a structure that maintains a small size. [Brief description of the drawings]

[0011] [Figure 1] 1 is an explanatory diagram illustrating a schematic planar configuration of a semiconductor device according to a first embodiment; [Diagram 2] 2 is an explanatory diagram illustrating a schematic circuit configuration of the semiconductor device illustrated in FIG. 1. [Diagram 3] 1 is a cross-sectional view showing a cross section of a semiconductor device according to a first aspect of the first embodiment. [Figure 4] 4 is a cross-sectional view showing a cross section of a semiconductor device according to a second aspect of the first embodiment. FIG. [Diagram 5] 11 is a cross-sectional view showing a cross section of a semiconductor device according to a third aspect of the first embodiment. FIG. [Figure 6] 10 is a cross-sectional view showing a cross section of a semiconductor device according to a first aspect of the second embodiment. FIG. [Figure 7] 11 is a cross-sectional view showing a cross section of a semiconductor device according to a second aspect of the second embodiment. FIG. [Figure 8] 13 is a cross-sectional view showing a cross section of a semiconductor device according to a third aspect of the second embodiment. FIG. [Figure 9] 11 is a cross-sectional view showing a cross section of a semiconductor device according to a first aspect of a third embodiment. FIG. [Figure 10] 13 is a cross-sectional view showing a cross section of a semiconductor device according to a second aspect of the third embodiment. FIG. [Figure 11] 13 is a cross-sectional view showing a cross section of a semiconductor device according to a first aspect of the fourth embodiment. FIG. [Figure 12] 13 is a cross-sectional view showing a cross section of a semiconductor device according to a second aspect of the fourth embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] <Embodiment 1> (Plane configuration and circuit configuration) Fig. 1 is an explanatory diagram showing a schematic planar configuration of a semiconductor device 100 according to a first embodiment of the present disclosure. The semiconductor device 100 is used as a general term including the semiconductor devices 101-108 and the semiconductor devices 201 and 202. The semiconductor devices 102-108, 201 and 202 will be described in detail later. That is, the structure shown in Fig. 1 is a planar structure common to the semiconductor devices 101-108 and the semiconductor devices 201 and 202 shown in the first to fourth embodiments.

[0013] As shown in FIG. 1, an N-type diffusion layer 30a is provided on the periphery of the high-side circuit region RH, and a P-type diffusion layer 40 is provided surrounding the N-type diffusion layer 30a in a plan view. The combination of the N-type diffusion layer 30a and the P-type diffusion layer 40 forms a first isolation region. The low-side circuit region RL and the high-side circuit region RH are electrically isolated by the N-type diffusion layer 30a and the P-type diffusion layer 40, which are the first isolation region. Therefore, the N-type diffusion layer 30a and the P-type diffusion layer 40 each form a first isolation diffusion region included in the first isolation region. In this specification, the first conductivity type is indicated as P type, and the second conductivity type is indicated as N type.

[0014] The high side circuit region RH includes a first high side circuit region RH1 and a second high side circuit region RH2. A first high side circuit CH1 is provided in the first high side circuit region RH1, and a second high side circuit CH2 is provided in the second high side circuit region RH2.

[0015] 2 is an explanatory diagram illustrating a schematic circuit configuration of the semiconductor device 100. As shown in the figure, the circuit configuration of the semiconductor device 100 includes a low-side circuit CL, a first high-side circuit CH1, a second high-side circuit CH2, and a level shift circuit 6 as main components.

[0016] As described above, the low-side circuit CL is a circuit provided in the low-side circuit area RL, the first high-side circuit CH1 is a circuit provided in the first high-side circuit area RH1, and the second high-side circuit CH2 is a circuit provided in the second high-side circuit area RH2.

[0017] The low-side circuit CL receives the ground potential GND as a reference potential, and receives the low-side power supply voltage VCC as an operating voltage with the ground potential GND as a reference potential. The ground potential GND serves as a first reference potential for the low-side circuit CL. Therefore, the low-side circuit CL executes circuit operations with the low-side power supply voltage VCC with the ground potential GND as a reference. The level shift circuit 6 transmits signals between the low-side circuit CL and the first high-side circuit area RH1.

[0018] The first high side circuit CH1 receives a high side reference potential VS as a reference potential and a high side power supply voltage VB1 as an operating voltage. Therefore, the first high side circuit CH1 performs circuit operation with the high side power supply voltage VB1 based on the high side reference potential VS.

[0019] The second high side circuit CH2 receives the high side reference potential VS as a reference potential and receives the high side power supply voltage VB2 as an operating voltage. Therefore, the second high side circuit CH2 executes circuit operation with the high side power supply voltage VB2 based on the high side reference potential VS. The high side power supply voltage VB2 is set to a voltage value different from the high side power supply voltage VB1.

[0020] The high-side reference potential VS is a second reference potential common to the first and second high-side circuits CH1 and CH2. The high-side reference potential VS is a potential different from the ground potential GND and is electrically isolated from the ground potential GND, so it is usually floating.

[0021] As described above, the first high side circuit CH1 performs circuit operations using the high side power supply voltage VB1 as an operating voltage, and the second high side circuit CH2 performs circuit operations using the high side power supply voltage VB2 as an operating voltage.

[0022] The high side power supply voltage VB1 received by the first high side circuit CH1 serves as the first power supply voltage, and the high side power supply voltage VB2 received by the second high side circuit CH2 serves as the second power supply voltage. As described above, the high side power supply voltage VB1 serving as the first power supply voltage and the high side power supply voltage VB2 serving as the second power supply voltage are set to different voltage levels.

[0023] Fig. 1 mainly shows a top view of the periphery of the high-side circuit region RH in the semiconductor device 100. In order to simplify the drawing, some of the diffusion layers corresponding to the cross-sectional structures in Fig. 3 and the like shown below are omitted in Fig. 1. Also, the high-voltage MOS used as the level shift circuit 6 shown in Fig. 2 is omitted.

[0024] 1, within the high side circuit region RH, an isolation region 7 is provided on the outer periphery of the second high side circuit region RH2. The isolation region 7 electrically isolates the first high side circuit region RH1 and the second high side circuit region RH2.

[0025] 2 controls IGBT2 and IGBT3 connected in series. A high voltage HV is applied to the collector of IGBT2, the emitter of IGBT2 and the collector of IGBT3 are connected at a node N1, and the emitter of IGBT3 is set to the ground potential GND.

[0026] The low-side circuit CL receives an input signal IN from the outside and outputs a low-side control signal SL to the gate of IGBT3. The first high-side circuit CH1 outputs a high-side control signal SH to the gate of IGBT2. A signal obtained at a node N1 is applied to the first and second high-side circuits CH1 and CH2, respectively. Signals are also exchanged between the first and second high-side circuits CH1 and CH2.

[0027] The low-side circuit region RL and the high-side circuit region RH are separated by an N-type diffusion layer 30a and a P-type diffusion layer 40, each of which serves as a first isolation diffusion region, with a high breakdown voltage of at least 100 V. The low-side circuit region RL and the high-side circuit region RH are separated by a RESURF isolation structure using the N-type diffusion layer 30a, which is a diffusion layer of N-type, which is a second conductivity type.

[0028] In this manner, the N-type diffusion layer 30a and the P-type diffusion layer 40, each of which serves as a first isolation diffusion region, isolate the low-side circuit region RL from the high-side circuit region RH so that no problems occur even if the voltage difference between the low-side circuit region RL and the high-side circuit region RH is 100 V or more.

[0029] The isolation region 7, which serves as the second isolation region, separates the first high side circuit region RH1 and the second high side circuit region RH2 with a withstand voltage of several tens of V. A high withstand voltage MOS, not shown in FIG 1, is provided in the N-type diffusion layer 30a or in the low side circuit region RL.

[0030] In this way, the isolation region 7, which serves as the second isolation region, isolates the first and second high side circuit regions RH1 and RH2 so that there is no problem if the voltage difference between the first high side circuit region RH1 and the second high side circuit region RH2 is approximately 10 V.

[0031] (First aspect) Fig. 3 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 101 according to a first aspect of the first embodiment. Fig. 3 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The cross-sectional structures shown in Fig. 3 and Figs. 4 to 12 described later are shown only as schematics, and the shapes, scales, and the like do not necessarily correspond to the cross-sectional structures that are actually manufactured.

[0032] As shown in Fig. 3, first and second high side circuit regions RH1 and RH2 are provided in an upper layer portion of a P type substrate 10, which is a semiconductor substrate of a first conductivity type. As shown in Fig. 3, an N type diffusion layer 30a and a P type diffusion layer 40 are provided in the upper layer portion of the P type substrate 10 as a first isolation region that isolates the high side circuit region RH and the low side circuit region RL. The P type diffusion layer 40 is provided so as to surround the high side circuit region RH in a plan view. The N type diffusion layer 30a satisfies the RESURF condition.

[0033] A portion of the surface of the P-type diffusion layer 40 is filled with P + A diffusion layer 60 is provided. +The diffusion layer 60 serves as a layer for making contact between the P-type diffusion layer 40 and a metal wiring layer not shown in FIG. 3. + A diffusion layer 50 is provided. + The diffusion layer 50 serves as a layer for making contact between the N-type diffusion layer 30a and a metal wiring layer not shown in FIG. + The diffusion layer 50 is provided at a position within the surface of the N-type diffusion layer 30a, spaced a certain distance of several tens of μm or more from the P-type diffusion layer 40.

[0034] P-type diffusion layer 40 and N + A thermal oxide film 81 is provided on the surface of N-type diffusion layer 30a between diffusion layer 50. A field plate made of polysilicon or a metal wiring layer is provided on the upper layer of thermal oxide film 81. Note that the field plate is not shown in Fig. 3 for simplification of the drawing. The field plate may be provided across the end of thermal oxide film 81.

[0035] In the first high side circuit region RH1, an N-type diffusion layer 31a is provided in an upper layer portion of a P-type substrate 10, which is a semiconductor substrate of a first conductivity type, and in the second high side circuit region RH2, an N-type diffusion layer 32a is provided in an upper layer portion of the P-type substrate 10.

[0036] The N-type diffusion layer 31a and the N-type diffusion layer 32a are formed at the same time, and the N-type diffusion layer 30a is formed after the formation of the N-type diffusion layers 31a and 32a. The formation depth of each of the N-type diffusion layers 31a and 32a is deeper than the diffusion depth of the N-type diffusion layer 30a, which is the first isolation diffusion region. The N-type diffusion layer 31a becomes the first circuit diffusion region, and the N-type diffusion layer 32a becomes the second circuit diffusion region. Therefore, the N-type diffusion layers 31a and 32a, which become the first and second circuit diffusion regions, satisfy the diffusion region depth requirement that "the formation depth of each of the first and second circuit diffusion regions is deeper than the formation depth of the first isolation diffusion region."

[0037] Components of the first high side circuit CH1 are provided on the upper layer of the N-type diffusion layer 31a, and components of the second high side circuit CH2 are provided on the upper layer of the N-type diffusion layer 32a. In FIG. 3, for example, a CMOS configuration is shown as the components.

[0038] In the first high side circuit region RH1, a P-type diffusion layer 41a is selectively provided in an upper layer portion of the N-type diffusion layer 31a, and N + Diffusion layers 51 and 52 are selectively provided. + The diffusion layers 51 and 52 are spaced apart from each other by a constant distance of 0.1 μm or more. + A polysilicon gate 90 is provided on the P-type diffusion layer 41a between the diffusion layers 51 and 52 via a gate oxide film (not shown). + A diffusion layer 61 is provided, and P + The diffusion layer 61 serves as a layer for making contact between the P-type diffusion layer 41a and a metal wiring layer (not shown in FIG. 3). + It is provided adjacent to the diffusion layer 51 .

[0039] Therefore, the P-type diffusion layer 41a and the N-type diffusion layer 31a are + The diffusion layers 51 and 52, the gate oxide film, and the polysilicon gate 90 constitute an NMOS transistor as a component element for the first high side circuit CH1.

[0040] In the first high side circuit region RH1, P + Diffusion layers 62 and 63 are selectively provided, and P + The diffusion layers 62 and 63 are spaced apart from each other by a constant distance of 0.1 μm or more. + A polysilicon gate 91 is provided on the N-type diffusion layer 31a between the diffusion layers 62 and 63 via a gate oxide film (not shown). + A diffusion layer 53 is provided. +The diffusion layer 53 serves as a layer for making contact between the N-type diffusion layer 31a and a metal wiring layer (not shown in FIG. 3). + It is provided adjacent to the diffusion layer 63 .

[0041] Therefore, the P + The diffusion layers 62 and 63, the gate oxide film, and the polysilicon gate 91 form a PMOS transistor as a component element for the first high side circuit CH1.

[0042] The combination structure of the above-mentioned NMOS transistor and PMOS transistor is a CMOS configuration provided in the first high side circuit region RH1. The first high side circuit CH1 includes this CMOS configuration.

[0043] On the other hand, in the second high side circuit region RH2, a P-type diffusion layer 42a is selectively provided in the upper layer portion of the N-type diffusion layer 32a, and N + Diffusion layers 55 and 56 are selectively provided, and N + The diffusion layers 55 and 56 are spaced apart from each other by a constant distance of 0.1 μm or more. + A polysilicon gate 93 is provided on the P-type diffusion layer 42a between the diffusion layers 55 and 56 via a gate oxide film (not shown). + A diffusion layer 66 is provided. + The diffusion layer 66 is a layer for making contact between the P-type diffusion layer 42a and a metal wiring layer not shown in FIG. + It is provided adjacent to the diffusion layer 56 .

[0044] Therefore, the P-type diffusion layer 42a and the N-type diffusion layer 32a are + The diffusion layers 55 and 56, the gate oxide film, and the polysilicon gate 93 form an NMOS transistor as a component element for the second high side circuit CH2.

[0045] In the second high side circuit region RH2, P+ Diffusion layers 64 and 65 are selectively provided, and P + The diffusion layers 64 and 65 are spaced apart from each other by a constant distance of 0.1 μm or more. + A polysilicon gate 92 is provided on the N-type diffusion layer 32a between the diffusion layers 64 and 65 via a gate oxide film (not shown). + A diffusion layer 54 is provided. + The diffusion layer 54 is a layer for making contact between the N-type diffusion layer 32a and a metal wiring layer not shown in FIG. + It is provided adjacent to the diffusion layer 64 .

[0046] Therefore, the P + The diffusion layers 64 and 65, the gate oxide film, and the polysilicon gate 92 form a PMOS transistor as a component element for the second high side circuit CH2.

[0047] The combination structure of the above-mentioned NMOS transistor and PMOS transistor is the CMOS configuration provided in the second high side circuit region RH2. The second high side circuit CH2 includes this CMOS configuration.

[0048] In Figure 3, N is used as the drain and source of a MOS transistor in a CMOS configuration. + Diffusion layers 51, 52, 55 and 56 and P + Each of the diffusion layers 62 to 65 is formed to have a single drain structure. In consideration of the drain-source breakdown voltage, a DDD (Double Diffused Drain) structure or an LDD (Lightly Doped Drain) structure may be adopted instead of the single drain structure.

[0049] A region in the P-type substrate 10 in which the first and second high-side circuits CH1 and CH2 are not provided is a circuit base region. The first high-side circuit CH1 is provided in and on the N-type diffusion layer 31a, and the second high-side circuit CH2 is provided in and on the N-type diffusion layer 32a.

[0050] In the first embodiment, a P-type substrate region of a first conductivity type in the P-type substrate 10, which exists below the P-type diffusion layer 40, the N-type diffusion layer 30a, the N-type diffusion layer 31a, and the N-type diffusion layer 32a, serves as a circuit base region. The P-type substrate region in the P-type substrate 10 is set to a ground potential GND, which is a first reference potential.

[0051] In the semiconductor device 101, an isolation trench 70 is provided in the isolation region 7. The isolation trench 70 is provided between the N-type diffusion layer 31a serving as the first circuit diffusion region and the N-type diffusion layer 32a serving as the second circuit diffusion region, and is provided so that its deepest portion reaches the P-type substrate region in the P-type substrate 10.

[0052] The N-type diffusion layer 31a and the N-type diffusion layer 32a are electrically isolated from each other by the isolation trench 70. The isolation trench 70 is formed, for example, as follows.

[0053] In the P-type substrate 10, a provisional N-type diffusion layer is formed in an upper layer portion including the first and second high side circuit regions RH1 and RH2 and the isolation region 7, and then an isolation trench 70 is formed in the isolation region 7 so as to extend from the surface of the P-type substrate 10 including the provisional N-type diffusion layer to the substrate region. The isolation trench 70 thus formed isolates the provisional N-type diffusion layer between the first and second high side circuit regions RH1 and RH2.

[0054] In this specification, the term "provisional..." is used to indicate a structure that is in an intermediate stage and not in a completed stage.

[0055] As a result, the provisional N-type diffusion layer remaining in the first high side circuit region RH1 becomes the N-type diffusion layer 31a, and the provisional N-type diffusion layer remaining in the second high side circuit region RH2 becomes the N-type diffusion layer 32a. Therefore, the N-type diffusion layer 31a and the N-type diffusion layer 32a are electrically isolated from each other by the isolation trench 70.

[0056] The isolation trench 70 has therein a buried insulating film 78 for insulating and isolating the first and second high-side circuit regions RH1 and RH2. There are first and second filling modes for the buried insulating film 78. The first filling mode is a mode in which the buried insulating film 78 is filled into the isolation trench 70. The second filling mode is a mode in which the buried insulating film 78 is selectively formed on the sidewalls in the isolation trench 70, and polysilicon (not shown) is filled into the isolation trench 70 including the buried insulating film 78.

[0057] The depth of the isolation trench 70 is set to, for example, about several μm to 20 μm, and the width is set to, for example, 1 to 2 μm. Here, several μm means 2 to 3 μm.

[0058] When the buried insulating film 78 is provided in the first embedding manner, the withstand voltage between the first and second high side circuit regions RH1 and RH2 is ensured by the withstand voltage of the buried insulating film 78 filled in the isolation trench 70. In this case, the film thickness of the buried insulating film 78 corresponds to the formation width of the isolation trench 70. When the buried insulating film 78 is provided in the second embedding manner, the withstand voltage between the first and second high side circuit regions RH1 and RH2 is ensured by the withstand voltage of the buried insulating film 78 provided on the sidewall of the isolation trench 70.

[0059] The N-type diffusion layer 31a, which is the first circuit diffusion region, is + A high-side power supply voltage VB1 is applied via the diffusion layer 53, and an N-type diffusion layer 32a, which is a second circuit diffusion region, is connected to the N-type diffusion layer 32a. + A high side power supply voltage VB2 is applied via the diffusion layer 54. Both the high side power supply voltages VB1 and VB2 are high voltages of 100V or more, and the potential difference between the high side power supply voltage VB1 and the high side power supply voltage VB2 is several volts to several tens of volts.

[0060] An insulating layer 88 is provided so as to cover the entire surface of the semiconductor device 101. A metal wiring layer is provided on the insulating layer 88. The metal wiring layer is connected to the N + Diffusion layers 50-56, P +The diffusion layers 60 to 66 are individually connected to the polysilicon gates 90 to 93. In order to simplify the drawing, the metal wiring layers and contact holes are not shown in FIG.

[0061] (effect) The N-type diffusion layer 31a provided in the first high side circuit region RH1 and the N-type diffusion layer 32a provided in the second high side circuit region RH2 are separated in the horizontal direction by the RESURF isolation structure of the first isolation region including the N-type diffusion layer 30a, and are separated in the vertical direction between the ground potential GND and a high voltage of 100 V or more by the reverse bias of the PN junction between the P-type substrate region of the P-type substrate 10 and the N-type diffusion layers 31a and 32a.

[0062] The first and second high side circuit regions RH1 and RH2 are both isolated between the ground potential GND and a high voltage, and the N-type diffusion layer 31a of the first high side circuit region RH1 and the N-type diffusion layer 32a of the second high side circuit region RH2 are electrically isolated by an isolation trench 70 having a buried insulating film 78 therein, which serves as a dielectric.

[0063] The high side power supply voltage VB1 applied to the N-type diffusion layer 31a corresponds to a first power supply voltage for the first high side circuit CH1 provided in the first high side circuit area RH1, and the high side power supply voltage VB2 applied to the N-type diffusion layer 32a corresponds to a second power supply voltage for the second high side circuit CH2 provided in the second high side circuit area RH2.

[0064] In this manner, in the semiconductor device 101 which is the first aspect of the first embodiment, the N-type diffusion layer 31 a and the N-type diffusion layer 32 a are electrically isolated by the isolation trench 70, so that the first and second high side circuits CH1 and CH2 can be operated by the high side power supply voltages VB1 and VB2 with the high side reference potential VS as a common second reference potential.

[0065] The semiconductor device 101, which is a first aspect of the first embodiment, has an isolation trench 70 as an isolation region 7 that electrically isolates the first and second high side circuit regions RH1 and RH2. Therefore, in the semiconductor device 101, no problems arise even if the first high side circuit CH1 provided in the first high side circuit region RH1 is operated with a high side power supply voltage VB1, which is a first power supply voltage, and the second high side circuit CH2 provided in the second high side circuit region RH2 is operated with a high side power supply voltage VB2, which is a second power supply voltage.

[0066] Therefore, in the semiconductor device 101 which is the first aspect of the first embodiment, the first and second high side circuits CH1 and CH2 which operate on different high side power supply voltages VB1 and VB2 can be provided in a high side circuit region RH which receives the high side reference potential VS as a common second reference potential, in a structure which maintains a compact size.

[0067] The N-type diffusion layers 31a and 32a, which are the first and second circuit diffusion regions in the semiconductor device 101, both satisfy the diffusion region depth requirement that they be formed deeper than the N-type diffusion layer 30a, which is the first isolation diffusion region. Therefore, the semiconductor device 101 can improve the breakdown voltage in the horizontal direction by the N-type diffusion layer 30a constituting the first isolation region, and improve the breakdown voltage in the vertical direction by the N-type diffusion layers 31a and 32a.

[0068] The semiconductor device 101 can suppress parasitic action between the first and second high side circuits CH1 and CH2 by the isolation trench 70 having the buried insulating film 78 therein.

[0069] (Second aspect) Fig. 4 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 102 according to a second aspect of the first embodiment. Fig. 4 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The planar configuration and circuit configuration of the semiconductor device 102 are similar to those shown in Figs. 1 and 2.

[0070] Hereinafter, the same reference numerals will be used to designate the same parts as those in the semiconductor device 101 of the first embodiment shown in FIG. 3, and the description will be omitted as appropriate, and the characteristic parts of the semiconductor device 102 of the second embodiment will be mainly described.

[0071] In the semiconductor device 102, an N-type N-type semiconductor layer is in contact with the substrate region of the P-type substrate 10 as a lower layer structure of the first and second high side circuit regions RH1 and RH2. + Buried diffusion layers 20 and 21 are provided. That is, first and second buried diffusion layers N + Buried diffusion layers 20 and 21 are selectively provided.

[0072] In the following, a first manufacturing method will be described in which a provisional N-type epitaxial layer is formed as an intermediate stage, and a second manufacturing method will be described in which a provisional P-type epitaxial layer is formed as an intermediate stage.

[0073] When the first manufacturing method is adopted, in the cross-sectional structure shown in FIG. + After the buried diffusion layers 20 and 21 are formed at the same time, N + A provisional N-type epitaxial layer is formed on the P-type substrate 10 including the buried diffusion layers 20 and 21. Then, a P-type diffusion layer 40 is selectively formed in the provisional N-type epitaxial layer outside the high-side circuit region RH. The provisional N-type epitaxial layer remaining after the formation of the P-type diffusion layer 40 outside the high-side circuit region RH becomes the N-type epitaxial layer 30b. The P-type diffusion layer 40 is provided so as to surround the high-side circuit region RH in a plan view.

[0074] The N-type epitaxial layer 30b functions as one of the first isolation diffusion regions, and the P-type diffusion layer 40 and the N-type epitaxial layer 30b form a first isolation region. The low-side circuit region RL and the high-side circuit region RH are electrically isolated by the P-type diffusion layer 40 and the N-type epitaxial layer 30b. At this time, the N-type epitaxial layer 30b satisfies the RESURF condition.

[0075] Furthermore, a P-type diffusion layer 41b and an N-type diffusion layer 31b are selectively formed in the provisional N-type epitaxial layer in the first high side circuit region RH1, and a P-type diffusion layer 42b and an N-type diffusion layer 32b are formed in the provisional N-type epitaxial layer in the second high side circuit region RH2. + It is formed so as to reach the buried diffusion layers 20 and 21 .

[0076] In the provisional N-type epitaxial layer, the region remaining after the formation of the P-type diffusion layer 40, the P-type diffusion layers 41b and 42b, and the N-type diffusion layers 31b and 32b becomes the N-type epitaxial layer 30b.

[0077] On the other hand, when the second manufacturing method is adopted, N is formed in the upper layer of the P-type substrate 10. + After the buried diffusion layers 20 and 21 are formed at the same time, N + A provisional P-type epitaxial layer is formed on the P-type substrate 10 including the buried diffusion layers 20 and 21. Then, an N-type diffusion layer 30b2 (not shown) is selectively formed in the provisional P-type epitaxial layer. The N-type diffusion layer 30b2 corresponds to the N-type epitaxial layer 30b shown in FIG. 4 and forms a RESURF region.

[0078] Furthermore, a P-type diffusion layer 40 is selectively formed in the provisional P-type epitaxial layer. The P-type impurity concentration of the P-type diffusion layer 40 is set to be higher than the P-type impurity concentration of the provisional P-type epitaxial layer. Therefore, the region surrounded by the P-type diffusion layer 40 in plan view becomes the N-type diffusion layer 30b2.

[0079] In addition, a P-type diffusion layer 41b and an N-type diffusion layer 31b are selectively formed in the provisional P-type epitaxial layer in the first high side circuit region RH1, and a P-type diffusion layer 42b and an N-type diffusion layer 32b are formed in the provisional P-type epitaxial layer in the second high side circuit region RH2. + It is formed so as to reach the buried diffusion layers 20 and 21 .

[0080] When the first method is adopted, N +The buried diffusion layers 20 and 21 contact the bottom surface of the provisional N-type epitaxial layer. Similarly, when the second manufacturing method is adopted, the N + The buried diffusion layers 20 and 21 come into contact with the bottom surface of the interim P-type epitaxial layer.

[0081] As described above, the N-type diffusion layers 31b and 32b and the P-type diffusion layers 41b and 42b are provided in the provisional N-type epitaxial layer or the provisional P-type epitaxial layer.

[0082] In the first manufacturing method, a part of the provisional N-type epitaxial layer may be made into the N-type diffusion layers 31b and 32b. In this case, the provisional N-type epitaxial layer remaining after the formation of the P-type diffusion layer 41b in the first high side circuit region RH1 becomes the N-type diffusion layer 31b, and the provisional N-type epitaxial layer remaining after the formation of the P-type diffusion layer 42b in the second high side circuit region RH2 becomes the N-type diffusion layer 32b.

[0083] In the second manufacturing method, a part of the provisional P-type epitaxial layer may be made into the P-type diffusion layers 41b and 42b. In this case, the provisional P-type epitaxial layer remaining after the formation of the N-type diffusion layer 31b in the first high side circuit region RH1 becomes the P-type diffusion layer 41b, and the provisional P-type epitaxial layer remaining after the formation of the N-type diffusion layer 32b in the second high side circuit region RH2 becomes the P-type diffusion layer 42b.

[0084] In the semiconductor device 102, the isolation region 7 includes N-type diffusion layers 31b and 32b and N + An isolation trench 71 is provided which penetrates the buried diffusion layers 20 and 21 and reaches the P-type substrate region in the P-type substrate 10 .

[0085] The N-type diffusion layer 31b and the N-type diffusion layer 32b are electrically isolated from each other by the isolation trench 71. The isolation trench 71 is formed, for example, as follows.

[0086] When the first manufacturing method is adopted, the provisional N-type epitaxial layer and the N +An isolation trench 71 is formed so as to reach the substrate region from the surface of the P-type substrate 10 including the buried diffusion layers 20 and 21. The isolation trench 71 thus formed separates the N + The buried diffusion layers 20 and 21 are electrically isolated from each other.

[0087] When the second manufacturing method is adopted, the provisional P-type epitaxial layer and the N + An isolation trench 71 is formed so as to reach the substrate region from the surface of the P-type substrate 10 including the buried diffusion layers 20 and 21. The isolation trench 71 thus formed separates the N + The buried diffusion layers 20 and 21 are electrically isolated from each other.

[0088] Furthermore, the N-type diffusion layers 31b and 32b may also be isolated by an isolation trench 71, similar to the N-type diffusion layers 31a and 32a formed in the semiconductor device 101.

[0089] In this manner, the semiconductor device 102 has an N GaN layer formed on the substrate region of the P-type substrate 10 as a first circuit diffusion region. + Buried diffusion layer 20 and N + and an N-type diffusion layer 31b selectively provided on the buried diffusion layer 20. + The buried diffusion layer 20 serves as a first buried diffusion layer, and the N-type diffusion layer 31b serves as a first surface diffusion layer.

[0090] The semiconductor device 102 further includes an N-type diffusion region provided on the substrate region of the P-type substrate 10 as a second circuit diffusion region. + Buried diffusion layer 21 and N + and an N-type diffusion layer 32b selectively provided on the buried diffusion layer 21. + The buried diffusion layer 21 serves as a second buried diffusion layer, and the N-type diffusion layer 32b serves as a second surface diffusion layer.

[0091] In addition, in the surface of the N-type diffusion layer 31b, similar to the N-type diffusion layer 31a, there is N + Diffusion layer 53, P +Diffusion layers 62 and 63 are selectively provided. In addition, in the surface of the N-type diffusion layer 32b, similar to the N-type diffusion layer 32a, N + Diffusion layer 54, P + Diffusion layers 64 and 65 are optionally provided.

[0092] In addition, in the surface of the P-type diffusion layer 41b, similar to the P-type diffusion layer 41a, + Diffusion layer 61, N + Diffusion layers 51 and 52 are selectively provided. In addition, in the surface of the P-type diffusion layer 42b, similar to the P-type diffusion layer 42a, + Diffusion layer 66, N + Diffusion layers 55 and 56 are optionally provided.

[0093] In the semiconductor device 102, an isolation trench 71 is provided in the isolation region 7. The isolation trench 71 is provided between the N-type diffusion layer 31b and the N + The buried diffusion layer 20 and the N-type diffusion layer 32b and N + It is provided between buried diffusion layer 21 and such that its deepest portion reaches the P-type substrate region in P-type substrate 10.

[0094] The isolation trench 71 separates the N-type diffusion layer 31b and the N + The buried diffusion layer 20 and the N-type diffusion layer 32b and N + The buried diffusion layer 21 is electrically isolated.

[0095] The isolation trench 71, like the isolation trench 70, has therein a buried insulating film 78 for insulating and isolating the first and second high side circuit regions RH1 and RH2.

[0096] The semiconductor device 102 according to the second aspect of the first embodiment has an isolation trench 71 as the isolation region 7 for electrically isolating the first and second high side circuit regions RH1 and RH2 from each other.

[0097] Therefore, in the semiconductor device 102, which is the second aspect of the first embodiment, like the semiconductor device 101, first and second high side circuits CH1 and CH2 operating on high side power supply voltages VB1 and VB2 can be provided within the high side circuit region RH in a structure that maintains a compact size.

[0098] A first buried diffusion layer constituting a part of a first circuit diffusion region in the semiconductor device 102, + A buried diffusion layer 20 and a second buried diffusion layer N + Both of the buried diffusion layers 21 are formed deeper than the N-type diffusion layer 30a which is the first isolation diffusion region.

[0099] N + The buried diffusion layer 20 and the N-type diffusion layer 31b constitute a first circuit diffusion region. + The buried diffusion layer 21 and the N-type diffusion layer 32b form a second circuit diffusion region. Therefore, like the semiconductor device 101, the semiconductor device 102 also satisfies the diffusion region depth requirement that "the formation depth of each of the first and second circuit diffusion regions is deeper than the formation depth of the first isolation diffusion region."

[0100] Therefore, the semiconductor device 102 has an improved breakdown voltage in the horizontal direction due to the N-type diffusion layer 30a constituting the first isolation region, and the N-type diffusion layer 31b and the N + The combination of the buried diffusion layer 20 and the N-type diffusion layers 32b and N + The combination of the buried diffusion layers 21 can improve the breakdown voltage in the vertical direction.

[0101] Like the semiconductor device 101, the semiconductor device 102 can suppress parasitic action between the first and second high side circuits CH1 and CH2 by using the isolation trench 71 having the buried insulating film 78 therein.

[0102] In the semiconductor device 102, N + The first combination structure of the buried diffusion layer 20 and the N-type diffusion layer 31b can relatively easily satisfy the above-mentioned diffusion region depth requirement, and +The second combination structure of the buried diffusion layer 21 and the N-type diffusion layer 32b can relatively easily satisfy the above-mentioned diffusion region depth requirement.

[0103] (Third aspect) Fig. 5 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 103 according to a third aspect of the first embodiment. Fig. 5 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The planar configuration and circuit configuration of the semiconductor device 103 are similar to those shown in Figs. 1 and 2.

[0104] Hereinafter, the features common to the semiconductor device 102 of the second embodiment shown in FIG. 4 will be denoted by the same reference numerals, and the description will be omitted as appropriate, and the characteristic features of the semiconductor device 103 of the third embodiment will be mainly described.

[0105] The semiconductor device 103 of the third embodiment is the same as the semiconductor device 102 except that + The buried diffusion layers 20 and 21 are N + This structure is characterized by replacing the buried diffusion layers 22 and 23 with an isolation trench 72 instead of the isolation trench 71 .

[0106] Therefore, N + The buried diffusion layer 22 becomes the first buried diffusion layer, and N + The buried diffusion layer 23 becomes the second buried diffusion layer. + Buried diffusion layers 22 and 23 are selectively provided on the substrate region of the P-type substrate 10 .

[0107] As in the second embodiment, the N-type diffusion layer 31b serves as a first surface diffusion layer, and the N-type diffusion layer 32b serves as a second surface diffusion layer. + An N-type diffusion layer 31b is selectively provided on the buried diffusion layer 22. + An N-type diffusion layer 32 b is selectively provided on the buried diffusion layer 23 .

[0108] In the semiconductor device 102 according to the second embodiment shown in FIG. + The buried diffusion layers 20 and 21 are separated by an isolation trench 71. +The buried diffusion layers 20 and 21 are in contact with the side walls of the isolation trench 71 .

[0109] On the other hand, the semiconductor device 103 according to the third embodiment has a structure as shown in FIG. + When the buried diffusion layers 22 and 23 are formed, they are separated by a pattern. + The buried diffusion layers 22 and 23 are formed separately from each other. + Between the buried diffusion layers 22 and 23 there is a P-type substrate region.

[0110] In addition, N + Except for forming the buried diffusion layers 22 and 23 discretely, + The buried diffusion layers 22 and 23 are N + It is formed by the same method as that for the buried diffusion layers 20 and 21 .

[0111] In the semiconductor device 103, the isolation region 7 is provided with an N-type diffusion layer 31b and an N-type diffusion layer 32b. + An isolation trench 72 is provided which reaches down to the substrate region of the P-type substrate 10 between the buried diffusion layers 22 and 23 .

[0112] As shown in Figure 5, + Since the buried diffusion layers 22 and 23 are spaced apart from each other by a certain distance that is wider than the width of the isolation trench 72, the sidewall of the isolation trench 72 is made of N. + It is not in contact with either the buried diffusion layers 22 or 23 .

[0113] The isolation trench 72 reaches the P-type substrate region of the P-type substrate 10, but the deepest part of the isolation trench 72 is N + It is provided so as to be shallower than the deepest parts of the buried diffusion layers 22 and 23 .

[0114] That is, the isolation trench 72 is N + The isolation trench 72 of the semiconductor device 103 does not have a contact relationship with the buried diffusion layers 22 and 23. The isolation trench 72 is formed to a depth equal to or larger than the depth of the first and second buried diffusion layers N +This satisfies the trench depth requirement that the trench depth be "shallower than the respective formation depths of the buried diffusion layers 22 and 23."

[0115] Similar to the isolation trenches 70 and 71, the isolation trench 72 has therein a buried insulating film 78 for insulating and isolating the first and second high side circuit regions RH1 and RH2.

[0116] The semiconductor device 103 according to the third aspect of the first embodiment has an isolation trench 72 as the isolation region 7 for electrically isolating the first and second high side circuit regions RH1 and RH2 from each other.

[0117] Therefore, in the semiconductor device 103, which is the third aspect of the first embodiment, like the semiconductor devices 101 and 102, first and second high side circuits CH1 and CH2 operating on high side power supply voltages VB1 and VB2 can be provided within the high side circuit region RH in a structure that maintains a compact size.

[0118] The first buried diffusion layer constituting a part of the first circuit diffusion region in the semiconductor device 103 is N + The buried diffusion layer 22 and the second buried diffusion layer N + Both of the buried diffusion layers 23 are formed deeper than the N-type epitaxial layer 30b which is the first isolation diffusion region.

[0119] N + The buried diffusion layer 22 and the N-type diffusion layer 31b constitute a first circuit diffusion region. + The buried diffusion layer 23 and the N-type diffusion layer 32b form a second circuit diffusion region. Therefore, like the semiconductor devices 101 and 102, the semiconductor device 103 also satisfies the diffusion region depth requirement that "the formation depth of each of the first and second circuit diffusion regions is deeper than the formation depth of the first isolation diffusion region."

[0120] Therefore, the semiconductor device 103 has an improved breakdown voltage in the horizontal direction due to the N-type epitaxial layer 30b constituting the first isolation region, and the N-type diffusion layer 31b and the N+ The first combination of the buried diffusion layer 22 and the N-type diffusion layer 32b and N + The second combination of the buried diffusion layers 23 can improve the breakdown voltage in the vertical direction.

[0121] Like the semiconductor devices 101 and 102, the semiconductor device 103 can suppress parasitic action between the first and second high side circuits CH1 and CH2 by using the isolation trench 72 having the buried insulating film 78 therein.

[0122] In addition, in the semiconductor device 103, N + The first combination structure of the buried diffusion layer 22 and the N-type diffusion layer 31b satisfies the above-mentioned diffusion region depth requirement relatively easily, and + The second combination structure of the buried diffusion layer 23 and the N-type diffusion layer 32b makes it relatively easy to satisfy the above-mentioned diffusion region depth requirement.

[0123] Furthermore, since the isolation trench 72 of the semiconductor device 103, which is the third aspect of the first embodiment, satisfies the above-mentioned trench depth requirement, the depth of the isolation trench 72 can be made relatively shallow, thereby reducing the process load during the formation of the isolation trench 72.

[0124] In addition, in the semiconductor device 103, the sidewalls of the isolation trenches 72 are made of N + Without contacting either the buried diffusion layer 22 or 23, + The distance between the buried diffusion layers 22 and 23 is set to be relatively long. + The degree of electrical isolation between the buried diffusion layers 22 and 23 can be further increased.

[0125] <Embodiment 2> (First aspect) Fig. 6 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 104 according to a first aspect of the embodiment 2. Fig. 6 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The planar configuration and circuit configuration of the semiconductor device 104 are similar to those shown in Figs. 1 and 2.

[0126] In the following, the parts common to the semiconductor device 101 of the first aspect of the embodiment 1 shown in Figure 3 are given the same symbols and their explanations are omitted as appropriate, and the description will focus on the characteristic parts of the semiconductor device 104 of the first aspect of the embodiment 2.

[0127] The semiconductor device 104 is characterized in that, in addition to the structure of the semiconductor device 101, it further includes a P-type diffusion layer 110 provided around the deepest part of the isolation trench 70 in the substrate region of the P-type substrate 10 so as to be in contact with the deepest part of the isolation trench 70. This P-type diffusion layer 110 serves as a trench bottom diffusion region. In the structure shown in Fig. 6, the upper surface of the P-type diffusion layer 110 is located higher than the lower surfaces of the N-type diffusion layers 31a and 32a, and the P-type diffusion layer 110 is also in contact with the N-type diffusion layers 31a and 32a.

[0128] The P-type impurity concentration in the P-type diffusion layer 110 is set to be higher than the P-type impurity concentration in the substrate region of the P-type substrate 10 .

[0129] In the process of forming the isolation trench 70, after an empty trench for the isolation trench 70 is formed by trench etching, a manufacturing process of the P-type diffusion layer 110 is performed before forming the buried insulating film 78 in the isolation trench 70. The P-type diffusion layer 110 is formed by ion implantation and diffusion processing of P-type impurities from above the P-type substrate 10 through the empty isolation trench 70.

[0130] The semiconductor device 104 according to the first aspect of the second embodiment provides the same effects as the semiconductor device 101 according to the first aspect of the first embodiment, and further provides the following unique effects.

[0131] Since the semiconductor device 104 which is the first aspect of the second embodiment has the P-type diffusion layer 110 which is the trench bottom diffusion region, it is possible to suppress leakage current due to a parasitic bipolar transistor passing through the P-type substrate region in the P-type substrate 10.

[0132] The parasitic bipolar transistor in the semiconductor device 101, which is the first aspect of the first embodiment, is a parasitic NPN bipolar transistor formed by the N-type diffusion layer 31a, the P-type substrate region in the P-type substrate 10, and the N-type diffusion layer 32a. That is, the operation of the parasitic NPN bipolar transistor described above is considered as a parasitic operation assumed in the semiconductor device 101. On the other hand, in the semiconductor device 104, which is the first aspect of the second embodiment, a P-type diffusion layer 110 is provided in the base region of the parasitic NPN bipolar transistor.

[0133] In this manner, by providing the P-type diffusion layer 110 having a relatively high concentration of P-type impurities at the bottom of the isolation trench 70, the semiconductor device 104 can reduce the current amplification factor hFE of the NPN bipolar transistor passing through the P-type substrate region in the P-type substrate 10, and suppress the leakage current between the first and second high side circuit regions RH1 and RH2 that is generated by the operation of the parasitic NPN bipolar transistor.

[0134] (Second aspect) Fig. 7 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 105 according to a second aspect of the embodiment 2. Fig. 7 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The planar configuration and circuit configuration of the semiconductor device 105 are similar to those shown in Figs. 1 and 2.

[0135] In the following, the parts common to the semiconductor device 102 of the second aspect of the embodiment 1 shown in FIG. 4 are given the same reference numerals and the explanation is omitted as appropriate, and the explanation will focus on the characteristic parts of the semiconductor device 105 of the second aspect of the embodiment 2.

[0136] The semiconductor device 105 is characterized in that, in addition to the structure of the semiconductor device 102, it further comprises a P-type diffusion layer 111 provided around the deepest part of the isolation trench 71 in the substrate region of the P-type substrate 10 so as to be in contact with the deepest part of the isolation trench 71. This P-type diffusion layer 111 serves as a trench bottom diffusion region. In the structure shown in FIG. 7, the upper surface of the P-type diffusion layer 111 is N + The P-type diffusion layer 111 is located at a position higher than the lower surfaces of the buried diffusion layers 20 and 21.+ It also has contact with the buried diffusion layers 20 and 21 .

[0137] The P-type impurity concentration in P-type diffusion layer 111 is set to be higher than the P-type impurity concentration in the substrate region of P-type substrate 10 .

[0138] In the process of forming the isolation trench 71, after an empty trench for the isolation trench 71 is formed by trench etching, a manufacturing process of the P-type diffusion layer 111 is performed before forming the buried insulating film 78 in the isolation trench 71. The P-type diffusion layer 111 is formed by ion implantation and diffusion processing of P-type impurities from above the P-type substrate 10 through the empty isolation trench 71.

[0139] As another manufacturing process for the P-type diffusion layer 111, when the first manufacturing method is adopted in manufacturing the semiconductor device 102, it is possible to selectively form the P-type diffusion layer 111 as a buried diffusion layer in the upper layer part of the P-type substrate 10 before forming the provisional N-type epitaxial layer.

[0140] The semiconductor device 105 according to the second aspect of the second embodiment provides the same effects as the semiconductor device 102 according to the second aspect of the first embodiment, and further provides the following unique effects.

[0141] Since semiconductor device 105, which is the second aspect of embodiment 2, has P-type diffusion layer 111 which is a trench bottom diffusion region, it is possible to suppress leakage current due to a parasitic bipolar transistor passing through the P-type substrate region in P-type substrate 10, similar to the first aspect of embodiment 2.

[0142] The parasitic bipolar transistor in the semiconductor device 102 according to the second aspect of the first embodiment is an N + The buried diffusion layer 20, the P-type substrate region of the P-type substrate 10, and the N +A parasitic NPN bipolar transistor is formed by the buried diffusion layer 21. That is, the above-mentioned operation of the parasitic NPN bipolar transistor is considered as a parasitic operation assumed in the semiconductor device 102. On the other hand, in the semiconductor device 105 which is the second aspect of the second embodiment, a P-type diffusion layer 111 is provided in the base region of the parasitic NPN bipolar transistor.

[0143] (Third aspect) Fig. 8 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 106 according to a third aspect of the embodiment 2. Fig. 8 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The planar configuration and circuit configuration of the semiconductor device 106 are similar to those shown in Figs. 1 and 2.

[0144] In the following, the parts common to the semiconductor device 103 of the third aspect of the embodiment 1 shown in FIG. 5 are given the same reference numerals and the explanation is omitted as appropriate, and the explanation will focus on the characteristic parts of the semiconductor device 106 of the third aspect of the embodiment 2.

[0145] The semiconductor device 106 is characterized in that, in addition to the structure of the semiconductor device 103, it further comprises a P-type diffusion layer 112 provided around the deepest part of the isolation trench 72 in the substrate region of the P-type substrate 10 and in contact with the deepest part of the isolation trench 72. This P-type diffusion layer 112 becomes a trench bottom diffusion region.

[0146] 8, the P-type diffusion layer 112 is also in contact with the N-type diffusion layers 31b and 32b. + It is provided in the substrate region of the P-type substrate 10 between the buried diffusion layers 22 and 23 .

[0147] The P-type impurity concentration in the P-type diffusion layer 112 is set to be higher than the P-type impurity concentration in the substrate region of the P-type substrate 10 .

[0148] In the process of forming the isolation trench 72, after an empty trench for the isolation trench 72 is formed by trench etching, a manufacturing process of the P-type diffusion layer 112 is performed before forming the buried insulating film 78 in the isolation trench 72. The P-type diffusion layer 112 is formed by ion implantation and diffusion processing of P-type impurities from above the P-type substrate 10 through the empty isolation trench 72.

[0149] As another manufacturing process for the P-type diffusion layer 112, when the first manufacturing method for forming a provisional N-type epitaxial layer at an intermediate stage is adopted during the manufacture of the semiconductor device 103, it is possible to selectively form the P-type diffusion layer 112 as a buried diffusion layer in the upper layer portion of the P-type substrate 10 before the formation of the provisional N-type epitaxial layer.

[0150] The semiconductor device 106 according to the third aspect of the second embodiment provides the same effects as the semiconductor device 103 according to the third aspect of the first embodiment, and further provides the following unique effects.

[0151] The semiconductor device 106, which is the third aspect of the second embodiment, includes the P-type diffusion layer 112, which is the trench bottom diffusion region, and therefore, similarly to the first and second aspects of the second embodiment, it is possible to suppress leakage current due to a parasitic bipolar transistor passing through the P-type substrate region in the P-type substrate 10.

[0152] The parasitic bipolar transistor in the semiconductor device 103 according to the third aspect of the first embodiment is an N + The buried diffusion layer 22, the P-type substrate region in the P-type substrate 10, and the N + A parasitic NPN bipolar transistor is formed by the buried diffusion layer 23. That is, the above-mentioned operation of the parasitic NPN bipolar transistor is considered as a parasitic operation assumed in the semiconductor device 103. On the other hand, in the semiconductor device 106 which is the third aspect of the second embodiment, a P-type diffusion layer 112 is provided in the base region of the parasitic NPN bipolar transistor.

[0153] <Embodiment 3> (First aspect) Fig. 9 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 107 according to a first aspect of the third embodiment. Fig. 9 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The planar configuration and circuit configuration of the semiconductor device 107 are similar to those shown in Figs. 1 and 2.

[0154] In the following, the parts common to the semiconductor device 101 of the first aspect of the embodiment 1 shown in FIG. 3 are given the same reference numerals and the explanation is omitted as appropriate, and the explanation will focus on the characteristic parts of the semiconductor device 107 of the first aspect of the embodiment 3.

[0155] In the semiconductor device 107, a P-type layer 11 is provided instead of the isolation trench 70 of the semiconductor device 101, an N-type diffusion layer 33a is provided instead of the N-type diffusion layer 31a, and an N-type diffusion layer 34a is provided instead of the N-type diffusion layer 32a.

[0156] A semiconductor device 107 which is a first aspect of the third embodiment has a P-type layer 11 which serves as a second isolation diffusion region as an isolation region 7. The P-type layer 11 is provided between an N-type diffusion layer 33a which serves as a first circuit diffusion region and an N-type diffusion layer 34a which serves as a second circuit diffusion region, in contact with each of the N-type diffusion layers 33a and 34a.

[0157] Hereinafter, a first and second manufacturing method for the P-type layer 11 will be described. The first manufacturing method is a method for selectively forming the N-type diffusion layers 33a and 34a in the upper layer portion of the P-type substrate 10. The remaining region in the surface of the P-type substrate 10 where the N-type diffusion layers 33a and 34a are not formed becomes the P-type layer 11.

[0158] The second manufacturing method is a method in which a P-type layer 11 having a higher P-type impurity concentration than the substrate region of the P-type substrate 10 is formed in the upper layer portion of the P-type substrate 10 by ion implantation, diffusion processing, and the like.

[0159] When the second manufacturing method is adopted, the N-type diffusion layers 33a and 34a can be manufactured using the same manufacturing method as that for the N-type diffusion layers 31a and 32a.

[0160] In addition, the surface of the N-type diffusion layer 33a contains N + Diffusion layer 53, P + Diffusion layers 62 and 63 are selectively provided. In addition, in the surface of the N-type diffusion layer 34a, similar to the N-type diffusion layers 32a and 32b, N + Diffusion layer 54, P + The diffusion layers 64 and 65 are selectively provided. Moreover, the thermal oxide film 84 provided on the P-type layer 11 is formed simultaneously with the thermal oxide film 81 after the N-type diffusion layer 30a is formed.

[0161] The semiconductor device 107 according to the first aspect of the third embodiment provides the same effects as the semiconductor device 101 according to the first aspect of the first embodiment, and further provides the following unique effects.

[0162] The semiconductor device 107 has a P-type layer 11 which is a second isolation diffusion region provided between an N-type diffusion layer 33a which is a first circuit diffusion region and an N-type diffusion layer 34a which is a second circuit diffusion region and in contact with each of the N-type diffusion layers 33a and 34a.

[0163] The semiconductor device 107, which is the first aspect of the third embodiment, has a P-type layer 11 in the isolation region 7 as a second isolation diffusion region, thereby making it possible to electrically isolate the first and second high side circuit regions RH1 and RH2 with a relatively simple structure.

[0164] Since the P-type layer 11 is electrically connected to the P-type substrate region of the P-type substrate 10, its potential is the ground potential GND, and the N-type diffusion layers 33a and 34a receiving the high side power supply voltages VB1 and VB2 are at a high voltage of 100 V or more, so that the PN junctions between the N-type diffusion layers 33a and 34a and the P-type substrate 10 and the P-type layer 12 are set to a reverse bias state.

[0165] Therefore, the first and second high side circuit regions RH1 and RH2 are electrically isolated from each other by the reverse bias of the PN junction.

[0166] The formation of the P-type layer 11 can be realized without adding any additional steps to the WP (Wafer Process) process, or by adding relatively few steps such as photolithography, ion implantation and a subsequent diffusion process, etc. That is, the process of forming the P-type layer 11 can reduce the process load compared to the process of forming the isolation trenches 70 to 72 described in the first and second embodiments.

[0167] (Second aspect) Fig. 10 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 108 according to a second aspect of the third embodiment. Fig. 10 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The planar configuration and circuit configuration of the semiconductor device 108 are similar to those shown in Figs. 1 and 2.

[0168] In the following, the parts common to the semiconductor device 103 of the third aspect of the embodiment 1 shown in FIG. 5 are given the same reference numerals and the explanation is omitted as appropriate, and the explanation will focus on the characteristic parts of the semiconductor device 108 of the second aspect of the embodiment 3.

[0169] In the semiconductor device 108, a P-type layer 12 is provided in place of the isolation trench 72 of the semiconductor device 103, an N-type diffusion layer 33b is provided in place of the N-type diffusion layer 31b, and an N-type diffusion layer 34b is provided in place of the N-type diffusion layer 32b. Therefore, the N-type diffusion layer 33b becomes a first surface diffusion layer, and the N-type diffusion layer 34b becomes a second surface diffusion layer.

[0170] A semiconductor device 108 according to a second aspect of the third embodiment is provided with a P-type layer 12 serving as a second diffusion region for isolation as the isolation region 7. The P-type layer 12 is connected to an N-type diffusion layer 33b and an N-type diffusion layer 33c serving as a first diffusion region for circuitry. + The first combination structure of the buried diffusion layer 22 and the N-type diffusion layer 34b and N + The P-type layer 12 is provided between the second combination structure of the buried diffusion layer 23 and the N-type diffusion layers 33b and 34b and the N + It is in contact with the buried diffusion layers 22 and 23 and functions as a second isolation diffusion region.

[0171] In addition, the surface of the N-type diffusion layer 33b contains N + Diffusion layer 53, P + Diffusion layers 62 and 63 are selectively provided. In addition, in the surface of the N-type diffusion layer 34b, similar to the N-type diffusion layers 32a, 32b, and 34a, N + Diffusion layer 54, P + Diffusion layers 64 and 65 are optionally provided.

[0172] The following describes the first and second manufacturing methods for the P-type layer 12. The first manufacturing method is a method in which a provisional N-type epitaxial layer is formed on the P-type substrate 10, and then the P-type layer 12 is formed from within the provisional N-type epitaxial layer to the substrate region of the P-type substrate 10 by ion implantation, diffusion processing, and the like.

[0173] The second manufacturing method is a method in which a provisional P-type epitaxial layer is formed on the P-type substrate 10, and the P-type layer 12 is formed in the provisional P-type epitaxial layer as a residual image region after the formation of the N-type diffusion layers 33b and 34b. In this case, the P-type impurity concentration of the provisional P-type epitaxial layer needs to be set to be equal to or higher than the P-type impurity concentration of the substrate region of the P-type substrate 10.

[0174] The N-type diffusion layers 33 b and 34 b can be manufactured in the same manner as the N-type diffusion layers 31 b and 32 b of the semiconductor device 103 .

[0175] The semiconductor device 108 according to the second aspect of the third embodiment provides the same effects as the semiconductor device 103 according to the third aspect of the first embodiment, and further provides the following unique effects.

[0176] The semiconductor device 108 has an N-type diffusion layer 33b and an N + The first combination structure of the buried diffusion layer 22 and the N-type diffusion layer 34b and N + The P-type layer 12 is disposed between the second combination structure of the buried diffusion layer 23 and the P-type layer 12. The P-type layer 12 is connected to the N-type diffusion layers 33b and 34b and the N + It is in contact with the buried diffusion layers 22 and 23, respectively.

[0177] The semiconductor device 108, which is the second aspect of the third embodiment, has a P-type layer 12 in the isolation region 7 as a second isolation diffusion region, thereby making it possible to electrically isolate the first and second high side circuit regions RH1 and RH2 with a relatively simple structure.

[0178] Since the P-type layer 12 is electrically connected to the P-type substrate region in the P-type substrate 10, its potential is the ground potential GND, and the N-type diffusion layers 33b and 34b that receive the high side power supply voltages VB1 and VB2 are at a high voltage of 100 V or more, so that the PN junctions between the N-type diffusion layers 33b and 34b and the P-type substrate 10 and the P-type layer 12 are set to a reverse bias state.

[0179] Therefore, the first and second high side circuit regions RH1 and RH2 are electrically isolated from each other by the reverse bias of the PN junction.

[0180] The formation of the P-type layer 12 can be realized without any additional steps in the WP process or with relatively few additional steps such as photolithography, ion implantation and subsequent diffusion processing, like the P-type layer 11. That is, the process load of the process of forming the P-type layer 12 can be reduced compared to the process of forming the isolation trenches 70 to 72 described in the first and second embodiments.

[0181] <Fourth embodiment> (First aspect) Fig. 11 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 201 according to a first aspect of the fourth embodiment. Fig. 11 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The planar configuration and circuit configuration of the semiconductor device 201 are similar to those shown in Figs. 1 and 2.

[0182] In the following, the parts common to the semiconductor device 101 of the first aspect of the embodiment 1 shown in FIG. 3 are given the same reference numerals and the explanation is omitted as appropriate, and the explanation will focus on the characteristic parts of the semiconductor device 201 of the first aspect of the embodiment 4.

[0183] The semiconductor device 201 employs an SOI substrate 9, generally called an SOI wafer, as a semiconductor substrate instead of the P-type substrate 10 of the semiconductor device 101. The SOI substrate 9 is configured with a laminated structure of a support substrate 10a, a buried oxide film 120, and an SOI layer 130, and the uppermost layer of the SOI substrate 9 is the SOI layer 130. In Fig. 11, the conductivity type of the support substrate 10a is P-type, but it may be N-type. The SOI layer 130, which is a silicon active layer, is configured with, for example, N-type.

[0184] As shown in Fig. 11, first and second high side circuit regions RH1 and RH2 are provided in an SOI layer 130. As shown in Fig. 11, an N-type diffusion layer 30c and a P-type diffusion layer 40 are provided in the SOI layer 130 as a first isolation region that isolates the high side circuit region RH and the low side circuit region RL. The P-type diffusion layer 40 is provided so as to surround the high side circuit region RH in a plan view. The N-type diffusion layer 30c satisfies the RESURF condition. The N-type diffusion layer 30c has N in the surface, similar to the N-type diffusion layer 30a. + A diffusion layer 50 is provided.

[0185] An N-type diffusion layer 31c is provided in the SOI layer 130 in the first high side circuit region RH1, and an N-type diffusion layer 32c is provided in the SOI layer 130 in the second high side circuit region RH2.

[0186] The N-type diffusion layer 31c and the N-type diffusion layer 32c are formed at the same time. The N-type diffusion layer 30c serves as a first diffusion region for isolation, the N-type diffusion layer 31c serves as a first diffusion region for a circuit, and the N-type diffusion layer 32c serves as a second diffusion region for a circuit.

[0187] Similar to the N-type diffusion layer 31b and the P-type diffusion layer 41b of the semiconductor device 102 shown in FIG. 4, components of the first high side circuit CH1 are provided in the upper layers of the N-type diffusion layer 31c and the P-type diffusion layer 41c, respectively, and similar to the N-type diffusion layer 32b and the P-type diffusion layer 42b of the semiconductor device 102 shown in FIG. 4, components of the second high side circuit CH2 are provided in the upper layers of the N-type diffusion layer 32c and the P-type diffusion layer 42c.

[0188] In the SOI substrate 9 serving as the semiconductor substrate of the fourth embodiment, a region in which the first and second high side circuits CH1 and CH2 are not provided is a circuit base region. The first high side circuit CH1 is provided in the N-type diffusion layer 31c, in the P-type diffusion layer 41c, on the N-type diffusion layer 31c, and on the P-type diffusion layer 41c. The second high side circuit CH2 is provided in the N-type diffusion layer 32c, in the P-type diffusion layer 42c, on the N-type diffusion layer 32c, and on the P-type diffusion layer 42c.

[0189] In the semiconductor device 201, the support substrate 10a and the buried oxide film 120 form a circuit base region. The P-type diffusion layer 40, the N-type diffusion layer 30c, the N-type diffusion layer 31c, the N-type diffusion layer 32c, the P-type diffusion layer 41c, and the P-type diffusion layer 42c are provided in the SOI layer 130, and are not provided in the support substrate 10a or the buried oxide film 120. Therefore, the support substrate 10a and the buried oxide film 120 form a circuit base region.

[0190] In addition, when the conductivity type of the SOI layer 130, which is a silicon active layer, is N-type, the remaining regions after forming the P-type diffusion layer 40, the P-type diffusion layer 41c, and the P-type diffusion layer 42c in the SOI layer 130 may be the N-type diffusion layer 30c, the N-type diffusion layer 31c, and the N-type diffusion layer 32c.

[0191] In addition, in the surface of the N-type diffusion layer 31c, similar to the N-type diffusion layers 31a, 31b, 33a, and 33b, there is N + Diffusion layer 53, P + Diffusion layers 62 and 63 are selectively provided. In addition, in the surface of the N-type diffusion layer 32c, similar to the N-type diffusion layers 32a, 32b, 34a, and 34b, N + Diffusion layer 54, P + Diffusion layers 64 and 65 are optionally provided.

[0192] In addition, the surface of the P-type diffusion layer 41c contains P + Diffusion layer 61, N + Diffusion layers 51 and 52 are selectively provided. In addition, in the surface of the P-type diffusion layer 42c, similar to the P-type diffusion layers 42a and 42b, P + Diffusion layer 66, N +Diffusion layers 55 and 56 are optionally provided.

[0193] In the semiconductor device 201, an isolation trench 73 is provided in the isolation region 7. The isolation trench 73 is provided between the N-type diffusion layer 31c serving as the first circuit diffusion region and the N-type diffusion layer 32c serving as the second circuit diffusion region, and is provided so that its deepest portion reaches the upper surface of the buried oxide film 120.

[0194] The N-type diffusion layer 31c and the N-type diffusion layer 32c are electrically isolated from each other by the isolation trench 73. The isolation trench 73 is formed, for example, as follows.

[0195] After forming a provisional N-type diffusion layer in the SOI layer 130 in a region including the first and second high side circuit regions RH1 and RH2 and the isolation region 7, an isolation trench 73 is formed in the isolation region 7 so as to extend from the surface of the SOI layer 130 including the provisional N-type diffusion layer to the upper surface of the buried oxide film 120. The isolation trench 73 isolates the provisional N-type diffusion layer between the first and second high side circuit regions RH1 and RH2.

[0196] As a result, the provisional N-type diffusion layer remaining in the first high side circuit region RH1 becomes the N-type diffusion layer 31c, and the provisional N-type diffusion layer remaining in the second high side circuit region RH2 becomes the N-type diffusion layer 32c. Therefore, the isolation trench 73 electrically isolates the N-type diffusion layer 31c from the N-type diffusion layer 32c.

[0197] The isolation trench 73 has a buried insulating film 78 therein, similar to the isolation trenches 70 to 72 in the first and second embodiments.

[0198] (effect) The semiconductor device 201 according to the first aspect of the fourth embodiment provides the same effects as the semiconductor device 101 according to the first aspect of the first embodiment, and further provides the following unique effects.

[0199] The semiconductor device 201, which is the first aspect of the fourth embodiment, is separated in the depth direction into the SOI layer 130 and the supporting substrate 10a by the buried oxide film 120, which is a dielectric, and therefore the leakage current between the first and second high side circuit regions RH1 and RH2 can be further reduced.

[0200] Furthermore, the semiconductor device 201 can suppress parasitic action between the first and second high side circuit regions RH1 and RH2 by the isolation trench 73 that is provided penetrating the SOI layer 130 and has a buried insulating film 78 therein.

[0201] (Second aspect) Fig. 12 is a cross-sectional view showing a schematic cross-sectional structure of a semiconductor device 202 according to a second aspect of the fourth embodiment. Fig. 12 shows a cross-sectional structure corresponding to the AA cross section in Fig. 1. The planar configuration and circuit configuration of the semiconductor device 202 are similar to those shown in Figs. 1 and 2.

[0202] In the following, the parts common to the semiconductor device 201 of the first aspect of the embodiment 4 shown in FIG. 11 are given the same symbols and the explanation is omitted as appropriate, and the explanation will focus on the characteristic parts of the semiconductor device 202 of the second aspect of the embodiment 4.

[0203] In the semiconductor device 202, a P-type layer 13 is provided in place of the isolation trench 73 of the semiconductor device 201, an N-type diffusion layer 33c is provided in place of the N-type diffusion layer 31c, and an N-type diffusion layer 34c is provided in place of the N-type diffusion layer 32c.

[0204] In addition, the surface of the N-type diffusion layer 33c contains N, as in the N-type diffusion layers 31a to 31c, 33a, and 33b. + Diffusion layer 53, P + Diffusion layers 62 and 63 are selectively provided. In addition, in the surface of the N-type diffusion layer 34c, similar to the N-type diffusion layers 32a to 32c, 34a, and 34b, N + Diffusion layer 54, P + Diffusion layers 64 and 65 are optionally provided.

[0205] In this way, the semiconductor device 202 which is the second aspect of the fourth embodiment is provided with the P-type layer 13 which serves as the second isolation diffusion region as the isolation region 7. The P-type layer 13 is provided between the N-type diffusion layer 33c which serves as the first circuit diffusion region and the N-type diffusion layer 34c which serves as the second circuit diffusion region, in contact with the N-type diffusion layers 33c and 34a. The P-type layer 13 functions as the second isolation diffusion region.

[0206] A method for manufacturing the P-type layer 13 will be described below. For example, this is a method for forming the P-type layer 13 by ion implantation and diffusion processing using P-type impurities in the N-type SOI layer 130. At this time, the P-type layer 13 needs to be provided so as to penetrate the SOI layer 130 and reach the upper surface of the buried oxide film 120.

[0207] The semiconductor device 202 according to the second aspect of the fourth embodiment provides the same effects as the semiconductor device 101 according to the first aspect of the first embodiment, and further provides the following effects.

[0208] In the semiconductor device 202 which is the second aspect of the fourth embodiment, the SOI layer 130 and the supporting substrate 10a are separated in the depth direction by the buried oxide film 120 which is a dielectric, and therefore the leakage current between the first and second high side circuit regions RH1 and RH2 can be further reduced.

[0209] Furthermore, the semiconductor device 202 has a P-type layer 13 as a second isolation diffusion region between the N-type diffusion layer 33c serving as the first circuit diffusion region and the N-type diffusion layer 34c serving as the second circuit diffusion region. The P-type layer 13 is provided in contact with each of the N-type diffusion layers 33c and 34a.

[0210] Therefore, the semiconductor device 202, which is the second aspect of the fourth embodiment, has a P-type layer 13 in the isolation region 7 as a second isolation diffusion region, and thus can electrically isolate the first and second high side circuit regions RH1 and RH2 with a relatively simple structure, similar to the semiconductor devices 107 and 108 of the third embodiment.

[0211] <Other> In this disclosure, the first conductivity type is shown as P type and the second conductivity type is shown as N type, but a modified example in which the first conductivity type is N type and the second conductivity type is P type is also conceivable.

[0212] In addition, within the scope of the present disclosure, it is possible to freely combine the respective embodiments, and to appropriately modify or omit the respective embodiments. [Explanation of symbols]

[0213] 7 isolation area, 9 SOI substrate, 10 P-type substrate, 10a support substrate, 11~13 P-type layer, 20~23 N + buried diffusion layer, 30a to 30c, 31a to 31c, 32a to 32c, 33a to 33c, 34a to 34c N-type diffusion layer, 40, 41a to 41c, 42a to 42c, 110 to 112 P-type diffusion layer, 70 to 73 isolation trenches, 101 to 108, 201, 202 semiconductor device, 120 buried oxide film, 130 SOI layer, CH1 first high side circuit, CH2 second high side circuit, RH high side circuit region, RH1 first high side circuit region, RH2 second high side circuit region, RL low side circuit region.

Claims

1. A semiconductor device comprising: A semiconductor substrate; a low-side circuit region provided on the semiconductor substrate and receiving a first reference potential; a high side circuit region provided on the semiconductor substrate and receiving a second reference potential different from the first reference potential; a first isolation region that electrically isolates the low side circuit region and the high side circuit region; the semiconductor substrate has a circuit base region in which the low-side circuit region and the high-side circuit region are not provided, the high side circuit region includes first and second high side circuit regions, a first high side circuit is provided in the first high side circuit region, a second high side circuit is provided in the second high side circuit region, the first high side circuit operates on a first power supply voltage based on the second reference potential, the second high side circuit operates on a second power supply voltage based on the second reference potential, and the first and second power supply voltages are different voltage values; The semiconductor device includes: a second isolation region electrically isolating the first high side circuit region and the second high side circuit region; Semiconductor device.

2. 2. The semiconductor device according to claim 1, the circuit underlayer region includes a substrate region of a first conductivity type; the first isolation region includes a first isolation diffusion region of a second conductivity type, the first isolation diffusion region being disposed on the substrate region; the first high side circuit region includes a first circuit diffusion region of a second conductivity type, the first circuit diffusion region being provided on the substrate region; the second high side circuit region includes a second circuit diffusion region of a second conductivity type, the second circuit diffusion region being disposed on the substrate region; the first and second circuit diffusion regions satisfy a diffusion depth requirement, the diffusion depth requirement being a requirement that the formation depth of each of the first and second circuit diffusion regions be greater than the formation depth of the first isolation diffusion region; Semiconductor device.

3. 3. The semiconductor device according to claim 2, The second isolation region includes: an isolation trench provided between the first circuit diffusion region and the second circuit diffusion region, the deepest portion of the isolation trench reaching the substrate region; the isolating trench has therein a buried insulating film for insulating and isolating the first and second high side circuit regions; Semiconductor device.

4. 4. The semiconductor device according to claim 3, the first circuit diffusion region includes a first buried diffusion layer of a second conductivity type selectively provided on the substrate region, and a first surface diffusion layer of the second conductivity type selectively provided on the first buried diffusion layer; the second circuit diffusion region includes a second buried diffusion layer of a second conductivity type selectively provided on the substrate region, and a second surface diffusion layer of a second conductivity type selectively provided on the second buried diffusion layer; Semiconductor device.

5. 5. The semiconductor device according to claim 4, the isolation trench is not in contact with the first and second buried diffusion layers; the isolation trench satisfies a trench depth requirement, the trench depth requirement being a requirement that the isolation trench is formed to a depth shallower than the respective formation depths of the first and second buried diffusion layers; Semiconductor device.

6. 6. The semiconductor device according to claim 3, a trench bottom diffusion region of a first conductivity type provided in the substrate region around an innermost portion of the isolation trench in contact with the innermost portion of the isolation trench; Semiconductor device.

7. 3. The semiconductor device according to claim 2, the second isolation region includes a second isolation diffusion region of a first conductivity type provided between the first circuit diffusion region and the second circuit diffusion region in contact with the first and second circuit diffusion regions; Semiconductor device.

8. 2. The semiconductor device according to claim 1, The semiconductor substrate includes an SOI substrate having a stacked structure of a support substrate, a buried oxide film, and an SOI layer; the circuit base region includes the support substrate and the buried oxide film, the low side circuit region, the high side circuit region and the second isolation region are provided in the SOI layer; Semiconductor device.

9. 9. The semiconductor device according to claim 8, The second isolation region includes: an isolation trench provided between the first high side circuit region and the second high side circuit region, the deepest portion of which reaches the buried oxide film; the isolating trench has a buried insulating film therein for insulating and isolating the first and second high side circuit regions; Semiconductor device.

10. 9. The semiconductor device according to claim 8, the first high side circuit region includes a first circuit diffusion region of a second conductivity type, the first circuit diffusion region being provided in the SOI layer; the second high side circuit region includes a second circuit diffusion region of a second conductivity type, the second circuit diffusion region being provided in the SOI layer; the second isolation region includes a second isolation diffusion region of a first conductivity type provided between the first circuit diffusion region and the second circuit diffusion region in contact with the first and second circuit diffusion regions; Semiconductor device.

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