Method of manufacturing nitride semiconductor device and nitride semiconductor device

Abstract

To provide a manufacturing method for a nitride semiconductor device, which can suppress the formation of a GaOx layer and can suppress Ga diffusion into an insulating film, and a nitride semiconductor device.SOLUTION: A method for manufacturing a nitride semiconductor device includes the steps of forming a non-oxide film substantially free of oxygen on a gallium nitride layer, forming an insulating film on the non-oxide film, and oxidizing and nitriding the non-oxide film covered with the insulating film by heat treatment in an atmosphere containing NO gas, thereby forming a first oxynitride film from the non-oxide film.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a nitride semiconductor device and a nitride semiconductor device. [Background technology]

[0002] When forming a gate insulating film on the surface of gallium nitride (GaN) by plasma CVD, an oxygen plasma is generated inside the equipment. The oxygen plasma oxidizes the GaN surface to form a GaOx layer. The GaOx layer can act as a carrier trap source, lowering the mobility of the MOSFET. The GaOx layer can also act as a source of Ga diffusion into the gate insulating film, resulting in fixed charges in the gate insulating film, which can lead to a decrease in the threshold voltage of the MOSFET. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2016-143842 A Summary of the Invention [Problem to be solved by the invention]

[0004] There is a need for a technology that can suppress the formation of a GaOx layer and suppress Ga diffusion into a gate insulating film. The present disclosure has been made in view of the above circumstances, and has an object to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device that can suppress the formation of a GaOx layer and suppress Ga diffusion into an insulating film. [Means for solving the problem]

[0005] In order to solve the above problems, a manufacturing method for a nitride semiconductor device according to one embodiment of the present disclosure includes the steps of forming a non-oxide film substantially free of oxygen on a gallium nitride layer, forming an insulating film on the non-oxide film, and oxidizing and nitriding the non-oxide film covered with the insulating film by heat treatment in an atmosphere containing NO gas, thereby forming a first oxynitride film from the non-oxide film.

[0006] A nitride semiconductor device according to one aspect of the present disclosure includes a gallium nitride layer and a field effect transistor provided on the gallium nitride layer. A gate insulating film of the field effect transistor includes a first oxynitride film adjacent to the gallium nitride layer and an insulating film provided on the first oxynitride film. An interface transition layer containing gallium oxide is substantially absent at the interface between the gallium nitride layer and the first oxynitride film and within a range of 10 nm from the interface toward the gallium nitride layer. Effect of the Invention

[0007] According to the present disclosure, it is possible to provide a method for manufacturing a nitride semiconductor device and a nitride semiconductor device that can suppress the formation of a GaOx layer and suppress Ga diffusion into an insulating film. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to a first embodiment of the present disclosure. [Diagram 2] FIG. 2 is a cross-sectional view showing a configuration example of the GaN semiconductor device according to the first embodiment of the present disclosure. [Diagram 3] FIG. 3 is an enlarged view of the cross-sectional view of FIG. 2, showing one vertical MOSFET (unit structure). [Figure 4] 4A to 4C are cross-sectional views illustrating the process steps of a method for manufacturing a GaN semiconductor device according to the first embodiment of the present disclosure. [Diagram 5] 5A to 5C are cross-sectional views illustrating the process steps of a method for manufacturing a GaN semiconductor device according to the second embodiment of the present disclosure. [Figure 6]FIG. 6 is a cross-sectional view showing a configuration example of a vertical MOSFET according to the third embodiment of the present disclosure. [Figure 7] FIG. 7 is a cross-sectional view showing a configuration example of a normally-off HEMT according to the fourth embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The following describes an embodiment of the present disclosure. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device and each member, and the like are different from the actual ones. Therefore, the specific thickness and dimensions should be determined with reference to the following description. In addition, it goes without saying that the drawings include parts with different dimensional relationships and ratios.

[0010] In the following description, directions may be described using the terms X-axis direction, Y-axis direction, and Z-axis direction. For example, the X-axis direction and the Y-axis direction are parallel to the surface 10a of the GaN substrate 10 described below. The Z-axis direction is perpendicular to the surface 10a of the GaN substrate 10. The X-axis direction, the Y-axis direction, and the Z-axis direction are mutually orthogonal.

[0011] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down". "Up" and "down" do not necessarily mean the vertical direction with respect to the ground. In other words, the directions of "up" and "down" are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship in regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present disclosure. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up".

[0012] In the following description, + or - may be added to p or n, which indicates the conductivity type of a semiconductor region. + and - mean that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same p and p (or n and n) are added to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0013] <Embodiment 1> (Configuration example) FIG. 1 is a plan view showing a configuration example of a GaN (gallium nitride) semiconductor device 100 (an example of a "nitride semiconductor device" of the present disclosure) according to embodiment 1 of the present disclosure. FIG. 2 is a cross-sectional view showing a configuration example of the GaN semiconductor device 100 according to embodiment 1 of the present disclosure. FIG. 2 shows a cross section taken along line AA' in the plan view of FIG. 1. FIG. 3 is an enlarged view of the cross-sectional view of FIG. 2, showing one vertical MOSFET 1 (unit structure).

[0014] GaN semiconductor device 100 shown in Fig. 1 and Fig. 2 is a power device. As shown in Fig. 1 and Fig. 2, GaN semiconductor device 100 includes GaN substrate 10 (an example of the "gallium nitride layer" of the present disclosure) having front surface 10a and back surface 10b, and multiple vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1 provided on GaN substrate 10.

[0015] The vertical MOSFET 1 is an example of a "field effect transistor" of the present disclosure. For example, multiple vertical MOSFETs 1 are repeatedly provided in one direction (e.g., the X-axis direction). One vertical MOSFET 1 is a repeated unit structure, and this unit structure is arranged side by side in one direction.

[0016] 1 to 3, GaN substrate 10 has an n+ type GaN single crystal substrate 11 and an n- type GaN layer 12 provided on GaN single crystal substrate 11. GaN single crystal substrate 11 is, for example, an n+ type c-plane GaN single crystal substrate. The n-type impurity contained in GaN single crystal substrate 11 is one or more of Si (silicon), O (oxygen), and Ge (germanium). As an example, GaN single crystal substrate 11 contains Si as an n-type impurity, and the impurity concentration of Si in GaN single crystal substrate 11 is 5×10 17 cm -3 That's all.

[0017] The GaN single crystal substrate 11 has a dislocation density of 1×10 7 cm -2 The GaN single crystal substrate 11 may be a low dislocation freestanding substrate having a dislocation density of less than 100 nm. When the GaN single crystal substrate 11 is a low dislocation freestanding substrate, the dislocation density of the GaN layer 12 formed on the GaN single crystal substrate 11 is also low. Furthermore, by using a low dislocation freestanding substrate, it is possible to reduce leakage current in the power device even when a large-area power device is formed on the GaN substrate 10. This enables the manufacturing equipment to manufacture power devices with a high yield rate. Furthermore, it is possible to prevent ion-implanted impurities from diffusing deeply along the dislocations during heat treatment.

[0018] The GaN layer 12 is a single crystal GaN layer epitaxially grown on one surface of the GaN single crystal substrate 11. The GaN layer 12 is formed by doping with an n-type impurity during the epitaxial growth process. The n-type impurity is, for example, Si. The GaN layer 12 is formed by doping with, for example, 1×10 15 cm -3 5×10 or more 16 cm -3 Contains the following concentrations:

[0019] The vertical MOSFET 1 has a p-type well region 13 and a p+ type contact region 15 provided on the front surface 10a (i.e., the front surface of the n-type GaN layer 12) of the GaN substrate 10. The vertical MOSFET 1 also includes a gate insulating film 21 provided on the front surface 10a of the GaN substrate 10, a gate electrode 22 provided on the gate insulating film 21, a source electrode 25 provided on the front surface 10a of the GaN substrate 10 and in contact with the source region 23 and the contact region 15, and a drain electrode 26 provided on the back surface 10b of the GaN substrate 10 and in contact with the n+ type GaN single crystal substrate 11.

[0020] On the surface 10a of the GaN substrate 10 (ie, the surface of the n-type GaN layer 12), a P-type well region 13, an n+ type source region 23, and a p+ type contact region 15 are provided.

[0021] The well region 13 is a p-type layer formed by ion-implanting a p-type impurity such as Mg on the surface 10a side of the GaN substrate 10 and activating the p-type impurity by heat treatment. The well region 13 is formed by ion-implanting a p-type impurity such as Mg at a concentration of 1×10 17 cm -3 More than 3×10 18 cm -3 The well region 13 faces the surface 10a of the GaN substrate 10. The surface of the well region 13 is in contact with the gate insulating film 21. The channel of the vertical MOSFET 1 is formed on the surface of the well region 13 in contact with the gate insulating film 21 and in the vicinity thereof.

[0022] The source region 23 is an n+ type layer formed by ion-implanting n-type impurities such as Si or O into the surface 10a of the GaN substrate 10 and activating the n-type impurities by heat treatment. 19 cm -3 5×10 or more 20 cm -3The source regions 23 are provided in the well region 13 below both sides of the gate electrode 22, and face the surface 10a of the GaN substrate 10. The source regions 23 are located inside the well region 13 and are in contact with the well region 13.

[0023] The contact region 15 is, for example, a p+ type layer formed by ion-implanting a p-type impurity such as Mg into the front surface 10a side of the GaN substrate 10 and activating the p-type impurity by heat treatment. 18 cm -3 More than 1×10 21 cm -3 More preferably, it is present at a concentration of 1×10 19 cm -3 More than 2×10 20 cm -3 Contains the following concentrations:

[0024] The contact region 15 faces the front surface 10a of the GaN substrate 10. The contact region 15 is located inside the well region 13 and is in contact with the well region 13. The contact region 15 also is in contact with the source region 23.

[0025] The well region 13 is connected to the source electrode 25 via the contact region 15. As a result, the potential of the well region 13 is fixed to the potential of the source electrode 25 (for example, a reference potential such as the ground potential (GND)).

[0026] The gate insulating film 21 has a SiON film 211 (an example of a "first oxynitride film" in the present disclosure) and a SiO2 film 212 (an example of an "insulating film" in the present disclosure) provided on the SiON film 211. The SiON film 211 and the SiO2 film 212 are laminated in this order on the GaN layer 12. The thickness of the SiON film 211 is thinner than the thickness of the SiO2 film 212. For example, the thickness of the SiON film 211 is 0.5 nm or more and 5 nm or less, and the thickness of the SiO2 film 212 is 30 nm or more and 200 nm or less.

[0027] The GaN layer 12 and the SiON film 211 are directly adjacent to each other. There is no interfacial transition layer containing gallium oxide (GaOx) at the interface between the GaN layer 12 and the SiON film 211 and within a range of 10 nm from this interface toward the GaN layer 12. In other words, there is no gallium oxide (GaOx) between the GaN layer 12 and the SiON film 211. This structure is realized by a manufacturing method described later.

[0028] Moreover, the nitrogen element concentration in the thickness direction (e.g., Z-axis direction) of the SiON film 211 is maximum at and near the interface with the GaN layer 12. This is believed to be because N of the NO gas is trapped at the interface between the single crystal GaN layer 12 and the amorphous silicon (hereinafter, a-Si) layer in the oxynitriding process described later.

[0029] The gate electrode 22 is adjacent to a region where a channel is formed (hereinafter, referred to as a channel region) via the gate insulating film 21. The gate electrode 22 is made of polysilicon doped with a metal such as Al, Ti, Ni, or W, or an impurity. The gate electrode 22 may also be made of a silicide such as WSi or NiSi.

[0030] The source electrode 25 is in ohmic contact with the source region 23, which is an n+ type layer, and the contact region 15, which is a p+ type layer. The drain electrode 26 is in ohmic contact with the other surface of the n+ type GaN single crystal substrate 11 (i.e., the surface opposite to the surface in contact with the GaN layer 12).

[0031] The source electrode 25 and the drain electrode 26 are made of Al or an Al-Si alloy, Ni, a Ni alloy, a Ti-Al alloy, a Ni-Au alloy, or the like. The source electrode 25 may have a barrier metal layer between itself and the source region 23. The drain electrode 26 may have a barrier metal layer between itself and the n+ type GaN single crystal substrate 11. The barrier metal layer may be made of Ti (titanium).

[0032] That is, the source electrode 25 and the drain electrode 26 may be a laminate of a Ti layer and an Al layer, or a laminate of a Ti layer and an Al-Si alloy layer. The source electrode 25 may also serve as a source pad (not shown), or may be an electrode provided separately from the source pad. The drain electrode 26 may also serve as a drain pad (not shown), or may be an electrode provided separately from the drain pad.

[0033] (Manufacturing method) Next, a method for manufacturing the GaN semiconductor device 100 will be described. Fig. 4 is a cross-sectional view showing the process steps of the method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present disclosure. The GaN semiconductor device 100 is manufactured using various types of equipment, such as a cleaning device, a film forming device, a heat treatment device, an exposure device, and an etching device. Hereinafter, these devices will be collectively referred to as manufacturing equipment.

[0034] 4, although not shown, a manufacturing device forms p-type well region 13 (see FIG. 3), n+ type source region 23 (see FIG. 3), and p+ type contact region 15 (see FIG. 3) on the surface side of GaN layer 12. P-type well region 13 is formed by partially ion-implanting magnesium (Mg) as a p-type impurity into the surface side of GaN layer 12, and activating the Mg by performing a heat treatment on the entire substrate including GaN layer 12.

[0035] The n+ type source region 23 is formed by partially ion-implanting silicon (Si) as an n-type impurity into the surface side of the well region 13, and activating the Si by performing a heat treatment on the entire substrate including the well region 13. The p+ type contact region 15 is formed by partially ion-implanting Mg as a p-type impurity into the surface side of the well region 13, and activating the Mg by performing a heat treatment on the entire substrate including the well region 13. Note that the heat treatment for forming the n+ type source region 23 and the heat treatment for forming the p+ type contact region 15 are, for example, the same process.

[0036] Next, the manufacturing equipment performs a cleaning process on GaN layer 12, in which well region 13, source region 23, and contact region 15 have been formed, in order to remove an oxide film (e.g., a natural oxide film of GaOx or the like) from the surface of GaN layer 12. The oxide film is removed by this cleaning process, and the surface of GaN layer 12 is exposed.

[0037] Next, the manufacturing equipment forms an amorphous silicon (a-Si) film 210 on the surface of the GaN layer 12 from which the oxide film has been removed by the cleaning process. The a-Si film 210 is formed by, for example, a thermal CVD method or a sputtering method. The thickness of the a-Si film 210 is, for example, 0.5 nm or more and 5 nm or less.

[0038] 4, the manufacturing equipment forms a SiO2 film 212 on the a-Si film 210. The SiO2 film 212 is formed by, for example, a plasma CVD method. The thickness of the SiO2 film 212 is, for example, 100 nm.

[0039] 4, the manufacturing equipment oxynitrides the a-Si film 210 covered with the SiO2 film 212 by heat treatment in an atmosphere containing nitric oxide (NO) gas (hereinafter also referred to as NO treatment), thereby forming a SiON film 211 from the a-Si film 210. The manufacturing equipment oxynitrides the entire a-Si film 210 through the SiO2 film 212 by the NO treatment, thereby forming the SiON film 211 from the a-Si film 210.

[0040] Specific examples of conditions for the NO treatment are given below. The NO treatment is performed in an atmosphere of a gas in which NO gas is diluted with nitrogen (N2) gas. The NO concentration in this gas is, for example, 10 vol% (volume percent). The maximum temperature in the NO treatment is, for example, 500°C or more and 1000°C or less, for example, 850°C. The treatment time at this maximum temperature is, for example, 30 minutes (min). As a result, in the a-Si film 210, oxynitridation progresses at a rate of 0.3 Å / min from the SiO2 film 212 side to the GaN layer 12 side, and the SiON film 211 is formed from the a-Si film 210. The nitrogen element (N) content of the SiON film 211 is, for example, 0.1 at% (atomic percent) or more and 5 at% or less in composition ratio, and 1×10 18 cm -3 5×10 or more 19 cm -3 The following is the result.

[0041] In this manufacturing method, the process of forming the gate insulating film 21 of the vertical MOSFET 1 includes the steps of forming an a-Si film 210, forming a SiO2 film 212, and forming a SiON film 211 from the a-Si film 210 by NO treatment.

[0042] Next, the manufacturing equipment forms a gate electrode 22 (see FIG. 3) on the gate insulating film 21. For example, the manufacturing equipment forms a gate electrode film on the SiO2 film 212 that is a part of the gate insulating film 21. The gate electrode film is made of Al or an Al-Si alloy, and the film formation method is a vapor deposition method. Alternatively, the gate electrode film may be made of polysilicon doped with impurities, and the film formation method may be a CVD method. Next, the manufacturing equipment forms the gate electrode 22 by patterning the gate electrode film.

[0043] Next, the manufacturing equipment forms source electrode 25 (see FIG. 3) on the surface side of GaN layer 12. Source electrode 25 is formed by depositing Al or an Al—Si alloy by a vapor deposition method and patterning the deposited Al or Al—Si alloy.

[0044] Next, the manufacturing equipment forms a drain electrode 26 (see FIG. 3) on the back surface 10b (see FIG. 3) side of the GaN substrate 10. The drain electrode 26 is formed by depositing an Al or Al-Si alloy by vapor deposition and patterning it as necessary. Through the above steps, the GaN semiconductor device 100 shown in FIGS. 1 to 3 is completed.

[0045] (Effects of the First Embodiment) As described above, the method for manufacturing the GaN semiconductor device 100 according to the first embodiment of the present disclosure includes the steps of forming an a-Si film 210 that is substantially free of oxygen on the GaN layer 12, forming an SiO2 film 212 on the a-Si film 210, and oxidizing and nitriding the a-Si film 210 covered with the SiO2 film 212 by heat treatment in an atmosphere containing NO gas to form a SiON film 211 from the a-Si film 210. The oxygen element (O) content of the a-Si film 210 is, for example, 5×10 21 cm -3 It is equal to or less than the detection limit, and preferably equal to or less than the detection limit.

[0046] According to this, after forming the a-Si film 210 on the GaN layer 12, NO gas is used as an oxygen supply source for the a-Si film 210. It is known that NO gas has extremely low reactivity with GaN compared to other oxidizing gases (O2, O3, H2O, N2O) (M.Sumiya et al.Sci.Technol.Adv.Mater.23,189(2022)). Therefore, the a-Si film 210 can be oxynitrided to form the SiON film 211 while suppressing oxidation of the surface of the GaN layer 12. In addition, in the oxynitridation by NO, a small amount of N (several percent or less) also remains in the SiON film 211. Therefore, Ga diffusion to the SiO2 film 212 side due to the heat treatment after forming the SiON film 211 (i.e., post-heat treatment) can also be suppressed. In this way, the formation of a GaOx layer can be suppressed, and Ga diffusion into the SiON film 211 and the SiO2 film 212 can be suppressed.

[0047] In the first embodiment, for example, a SiON film 211 and a SiO2 film 212 are formed as the gate insulating film 21. The gate insulating film 21 can be formed without forming a GaOx layer on the surface of the GaN layer 12. This makes it possible to prevent the GaOx layer from becoming a carrier trap source, thereby reducing the mobility of the MOSFET, or the GaOx layer from becoming a Ga diffusion source, thereby forming fixed charges in the film and reducing the threshold value. It is possible to realize a vertical MOSFET 1 that has low channel resistance (high mobility), little fixed charge, and is capable of suppressing fluctuations in the threshold value.

[0048] In the first embodiment, unlike the comparative examples 1 and 2 described later, the gate insulating film 21 can be formed under optimal conditions for good film quality without forming a GaOx layer. For example, the gate insulating film 21 can be formed at an optimal temperature for good film quality. This makes it possible to realize a vertical MOSFET 1 with good insulation leakage characteristics.

[0049] In addition, hydrogen elements (H) may remain in the SiO2 film. For example, when silane (SiH4) is used as a source gas when forming a SiO2 film by a CVD method, some of the H constituting SiH4 remains in the SiO2 film. The H remaining in the SiO2 film (hereinafter, referred to as residual H) may form a fixed charge in a subsequent heat treatment. In the first embodiment, the NO treatment is performed after the SiO2 film 212 is formed, so that the residual H can be removed from the SiO2 film 212. This can also suppress the formation of fixed charges caused by the residual H.

[0050] Comparative Example 1 As Comparative Example 1, a method of forming a SiO2 film on the surface of a GaN substrate by plasma CVD is considered. In the method of Comparative Example 1, a GaOx layer is formed at the interface between the GaN substrate and the SiO2 film, which causes characteristic defects. Specifically, the GaOx layer may become a carrier trap source and reduce the mobility of the MOSFET. In addition, the GaOx layer may become a Ga diffusion supply source into the gate insulating film, which may cause fixed charges in the gate insulating film and may lead to a decrease in the threshold voltage of the MOSFET.

[0051] Comparative Example 2 As Comparative Example 2, a method is considered in which a SiON film is formed on the surface of a GaN substrate by plasma CVD, and a SiO2 film is formed thereon. In the method of Comparative Example 2, the thickness of the GaOx layer is thinner than in Comparative Example 1, but the GaOx layer is formed when the SiON film is formed. In addition, it is difficult to control the amount of nitrogen in the SiON film, compared to the method of the first embodiment.

[0052] <Embodiment 2> A film containing nitrogen at a high concentration may be formed on an a-Si film 210, which is an example of a non-oxide film, and then an SiO2 film 212 may be formed on this film, after which the NO treatment may be performed.

[0053] 5 is a cross-sectional view showing a process sequence of a method for manufacturing a GaN semiconductor device 100 according to embodiment 2 of the present disclosure. In step ST11 in FIG. 5, the process up to the step of forming an a-Si film 210 is the same as step ST1 in FIG. 4 described in embodiment 1. After forming the a-Si film 210, the manufacturing equipment forms a SiON film 213 (an example of a "second oxynitride film" in the present disclosure) on the a-Si film 210.

[0054] The SiON film 213 is formed by, for example, a plasma CVD method. The thickness of the SiON film 213 is, for example, 10 nm. The N content in the SiON film 213 is, for example, 1×10 19 cm -3 The N content in the SiON film 213 is, for example, 1.0×10 19 / cm 3 That's it, 1.0 x 10 20 / cm 3 It may be the following.

[0055] The SiON film 213 has a higher concentration of nitrogen element (N) than the SiON film 211 (one example of a "first oxynitride film" in the present disclosure) formed in the NO treatment (step ST13) described later. The high concentration of N in the SiON film 213 can suppress the diffusion of gallium in the GaN substrate 10 including the GaN layer 12 above the SiON film 213. This makes it possible to perform a high-temperature heat treatment after the formation of the SiON film 213, improving the degree of freedom in the heat treatment.

[0056] Next, as shown in step ST12 of FIG. 5, the manufacturing equipment forms a SiO2 film 212 on the SiON film 213. The SiO2 film 212 is formed by, for example, a plasma CVD method. The thickness of the SiO2 film 212 is, for example, 100 nm. In the second embodiment, the stacked film formed of the SiON film 213 and the SiO2 film 212 is an example of the "insulating film" of the present disclosure.

[0057] 5, the manufacturing equipment oxynitrides the a-Si film 210 covered with the SiON film 213 and the SiO2 film 212 by heat treatment in an atmosphere containing nitric oxide (NO) gas (i.e., NO treatment), thereby forming the SiON film 211 from the a-Si film 210. The manufacturing equipment oxynitrides the entire a-Si film 210 through the SiO2 film 212 and the SiON film 213 by the NO treatment, thereby forming the SiON film 211 from the a-Si film 210. Specific examples of conditions for the NO treatment are the same as those in the first embodiment.

[0058] In the second embodiment, the process of forming the gate insulating film 21 of the vertical MOSFET 1 includes a process of forming an a-Si film 210, a process of forming a SiON film 213, a process of forming a SiO2 film 212, and a process of forming a SiON film 211 from the a-Si film 210 by NO treatment. A laminated film in which the SiON film 211, the SiON film 213, and the SiO2 film 212 are laminated in this order on the GaN layer 12 serves as the gate insulating film 21.

[0059] The subsequent steps are the same as those in the manufacturing method of embodiment 1. The manufacturing equipment sequentially forms gate electrode 22 (see FIG. 3), source electrode 25 (see FIG. 3), and drain electrode 26. Through the above steps, GaN semiconductor device 100 shown in FIGS. 1 to 3 is completed.

[0060] As described above, the method for manufacturing the GaN semiconductor device 100 according to the second embodiment includes the steps of forming an a-Si film 210 containing substantially no oxygen on the GaN layer 12, forming a SiON film 213 on the a-Si film 210, forming a SiO2 film 212 on the SiON film 213, and oxidizing and nitriding the a-Si film 210 covered with the SiO2 film 212 and the SiON film 213 by heat treatment in an atmosphere containing NO gas, thereby forming a SiON film 211 from the a-Si film 210.

[0061] This provides the same effects as the manufacturing method of embodiment 1. In addition, in the manufacturing method of embodiment 2, a SiON film 213 containing N at a higher concentration than the SiON film 211 is formed between the SiON film 211 and the SiO2 film 212. This can further suppress Ga diffusion toward the SiO2 film 212 side due to a subsequent heat treatment. It is possible to suppress the formation of a GaOx layer, and further suppress Ga diffusion into the SiO2 film 212.

[0062] In the second embodiment, the a-Si film 210 covered with the SiON film 213 may be subjected to NO treatment before forming the SiO2 film 212, not after forming the SiO2 film 212. Then, the SiO2 film 212 may be formed after forming the SiON film 211 from the a-Si film 210 by NO treatment. In this case, the SiON film 213 is an example of the "insulating film" of the present disclosure. Even with such a method, the formation of a GaOx layer can be suppressed, and Ga diffusion into the SiO2 film 212 can be suppressed.

[0063] <Embodiment 3> In the above-described first embodiment, the vertical MOSFET 1 included in the GaN semiconductor device 100 is of a planar type. However, in each embodiment of the present disclosure, the vertical MOSFET included in the GaN semiconductor device 100 is not limited to a planar type, and may be a trench gate type.

[0064] Fig. 6 is a cross-sectional view showing a configuration example of a vertical MOSFET 1A according to embodiment 3 of the present disclosure. As shown in Fig. 6, the vertical MOSFET 1A according to embodiment 3 has a trench H provided in a GaN substrate 10. The trench H opens on the front surface 10a side of the GaN substrate 10. The trench H is formed deeper than the p-type well region 13, and the bottom of the trench H reaches the n-type GaN layer 12 (drift region).

[0065] A gate insulating film 21 and a gate electrode 22 are disposed inside the trench H. The inner side and bottom surface of the trench H are covered with the gate insulating film 21. The gate electrode 22 is embedded in the trench H via the gate insulating film 21. In the trench-gate vertical MOSFET 1A, a region of the well region 13 facing the gate electrode 22 via the gate insulating film 21 provided on the side surface of the trench H serves as a channel region.

[0066] The vertical MOSFET 1A according to the third embodiment has, as the gate insulating film 21, a SiON film 211 covering the inner side and bottom surface of the trench H, and a SiO2 film 212 provided on the SiON film 211. The SiON film 211 and the SiO2 film 212 provided on the SiON film 211 are laminated in this order to configure the gate insulating film 21. The configurations of the SiON film 211 and the SiO2 film 212 are as described in the first embodiment.

[0067] Like the vertical MOSFET 1, the vertical MOSFET 1A can be manufactured by the manufacturing method including the oxynitridation step by NO treatment described in the embodiment 1. Furthermore, the vertical MOSFET 1A employs a trench gate structure, which allows the channel regions to be arranged more densely, facilitating miniaturization of the element.

[0068] The gate insulating film 21 of the vertical MOSFET 1A according to the third embodiment may have the same configuration as that described in the second embodiment. That is, the gate insulating film 21 may be a laminated film in which a SiON film 211, a SiON film 213, and a SiO2 film 212 are laminated in this order on the side and bottom surfaces of a trench H provided in a GaN substrate 10. This structure can be manufactured by the manufacturing method including the oxynitridation step by NO treatment described in the second embodiment.

[0069] <Embodiment 4> The "field effect transistor" of the present disclosure is not limited to a MOSFET, and may be a HEMT (High Electron Mobility Transistor).

[0070] Fig. 7 is a cross-sectional view showing a configuration example of a normally-off type HEMT2 according to embodiment 4 of the present disclosure. As shown in Fig. 7, the HEMT2 includes a high-purity GaN layer 112 (an example of a "gallium nitride layer" in the present disclosure) and an AlGaN layer 31 serving as an electron supply layer disposed on the GaN layer 112. In the GaN layer 112, a two-dimensional electron gas (2DEG) is induced at the interface with the AlGaN layer 31 and in the vicinity thereof (for example, a region up to about 10 nm from the interface in the thickness direction).

[0071] In the HEMT 2, an opening h having a bottom surface on the GaN layer 112 is provided in the AlGaN layer 31. A gate insulating film 21 is provided from the bottom and side surfaces of the opening h to the AlGaN layer 31. A channel is formed in the GaN layer 112 in a region that forms the bottom surface of the opening h (i.e., a region in contact with the gate insulating film 21).

[0072] 7, the gate insulating film 21 has a SiON film 211 and a SiO2 film 212 provided on the SiON film 211. The method for forming the SiON film 211 and the SiO2 film 212 is as described in the first embodiment with reference to FIG.

[0073] Alternatively, the gate insulating film 21 may be a laminated film in which a SiON film 211, a SiON film 213, and a SiON film 211 are laminated in this order on the GaN layer 112. The methods for forming the SiON film 211, the SiON film 213, and the SiO2 film 212 are as described in the second embodiment with reference to FIG.

[0074] In this way, the HEMT 2 can be manufactured by a manufacturing method including an oxynitridation step using NO treatment, similar to the vertical MOSFET 1 described in embodiment 1 (or the vertical MOSFET 1A described in embodiment 2). By applying the technology disclosed herein to a HEMT, it is possible to realize a transistor capable of high-speed operation with gate drive using a small charge while achieving the above-mentioned effects.

[0075] <Other embodiments> As described above, the present disclosure has been described by the embodiments and modifications, but the descriptions and drawings forming a part of this disclosure should not be understood as limiting the present disclosure. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.

[0076] For example, in the above embodiment 1, the "insulating film" of the present disclosure is described as the SiO2 film 212. Also, in the above embodiment 2, the "insulating film" of the present disclosure is described as the SiO2 film 212 and the SiON film 213. However, the "insulating film" of the present disclosure is not limited to these. The "insulating film" of the present disclosure may include an oxide or oxynitride containing one or more elements of B, Al, Si, Ga, Ti, Y, Zr, Hf, Ta, and W.

[0077] In the above embodiment, the a-Si film 210 is used as an example of the "non-oxide film" of the present disclosure, but the "non-oxide film" is not limited to this. The "non-oxide film" of the present disclosure may be a polysilicon film. The "non-oxide film" of the present disclosure is not limited to an amorphous structure, but may be a polycrystalline structure. The "non-oxide film" of the present disclosure is not limited to a single layer of Si having an amorphous or polycrystalline structure. The "non-oxide film" of the present disclosure may include one or more of a Si film, a Si nitride film, an Al film, or an Al nitride film.

[0078] Thus, the present disclosure naturally includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the gist of the above-mentioned embodiments and modifications. Furthermore, the effects described in this specification are merely examples and are not limited thereto, and other effects may also be present. The technical scope of the present disclosure is determined only by the invention-specific matters related to the scope of the claims that are appropriate from the above description.

[0079] The present disclosure can also be configured as follows. (1) forming a non-oxide film substantially free of oxygen on the gallium nitride layer; forming an insulating film on the non-oxide film; and forming a first oxynitride film from the non-oxide film by oxidizing and nitriding the non-oxide film covered with the insulating film by heat treatment in an atmosphere containing NO gas. (2) The oxygen content of the non-oxide film is 5×10 21 cm -3 A method for manufacturing a nitride semiconductor device according to (1) above, which comprises the following steps: (3) Before the step of forming the non-oxide film, The method for producing a nitride semiconductor device according to (1) or (2) above, further comprising the step of performing a cleaning treatment to remove an oxide film from a surface of the gallium nitride layer. (4) The method for manufacturing a nitride semiconductor device according to any one of (1) to (3), wherein the non-oxide film has a thickness smaller than a thickness of the insulating film. (5) The method for manufacturing a nitride semiconductor device according to any one of (1) to (4), wherein the non-oxide film has a thickness of 0.5 nm or more and 5 nm or less. (6) The method for manufacturing a nitride semiconductor device according to any one of (1) to (5), wherein the non-oxide film includes at least one of a Si film, a Si nitride film, an Al film, and an Al nitride film. (7) In the step of forming the non-oxide film, The method for manufacturing a nitride semiconductor device according to any one of (1) to (6), wherein the non-oxide film is formed by a thermal CVD method or a sputtering method. (8) The method for manufacturing a nitride semiconductor device according to any one of (1) to (7), wherein the insulating film has a thickness of 30 nm or more and 200 nm or less. (9) The method for manufacturing a nitride semiconductor device according to any one of (1) to (8), wherein the insulating film includes a second oxynitride film having a higher concentration of nitrogen element than the first oxynitride film. (10) The method for manufacturing a nitride semiconductor device according to any one of (1) to (9), wherein the insulating film includes an oxide or an oxynitride containing one or more elements of B, Al, Si, Ga, Ti, Y, Zr, Hf, Ta, and W. (11) The method for manufacturing a nitride semiconductor device according to any one of (1) to (10), wherein the maximum temperature of the heat treatment is 500° C. or higher and 1000° C. or lower. (12) In the step of forming the first oxynitride film, The method for manufacturing a nitride semiconductor device according to any one of (1) to (11), wherein the heat treatment is performed on the non-oxide film in an atmosphere of a gas in which the NO gas is diluted with N2 gas. (13) As a step of forming a gate insulating film of a field effect transistor on the gallium nitride layer, The method for manufacturing a nitride semiconductor device according to any one of (1) to (12), comprising the steps of forming the non-oxide film, forming the insulating film, and forming the first oxynitride film from the non-oxide film by the heat treatment in an atmosphere containing NO gas. (14) a gallium nitride layer; a field effect transistor provided on the gallium nitride layer, The gate insulating film of the field effect transistor is a first oxynitride film adjacent to the gallium nitride layer; an insulating film provided on the first oxynitride film; a nitride semiconductor device in which an interface transition layer containing gallium oxide is not present at the interface between the gallium nitride layer and the first oxynitride film, or within a range of 10 nm from the interface toward the gallium nitride layer. (15) The nitride semiconductor device according to (14), wherein a concentration of nitrogen element in a thickness direction of the first oxynitride film is maximum at and in the vicinity of the interface with the gallium nitride layer. [Explanation of symbols]

[0080] 1, 1A vertical MOSFET 2 HEMT 10 GaN substrate 10a surface 10b back side 11 GaN single crystal substrate 12, 112 GaN layer 13 Well Area 15 Contact Area 21 Gate insulating film 22 Gate electrode 23 Source Region 25 Source electrode 26 Drain electrode 31 AlGaN layer 100 GaN semiconductor device 210 a-Si (amorphous silicon) film 211, 213 SiON film 212 SiO2 film 213 SiON membrane h opening H Trench

Claims

1. forming a non-oxide film substantially free of oxygen on the gallium nitride layer; forming an insulating film on the non-oxide film; and forming a first oxynitride film from the non-oxide film by oxidizing and nitriding the non-oxide film covered with the insulating film by heat treatment in an atmosphere containing NO gas.

2. The oxygen content of the non-oxide film is 5×10 ２１ cm －３ The method for manufacturing a nitride semiconductor device according to claim 1 , wherein:

3. Before the step of forming the non-oxide film, 3. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising the step of performing a cleaning process to remove an oxide film from a surface of the gallium nitride layer.

4. The method for manufacturing a nitride semiconductor device according to claim 1 , wherein the non-oxide film has a thickness smaller than a thickness of the insulating film.

5. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the non-oxide film has a thickness of 0.5 nm or more and 5 nm or less.

6. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the non-oxide film includes at least one of a Si film, a Si nitride film, an Al film, and an Al nitride film.

7. In the step of forming the non-oxide film, 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the non-oxide film is formed by a thermal CVD method or a sputtering method.

8. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the insulating film has a thickness of 30 nm or more and 200 nm or less.

9. 3 . The method for manufacturing a nitride semiconductor device according to claim 1 , wherein said insulating film includes a second oxynitride film having a higher concentration of nitrogen elements than said first oxynitride film.

10. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the insulating film includes an oxide or an oxynitride containing one or more elements selected from the group consisting of B, Al, Si, Ga, Ti, Y, Zr, Hf, Ta, and W.

11. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein a maximum temperature of said heat treatment is 500° C. or more and 1000° C. or less.

12. In the step of forming the first oxynitride film, The NO gas is N ２ 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the heat treatment is performed on the non-oxide film in an atmosphere of a gas diluted with a gas.

13. As a step of forming a gate insulating film of a field effect transistor on the gallium nitride layer, 3. The method for manufacturing a nitride semiconductor device according to claim 1, comprising the steps of: forming the non-oxide film; forming the insulating film; and forming the first oxynitride film from the non-oxide film by the heat treatment in an atmosphere containing NO gas.

14. a gallium nitride layer; a field effect transistor provided on the gallium nitride layer, The gate insulating film of the field effect transistor is a first oxynitride film adjacent to the gallium nitride layer; an insulating film provided on the first oxynitride film; a nitride semiconductor device in which an interface transition layer containing gallium oxide is not present at the interface between the gallium nitride layer and the first oxynitride film, or within a range of 10 nm from the interface toward the gallium nitride layer.

15. The nitride semiconductor device according to claim 14 , wherein a concentration of nitrogen element in a thickness direction of said first oxynitride film is maximum at and in the vicinity of the interface with said gallium nitride layer.

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