Oxide semiconductor element

Abstract

To provide an oxide semiconductor element with high mobility, including a semiconductor layer in which an oxide semiconductor having crystallinity is used.SOLUTION: Provided is an oxide semiconductor element in which a layer having a stacked-layer structure of a first oxide semiconductor film and a second oxide semiconductor film is used as an oxide semiconductor layer, the second oxide semiconductor film being in contact with the first oxide semiconductor film and having a wider band gap than the first oxide semiconductor film. Thus, a channel region is formed in the vicinity of an interface of the first oxide semiconductor film in contact with the second oxide semiconductor film (that is, in the vicinity of an interface of an oxide semiconductor film having a smaller band gap). Further, dangling bonds in the first oxide semiconductor film and the second oxide semiconductor film are bonded to each other at the interface therebetween. Accordingly, a decrease in mobility resulting from an electron trap or the like due to dangling bonds can be reduced in the channel region formed in the vicinity of an interface of the first oxide semiconductor film in contact with the second oxide semiconductor film.SELECTED DRAWING: Figure 8

Description

[Technical field]

[0001] The present invention relates to an oxide semiconductor element and a semiconductor device. [Background technology]

[0002] Semiconductor elements such as transistors that use silicon as the semiconductor layer (hereafter referred to as silicon semiconductor These elements are used in various semiconductor devices and are essential for manufacturing semiconductor devices. In order to manufacture large semiconductor devices, a silicon substrate is required. Using materials suitable for large-scale printing, such as glass, a thin-film semiconductor layer that can be formed on a large surface area is produced. The method using recombinant DNA technology has been widely adopted.

[0003] In semiconductor devices using such thin-film silicon, the semiconductor layer is formed at temperatures below the heat-resistant temperature of the substrate. Therefore, amorphous silicon and polysilicon, which can be formed at a relatively low temperature, are used. Recon is widely used.

[0004] Amorphous silicon can be deposited over a large area, and it is relatively inexpensive and easy to process. Since it has the advantage of being able to form semiconductor elements with uniform element characteristics, it is suitable for use in solar cells and other It is widely used in semiconductor devices that require a large area. The drawback is that electron mobility is low because electrons are scattered at the grain boundaries.

[0005] To compensate for this shortcoming, amorphous silicon is irradiated with a laser or other light to locally melt and recrystallize it. Crystallization is achieved by using a catalyst element, etc. Polysilicon is a material that has improved mobility by using silicon. These devices are widely used in semiconductor devices such as liquid crystal displays, which require high-quality displays.

[0006] In addition, in recent years, the advantages of polysilicon, namely high mobility, and the long life of amorphous silicon have been combined. Metals that exhibit semiconducting properties are being considered as new semiconductor layer materials that combine the uniform device characteristics required for semiconductor devices. Oxide semiconductors, which are oxides, have been attracting attention.

[0007] A semiconductor element such as a transistor using an oxide semiconductor in the semiconductor layer (hereinafter, an oxide semiconductor element) Examples of the tin oxide and indium oxide are described in Patent Documents 1 and 2. Thin film transistors using, for example, zinc oxide or tungsten oxide have been proposed.

[0008] Thus, oxide semiconductor elements have many advantages. However, they also have a threshold voltage that is sensitive to light irradiation. This causes a change in the voltage level, which can be said to be a reliability problem. Recently, it has been reported that oxygen vacancies and hydrogen in the oxide semiconductor layer affect the threshold voltage change due to light irradiation. There is some debate as to the impact this has. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2007-123861 A [Patent Document 2] JP 2007-96055 A Summary of the Invention [Problem to be solved by the invention]

[0010] As one method for solving the above-mentioned problem, a method for crystallizing an oxide semiconductor layer by heating the oxide semiconductor layer is known. A crystallized oxide semiconductor layer has a higher degree of metal-oxygen bonding than an amorphous oxide semiconductor layer. The bonds are ordered, and the coordination number of oxygen atoms in the metal atoms is almost constant. Microscopic oxygen deficiencies can be suppressed. In addition, the heat treatment for crystallization reduces the oxide semiconductor Hydrogen is released from the film, and the hydrogen concentration in the film is reduced. This has the effect of reducing the change.

[0011] However, in the crystallized oxide semiconductor layer, many dangling bonds exist on the film surface. When a channel region is formed in a region including a film surface where dangling bonds exist, the dangling bonds This causes a decrease in mobility due to carrier traps and other factors.

[0012] However, it is clear that oxide semiconductor elements will be required to have even higher mobility in the future. It is.

[0013] The present invention has been made under such technical background. A crystalline oxide semiconductor is used for the semiconductor layer, and the threshold voltage changes due to light irradiation. An object of the present invention is to provide an oxide semiconductor element which is free from the above problems and has high mobility.

[0014] Also, a semiconductor device having a high operating speed is manufactured by using the above-mentioned oxide semiconductor element as at least a part thereof. One of the objectives is to provide a body device. [Means for solving the problem]

[0015] In order to solve the above problem, it is necessary to reduce dangling bonds in a region where a channel region is formed. Therefore, in the present invention, it is necessary to stack oxide semiconductor films having crystallinity. This allows the dangling bonds to be bonded together, reducing the number of dangling bonds at the stacking interface. The oxide is deposited such that a channel region is formed in the region containing the reduced interface. The band gap values ​​of the semiconductor films are made to differ from each other. A second oxide semiconductor film is in contact with the first oxide semiconductor film and has a band gap larger than that of the first oxide semiconductor film. A layer having a stacked structure of oxide semiconductor films was used as the oxide semiconductor layer.

[0016] As described above, the band gap between the first oxide semiconductor film and the second oxide semiconductor film is By forming the second oxide semiconductor film having a large surface area in contact with the second oxide semiconductor film, the channel region is The vicinity of the interface of the first oxide semiconductor film in contact with the oxide semiconductor film (i.e., the vicinity of the interface of the first oxide semiconductor film In the present embodiment, the oxide semiconductor film is formed in the vicinity of the interface between the oxide semiconductor film and the insulating film.

[0017] Therefore, the oxide semiconductor film formed in the vicinity of the interface between the first oxide semiconductor film and the second oxide semiconductor film is In the channel region, the decrease in mobility caused by electron traps due to dangling bonds can be reduced. Therefore, the threshold voltage does not change due to light irradiation, and the mobility is high. An oxide semiconductor element can be provided.

[0018] A semiconductor device is manufactured by using at least a part of the oxide semiconductor element having the above characteristics. This makes it possible to provide a semiconductor device with a high operating speed.

[0019] That is, one embodiment of the present invention is a semiconductor device including an oxide semiconductor layer formed on an insulating surface and an oxide semiconductor a gate insulating layer formed over the oxide semiconductor layer, and a region overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween; a gate electrode formed on the oxide semiconductor layer, a pair of source electrodes electrically connected to the oxide semiconductor layer, and The drain electrode is provided, and the oxide semiconductor layer includes a first oxide semiconductor film and a second oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film have a stacked structure of The second oxide semiconductor film is formed between the source electrode and the drain electrode and serves as a gate insulating layer and a The gate electrode is sandwiched between the oxide semiconductor film of 1, and the gap between the source electrode and the drain electrode overlaps with the gate electrode. The band gap value of the first oxide semiconductor film is larger than the band gap value of the second oxide semiconductor film. The oxide semiconductor element is characterized by being smaller.

[0020] According to the above aspect of the present invention, a boundary between the first oxide semiconductor film and the second oxide semiconductor film is The channel region is formed in the area with few dangling bonds near the surface. It is possible to provide an oxide semiconductor element having high mobility without causing a change in the value voltage.

[0021] Another embodiment of the present invention is a gate electrode formed on an insulating surface, a gate insulating layer formed on the oxide semiconductor layer; The oxide semiconductor layer has a pair of a source electrode and a drain electrode which are electrically connected to each other. The first oxide semiconductor film and the second oxide semiconductor film are stacked on each other. The second oxide semiconductor film has crystallinity, and the second oxide semiconductor film is a source electrode and a drain electrode. The gate insulating layer and the first oxide semiconductor film are sandwiched in the gap between the electrodes, and the source electrode and the drain electrode are The gap of the first oxide semiconductor film overlaps with the gate electrode, and the band gap value of the first oxide semiconductor film is larger than that of the second oxide semiconductor film. The oxide semiconductor element is characterized in that the band gap value of the oxide semiconductor film is smaller than that of the oxide semiconductor film. do.

[0022] According to the above aspect of the present invention, a boundary between the first oxide semiconductor film and the second oxide semiconductor film is The channel region is formed in the area with few dangling bonds near the surface. It is possible to provide an oxide semiconductor element having high mobility without causing a change in the value voltage.

[0023] Further, one embodiment of the present invention is a semiconductor device including an oxide semiconductor layer formed such that one surface of the oxide semiconductor layer is in contact with an insulating surface, A pair of low resistance electrodes are formed in contact with the side surfaces of the oxide semiconductor layer and one surface of the low resistance electrodes is in contact with the insulating surface. a pair of low-resistance regions, the pair of low-resistance regions being in contact with the other surface of the oxide semiconductor layer and the other surfaces of the pair of low-resistance regions; a gate insulating layer formed in a region overlapping with the oxide semiconductor layer with the gate insulating layer interposed therebetween; a pair of source and drain electrodes electrically connected to the pair of low resistance regions; the other surface of the oxide semiconductor layer and the other surfaces of the pair of low-resistance regions are flush with each other; The oxide semiconductor layer has a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film. The first oxide semiconductor film and the second oxide semiconductor film have crystallinity. A gate insulating layer and a first oxide semiconductor film are sandwiched between the gate insulating layer and the first oxide semiconductor film. The band gap value is smaller than the band gap value of the second oxide semiconductor film, and the resistivity of the low resistance region is 1× 10 -4 The oxide semiconductor element is characterized by a resistivity of Ω·cm or more and 3 Ω·cm or less.

[0024] According to the above aspect of the present invention, a boundary between the first oxide semiconductor film and the second oxide semiconductor film is The channel region is formed in the area with few dangling bonds near the surface. It is possible to provide an oxide semiconductor element having high mobility without causing a change in the value voltage.

[0025] Furthermore, the source electrode and the drain electrode are in contact with the low resistance region, and the source electrode-channel region The current flows between the drain electrode and the channel region and between the drain electrode and the channel region, and the resistance is lower than that of the oxide semiconductor layer. Since the current flows through a low resistance region, the decrease in the ON current value can be suppressed. It is possible to provide an oxide semiconductor element with a high ratio.

[0026] In one embodiment of the present invention, the band gap value of the second oxide semiconductor film is set to be smaller than that of the first oxide semiconductor film. The band gap value of the oxide semiconductor element is 0.2 eV or more larger than that of the semiconductor film. be.

[0027] According to the above aspect of the present invention, leakage current flowing in areas other than the channel region can be suppressed, The power consumption of the oxide semiconductor element can be reduced.

[0028] Another embodiment of the present invention is a semiconductor device including at least one of the above-described oxide semiconductor elements. The semiconductor device is as follows.

[0029] According to the above aspect of the present invention, a semiconductor device with high operating speed can be provided.

[0030] In the present specification and the like, the phrase "B is formed on A" or "B is formed on A" is used. When explicitly stating that "A is formed on B," this means that B is formed directly on A. The term is not limited to cases where A and B are not in direct contact, i.e., where there is another object between A and B. Here, A and B are objects (e.g., devices, elements, circuits, wiring, etc.). wire, electrode, terminal, film, or layer).

[0031] Thus, for example, if a layer B is explicitly described as being formed on or above a layer A, In the case of a layer B, layer B is formed directly on layer A, and layer B is formed directly on layer A. Another layer (such as layer C or layer D) is formed, and layer B is formed directly on top of it. The case where the other layers (e.g., layers C and D) are single layers is also included. Alternatively, it may be multi-layered.

[0032] In addition, in this specification, terms with numerals such as "first" or "second" are used to distinguish elements. The numbers are used for convenience and are not intended to be limiting. The order of the above is not limited. Effect of the Invention

[0033] According to the present invention, a threshold voltage is generated by irradiating light using a crystalline oxide semiconductor in a semiconductor layer. It is possible to provide an oxide semiconductor element which does not cause a change in pressure and has high mobility.

[0034] Moreover, according to the present invention, a semiconductor device with high operating speed can be provided. [Brief description of the drawings]

[0035] [Figure 1] 1A to 1C illustrate a structure of an oxide semiconductor element described in Embodiment 1. [Diagram 2] 1A to 1C illustrate a method for manufacturing the oxide semiconductor element described in Embodiment 1. [Diagram 3] 1A to 1C illustrate a method for manufacturing the oxide semiconductor element described in Embodiment 1. [Figure 4] 4A to 4C illustrate a method for manufacturing an oxide semiconductor layer described in Embodiment 2. [Diagram 5] 1A to 1C illustrate a method for manufacturing an oxide semiconductor layer described in Embodiment 3. [Figure 6] 1 illustrates a structure of an oxide semiconductor element described in Embodiment 4. [Figure 7] 1A to 1C illustrate a manufacturing method of an oxide semiconductor element described in Embodiment 4. [Figure 8]1 illustrates a structure of an oxide semiconductor element described in Embodiment 5. [Figure 9] 10A to 10C illustrate a manufacturing method of an oxide semiconductor element described in Embodiment 5. [Figure 10] 10A to 10C illustrate a manufacturing method of an oxide semiconductor element described in Embodiment 5. [Figure 11] 13A to 13C illustrate an example of a semiconductor device described in Embodiment 6. [Figure 12] FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0036] The embodiment will be described in detail with reference to the drawings. However, the present invention is not limited to the following description. The present invention is not limited to the above embodiment, and various changes and modifications may be made in the form and details without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the above-mentioned invention can be obtained by the following embodiments. The present invention should not be construed as being limited to the contents described below. The same reference numerals are used in different drawings to indicate the same parts or parts having similar functions. A repeated explanation will be omitted.

[0037] (Embodiment 1) In this embodiment, a manufacturing method of an oxide semiconductor element according to one embodiment of the disclosed invention will be described. The following will be explained with reference to FIG. 1 to FIG.

[0038] <Method for Manufacturing Oxide Semiconductor Element in This Embodiment> FIG. 1 shows a top gate semiconductor device manufactured by the method of the present embodiment. 1A and 1B are diagrams of a transistor 120 having a transistor structure. 1A is a top view and a cross-sectional view of the star 120. Therefore, some of the components (such as the substrate 100) are omitted. The transistor 120 is an n-channel transistor in which the carriers are electrons. However, the manufacturing method is not limited to the n-channel type.

[0039] A method for fabricating the transistor 120 will be described below with reference to FIGS. 2 and 3. .

[0040] First, an insulating layer 102 is formed on a substrate 100, and then a first oxide semiconductor film 104 is formed. (See Figure 2(A)).

[0041] The substrate 100 may be any substrate having an insulating surface, such as an aluminosilicate glass substrate. Uses non-alkali glass substrates such as aluminoborosilicate glass and barium borosilicate glass. These glass substrates are suitable for large areas, and are available in sizes G10 (2850 mm x 3050mm) and G11 sizes (3000mm x 3320mm) are also produced. Therefore, the semiconductor device according to one embodiment of the present invention can be mass-produced at low cost. The substrate 100 may be an insulating substrate made of an insulator such as a quartz substrate or a sapphire substrate, or a silicon substrate. The surface of a semiconductor substrate made of semiconductor materials such as these is covered with an insulating material, and metal, stainless steel, etc. A conductive substrate made of a conductor such as the above and having its surface covered with an insulating material can be used.

[0042] The insulating layer 102 prevents impurities from diffusing from the substrate 100 and is formed by a CVD method or a sputtering method. By using a method such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, an aluminum oxide film, A tantalum oxide film, hafnium oxide film, tantalum oxide film, or the like may be formed on the insulating layer 10. 2 may be either a single-layer structure or a laminated structure. In the case of a laminated structure, the above-mentioned film It may be formed in combination.

[0043] Note that the insulating layer 102 is formed using an oxide insulating film from which part of oxygen is released by heating. As an oxide insulating film from which part of oxygen is released by heating, it is preferable that the oxide insulating film has a stoichiometric ratio of 1:1 or more and a stoichiometric ratio of 1:1 or more. It is preferable to use an oxide insulating film containing more oxygen than oxygen plus oxygen. and an oxide semiconductor film are provided in contact with each other, and heat treatment is performed to convert the oxide insulating film into an oxide semiconductor film. The oxygen desorbed from the insulating layer 102 can be diffused into the conductive film. By diffusing the oxide semiconductor film 104 into the insulating layer 102, the interface state between the insulating layer 102 and the first oxide semiconductor film 104 is reduced. As a result, charges that may be generated due to the operation of the transistor, etc., can be The above-mentioned trapping at the interface between the insulating layer 102 and the first oxide semiconductor film 104 is suppressed. This makes it possible to improve the field effect mobility of the transistor. In addition, the variation and fluctuation of the threshold voltage can be suppressed. The oxide insulating film to be removed may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. Examples of the oxide include gallium oxide, hafnium oxide, and yttrium oxide.

[0044] Here, the term "oxide insulating film from which part of the oxygen is released by heating" refers to a thermal desorption (TDS) insulating film. Desorption Spectroscopy: Thermal Desorption Spectroscopy , the amount of oxygen released in terms of oxygen atoms is 1.0 × 10 18 atoms / cm 3 Above, I like Or 3.0×10 20 atoms / cm 3 It refers to the above.

[0045] The thickness of the insulating layer 102 is not particularly limited, but is, for example, 10 nm or more and 500 nm or less. It is preferable that the thickness of the film is less than 10 nm. Therefore, there is a possibility that an area where the insulating layer 102 is not formed may occur. A thick film thickness is not preferable in terms of film formation time and production costs. It is also possible to have a configuration in which this is not the case.

[0046] The first oxide semiconductor film 104 has a single crystal state, a polycrystalline state (also referred to as polycrystal), or the like. Take a stance.

[0047] The first oxide semiconductor film 104 is preferably a CAAC-OS (C Axis Alig The film is made of ned Crystalline Oxide Semiconductor. .

[0048] The CAAC-OS film is neither completely single crystalline nor completely amorphous. is an oxide semiconductor film with a crystalline-amorphous mixed phase structure having crystalline and amorphous parts in the amorphous phase. The crystal part must be small enough to fit within a cube with one side less than 100 nm. In addition, transmission electron microscopes (TEM) In the observation image by a microscope, the amorphous part and the The boundary between the crystal and the crystalline part is not clear. Therefore, the CAAC-OS film does not have any in-boundary defects. The resulting decrease in electron mobility is suppressed.

[0049] The crystal parts in the CAAC-OS film have c-axes that are normal vectors to the surface on which the CAAC-OS film is formed. The triangle is aligned parallel to the normal vector of the ab plane and perpendicular to the ab plane. The metal atoms are arranged in a layered or hexagonal shape when viewed perpendicular to the c-axis. Metal atoms and oxygen atoms are arranged in layers. The orientation of the a and b axes may be different. In this specification, when it is simply described as vertical, it means that This also includes the range of 5° to 95°.

[0050] In the CAAC-OS film, the distribution of the crystal parts may not be uniform. In the process of forming the C-OS film, when crystal growth is performed from the surface side of the oxide semiconductor film, The proportion of crystalline parts may be higher near the surface than near the growth surface. By adding impurities to the AC-OS film, the crystalline part becomes amorphous in the impurity-added region. It may also be pawned.

[0051] The c-axis of the crystal part in the CAAC-OS film is the normal vector of the surface on which the CAAC-OS film is formed. The CAAC-OS film shape (the shape of the film on which the film is formed) is Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface, the directions may differ from each other. When the deposited CAAC-OS film is processed (for example, when an island-shaped semiconductor layer is formed), In the case of the CAAC-OS film, the direction of the c-axis of the crystal part is the same as that of the CAAC-OS film formed. The direction is the normal vector of the growing surface or parallel to the normal vector of the surface. Alternatively, the film may be subjected to a crystallization treatment such as a heat treatment after the film is formed.

[0052] The electrical characteristics of transistors using CAAC-OS films change when exposed to visible or ultraviolet light. Therefore, the transistor has high reliability.

[0053] The oxide semiconductor used for the first oxide semiconductor film 104 is at least indium (I It is preferable that the alloy contains In and zinc (Zn). It is particularly preferable that the alloy contains In and Zn. In addition, a transistor using the oxide semiconductor can be formed by a starter in order to reduce variations in electrical characteristics of the transistor. It is preferable to have gallium (Ga) as a ballast in addition to the above. It is preferable to have tin (Sn) as a stabilizer. Hafnium (Hf), Zirconium (Zr), Titanium (Ti), Scandium (Sc), It is preferable that one or more elements selected from yttrium (Y) are contained. Other stabilizers include the lanthanides lanthanum (La) and cerium (Ce). , praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu ), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium The compound may have one or more of the following:

[0054] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and oxides of binary metals. In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Oxides, Sn-Mg oxides, In-Mg oxides, In-Ga oxides, ternary metal oxides In-Ga-Zn oxide (also written as IGZO), In-Al-Zn oxide Oxides, In-Sn-Zn oxides, Sn-Ga-Zn oxides, Al-Ga-Zn oxides oxides, Sn-Al-Zn oxides, In-Hf-Zn oxides, In-Zr-Zn oxides In-Ti-Zn oxides, In-Sc-Zn oxides, In-Y-Zn oxides, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, I n-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In -Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide, In- Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn oxide, In-Y b-Zn oxide, In-Lu-Zn ​​oxide, and oxides of quaternary metals In-Sn- Ga-Zn oxide, In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, In-Hf- Al-Zn based oxides can be used.

[0055] Here, the In-Ga-Zn oxide is an oxide having In, Ga, and Zn as the main components. The ratio of In, Ga, and Zn does not matter. Metal elements may also be included.

[0056] In addition, as an oxide semiconductor, InMO3(ZnO) m (m>0 and m is not an integer) In addition, M may be selected from Ga, Fe, Mn, and Co. Indicates one or more metal elements, or the above-mentioned elements as stabilizers In addition, as an oxide semiconductor, In2SnO5(ZnO) n (n>0 and n is an integer) Materials represented by the formula:

[0057] As an example, the composition ratio of the target used is In:Ga:Zn=1:1:1 in atomic ratio. (=1 / 3:1 / 3:1 / 3), In:Ga:Zn=2:2:1(=2 / 5:2 / 5:1 / 5), or the number of atoms is In:Ga:Zn=3:1:2 (=1 / 2:1 / 6:1 / 3). In-Ga-Zn oxides having the same composition or oxides having a similar composition can be used. is In:Sn:Zn=1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn= 2:1:3 (=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5 (=1 In-Sn-Zn oxides with atomic ratios of 4:1 / 8:5 / 8 and oxides with similar compositions It is a good idea to use objects.

[0058] However, oxide semiconductors that contain at least indium (In) or zinc (Zn) Not limited to these, appropriate semiconductor properties (mobility, threshold, variation, etc.) may be selected according to the required semiconductor properties. In order to obtain the required semiconductor characteristics, the carrier concentration and The impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond distance, density, etc. are appropriately adjusted. For example, In-Sn-Zn oxides are relatively easy to form and have high mobility. However, even in In-Ga-Zn oxides, it is necessary to reduce the defect density in the bulk. This can increase the mobility.

[0059] The relative density of the oxide semiconductor in the target is 80% or more, preferably 95% or more, and more preferably The relative density is preferably 99.9% or more. By using an oxide semiconductor target with a high relative density, A denser film is formed.

[0060] The sputtering gas used in the formation of the first oxide semiconductor film 104 contains at least one of nitrogen and phosphorus. In addition to nitrogen and phosphorus, a gas containing one or more rare gases (typically arsenic) may be used. The gas may contain hydrogen, water, oxygen, or a mixture of rare gases and oxygen. Impurities such as hydroxyl groups and hydrides are reduced to concentrations of about ppm (preferably to about ppb). It is preferable to use a high purity gas in which the ions have been removed. In this embodiment, the sputtering gas is Nitrogen is used and is supplied to the sputtering device at a flow rate of 40 sccm to perform film formation.

[0061] By using a gas containing at least one of nitrogen and phosphorus as a sputtering gas, In addition, the first oxide semiconductor film 104 is converted into a semiconductor material containing nitrogen and lithium by a first heat treatment performed in a later step. The band gap value is smaller than that of the case where the sputtering gas does not contain fluorine. For example, as shown in Table 1, the In2O3:Ga2O3:ZnO= A metal oxide target with a molar ratio of 1:1:2 was used, and the oxygen flow rate was set at 40 sccm. The band gap value of the film formed with the nitrogen flow rate of 40 sccm was 3.2 eV. It has been experimentally confirmed that the band gap value of the film formed as above is 1.8 eV. do.

[0062] [Table 1]

[0063] When the first oxide semiconductor film 104 is formed, for example, a treatment chamber is maintained in a reduced pressure state. The substrate is held at a temperature of 100° C. to 600° C., preferably 200° C. to 400° C. Then, the temperature is adjusted to 0.4 °C or lower. Then, the remaining moisture in the processing chamber is removed while hydrogen, water, hydroxyl groups, hydrides, etc. are removed. A high-purity gas from which all impurities have been removed is introduced, and the first oxidation is performed on the metal oxide as the target. The first oxide semiconductor film 104 is formed by heating the substrate 100 at a high temperature. By forming the film 104, the hydrogen concentration in the first oxide semiconductor film 104 is reduced. In addition, by heating the substrate at the above-mentioned temperature during the formation, the first oxide semiconductor The film 104 can be a CAAC-OS film.

[0064] The CAAC-OS film can be formed by the following three methods. The first oxide semiconductor film 104 is formed at a formation temperature of 200° C. or higher and 450° C. or lower. The second method is to form an oxide semiconductor film with a thin thickness (for example, about several nm) and then The third method is to perform heat treatment at a temperature higher than or equal to 200° C. and lower than or equal to 700° C. After forming a thin film (for example, about a few nm), heat treatment is performed at 200°C to 700°C. In the first oxide semiconductor film described in this embodiment, The method for forming the organic semiconductor film 104 corresponds to the second method described above.

[0065] The targets are indium oxide, tin oxide, zinc oxide, and binary metal oxides, such as I n-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, S n-Mg oxide, In-Mg oxide, In-Ga oxide, and oxides of ternary metals. In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, I n-Hf-Zn oxide, In-Zr-Zn oxide, In-La-Zn oxide, In -Ce-Zn oxide, In-Pr-Zn oxide, In-Nd-Zn oxide, In- Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-T b-Zn oxide, In-Dy-Zn oxide, In-Ho-Zn oxide, In-Er -Zn oxide, In-Tm-Zn oxide, In-Yb-Zn oxide, In-Lu- Zn-based oxides, In-Sn-Ga-Zn-based oxides, which are oxides of quaternary metals, In-Hf -Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-Al-Zn oxide targets such as In-Sn-Hf-Zn oxides, In-Hf-Al-Zn oxides, etc. A cot can be used.

[0066] As an example of the target, a metal oxide target containing In, Ga, and Zn is used. The composition ratio is O3:Ga2O3:ZnO=1:1:1 [molar ratio]. In2O A target having a composition ratio of 3:Ga2O3:ZnO=1:1:2 [molar ratio], The target has a composition ratio of In2O3:Ga2O3:ZnO=1:1:4 [molar ratio]. The composition ratio of In2O3:Ga2O3:ZnO=2:1:8 [molar ratio] A target of In2O3:ZnO=25:1 [molar ratio] or more can also be used. A target having a composition ratio of 1:4 can also be used.

[0067] Before the formation of the first oxide semiconductor film 104, moisture remaining in the sputtering apparatus is removed. In order to remove the ions, it is advisable to carry out a preheating process. A method of heating to 200°C or higher and 600°C or a method of introducing nitrogen or inert gas while heating After the preheating process is completed, the substrate or sputtering device is cooled. After cooling, the film is formed without exposing the target to the air. The target coolant in this case is water. It is better to use oils and fats instead of heat. Repeated nitrogen introduction and exhaust without heating has a certain effect. This can be achieved, but it is better if it is done while heating.

[0068] Furthermore, before, during, or after the formation of the first oxide semiconductor film 104, As a method for removing moisture remaining in the sputtering device, a vacuum pump installed in the processing chamber is used. It is preferable to use an adsorption type vacuum pump for the pump. For example, a cryopump or an ion pump A cold pump or a titanium sublimation pump can be used. A trap may be added. The treatment chamber is evacuated using the pump described above, and hydrogen and Since water and the like are removed, the impurity concentration of the first oxide semiconductor film 104 can be reduced.

[0069] The first oxide semiconductor film 104 was formed, for example, by using a sputtering apparatus. A metal oxide having a composition ratio of In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] A nitride target was used, the distance between the target and the substrate was 170 mm, and the pressure was 0.4 Pa. The direct current (DC) power was 0.5 kW, and the atmosphere was a mixture of nitrogen and oxygen (e.g., nitrogen flow The conditions that can be applied are as follows: It is preferable to use the above because it reduces particles and makes the film thickness distribution uniform. The appropriate thickness varies depending on the oxide semiconductor material and the application. It may be appropriately selected depending on the material, application, etc.

[0070] Next, the first oxide semiconductor film 104 is formed and then subjected to a first heat treatment. The oxide semiconductor film 104 is a CAAC-OS film. Impurities such as water (including hydroxyl groups) and hydrogen in the organic semiconductor film 104 can be removed.

[0071] The first heat treatment is performed using nitrogen, a rare gas, oxygen, a mixed gas of nitrogen or a rare gas and oxygen, or a dry The first heat treatment may be performed in an atmosphere selected from air. The temperature of the first heat treatment is 400° C. to 800° C. The heating temperature is preferably 550° C. or higher and 750° C. or lower. The heating time is 1 minute or higher and 24 hours or lower. In this embodiment, the first heat treatment is performed in a nitrogen atmosphere at 700° C. for 1 hour. After the heat treatment is performed, the atmosphere is changed to oxygen atmosphere. By this, oxygen is supplied to the inside of the oxide semiconductor film, and the above-mentioned water, hydrogen, and the like are removed. Since oxygen vacancies due to the oxidation can be compensated for, the first oxide semiconductor film 104 can be made into an i-type or It can essentially be made into an i-type.

[0072] Note that the nitrogen, oxygen, or a dilute gas such as helium, neon, or argon used in the first heat treatment is It is preferable that the gas does not contain impurities such as hydrogen, water, hydroxyl groups, hydrides, etc. is nitrogen, oxygen, or rare gas such as helium, neon, or argon introduced into the heat treatment device. The purity of is 6N (99.9999%) or more, preferably 7N (99.99999%) or more. (i.e., the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less). In addition, the water content is preferably 20 ppm or less in ultra-dry air, and more preferably 1 ppm or less in ultra-dry air. The first heat treatment may be performed in ultra-dry air. Water (including a hydroxyl group), hydrogen, and the like in the oxide semiconductor film 1 can be removed.

[0073] The heat treatment device used in the first heat treatment is not particularly limited, and may be a heat treatment device that uses a heat source such as a resistance heating element. A device for heating the workpiece by thermal conduction or thermal radiation from the heat source can be used. For example, electric furnaces and GRTA (Gas Rapid Thermal Anneal) equipment RTA equipment such as LRTA (Lamp Rapid Thermal Anneal) equipment A Rapid Thermal Anneal (LRTA) device can be used. The lamps are halogen lamps, metal halide lamps, xenon arc lamps, and carbon arc lamps. The light (electromagnetic waves) emitted from lamps such as high-pressure sodium lamps and high-pressure mercury lamps This is a device that heats the workpiece by radiation. The GRTA device uses high-temperature gas for heating. It is a device that performs processing.

[0074] The first oxide semiconductor film 104 formed through the above-described steps has few oxygen vacancies. The CAAC-OS film is obtained by removing hydrogen and water from the film. Although the above description is directed to an example of forming a CAAC-OS film as the compound semiconductor film 104, the present invention is not limited to this. Note that at least the surface of the first oxide semiconductor film 104 (that is, the surface to be treated in a later process) is The thickness direction of the oxide semiconductor film 106 is preferably within 3 nm from the interface with the second oxide semiconductor film 106 formed in the It is preferable that the above range, desirably a range of 5 nm or more, is crystallized.

[0075] Next, the second oxide semiconductor film 106 is formed over the first oxide semiconductor film 104 (FIG. 2). (See (B)).

[0076] The second oxide semiconductor film 106 formed on the first oxide semiconductor film 104 is A material similar to that of the oxide semiconductor film 104 in the first embodiment can be used.

[0077] The second oxide semiconductor film 106 formed here constitutes the first oxide semiconductor film 104. It is preferable to use a film whose composition does not include nitrogen, phosphorus, or nitrogen and phosphorus as elements. As a result, the second oxide semiconductor film 106 is crystallized using the first oxide semiconductor film 104 as a seed crystal. Since this facilitates crystal growth, it is preferable to have lattice constants close to each other (mismatch of 1% or less). or 0.7% or less), effectively reducing the number of dangling bonds at the interface between the two. However, the interface between the first oxide semiconductor film 104 and the second oxide semiconductor film 106 , if they have the same axial orientation and similar lattice constants (mismatch of 1% or less), A material (a target) different from that of the first oxide semiconductor film 104 may be used.

[0078] Note that the second oxide semiconductor film 106 has a band gap value larger than that of the first oxide semiconductor film 104. The band gap value must be at least 0.2 eV larger than the band gap value of the In addition, it is preferable to make the conduction band level of the first oxide semiconductor film 104 larger than that of the second oxide semiconductor film 104. The conduction band level of the second oxide semiconductor film 106 is lower than that of the oxide semiconductor film 106. The band gap value of the oxide semiconductor film 106 is compared with the band gap value of the first oxide semiconductor film 104. By providing a difference between the first oxide semiconductor film 1 and the second oxide semiconductor film 2, as shown in the band diagram of FIG. 06 (that is, the vicinity of the interface of the first oxide semiconductor film 104 with Carriers flow to the oxide semiconductor film (close to the interface of the oxide semiconductor film) (black circle in FIG. 12). The film type of the oxide semiconductor film 106 is determined based on the band gap value of the first oxide semiconductor film 104. , a film having a band gap value larger than 0.2 eV, preferably a film having a band gap value of 0.4e An appropriate selection may be made from films with a V or larger.

[0079] The first oxide semiconductor film 104 is formed of an element other than nitrogen, phosphorus, or both nitrogen and phosphorus. When the film having the above structure is formed as the second oxide semiconductor film 106, the first oxide semiconductor film It is easy to grow crystals using 104 as a seed crystal. In addition, the effective film thickness can be increased. This makes it suitable for use in power devices and other applications. The properties and electrical characteristics are also improved.

[0080] In this embodiment, a target for forming the second oxide semiconductor film 106 by a sputtering method is The composition ratio of In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] is The sputtering method is carried out by depositing a metal oxide target on the substrate 100. The deposition may be performed in a manner similar to that of the first oxide semiconductor film 104, but a rare gas is used. (typically argon), oxygen, or a mixture of noble gases (typically argon) and oxygen The film is formed using gases. Note that impurities such as hydrogen, water, hydroxyl groups, and hydrides are present at concentrations of ppm. It is preferable to use a high-purity gas in which the concentration has been reduced to the order of ppb. In this embodiment, oxygen is used as the sputtering gas at a flow rate of 40 sccm. The deposition was carried out while supplying the gas to the position.

[0081] Similarly to the first oxide semiconductor film 104, the second oxide semiconductor film 106 was The second oxide semiconductor film 106 is subjected to the heat treatment in step 2 so that the second oxide semiconductor film 106 has few oxygen vacancies and is free of water. The CAAC-OS film is made from the catalyst and water removed.

[0082] The second heat treatment is performed at a temperature of 400° C. or higher and 800° C. or lower, using nitrogen, a rare gas, oxygen, nitrogen or A combination of temperature and atmosphere selected from a mixture of rare gas and oxygen, or dry air. The heat treatment is performed under one or more of the following conditions for crystallizing the second oxide semiconductor film. The heating time for the purpose is from 1 minute to 24 hours. When using a heat treatment device such as an electric furnace, The time is preferably 5 hours or more and 20 hours or less, typically 10 hours. When a rapid thermal processing device is used, the time is from 1 minute to 30 minutes, preferably from 1 minute to 10 minutes. Typically, it is 5 minutes.

[0083] Note that in this embodiment, the crystallization and dehydration or dehydrogenation of the second oxide semiconductor film 106 are performed. The first step is to promote the crystallization of the second oxide semiconductor film 106 and to eliminate oxygen deficiency in the crystallized second oxide semiconductor film 106. The second step is to carry out a second heat treatment in two steps to compensate for the loss. The temperature of the step is preferably 550°C or more and 800°C or less, more preferably 600°C or more and 750°C or less. The temperature of the second step is preferably 400° C. or higher and 600° C. or lower, and more preferably 45 A temperature range of 0°C or higher and 550°C or lower is more preferable.

[0084] In the first step, the atmosphere was nitrogen and the sample was heated at 650°C for 6 minutes using an RTA apparatus. In the second step, the material is heated at 450°C for 60 minutes in a mixed gas atmosphere of oxygen and nitrogen. The number of steps is not limited to two, but may be increased by adjusting the conditions as appropriate. For example, the first step conditions and the second step conditions may be repeated. Since high-temperature heat treatment in a nitrogen atmosphere may increase oxygen vacancies, do not use an oxygen-containing atmosphere. It is advisable to finish the heat treatment under conditions using an atmosphere containing oxygen. Alternatively, the oxygen concentration in the atmosphere may be increased with the passage of time during the heat treatment. The gas containing oxygen is used as the atmosphere for the step, and the crystallization, dehydration, and In this case, the second and subsequent steps may be omitted.

[0085] By performing heat treatment at a constant temperature in an oxygen-containing atmosphere, Oxygen deficiency can be efficiently compensated for with oxygen.

[0086] In the second heat treatment, nitrogen, oxygen, helium, neon, argon, etc. It is preferable that the rare gas does not contain water, hydrogen, etc. The purity of nitrogen, oxygen, or rare gas such as helium, neon, or argon is preferably 6N or more. It is preferable to use a pressure of at least 7N. In addition, in ultra-dry air with a water content of 20 ppm or less, More preferably, the second heat treatment may be carried out in ultra-dry air containing 1 ppm or less of water. By such a second heat treatment, oxygen vacancies in the second oxide semiconductor film 106 are filled. Therefore, the second oxide semiconductor film 106 which is i-type or substantially i-type can be obtained. can be formed.

[0087] In addition, the inside of the furnace was kept in a nitrogen atmosphere during the heating of the second heat treatment, and the inside of the furnace was kept in an oxygen atmosphere during the cooling. Alternatively, a method of crystallizing and dehydrating in a nitrogen atmosphere or an oxygen atmosphere may be used. After dehydrogenation, the atmosphere is switched to an oxygen atmosphere to form a second oxide semiconductor. Oxygen can be supplied to the interior of the membrane 106 .

[0088] In this manner, by performing the second heat treatment, the first oxide semiconductor film 104 is used as a seed crystal. As a result, the second oxide semiconductor film 106 formed over the first oxide semiconductor film 104 is crystallized. In addition, the first oxide semiconductor film 104 can be further heated by the second heat treatment. The second oxide semiconductor film 106 can be a crystalline film having orientation. It is not necessary for the entire film to be crystallized. At least the interface with the first oxide semiconductor film 104 is crystallized. The range of 3 nm or more, preferably 5 nm or more, in the thickness direction is crystallized from the It is preferable.

[0089] In addition, the first oxide semiconductor film 104 may have an amorphous region at the interface with the insulating layer 102. In the case of the structure, the second heat treatment is performed to form a surface of the first oxide semiconductor film 104. Crystal growth occurs from the crystalline region formed on the first oxide semiconductor film toward the bottom surface of the first oxide semiconductor film. In some cases, the amorphous region may be crystallized. Depending on the conditions, the amorphous regions may remain.

[0090] The first oxide semiconductor film 104 is formed of an element other than nitrogen, phosphorus, or both nitrogen and phosphorus. When the film having the above structure is formed as the second oxide semiconductor film 106, the first oxide semiconductor film The second oxide semiconductor film 106 formed on the first oxide semiconductor film 104 is a semiconductor film that is formed by bonding the first oxide semiconductor film 104 to the first oxide semiconductor film 104. As a seed for crystal growth, the crystals tend to grow upward toward the surface of the second oxide semiconductor film 106. There is a direction.

[0091] The heat treatment apparatus used for the second heat treatment is set under the same conditions as those for the first heat treatment. This can be done.

[0092] In this manner, the second oxide semiconductor film 106 is formed on and in contact with the first oxide semiconductor film 104. As a result, at the interface between the first oxide semiconductor film 104 and the second oxide semiconductor film 106, In this case, dangling bonds in the first oxide semiconductor film 104 and the second oxide semiconductor film 106 are Furthermore, in this embodiment, the elements constituting the first oxide semiconductor film 104 are bonded to each other. A film having a structure in which nitrogen, phosphorus, or both nitrogen and phosphorus are removed from the above is used as the second oxide semiconductor film 106. By using the first oxide semiconductor film 104 as a seed, the second oxide semiconductor film 105 can be grown using the crystalline region of the first oxide semiconductor film 104 as a seed. The formation of the conductive film 106 facilitates crystal growth, and the dangling bonds at the interface are more efficiently are effectively combined.

[0093] In this embodiment, the first oxide semiconductor film 104 is used as a seed crystal to grow a second oxide semiconductor. The first oxide semiconductor film 104 is not necessarily formed as a seed crystal. There is no need to use it as a

[0094] Next, the first oxide semiconductor is formed by a method such as etching using a photoresist mask. The oxide semiconductor film 104 and the second oxide semiconductor film 106 are processed to form an island-shaped first oxide semiconductor film 10 The oxide semiconductor layer 108 has a stacked structure of the first oxide semiconductor film 4a and the island-shaped second oxide semiconductor film 106a. (See FIG. 2(C)).

[0095] The above etching may be either dry etching or wet etching. Of course, both of these methods can be used in combination. The etching conditions (etching gas and etching The etching conditions (liquid, etching time, temperature, etc.) are set appropriately.

[0096] Etching gases that can be used for dry etching include, for example, chlorine-containing gases ( Chlorine-based gases, such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4 ), carbon tetrachloride (CCl4), etc. In addition, gases that contain fluorine (fluorine-based gases For example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoride Fluoromethane (CHF3), hydrogen bromide (HBr), oxygen (O2), and these gases A gas containing rare gases such as helium (He) or argon (Ar) may be used. stomach.

[0097] In addition, the etching solution that can be used for wet etching is phosphoric acid, acetic acid, and nitric acid. A solution of mixed acid, ammonia peroxide (31% by weight hydrogen peroxide solution: 28% by weight ammonia solution: Water = 5:2:2). In addition, etching such as ITO-07N (Kanto Chemical Co., Ltd.) A liquid may also be used.

[0098] Next, a conductive layer 110 is formed so as to be in contact with the second oxide semiconductor film 106a (FIG. 2(D) )reference).

[0099] The conductive layer 110 is formed by using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The conductive layer 110 can be formed of aluminum, chromium, copper, tantalum, or the like. , titanium, molybdenum, tungsten, or a composite material containing the above elements. The conductive layer 110 can be formed of manganese, magnesium, Materials containing one or more of zirconium and beryllium may also be used. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, steel A material containing one or more elements selected from the group consisting of candium and copper may be used. Other materials for the layer 110 include titanium nitride, tantalum nitride, and other materials with high barrier properties. A material with high barrier properties, such as a titanium nitride film or a tantalum nitride film, may be formed on the second oxide semiconductor. By using the second oxide semiconductor film 106a in the portion in contact with the conductive film 106a, impurities in the second oxide semiconductor film 106a can be prevented. This can suppress the intrusion of foreign matter and the adverse effects on transistor characteristics.

[0100] The conductive layer 110 may be formed using a conductive metal oxide. The materials include indium oxide, tin oxide, zinc oxide, and indium tin oxide (abbreviated as ITO). Indium zinc oxide, or these metal oxide materials with silicon or Alternatively, one containing silicon oxide can be used.

[0101] The conductive layer 110 is a laminate of an aluminum layer on a titanium layer, and a titanium layer on the aluminum layer. It is preferable that the conductive layer 110 has a three-layer laminate structure including an aluminum layer and a tantalum layer. Two-layer laminated structure with a copper layer and a tungsten layer, two-layer laminated structure with a copper layer and a tungsten layer Alternatively, it may have a two-layer structure in which an aluminum layer and a molybdenum layer are laminated. In this embodiment, a single layer structure of a titanium film is used. A single-layer titanium film structure is used to obtain a good taper shape during the subsequent etching. It is possible to achieve etching that forms a shape.

[0102] Next, the conductive layer 110 is selectively etched to form the source electrode layer 110a and the drain electrode layer 110b. The pole layer 110b is formed (see FIG. 2(E)). In this specification, as shown in FIG. 2(E), The electrode formed on the left side is the source electrode layer 110a, and the electrode formed on the right side is the drain electrode layer. Although it is stated as 110b, it is also fine if it is the other way around.

[0103] The photoresist mask used for etching is formed using ultraviolet light, KrF laser light, etc. It is preferable to use ArF laser light. In particular, the exposure with a channel length (L) of less than 25 nm is When performing this, extreme ultraviolet rays with extremely short wavelengths of several nanometers to several tens of nanometers are used. It is preferable to use ultraviolet light for the exposure of the mask. The exposure by this method has high resolution and a large depth of focus. It is also possible to set the channel length (L) to 10 nm or more and 1000 nm (1 μm) or less. By reducing the channel length in this way, the operating speed can be improved. In addition, since the off-state current of the transistor using the oxide semiconductor is extremely small, This can suppress the increase in power consumption due to the

[0104] When the conductive layer 110 is etched, a SiO 2 film is formed so as not to remove the second oxide semiconductor film 106a. The materials and etching conditions are adjusted accordingly. Depending on the conditions, part of the second oxide semiconductor film 106a may be etched in this step. In some cases, the oxide semiconductor layer may have a groove (a recess).

[0105] In addition, on the side surfaces of the first oxide semiconductor film 104a and the second oxide semiconductor film 106a, As a result, the portion in contact with the source electrode layer 110a or the drain electrode layer 110b becomes amorphous. This can sometimes happen.

[0106] Next, the gate insulating layer 112 is formed in contact with the second oxide semiconductor film 106a (FIG. 3(A)). The gate insulating layer 112 is formed by using a plasma CVD method, a sputtering method, or the like. The gate insulating layer 112 can be formed of silicon oxide, silicon oxynitride, silicon nitride oxide, or oxide. It is preferable to form the insulating film using aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer 112 may have either a single layer structure or a stacked structure. In the case of the structure, the layer in contact with the oxide semiconductor is made of the above material, and a silicon nitride film is laminated thereon. The thickness of the gate insulating layer 112 is not particularly limited, but may be, for example, 10 nm or less. The thickness can be set to at most 500 nm, preferably at least 50 nm and at most 200 nm.

[0107] In this embodiment, a silicon oxide film is formed in an oxygen atmosphere by sputtering to form a gate insulating film. When the gate insulating layer 112 is formed, a part of the second oxide semiconductor film 106a is Oxygen can be supplied to the area.

[0108] Also, 1×10 11 / cm 3 Using a high-density plasma device that can achieve a plasma density of Alternatively, a high-quality gate insulating layer 112 that is dense and has a high withstand voltage may be formed.

[0109] After that, a third heat treatment may be performed under an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment in step 3 is 200° C. or higher and 450° C. or lower, preferably 250° C. or higher and 350° C. or lower. For example, heat treatment may be performed at 250° C. for 1 hour in an oxygen-containing atmosphere. By performing the heat treatment, oxygen is supplied to the second oxide semiconductor film 106a, and the second oxide semiconductor film 106a is heated. This makes it possible to compensate for the oxygen deficiency in the conductive film 106a.

[0110] Next, the first oxide semiconductor film 104a and the second oxide semiconductor film 104b are A gate electrode 114 is formed in a region overlapping with the body membrane 106a (see FIG. 3(B)). The gate electrode 114 is formed by forming a conductive layer on the gate insulating layer 112 and then selectively removing the conductive layer. It can be formed by etching.

[0111] The conductive layer is formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. The conductive layer can be formed using aluminum, chromium, copper, tantalum, or the like. , titanium, molybdenum, tungsten, or a composite material containing the above elements. The nitride of the above-mentioned elements, such as titanium nitride, Tantalum nitride may also be used. Manganese, magnesium, zirconium, borium Alternatively, a material containing one or more of the following may be used: Choose from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium. Materials containing one or more of the above elements may also be used.

[0112] Next, a first interlayer insulating layer 116 is formed on the gate insulating layer 112 and the gate electrode 114. The first interlayer insulating layer 116 is formed by using a plasma CVD method or the like. In this embodiment, a nitride insulating layer obtained by a plasma CVD method can be formed. A silicon nitride film, which is one of the films, is used.

[0113] After the first interlayer insulating layer 116 is formed, a fourth heat treatment may be performed. The treatment is carried out in a nitrogen atmosphere at a temperature of 150°C to 450°C, preferably 250°C to 440°C. The fourth heat treatment is not limited to being performed under a nitrogen atmosphere, but may be performed under an oxygen atmosphere or a rare gas atmosphere. The heating may be performed in a dry air atmosphere.

[0114] Through the above steps, a top-gate transistor 12 according to one embodiment of the disclosed invention is obtained. 0 can be formed.

[0115] In addition, a second interlayer insulating layer 118 is further formed on the first interlayer insulating layer 116 and a planarization process is performed. The second interlayer insulating layer 118 may be formed by a method such as PVD or CVD. Silicon oxide, silicon nitride oxide, silicon nitride, hafnium oxide, aluminum oxide, oxide The insulating film is formed using a material containing an inorganic insulating material such as tantalum. The insulating layer material is polyimide, acrylic, benzocyclobutene resin, polyamide, Alternatively, an organic resin such as epoxy may be used. However, one embodiment of the present invention is not limited to this. It may be a single layer or a laminated structure of three or more layers.

[0116] By performing planarization treatment using the second interlayer insulating layer 118, an electrode or a Wiring and the like can be formed suitably.

[0117] The transistor 120 shown in FIG. 1B is provided over the substrate 100 with an insulating layer 102 interposed therebetween. In addition, an oxide semiconductor film having a first oxide semiconductor film 104a and a second oxide semiconductor film 106a is A conductor layer 108, a gate insulating layer 112 formed on the oxide semiconductor layer 108, and a gate insulating A gate electrode 114 is formed in a region overlapping the oxide semiconductor layer 108 via the edge layer 112. A pair of a source electrode layer 110a and a drain electrode layer 110b electrically connected to the oxide semiconductor layer 108 The semiconductor device has a first electrode layer 110b.

[0118] Although not shown, the source electrode layer 110a and the drain electrode layer 110b are The insulating layer 112, the first interlayer insulating layer 116, and the second interlayer insulating layer 118 are partially opened to form The second interlayer insulating layer 11 is connected to the second insulating layer 11 via the conductive wiring layer by using the contact holes formed in the contact holes. 8. The gate electrode 114 may also be electrically connected to the first interlayer insulating film 8. A contact hole is formed by opening a part of the edge layer 116 and the second interlayer insulating layer 118. The wiring layer is electrically connected to the second interlayer insulating layer 118. Good too.

[0119] In addition, in the first oxide semiconductor film 104a and the second oxide semiconductor film 106a, The carrier concentration in a silicon wafer (1×10 14 / cm 3 Compared to the degree Small carrier concentration values ​​(e.g., 1×10 12 / cm 3 Less than 1.0, more preferably 1. 45×10 10 / cm 3 In addition, the drain voltage is in the range of 1V to 10V. At any voltage, the off-state current (source current when the gate-source voltage is set to 0 V or less) The current flowing between the drain and the channel is 10 μm long and the total thickness of the oxide semiconductor layer is 3 In the case of 0 nm, 1×10 -13 A or less, or off-state current density (off-state current The value divided by the channel width of the transistor is 10aA (a (atom) is 10 -18 times) / μ m or less, preferably 1 aA / μm or less, and more preferably 100 zA (z (zepto) is 10 -21 The off-current and drain voltage values ​​are If we know this, we can use Ohm's law to calculate the resistance when the transistor is off (off resistance R). If the cross-sectional area A of the channel formation region and the channel length L are known, the equation ρ=RA / L can be obtained. (R is the off-resistance) and the off-resistance ρ can be calculated. The off-resistance is 1×10 9 Ω m or more (or 1×10 10 Here, the cross-sectional area A is the channel shape. When the thickness of the formed region is d and the channel width is W, A can be calculated as A=dW. .

[0120] In addition, hydrogen contained in the first interlayer insulating layer 116 is removed by heating the first oxide semiconductor film 104. a and the second oxide semiconductor film 106a. , the carrier concentration is 1×10 14 / cm 3 More than 1×10 18 / cm 3 It can be less than.

[0121] The off-state current of an amorphous silicon transistor is 10 -12 A level, whereas acid The off-state current of a transistor using a nitride semiconductor is 1 / 10,000 or less of that of the conventional transistor. Thus, by using high-quality oxide semiconductors with a wide band gap, extremely excellent In this way, the transistor 120 having improved off-state current characteristics can be obtained.

[0122] In addition, a region of the oxide semiconductor layer that becomes a channel region has at least a flat surface. In addition, it is preferable that the first oxide semiconductor film and the second oxide semiconductor film have the same c-axis orientation. The second oxide semiconductor film is a non-single-crystal film having a gate electrode. In the region overlapping with the electrode layer (channel forming region), the thickness is 1 nm or less (preferably 0.2 nm It is preferable that

[0123] In the above-described method for manufacturing a transistor (oxide semiconductor element) having a top gate structure, The source electrode layer 110a and the drain electrode layer 110b are formed by the second oxide semiconductor layer 108. The first oxide semiconductor film 104a is formed in contact with the upper side of the first oxide semiconductor film 106a. It may be formed adjacent to the underside.

[0124] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0125] (Embodiment 2) In this embodiment, a method for forming the oxide semiconductor layer 108 described in Embodiment 1 will be described. This will be explained with reference to FIG.

[0126] <Method for Forming Oxide Semiconductor Layer 108 in This Embodiment> First, an insulating layer 102 is formed on a substrate 100, and then a first oxide semiconductor layer is formed on the insulating layer 102. The conductive film 104 is formed, and at least the first oxide semiconductor film 104 is heated by a first heat treatment. The region including the surface of the substrate is crystallized (see FIG. 4(A)). FIG. 4(A) shows the structure of the substrate according to the first embodiment. The process up to this point is the same as in the first embodiment, so I will skip the explanation here.

[0127] Next, impurity addition treatment 405 is performed on the first oxide semiconductor film 104 (see FIG. 4B). ) and the surface of the first oxide semiconductor film 104 (which will be used for forming the gate insulating layer 112 in a later step). An impurity doped region functioning as the second oxide semiconductor film 106 is formed in the film including the oxide semiconductor film (See FIG. 4(C)). The impurities to be added are oxygen, boron, and aluminum. At least one type may be used.

[0128] The impurity doping process can be performed using an ion doping device or an ion implantation device. A typical example of an ion doping device is a device that uses plasma generated by exciting a process gas. There is a non-mass separation type apparatus in which all ion species are irradiated onto the object to be treated. The ion species in the plasma are irradiated onto the workpiece without being mass-separated. The ion implantation device is a mass separation type device. In the ion implantation device, the ion species in the plasma are separated into Mass separation is performed, and ion species having a specific mass are irradiated onto the object to be processed.

[0129] In this embodiment, the impurity doping process 405 is carried out by using an ion doping apparatus to dope oxygen ( An example in which the first oxide semiconductor film 104 is irradiated with an O) gas will be described.

[0130] When oxygen is used as the source gas, the acceleration voltage is set to 10 kV to 100 kV and the dose is set to 1× 10 15 ions / cm 2 ~1×10 17 ions / cm 2 Impurity addition processing is performed within the range In this case, the second oxide semiconductor film 106 may be formed in the first oxide semiconductor film 104 .

[0131] Through the above steps, the first oxide semiconductor film 104 and the A stacked structure of the first oxide semiconductor film 106 and the second oxide semiconductor film 107 is formed. Since the method can be the same as that of the first embodiment, the explanation will be omitted here.

[0132] (Embodiment 3) In this embodiment, a method for forming the oxide semiconductor layer 108 described in Embodiment 1 will be described. This will be explained with reference to FIG. 5.

[0133] <Method for Forming Oxide Semiconductor Layer 108 in This Embodiment> First, an insulating layer 102 is formed on a substrate 100, and then a second oxide semiconductor is formed on the insulating layer 102. The conductive film 106 is formed, and the second oxide semiconductor film 106 is crystallized by a second heat treatment. (See FIG. 5(A)). Note that the same reference numerals as those in the first embodiment are used for the components. The film forming conditions, materials used, and processing method are the same as those in the first embodiment. Therefore, the description will be omitted here.

[0134] Next, an impurity addition treatment 505 is performed on the second oxide semiconductor film 106 (see FIG. 5B). In the second oxide semiconductor film 106, the back surface (the surface in contact with the insulating layer 102) is provided with the first oxide semiconductor layer 104. An impurity-doped region that functions as the oxide semiconductor film 104 of No. 1 is formed (see FIG. 5C). The impurities to be added may be at least one of nitrogen and phosphorus.

[0135] The impurity doping process can be performed using an ion doping device or an ion implantation device. A typical example of an ion doping device is a device that uses plasma generated by exciting a process gas. There is a non-mass separation type apparatus in which all ion species are irradiated onto the object to be treated. The ion species in the plasma are irradiated onto the workpiece without being mass-separated. The ion implantation device is a mass separation type device. In the ion implantation device, the ion species in the plasma are separated into Mass separation is performed, and ion species having a specific mass are irradiated onto the object to be processed.

[0136] In this embodiment, the impurity doping process 505 is performed by using an ion doping device to dope nitrogen ( An example in which the second oxide semiconductor film 106 is irradiated with N gas will be described.

[0137] When nitrogen is used as the source gas, the acceleration voltage is set to 10 kV to 100 kV and the dose is set to 1× 10 15 ions / cm 2 ~1×10 17 ions / cm 2 Impurity addition processing is performed within the range In this case, the first oxide semiconductor film 104 may be formed in the second oxide semiconductor film 106 .

[0138] In addition, since nitrogen is an inert gas, it is easy to control the gas atmosphere and temperature during ion irradiation. This can improve work efficiency and safety.

[0139] Through the above steps, the first oxide semiconductor film 104 and the second oxide semiconductor film 106 are stacked. The structure is formed. The subsequent steps may be carried out in the same manner as in the first embodiment. Therefore, the description will be omitted here.

[0140] (Embodiment 4) In this embodiment, an oxide semiconductor element and a manufacturing method thereof according to a different embodiment from that of Embodiment 1 will be described. This will be described with reference to FIG. 6 and FIG.

[0141] <Method for Manufacturing Oxide Semiconductor Element in This Embodiment> FIG. 6 shows a bottom gate structure of a semiconductor device fabricated by the method of the present embodiment. 6A and 6B are diagrams of a transistor 420 having a transistor structure. 6A is a top view and a cross-sectional view of the star 420. Therefore, some of the components (such as the substrate 100) are omitted. The transistor 420 is assumed to be an n-channel transistor in which the carriers are electrons. However, the manufacturing method is not limited to the n-channel type.

[0142] A method for fabricating the transistor 420 will be described below with reference to FIG.

[0143] First, an insulating layer 102 is formed on a substrate 100, and a gate electrode 114 is formed on the insulating layer 102. Then, a gate insulating layer 112 is formed on the gate electrode 114, and a source An electrode layer 110a and a drain electrode layer 110b are formed (see FIG. 7A). Regarding the components using the same reference numerals as in the first embodiment, the film forming conditions, materials used and processing methods are as follows: The above is the same as in the first embodiment, so the description will be omitted here.

[0144] Next, the second oxide semiconductor film 106 described in Embodiment 1 was formed over the gate insulating layer 112. After the deposition, a second heat treatment is performed to remove at least the surface of the second oxide semiconductor film 106. After that, the first oxide semiconductor film 104 described in Embodiment 1 is crystallized. After the deposition, a first heat treatment is performed. The oxide semiconductor film 106 is patterned to form an island-shaped first oxide semiconductor film 104a The oxide semiconductor layer 108 having the island-shaped second oxide semiconductor film 106a is formed (FIG. 7(B)). Note that the same reference numerals as those in the first embodiment are used for the components. The conditions, materials used, and processing methods are the same as those in the first embodiment. The explanation will be omitted here.

[0145] Next, a first interlayer insulating layer 116 is formed on the oxide semiconductor layer 108. According to one embodiment, the transistor 420 can be formed in a bottom gate structure. As in the first embodiment, a second interlayer insulating layer 116 is formed in contact with the first interlayer insulating layer 116 for the purpose of planarization. 118 may be formed (see FIG. 7(C)). Note that the same reference numerals as in the first embodiment are used. The film forming conditions, materials used, and processing methods of the components are the same as those in the first embodiment. Therefore, the explanation is omitted here.

[0146] The transistor 420 shown in FIG. 6 is a gate insulating layer 102 disposed on the substrate 100. a gate electrode 114, a gate insulating layer 112 formed on the gate electrode 114, and a gate insulating layer The island-shaped first oxide semiconductor film 104a and the island-shaped second oxide semiconductor film 104b are formed on the insulating film 112. The oxide semiconductor layer 108 having the conductor film 106a and the oxide semiconductor layer 108 are electrically connected The semiconductor device has a pair of source and drain electrode layers 110a and 110b.

[0147] Although not shown, the source electrode layer 110a and the drain electrode layer 110b are the first A contact hole is formed by opening a part of the interlayer insulating layer 116 and the second interlayer insulating layer 118. The wiring layer is electrically connected to the second interlayer insulating layer 118 via a conductive wiring layer. The gate electrode 114 may be formed by interposing the gate insulating layer 112 and the first interlayer insulating layer 11 The contact holes are formed by opening parts of the second interlayer insulating layer 118 and the second interlayer insulating layer 118. The wiring layer may be electrically connected to the second interlayer insulating layer 118 via a conductive wiring layer.

[0148] In addition, in the first oxide semiconductor film 104a and the second oxide semiconductor film 106a, The carrier concentration in a silicon wafer (1×10 14 / cm 3 Compared to the degree Small carrier concentration values ​​(e.g., 1×10 12 / cm 3 Less than 1.0, more preferably 1. 45×10 10 / cm 3 In addition, the drain voltage is in the range of 1V to 10V. At any voltage, the off-state current (source current when the gate-source voltage is set to 0 V or less) The current flowing between the drain and the channel is 10 μm long and the total thickness of the oxide semiconductor layer is 3 In the case of 0 nm, 1×10 -13 A or less, or off-state current density (off-state current The value divided by the channel width of the transistor is 10aA (a (atom) is 10 -18 times) / μ m or less, preferably 1 aA / μm or less, and more preferably 100 zA (z (zepto) is 10 -21 The off-current and drain voltage values ​​are If we know this, we can use Ohm's law to calculate the resistance when the transistor is off (off resistance R). If the cross-sectional area A of the channel formation region and the channel length L are known, the equation ρ=RA / L can be obtained. (R is the off-resistance) and the off-resistance ρ can be calculated. The off-resistance is 1×10 9 Ω m or more (or 1×10 10 Here, the cross-sectional area A is the channel shape. When the thickness of the formed region is d and the channel width is W, A can be calculated as A=dW. .

[0149] In addition, hydrogen contained in the first interlayer insulating layer 116 is removed by heating the first oxide semiconductor film 104. In order to diffuse hydrogen into the oxide semiconductor film 106a and the second oxide semiconductor film 106a, depending on the amount of diffusion of hydrogen, The carrier concentration is 1×10 14 / cm 3 More than 1×10 18 / cm 3 It can be less than.

[0150] The off-state current of an amorphous silicon transistor is 10 -12 A level, whereas acid The off-state current of a transistor using a nitride semiconductor is 1 / 10,000 or less of that of the conventional transistor. Thus, by using high-quality oxide semiconductors with a wide band gap, extremely excellent In this way, the transistor 420 having improved off-state current characteristics can be obtained.

[0151] In the above-described method for manufacturing a bottom-gate transistor (oxide semiconductor element), The source electrode layer 110a and the drain electrode layer 110b are disposed under the second oxide semiconductor film 106a. The first oxide semiconductor film 104a is formed in contact with the upper side of the first oxide semiconductor film 104b. Good too.

[0152] In this embodiment, a patterning step is not performed after the oxide semiconductor layer 108 is formed. Therefore, the oxide semiconductor layer 108 is not easily damaged by etching or the like during pattern formation. There is no impact.

[0153] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0154] (Embodiment 5) In this embodiment, an oxide semiconductor element and a manufacturing method thereof according to a different embodiment from that of Embodiment 1 will be described. This will be described with reference to FIG. 8 to FIG.

[0155] <Method for Manufacturing Oxide Semiconductor Element in This Embodiment> FIG. 8 shows a transistor, which is an example of the configuration of a semiconductor device manufactured by the method of this embodiment. 8A and 8B are top views of transistor 720. In FIG. 8(A), in order to avoid complication, only some of the components are shown. In this embodiment, the transistor 720 is The fabrication method will be described assuming that the carriers are electrons in an n-channel transistor. However, it is not limited to the n-channel type.

[0156] First, an insulating layer 102 is formed on a substrate 100, and then a first oxide semiconductor layer is formed on the insulating layer 102. The conductive film 104 is formed, and at least the first oxide semiconductor film 104 is heated by a first heat treatment. The second oxide semiconductor film is formed on the first oxide semiconductor film 104 by crystallizing a region including the surface of the first oxide semiconductor film 104. The second oxide semiconductor film 106 is crystallized by a second heat treatment. The first oxide semiconductor film 104 and the second oxide semiconductor film 106 are formed using a photoresist mask. The first oxide semiconductor film 104a and the second oxide semiconductor film 104b are formed by etching the first oxide semiconductor film 104a and the second oxide semiconductor film 104b. The oxide semiconductor layer 108 having an island-shaped stacked structure of the second oxide semiconductor film 106a is formed. (See FIG. 9(A)). FIG. 9(A) corresponds to FIG. 2(C) in the first embodiment. The processing in is the same as in the first embodiment, so a description thereof is omitted here.

[0157] Next, the gate insulating layer 112 is formed, and the first oxide semiconductor film A gate electrode 114 is formed in a region overlapping with the oxide semiconductor film 104a and the second oxide semiconductor film 106a. (See FIG. 9(B)). Note that the same reference numerals as those in the first embodiment are used for the components. The film forming conditions, materials used, and processing method are the same as those in the first embodiment. Therefore, the description will be omitted here.

[0158] Next, impurity addition treatment 705 is performed on the region including the oxide semiconductor layer 108. In other words, in a region of the oxide semiconductor layer 108 on which a gate electrode is not formed, Impurities are added through the gate insulating layer 112 to form a low resistance region 707. In the region where the gate electrode is formed on the upper part, the impurity is not added by the gate electrode 114. Since the heat is blocked, the first oxide semiconductor film 704a and the low-resistance region are in contact with the side surfaces of the low-resistance region. An oxide semiconductor layer 708 having a second oxide semiconductor film 706a in contact with the side surface of the region is formed. (See FIG. 9(C)). The impurities to be added are argon (Ar), krypton ( Rare gases such as Kr, xenon (Xe), nitrogen (N), phosphorus (P), arsenic (As), At least one element selected from the 15th group of elements such as Sb (antimony) is used. That's good.

[0159] The impurity doping process can be performed using an ion doping device or an ion implantation device. A typical example of an ion doping device is a device that uses plasma generated by exciting a process gas. There is a non-mass separation type apparatus in which all ion species are irradiated onto the object to be treated. The ion species in the plasma are irradiated onto the workpiece without being mass-separated. The ion implantation device is a mass separation type device. In the ion implantation device, the ion species in the plasma are separated into Mass separation is performed, and ion species having a specific mass are irradiated onto the object to be processed.

[0160] In this embodiment, the impurity doping process is performed by using an ion doping apparatus to dope argon (A r) An example in which a region including a portion where the oxide semiconductor layer 708 is to be formed is irradiated with a gas will be described. do.

[0161] When using argon as the source gas, the acceleration voltage is set to a range of 0.1 kV to 100 kV, and the dose is set to 1×10 14 ions / cm 2 ~1×10 17 ions / cm 2 Irradiate in the range of low resistance The low resistance region 707 has a resistivity of 1×10 -4 Ω cm or more 3Ω cm or less, preferably 1×10 -3 Ω cm or more 3×10 -1 Ω·cm or less is preferable In addition, the first oxide semiconductor film 70 is formed under the gate electrode 114 and in contact with the low resistance region on the side. 4a and a second oxide semiconductor film 706a in contact with the low-resistance region on the side thereof. Layer 708 is formed in a self-aligned manner.

[0162] As described above, the low-resistance region 707 and the oxide semiconductor layer 708 are formed by the impurity addition treatment 705. By performing the above, one film (that is, the first oxide semiconductor film 104a and the second oxide semiconductor film The low resistance region 707 is formed in a self-aligned manner from the laminated film of the conductor film 106a. The interface of the gate insulating layer 112 and the interface of the oxide semiconductor layer 708 and the gate insulating layer 112 are the same. It is flat.

[0163] The lower limit of the resistivity of the low-resistance region 707 is determined by the impurity doping using an ion doping device or the like. This is the practical lower limit of the range that can be formed by material injection, and the lower limit will continue to decrease with advances in equipment technology. In addition, the resistivity of the low resistance region 707 can be set within the upper limit range described above. As a result, the source electrode layer 110a and the drain electrode layer 110b formed in the subsequent process can be formed without any problem. Since the resistance between the source electrode layer 110a and the channel forming region can be suppressed to a low level, The decrease in the ON current value between the drain electrode layer 110b and the channel region and between the drain electrode layer 110b and the channel region is suppressed. Therefore, an oxide semiconductor element with a high ON / OFF ratio can be provided.

[0164] In addition, since argon is an inert gas, it is easy to control the gas atmosphere and temperature during ion irradiation. This makes it easier to carry out the work, and improves work efficiency and safety.

[0165] Next, a low resistance region 707 is formed by a method such as etching using a photoresist mask. An opening 709 is formed in a part of the gate insulating layer 112 formed thereon (see FIG. 9(D)). .

[0166] The above etching may be either dry etching or wet etching. Of course, both of these can be used in combination. The etching conditions (etching gas and etching The etching conditions (liquid, etching time, temperature, etc.) are set appropriately.

[0167] Etching gases that can be used for dry etching include, for example, chlorine-containing gases ( Chlorine-based gases, such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4 ), carbon tetrachloride (CCl4), etc. In addition, gases that contain fluorine (fluorine-based gases For example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoride Fluoromethane (CHF3), hydrogen bromide (HBr), oxygen (O2), and these gases A gas containing rare gases such as helium (He) or argon (Ar) may be used. stomach.

[0168] In addition, the etching solution that can be used for wet etching is phosphoric acid, acetic acid, and nitric acid. A solution of mixed acid, ammonia peroxide (31% by weight hydrogen peroxide solution: 28% by weight ammonia solution: Water = 5:2:2). In addition, etching such as ITO-07N (Kanto Chemical Co., Ltd.) A liquid may also be used.

[0169] Next, a conductive layer is formed and selectively etched to form the source electrode layer 110a and The drain electrode layer 110b is formed (see FIG. 10(A)). A source electrode layer 110a and a drain electrode layer 110b are formed in contact with the gate insulating film 7. In the specification, as shown in FIG. 10A, the electrode formed on the left side is the source electrode layer 110a, and the electrode on the right side is the In the present embodiment, the electrode formed on the first side is the drain electrode layer 110b, but the reverse is also possible. Regarding the components having the same reference numerals as those in the first embodiment, the film forming conditions, materials used, and processing conditions are the same as those in the first embodiment. The manufacturing method and the like are the same as those in the first embodiment. Therefore, the description will be omitted here. do.

[0170] Next, the source electrode layer 110a, the drain electrode layer 110b, the gate insulating layer 112 and the gate A first interlayer insulating layer 116 is formed on the electrode 114. According to one embodiment, a transistor 720 can be formed on the first interlayer insulating layer 116. Furthermore, a second interlayer insulating layer 118 may be formed and planarized (see FIG. 10B). In addition, the same reference numerals as those in the first embodiment are used for the components, and the film forming conditions and materials used are the same as those in the first embodiment. The processing method and the like are the same as those in the first embodiment. Omitted.

[0171] The transistor 720 shown in FIG. 8B is provided over the substrate 100 with an insulating layer 102 interposed therebetween. In addition, an oxide semiconductor film having a first oxide semiconductor film 704a and a second oxide semiconductor film 706a is A conductor layer 708, a low-resistance region 707 formed in contact with a side surface of the oxide semiconductor layer 708, The gate insulating layer 112 formed on the oxide semiconductor layer 708 and the low resistance region 707, A gate electrode 1 is formed in a region overlapping with the oxide semiconductor layer 708 via the insulating layer 112. 14, and a pair of source electrode layer 110a and drain electrode layer 110b electrically connected to the low resistance region 707. The semiconductor device has a first electrode layer 110b.

[0172] Although not shown, the source electrode layer 110a, the drain electrode layer 110b and the gate The electrode 114 is formed by opening a part of the first interlayer insulating layer 116 and the second interlayer insulating layer 118. The second interlayer insulating layer 11 is connected to the second insulating layer 11 via the conductive wiring layer by using the contact holes formed in the contact holes. 8.

[0173] In addition, in the first oxide semiconductor film 104a and the second oxide semiconductor film 106a, The carrier concentration in a silicon wafer (1×10 14 / cm 3 Compared to the degree Small carrier concentration values ​​(e.g., 1×10 12 / cm 3 Less than 1.0, more preferably 1. 45×10 10 / cm 3 In addition, the drain voltage is in the range of 1V to 10V. At any voltage, the off-state current (source current when the gate-source voltage is set to 0 V or less) The current flowing between the drain and the channel is 10 μm long and the total thickness of the oxide semiconductor layer is 3 In the case of 0 nm, 1×10 -13 A or less, or off-state current density (off-state current The value divided by the channel width of the transistor is 10aA (a (atom) is 10 -18 times) / μ m or less, preferably 1 aA / μm or less, and more preferably 100 zA (z (zepto) is 10 -21 The off-current and drain voltage values ​​are If we know this, we can use Ohm's law to calculate the resistance when the transistor is off (off resistance R). If the cross-sectional area A of the channel formation region and the channel length L are known, the equation ρ=RA / L can be obtained. (R is the off-resistance) and the off-resistance ρ can be calculated. The off-resistance is 1×10 9 Ω m or more (or 1×10 10 Here, the cross-sectional area A is the channel shape. When the thickness of the formed region is d and the channel width is W, A can be calculated as A=dW. .

[0174] In addition, hydrogen contained in the first interlayer insulating layer 116 is removed by heating the first oxide semiconductor film 704. In order to diffuse hydrogen into the oxide semiconductor film 706a and the second oxide semiconductor film 706b, the amount of hydrogen that diffuses may be increased. , the carrier concentration is 1×10 14 / cm 3 More than 1×10 18 / cm 3 It can be less than.

[0175] The off-state current of an amorphous silicon transistor is 10 -12 A level, whereas acid The off-state current of a transistor using a nitride semiconductor is 1 / 10,000 or less of that of the conventional transistor. Thus, by using high-quality oxide semiconductors with a wide band gap, extremely excellent In this way, a transistor 720 having improved off-state current characteristics can be obtained.

[0176] Note that in this embodiment, the first oxide semiconductor film 104 and the second oxide semiconductor film 106 The first oxide semiconductor film 104 and the second oxide semiconductor film 106 were made of the same material. The first oxide semiconductor film 104 and the second oxide semiconductor film 105 may be made of different materials. If the material in 06 is different (so-called heteroepitaxial growth), For example, the first oxide semiconductor film 104 may be made of a binary metal oxide, such as In-Zn-O. The second oxide semiconductor film 106 is made of a ternary metal oxide, In-Ga-Zn-O. Composition etc. can be adopted.

[0177] In addition, a portion of the oxide semiconductor layer that becomes a channel region has at least a flat surface. Note that the height difference of the surface of the second oxide semiconductor film is preferably such that the second oxide semiconductor film overlaps with the gate electrode layer. In the region where the insulating film is formed (channel forming region), the thickness is 1 nm or less (preferably 0.2 nm or less). It is preferable.

[0178] By using this embodiment, the first oxide semiconductor film in contact with the second oxide semiconductor film 706a can be formed. A channel region is formed in a region with few dangling bonds near the interface of the semiconductor film 704a. Therefore, the threshold voltage does not change due to light irradiation, and the oxide semiconductor has high mobility. The body element can be provided.

[0179] In addition, in this embodiment, the source electrode layer 110a, the drain electrode layer 110b and the channel Since the resistance between the source electrode layer 110a and the channel formation region can be kept low, Suppresses the decrease in the ON current value between the drain electrode layer 110b and the channel region and between the drain electrode layer 110b and the channel region. Therefore, an oxide semiconductor element with a high ON / OFF ratio can be provided.

[0180] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0181] (Embodiment 6) The oxide semiconductor element disclosed in this specification can be applied to various electronic devices (including gaming machines). Examples of electronic devices include television sets, computers, etc. Monitors, digital cameras, digital video cameras and other cameras, digital photo frames, Mobile phones (also called mobile phones or mobile phone devices), portable game machines, portable information terminals, audio Examples of the devices include playback devices, large game machines such as pachinko machines, etc. An example of an electronic device including an oxide semiconductor element will be described with reference to FIG.

[0182] FIG. 11A shows a portable information terminal, which includes a housing 1001, a housing 1002, a first display unit, and a The first display unit 1003a, the second display unit 1003b, etc. The first display unit 1003a and the second display unit 1003b are panels having a touch input function. For example, as shown in the left diagram of FIG. 11(A), the selection button 100 displayed on the first display unit 1003a 4 allows you to select the input method. The selection buttons can be displayed in various sizes, making them suitable for a wide range of users. For example, if you select "Keyboard input", As shown in the right diagram of FIG. 11(A), a keyboard 1005 is displayed on the first display unit 1003a. This allows for quick text input using keys, just like with conventional information terminals. become.

[0183] In addition, the portable information terminal shown in FIG. 11(A) has a first table as shown in the right diagram of FIG. A housing 1001 having a first display unit 1003a and a housing 1002 having a second display unit 1003b. Therefore, only the housing 1001 or only the housing 100 can be separated as required. Only 2 can be removed and used as a lighter, portable information terminal.

[0184] The portable information terminal shown in FIG. 11(A) displays various information (still images, videos, text images, etc.). ), calendar, date or time display function, The ability to manipulate or edit the information displayed, and to process it using various software (programs) In addition, the rear and side of the housing can have external connection terminals ( It may also be configured to include an earphone jack, a USB terminal, a recording medium insertion portion, etc.

[0185] The portable information terminal shown in FIG. 11(A) can also be configured to transmit and receive information wirelessly. You can wirelessly purchase and download the desired book data from the electronic book server. It is also possible to configure it in this way.

[0186] Furthermore, the housing 1002 shown in FIG. 11A is provided with an antenna, a microphone function, and a wireless function. It may also be used as a mobile phone.

[0187] Fig. 11(B) shows one embodiment of an image display device. The display unit 1101 has a touch input function. The display unit 1101 is connected to the window glass. An image display device manufactured using the oxide semiconductor element disclosed in this specification The visible light transmission must be sufficient to allow the exterior view to be visible (e.g., 50% or more visible light transmission). For example, as shown in the left diagram of FIG. 11(B), the display unit 1101 functions as a window glass in a normal state, but when you touch the surface of the display unit 1101, As a result, necessary information can be displayed on the display unit 1101 as shown in the right diagram of FIG. 11(B). can be done.

[0188] In addition, a mechanism for wirelessly transmitting and receiving information may be provided in part of the display unit 1101. For example, A piezoelectric vibrator 1102 is installed in a part of the display unit 1101, and a wireless The mechanism transmits a sound signal to the piezoelectric transducer 1102, and the piezoelectric transducer 1102 is equipped with a wireless By receiving a sound signal by the mechanism, the display unit 1101 is vibrated to a stable level. The sound can be radiated evenly around the room.

[0189] FIG. 11(C) shows one form of a goggle-type display (head-mounted display). The goggle-type display shown in FIG. 11C has a left-eye lens attached to a main body 1201 of the glasses. A panel 1202a for the right eye, a panel 1202b for the right eye, and an image display button 1203 are provided. The left-eye panel 1202a and the left-eye panel 1202b are manufactured using the oxide semiconductor element disclosed in this specification. The right-eye panel 1202b has sufficient visible light transmittance (e.g. For example, the visible light transmittance is 50% or more. Thus, the user can see the surrounding scenery in the same way as with normal glasses. When the user wishes to obtain necessary information, the image display button 1203 is pressed, and the As shown in the figure, an image is displayed on one or both of the left-eye panel 1202a and the right-eye panel 1202b. It will be displayed.

[0190] As described above, the configurations, methods, etc. described in this embodiment may be used in conjunction with the configurations, methods, etc. described in other embodiments. They can be used in any suitable combination. [Explanation of symbols]

[0191] 100 Substrates 102 Insulating layer 104 First oxide semiconductor film 104a First oxide semiconductor film 106 Second oxide semiconductor film 106a Second oxide semiconductor film 108 Oxide semiconductor layer 110 Conductive layer 110a source electrode layer 110b Drain electrode layer 112 Gate insulating layer 114 Gate electrode 116 First interlayer insulating layer 118 Second interlayer insulating layer 120 Transistor 405 Impurity Addition Processing 505 Impurity Addition Processing 420 Transistor 704a First oxide semiconductor film 706a Second oxide semiconductor film 705 Impurity Addition Processing 707 Low resistance region 708 Oxide semiconductor layer 709 Opening 720 Transistor 1001 Case 1002 Case 1003a First display unit 1003b Second display unit 1004 Selection button 1005 Keyboard 1101 Display section 1102 Piezoelectric vibrator 1201 Glasses body 1202a Left eye panel 1202b Right eye panel 1203 Image display button

Claims

[Claim 1] an oxide semiconductor layer on an insulating surface; a gate insulating layer on the oxide semiconductor layer; a gate electrode overlapping the oxide semiconductor layer with the gate insulating layer interposed therebetween; a pair of source and drain electrodes electrically connected to the oxide semiconductor layer; the oxide semiconductor layer has a stacked structure of a first oxide semiconductor film and a second oxide semiconductor film, the first oxide semiconductor film and the second oxide semiconductor film have crystallinity; a gap between the source electrode and the drain electrode overlapping the gate electrode; the second oxide semiconductor film is sandwiched between the gate insulating layer and the first oxide semiconductor film in a gap between the source electrode and the drain electrode; an oxide semiconductor element, wherein a band gap value of the first oxide semiconductor film is smaller than a band gap value of the second oxide semiconductor film.

Images