Chip, manufacturing method thereof, and semiconductor package including chip

Abstract

To provide a chip and a manufacturing method thereof, and a semiconductor package in which a platform is covered with a molding layer having the chip, and the chip is caught like a hook to make it difficult to separate from the molding layer.SOLUTION: In a semiconductor package, a chip 210 has a top surface 241, a number of side surfaces 213, a bottom surface 242 connected to the plurality of side surfaces, a circuit layer 216 formed on the bottom surface, and a platform 250 surrounding the top surface and parallel to the top surface and the bottom surface, and the distance from the platform to the bottom surface is smaller than the distance from the top surface to the bottom surface, and the platform is vertically connected to the plurality of side surfaces.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a chip, a manufacturing method thereof, and a semiconductor package having the chip, and in particular to a chip capable of preventing separation from a molding layer, a manufacturing method thereof, and a semiconductor package having the chip. [Background technology]

[0002] 1, a conventional semiconductor package manufactured by flip chip technology includes a chip 110 disposed on a substrate 120. A circuit layer 116 is provided on the front side of the chip 110, which is electrically connected to the substrate 120 using a number of metal bumps 130. A molding layer 140 is further formed on the substrate 120, which covers a number of side surfaces of the chip 110 but does not cover the top surface of the chip 110.

[0003] A heat sink (not shown) may be provided on the top of the semiconductor package to help dissipate heat from the chip 110. However, since the top of the chip 110 is not covered with the molding layer 140, the side of the chip 110 is likely to peel off from the molding layer 140 due to the difference in thermal expansion coefficient between the chip 110 and the molding layer 140. Summary of the Invention [Problem to be solved by the invention]

[0004] In view of the above, in order to solve the above problems, the present invention provides a chip, a manufacturing method thereof, and a semiconductor package having the chip. [Means for solving the problem]

[0005] In order to achieve the above-mentioned object, the chip of the present invention comprises a top surface, a plurality of side surfaces, a bottom surface connected to the plurality of side surfaces, a circuit layer formed on the bottom surface, and a platform surrounding the top surface and parallel to the top surface and the bottom surface, wherein the distance from the platform to the bottom surface is smaller than the distance from the top surface to the bottom surface, and the platform is connected perpendicularly to the plurality of side surfaces.

[0006] The semiconductor package of the present invention comprises a substrate, the above-mentioned chip provided on the substrate, a plurality of bumps disposed between the substrate and the bottom surface of the chip and electrically connected to the circuit layer of the chip, and a molding layer formed on the substrate and covering the plurality of side surfaces and the platform of the chip, the molding layer being exposed on the top surface of the chip.

[0007] The method of manufacturing a chip of the present invention includes the steps of: providing a wafer having a front surface and a back surface opposite to the front surface, the front surface having a circuit layer; polishing the back surface of the wafer with a polishing wheel to thin the wafer to a predetermined thickness; forming a plurality of grooves on the back surface of the wafer; and cutting the wafer from the front surface of the wafer using a cutter to the positions of the plurality of grooves. Includes. Effect of the Invention

[0008] In the semiconductor package of the present invention, the platform is covered with a molding layer, and the chip is hooked like a hook, making it difficult to separate from the molding layer. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is an explanatory diagram of a conventional semiconductor package. [Diagram 2] FIG. 2 is an explanatory diagram of a semiconductor package according to the present invention. [Diagram 3] 3A to 3C are diagrams illustrating a method for manufacturing the chip illustrated in FIG. 2. [Figure 4] 3A to 3C are diagrams illustrating a method for manufacturing the chip illustrated in FIG. 2. [Diagram 5] 3A to 3C are diagrams illustrating a method for manufacturing the chip illustrated in FIG. 2. [Figure 6] 3A to 3C are diagrams illustrating a method for manufacturing the chip illustrated in FIG. 2. [Figure 7] 3A to 3C are diagrams illustrating a method for manufacturing the chip illustrated in FIG. 2. [Figure 8] 3A to 3C are diagrams illustrating a method for manufacturing the chip illustrated in FIG. 2. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In order to make the above and other objects, features and advantages of the present invention clearer, the present invention will be described in detail below with reference to the accompanying drawings.

[0011] Aspects of the present disclosure are best understood by reading the following detailed description in conjunction with the accompanying drawings, in which: It should be noted that, in accordance with standard industry practice, various components have not been drawn to scale, and in fact, dimensions of various components may be arbitrarily increased or decreased for clarity of illustration.

[0012] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. To simplify the present disclosure, specific examples of members and configurations are described below. Of course, these members and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first member above or on a second member can include an embodiment in which the first member and the second member are formed in direct contact with each other, and can also include an embodiment in which an additional member is formed between the first member and the first member and the second member are not in direct contact with each other. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for simplicity and clarity, and does not in itself indicate a relationship between the various embodiments and / or configurations being discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "lower," "bottom," "over," "top," etc. may be used in the text to describe the relationship of one member or component shown in the figures to another member or components. The spatially relative terms are intended to cover different orientations of the device during use or operation other than the orientation shown in the figures. The device may be oriented in other ways (rotated 90 degrees or at other orientations) and the spatially relative descriptions used in the text should be interpreted accordingly.

[0014] In the present invention, the sign ">" means greater than, the sign "<" means less than, the sign "≧" means greater than or equal to, and the sign "≦" means less than or equal to.

[0015] Referring to FIG. 2, the semiconductor package of the present invention includes a chip 210 disposed on a substrate 220 and electrically connected to a plurality of metal bumps 230 and the substrate 220 .

[0016] In detail, the chip 210 has opposing top surface 211, bottom surface 212, and a number of side surfaces 213. The bottom surface 212 is an active surface on which a circuit layer 216 is disposed. The top surface 211 and the bottom surface 212 are located on different planes. The bottom surface 212 is perpendicularly connected to the side surfaces 213. The circuit layer 216 of the chip 210 is electrically connected to the substrate 220 using the metal bumps 230.

[0017] Also, a platform 250 is formed on the chip 210 and disposed around the top surface 211. The platform 250 is substantially flat and parallel to the top surface 211 and the bottom surface 212. A distance from the platform 250 to the bottom surface 212 is smaller than a distance from the top surface 211 to the bottom surface 212, i.e., the platform 250 is lower than the top surface 211. Thus, a gap is formed between the top surface 211 and the platform 250. An outer periphery 253 of the platform 250 is connected to the side surface 213. The platform 250 is connected perpendicularly to the side surface 213.

[0018] A molding layer 240 is formed on the substrate 220, and is made of a sealant material such as, but not limited to, an epoxy resin material. The molding layer 240 has opposing top and bottom surfaces 241 and 242, and the bottom surface 242 contacts the substrate 220. The molding layer 240 covers the side surface 213 and the platform 250 of the chip 210, and is not formed on the top surface 211 of the chip 210. The molding layer 240 exposes the top surface 211 of the chip 210. The top surface 241 of the molding layer 240 is connected to the top surface 211 of the chip 210 and is flush with the top surface 211 of the chip 210.

[0019] The semiconductor package of the present invention further includes a heat sink 260 attached to the top surface 211 of the chip 210. The heat sink 260 may be made of copper or other thermally conductive material and assists in dissipating heat from the chip 210. In addition, a plurality of solder balls 270 are provided on a bottom surface of the substrate 220, and the solder balls 270 are electrically connected to the substrate 220. The chip 210 may be electrically connected to an external circuit via the substrate 220 using the solder balls 270.

[0020] According to the semiconductor package of the present invention, if the distance from the top surface 211 of the chip 210 to the platform 250, i.e., the depth of the platform 250, is defined as d, and the distance from the top surface 211 to the bottom surface 212 of the chip 210, i.e., the thickness of the chip 210, is defined as D, then D and d have the following relationship: 1 / 2 <d / D<2 / 3

[0021] According to the semiconductor package of the present invention, the molding layer covers the platform and catches the chip like a hook, making it difficult to separate the chip from the molding layer.

[0022] Figures 3 to 8 show a method for manufacturing the chip 210 of Figure 2. First, as shown in Figure 3, an unprocessed wafer 310 is provided, and the wafer 310 has a front surface 312 and a back surface 311 opposite to the front surface 312. In addition, the front surface 312 of the wafer 310 has a circuit layer 316.

[0023] A protective film 360 is then attached to the surface 312 of the wafer 310 to protect the circuit layer 316 from damage, as shown in FIG.

[0024] Next, as shown in Fig. 5, the protective film 360 on the wafer 310 is held by a holding surface (not shown) of a work table, and the back surface 311 of the wafer 310 is ground by a polishing roller 391 to thin the wafer 310 to a predetermined thickness. Fig. 6 shows that the wafer 310 has a thickness D after polishing.

[0025] Then, as shown in FIG. 7, a cutter or a laser beam is used to form a plurality of grooves 370 on the back surface 311 of the wafer 310, and the depth of the plurality of grooves 370 is d and the width of the plurality of grooves 370 is W1.

[0026] In one embodiment, the thickness D of the wafer 310 and the depth d of the plurality of grooves 370 have the following relationship: 1 / 2 <d / D<2 / 3

[0027] In another embodiment of the present invention, the grooves 370 may be formed in the backside 311 of the wafer 310 first, and then the wafer 310 may be thinned.

[0028] 8, the protective film 360 attached to the front surface 312 of the wafer 310 is removed. Then, a cutter 392 having a thickness W2 is used to cut the wafer 310 from the front surface 312 of the wafer 310 to the positions of the grooves 370. The wafer 310 is then separated to obtain the chips 210 shown in FIG.

[0029] In one embodiment, the width W1 of the groove 370 and the thickness W2 of the cutter have the following relationship: 1 / 2 <W2 / W1<1

[0030] The chip 210 obtained above can be placed on a substrate 220 using flip-chip technology and electrically connected to the substrate 220 using a number of metal bumps 230. Then, a molding layer 240 can be formed on the substrate 220, a number of solder balls 270 can be formed on the bottom surface of the substrate 220, and a heat sink 260 can be attached to the top surface 211 of the chip 210 to obtain the semiconductor package shown in FIG.

[0031] Although the present invention has been disclosed in the above embodiments, the present invention is not limited thereto, and those skilled in the art can make various changes and modifications without departing from the spirit of the present invention. Therefore, the scope of protection of the present invention is subject to the scope of the following claims. [Explanation of symbols]

[0032] 110 Chips 116 circuit layer 120 Substrate 130 Bump 140 Molding layer 210 Chips 211 Top surface 212 Bottom 213 Side 216 circuit layer 220 Substrate 230 Bump 240 Molding layer 241 Top surface 242 Bottom 250 Platform 253 Outer rim 260 Heatsink 270 Solder Balls 310 Wafer 311 Back side 312 Surface 316 circuit layer 360 Protective film 370 Groove 391 Polishing Roller 392 Cutter d Depth D Thickness W1 width W2 Thickness

Claims

1. The top surface and With multiple aspects, A bottom surface connected to the plurality of side surfaces; a circuit layer formed on the bottom surface; a platform surrounding the top surface and parallel to the top surface and the bottom surface; Equipped with A chip, wherein a distance from the platform to the bottom surface is smaller than a distance from the top surface to the bottom surface, and the platform is vertically connected to the multiple side surfaces.

2. 2. The chip according to claim 1, wherein the distance from the top surface to the platform is defined as d, and the distance from the top surface to the bottom surface is defined as D, where D and d have a relationship of 1 / 2<d / D<2 / 3.

3. A substrate; The chip according to claim 1 or 2 provided on the substrate; a plurality of bumps disposed between the substrate and the bottom surface of the chip and electrically connected to the circuit layer of the chip; a molding layer formed on the substrate and covering the side surfaces and the platform of the chip; Equipped with The molding layer is exposed on the top surface of the chip.

4. The semiconductor package of claim 3 , wherein a top surface of the molding layer is flush with the top surface of the chip.

5. 5. The semiconductor package according to claim 3, further comprising a heat dissipation sheet attached to the top surface of the chip.

6. providing a wafer having a front surface and an opposing back surface, the front surface having a circuit layer thereon; grinding the backside of the wafer with a grinding wheel to thin the wafer to a predetermined thickness; forming a plurality of grooves on the back surface of the wafer; cutting the wafer from the surface of the wafer using a cutter to the location of the plurality of grooves; A method for manufacturing a chip comprising:

7. 7. The method for manufacturing a chip according to claim 6, wherein the thickness of the wafer after thinning is defined as D and the depth of the groove is defined as d, where D and d have a relationship of 1 / 2<d / D<2 / 3.

8. 7. The method for manufacturing a tip according to claim 6, wherein the width of the groove is defined as W1 and the thickness of the cutter is defined as W2, where W1 and W2 have a relationship of 1 / 2<W2 / W1<1.

9. 7. The method for manufacturing a chip according to claim 6, wherein the wafer is thinned after the plurality of grooves are formed on the rear surface of the wafer.

10. applying a protective film to the surface of the wafer prior to polishing the wafer; removing the protective film attached to the surface of the wafer after polishing the wafer; The method of claim 6 further comprising:

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