Semiconductor device structure having efficient heat removal structure across chip, and monolithic manufacturing method for the same

Abstract

To provide a transistor structure including a heat removal structure such as a highly heat-conductive column or a plate within a semiconductor substrate, for improving dissipation of heat generated from a transistor, and a circuit thereof.SOLUTION: A cool transistor comprises: a semiconductor substrate having an initial semiconductor surface; a circuit element which is positioned within a semiconductor body area of the semiconductor substrate; and a vertical heat dissipation column which is provided within the semiconductor substrate and which surrounds the semiconductor body area. The vertical heat release column includes a heat release material higher in heat conductivity than the semiconductor substrate or oxide silicon.SELECTED DRAWING: Figure 11

Description

Detailed Description of the Invention

[0001] BACKGROUND OF THEINVENTION 1. FIELD OF THEINVENTION The present invention relates to semiconductor device structures, and in particular to transistor structures and circuits thereof that include heat removal structures (such as highly thermally conductive columns and / or plates in a semiconductor substrate) to improve the dissipation of heat generated by the transistors.

[0002] 2. Description of the Prior Art The monolithic integration capability of silicon chips has grown from GSI (gigascale integration: integrating billions of transistors on a die) to TSI (terascale integration: integrating trillions of transistors on a die), and the performance of chips has improved significantly. Accordingly, the power consumed to operate such a huge number of transistors has increased sharply, and due to the current limited heat dissipation capability (e.g., the thermal conductivity of silicon dioxide is very low (1.3 to 1.5 W / m×K), and the thermal conductivity of silicon itself is not very high (~148 W / m×K)), it increases the junction temperature of the transistors and thus the temperature of the entire chip. This material and device structural problem causes a negative circular effect. That is, the higher die temperature reduces the speed of the transistors, which inevitably forces the design to increase the power to the circuit to promote the performance of the transistors, but this mechanism increases the die temperature so much that the heat dissipation problem is aggravated. In fact, this problem of insufficient heat dissipation, which causes chip operating temperatures to rise, is the worst problem the entire chip industry needs to solve in order to avoid a major roadblock to integrating more devices on a die.

[0003] However, progress in reducing the temperature of GSI chips has not improved at present. In fact, as the technology node is further scaled down, the dimensions of the transistors are forced to become smaller (e.g., the minimum feature size is scaled down from 7nm to 5nm and then to 3nm), the coverage of the oxide layer relative to the total size of the transistor becomes higher, and the heat dissipation capability of the entire device junction becomes more concentrated. Many heat dissipation methods have been created, such as covering the entire chip with high heat removal pads outside the chip or circulating liquid cooling outside the packaged chip, but both are very expensive and less efficient in effectively reducing the junction temperature of the transistors. Summary of the Invention

[0004] The present invention focuses on forming heat removal (HHR) structures in particular in the monolithic process of manufacturing transistors. Such HHR structures are such that they are connected across the entire die as a single component of a heat sink designed to maximize the heat dissipation area. Furthermore, the HHR structures can be connected across the entire edge of the die, making it easier to connect to several heating pads or thermal vias, forming a larger heat dissipation path from the die to the environment outside the die and thus to the packaged chip.

[0005] This new HHR structure is believed to be the closest route to achieving a highly effective heat sink function directly associated with each individual transistor, and furthermore, all these HHR structures are directly connected to the whole die as a component of an optimized "heat sink" built either within the die (named HSiD: Heat Sink in Die) or within the substrate. Thus, the present invention provides a disclosure on how to build transistors with associated HHR structures using well-known monolithic integration processes, and how the die itself can have an internal HSiD integrated to create an effective heat dissipation path within the chip.

[0006] An embodiment of the present invention provides a device structure that includes heat removal structures (such as high thermal conductivity columns and / or plates in a semiconductor substrate) for improving heat dissipation. The device structure includes a semiconductor substrate having an initial semiconductor surface, circuit elements located in a semiconductor body region of the semiconductor substrate, and vertical heat dissipation columns in the semiconductor substrate and surrounding the semiconductor body region. The vertical heat dissipation columns include a heat dissipation material having a thermal conductivity higher than the thermal conductivity of the semiconductor substrate or silicon oxide.

[0007] According to one aspect of the invention, the semiconductor substrate has an edge region away from the circuit elements, and the vertical heat dissipation columns extend from a position close to or adjacent to the circuit elements to a position near the edge region of the semiconductor substrate.

[0008] According to one aspect of the present invention, the heat dissipation material is BN, AlN, or a metal.

[0009] According to one aspect of the invention, the vertical heat dissipation columns include a layer of the heat dissipation material and a thermally conductive column overlying the layer of the heat dissipation material.

[0010] According to one aspect of the invention, the thermally conductive columns comprise a metal.

[0011] According to one aspect of the invention, the semiconductor substrate has an edge region remote from the circuit elements, and the layer of heat dissipation material extends from a position close or adjacent to the circuit elements to a position proximate the edge region of the semiconductor substrate.

[0012] According to one aspect of the invention, the vertical heat dissipation columns include a layer of heat dissipation material and insulating columns covering the thin layer of heat dissipation material.

[0013] According to one aspect of the invention, the insulating columns comprise silicon oxide.

[0014] According to one aspect of the invention, the semiconductor substrate has an edge region that is remote from the circuit elements, and the layer of heat dissipation material extends from a location close to or adjacent to the circuit elements to another location near the edge region of the semiconductor substrate.

[0015] According to one aspect of the invention, the device structure further comprises a shallow trench isolation (STI) region surrounding the semiconductor body region, the vertical heat dissipation column being within the STI region.

[0016] According to one aspect of the invention, the circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor.

[0017] Another embodiment of the present invention provides a semiconductor device structure comprising: a semiconductor substrate having an initial semiconductor surface, a first transistor located in a first semiconductor body region of the semiconductor substrate, a second transistor located in a second semiconductor body region of the semiconductor substrate, the second transistor being spaced apart from but not adjacent to the first transistor, and a vertical heat dissipation column in the semiconductor substrate, the vertical heat dissipation column including a heat dissipation material having a thermal conductivity greater than a thermal conductivity of the semiconductor substrate or a thermal conductivity of silicon oxide, the vertical heat dissipation column extending from the first semiconductor body region to the second semiconductor body region.

[0018] According to one aspect of the invention, the semiconductor substrate has an edge region remote from the first transistor and the second transistor, and the vertical heat dissipation column further extends to a position proximate to the edge region of the semiconductor substrate.

[0019] According to one aspect of the invention, the device structure includes a first horizontal heat dissipation plate underlying the first transistor and a second horizontal heat dissipation plate underlying the second transistor, the vertical heat dissipation column is connected or thermally coupled to both the first and second horizontal heat dissipation plates, and the first and / or second horizontal heat dissipation plates further include another heat dissipation material having a different thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.

[0020] According to one embodiment of the invention, the heat dissipation material and / or the further heat dissipation material is BN, AlN or a metal.

[0021] According to one aspect of the present invention, the first horizontal heat dissipation plate is connected or thermally coupled to the bottom surface of the drain region and the source region of the first transistor and the first horizontal heat dissipation plate is connected to the vertical heat dissipation column, the second horizontal heat dissipation plate is connected or thermally coupled to the bottom surface of the drain region and the source region of the second transistor and the second horizontal heat dissipation plate is connected to the vertical heat dissipation column. According to one aspect of the present invention, the device structure further comprises a shallow trench isolation (STI) region, and the vertical heat dissipation column is within the STI region.

[0022] According to one aspect of the invention, an upper surface of the STI region is higher than the initial semiconductor surface, a recess is formed between the STI region and a gate structure of a first transistor, and a metal plug is formed in the recess to contact an upper surface of the drain region or the source region of the first transistor.

[0023] According to one aspect of the invention, the first horizontal heat dissipation plate and / or the second horizontal heat dissipation plate further comprise a thin oxide layer covering the further heat dissipation material.

[0024] One embodiment of the present invention provides a device structure including heat removal structures (such as highly thermally conductive columns and / or plates in the semiconductor substrate) for improving heat dissipation. The device structure includes a semiconductor substrate having an initial semiconductor surface, circuit elements located in the semiconductor body region of the semiconductor substrate, and a horizontal heat dissipation plate in the semiconductor substrate and below the circuit elements. The horizontal heat dissipation plate includes a first heat dissipation material having a first thermal conductivity greater than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.

[0025] According to one embodiment of the present invention, the first heat dissipation material is BN, AlN, or a metal.

[0026] According to one aspect of the invention, the horizontal heat dissipation plate further comprises a thin oxide layer covering the first heat dissipation material.

[0027] According to one aspect of the invention, the device structure further comprises a shallow trench isolation (STI) region surrounding the semiconductor body region, and the horizontal heat sink plate extends outside the STI region.

[0028] According to one aspect of the invention, the semiconductor substrate includes an edge region remote from the circuit elements, and the horizontal heat sink plate extends further to a position proximate the edge region of the semiconductor substrate.

[0029] According to one aspect of the invention, a heat dissipation sink is connected to the horizontal heat dissipation plate near the edge region of the semiconductor substrate through an opening above the horizontal heat dissipation plate.

[0030] According to one aspect of the invention, a heat dissipation substrate is connected to the horizontal heat dissipation plate through an opening below the horizontal heat dissipation plate.

[0031] According to one aspect of the invention, the heat dissipation substrate includes thermal vias or a heat sink connected to the horizontal heat dissipation plate.

[0032] According to one aspect of the present invention, the circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor.

[0033] According to one aspect of the present invention, the circuit element is a transistor having a source region, a drain region and a channel region, and the horizontal heat dissipation plate is connected to a lower surface of the source region and a lower surface of the drain region.

[0034] According to one aspect of the present invention, the horizontal heat dissipation plate comprises a first horizontal heat dissipation plate and a second horizontal heat dissipation plate, and a gap is provided between the first horizontal heat dissipation plate and the second horizontal heat dissipation plate, the gap being located directly below the channel region of the transistor.

[0035] According to one embodiment of the present invention, a first PN junction is present between the source region and the channel region, and a second PN junction is present between the drain region and the channel region, and both the first PN junction and the second PN junction are present directly above the horizontal heat sink plate.

[0036] According to one aspect of the invention, the transistor is a fin-structure transistor, and a fin width of the fin-structure transistor is substantially the same as a width of a horizontal heat sink plate directly below the fin-structure transistor.

[0037] According to one aspect of the invention, the device structure further comprises a vertical heat dissipation column in a semiconductor substrate and surrounding the circuit element, the horizontal heat dissipation plate being connected to the vertical heat dissipation column, the vertical heat dissipation column including a second heat dissipation material having a second thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.

[0038] According to one aspect of the invention, the semiconductor substrate has an edge region remote from the circuit elements, and the vertical heat dissipation columns extend from the circuit elements to a location proximate the edge region of the semiconductor substrate.

[0039] According to one aspect of the invention, the device structure includes a shallow trench isolation (STI) region surrounding the semiconductor body region, and the vertical heat dissipation columns are within the STI region.

[0040] Another embodiment of the present invention provides a method for fabricating a semiconductor device structure, the method comprising: providing a semiconductor substrate made of a semiconductor material and having an initial semiconductor surface, forming a shallow trench isolation (STI) region in a semiconductor body defining an active area, surrounding the active area and extending to an edge region of the semiconductor substrate, and depositing a first heat dissipation material in the STI region, the first heat dissipation material having a first thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.

[0041] According to one aspect of the invention, the first heat dissipation material extends from the active region to a location near an edge region of the semiconductor substrate.

[0042] According to one aspect of the present invention, after forming the first heat dissipation material, the method further includes forming a circuit element in the active area, the circuit element being a transistor, a resistor, a capacitor, a diode, or an inductor.

[0043] According to one embodiment of the present invention, the first heat dissipation material is BN, AlN, or a metal.

[0044] According to one aspect of the present invention, the step of forming the first heat dissipation material includes the steps of etching down the STI region to expose sidewalls of the semiconductor body, forming a vertical spacer covering the exposed sidewalls of the semiconductor body, further etching down the STI region to expose deeper silicon sidewalls of the semiconductor body, removing the semiconductor material from the exposed deeper silicon sidewalls to a cavity tunnel region in the active area, and depositing the first heat dissipation material in the cavity tunnel region and above the STI region.

[0045] According to one aspect of the invention, removing the semiconductor material from the exposed deeper silicon sidewalls includes thermally oxidizing the semiconductor material from the exposed deeper silicon sidewalls and etching the oxidized semiconductor material to form a cavity tunnel region.

[0046] According to one aspect of the invention, removing the semiconductor material from the exposed deeper silicon sidewalls includes laterally etching the semiconductor material from the exposed deeper silicon sidewalls to form the cavity tunnel region.

[0047] According to one aspect of the invention, the method further comprises thermally oxidizing the semiconductor material exposed by the cavity tunnel region before depositing the first heat dissipation material in the cavity tunnel region.

[0048] According to one aspect of the invention, the method further comprises removing the vertical spacers before depositing the first heat dissipation material in the cavity tunnel regions.

[0049] According to one aspect of the invention, the method further includes forming a protective layer covering a central portion of the active region before etching down the STI region to expose sidewalls of the semiconductor body.

[0050] These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] FIG. 1 is a flow chart illustrating a method for fabricating a heat removal (HHR) structure in a substrate or die according to one embodiment of the present invention.

[0052] FIG. 2 (including FIGS. 2a and 2b) illustrates a top view and a cross-sectional view after forming active areas and shallow trench isolation (STI) regions.

[0053] FIG. 3 (including FIGS. 3a and 3b) shows a top view and a cross-sectional view after forming a protective region of nitride over the center of the active area.

[0054] FIG. 4 (including FIGS. 4a and 4b) shows top and cross-sectional views after vertical spacers have been formed covering the exposed silicon sidewalls.

[0055] FIG. 5 (including FIGS. 5a and 5b) shows top and cross-sectional views after the deep silicon sidewalls are exposed.

[0056] FIG. 6 (including FIGS. 6a, 6b and 6c) shows a top view and two different cross-sectional views after the hollow tunnel region has been formed.

[0057] FIG. 7 (including FIG. 7a and FIG. 7b) shows a top view and a cross-sectional view after the heat-dissipating material has been deposited.

[0058] FIG. 8 (including FIG. 8a and FIG. 8b) shows a top view and a cross-sectional view after the horizontal heat dissipation plates (HHDPs) and vertical heat dissipation columns (VHDCs) have been formed.

[0059] FIG. 9 (including FIGS. 9a and 9b) shows a top view and a cross-sectional view of another embodiment after the HHDP and VHDC have been formed.

[0060] FIG. 10 shows that the HHDP and VHDC are connected and extend to the edge of the chip / die.

[0061] FIG. 11 is a diagram showing a cool transistor according to the present invention. FIG. B-5 (including FIG. B-5a and FIG. B-5b) shows a top view and a cross-sectional view of another embodiment after the deep silicon sidewalls are exposed. FIG. B-6 (including FIG. B-6a, FIG. B-6b, and FIG. B-6c) shows a top view and two different cross-sectional views of another embodiment after thermal oxide has been formed along the deep silicon sidewalls. FIG. B-7 (including FIG. B-7a and FIG. B-7b) shows a top view and a cross-sectional view of another embodiment after the cavity tunnel regions have been formed. FIG. B-8 (including FIG. B-8a and FIG. B-8b) shows a top view and a cross-sectional view of another embodiment after a thin thermal oxide layer is formed. FIG. B-9 (including FIG. B-9a and FIG. B-9b) shows a top view and a cross-sectional view of another embodiment after a high heat dissipation material has been deposited. FIG. B-10 (including FIG. B-10a and FIG. B-10b) shows a top view and a cross-sectional view of another embodiment after the horizontal heat dissipation plates (HHDPs) and vertical heat dissipation columns (VHDCs) have been formed. FIG. B-11 shows another embodiment where the HHDP and VHDC are connected and extend to the edge of the chip / die. FIG. B-12 is a diagram showing a cool transistor according to another embodiment of the present invention. FIG. B-13 shows the results of a three-dimensional cool transistor operation simulation and heat generation model.

[0062] Currently, the most popular transistors use FinFET / Tri-Gate structures in CMOS circuit configurations with both NMOS and PMOS. Therefore, FinFET NMOS is used here as an example to illustrate the key features of this invention regarding high heat removal (HHR) structures of the substrate or die. This can be easily extended to other types of transistors such as PMOS, All Gate Around (GAA), sheet transistors, or planar transistors. Another inventive feature is that the fabrication method requires few processing steps.

[0063] Please refer now to FIG. 1, which is a flow chart illustrating a method for fabricating a high heat removal (HHR) structure in a substrate or die according to one embodiment of the present invention. Step 10: Start Step 15: Based on a substrate (such as a p-type silicon substrate), define active areas and form shallow trench isolation (STI) regions. Step 20: Form a protective nitride layer over the center of the active area. Step 25: Etch down the STI regions and form vertical spacers covering the exposed silicon sidewalls. Step 30: Etch down further in the STI areas to expose the deep silicon sidewalls. Step 35: Remove silicon material from exposed deep silicon sidewalls and cavity tunnel areas. Step 40: Remove the vertical spacers and form horizontal heat dissipation plates (HHDPs) in the vertical cavity areas and vertical heat dissipation columns (VHDCs) in the STI areas. Step 45: Form transistors in the active areas. Step 50: Finished.

[0064] A detailed description of the manufacturing method is as follows. [Option A: Implementing HHR Structure] For step 15, see Figure 2. First, a thin pad oxide layer 101 is thermally grown on the silicon surface (original silicon surface: OSS), and then a pad nitride layer 102 is deposited. Using photolithography etching techniques, an active area with a transistor body or fin structure is defined. An island-shaped active area 103 having a composite layer of a pad nitride-1 layer 102 and a pad oxide layer 101 is formed on the active area 103, and a concave trench area 104 (e.g., depth t1 ~ 250 nm) is formed that is connected to the wafer outside the active area 103. Next, a thick oxide is deposited and a shallow trench isolation (STI) 201 is fabricated using a chemical mechanical polishing (CMP) technique such that the top surface of the shallow trench isolation (STI) 201 is at the same height as the top surface of the pad nitride-1 layer 102 (see Figure 2, top view and cross-sectional view are shown in Figure 2a and Figure 2b, respectively).

[0065] See Figure 3 for step 20. A pad nitride-2 layer 301 is deposited and a portion of the nitride-2 layer 301 is left in the center of the active area 103 using photolithographic masking techniques. The active area 103 is purposely designed to leave a silicon pillar region to ensure that the NMOS is a bulk device rather than an SOI device (as will become apparent later in Figure 6). In Figure 3, a top view is shown in Figure 3a and a cross-sectional view is shown in Figure 3b.

[0066] See FIG. 4 for step 25. Etch away the oxide in the exposed STI regions 201 to a depth t2 (e.g., 70 nm deep). Leave the pad nitride layer-2 layer 301 intact, but leave the oxide in the STI regions 201 in the areas protected by the pad nitride layer-2 layer 301 intact, up to the height of the surface of the pad nitride layer-1 layer 102. Thus, all silicon surfaces below the initial silicon surface (OSS) are exposed. Then, using thermal oxide, grow a thin layer of oxide 401 on these sidewalls (e.g., about 1.5 nm thick). Then, deposit another pad nitride-3 layer 403. Use an anisotropic etching technique to make the pad nitride-3 layer 403 a spacer on the vertical sidewalls. By design and under proper design, the pad nitride-2 layer 301 remains on its plane, but is thinned by the anisotropic etching that produces the pad nitride-3 spacer 403. (See Figure 4, where the top view and cross-sectional view are shown in Figure 4a and Figure 4b, respectively)

[0067] See Figure 5 for step 30. Using anisotropic etching techniques, the exposed oxide layer inside most of the STI regions 201 is removed to a thickness t3 of 8 nm. This results in a flat oxide surface with a distance from the top of the exposed oxide surface to the OSS of about 78 nm (t2+t3). Using an isotropic etching technique, the exposed thin oxide layer 401 is removed to a thickness of about 1.5 nm, exposing the sidewall silicon (see Figure 5, top and cross-sectional views are shown in Figures 5a and 5b, respectively).

[0068] For step 35, see FIG. 6. An isotropic etching technique is used to remove a portion of the exposed silicon surface, and the etching rate over the (110) crystal orientation can be optimally adjusted to be much faster than that of the (100). In particular, the etching rate over the (110) crystal orientation can be optimally adjusted to be much faster than that of the (100) (see reference [1], Prem Pal, Kazuo Sato et al., “Adsorption of Surfactants on Single Crystal Silicon Surface in TMAH Solution: In Situ Infrared Spectroscopy Detected by Orientation-Dependent Adsorption”, JOURNAL OF MICROELECTROMECHANICAL SYSTEMS, VOL.18, No.6, December 2009, pp1345-1356). Thus, the silicon layer along the formed exposed regions can be removed to form cavity tunnel regions 601, but the removal process can be well controlled to end at a suitable adjusted time to leave the silicon protected by a vertical distance under the pad nitride-3 layer 403 (spacer) (see FIG. 6, top and cross-sectional views are shown in FIG. 6a and FIG. 6b respectively, and top and cross-sectional views based on different cutting lines are shown in FIG. 6c).

[0069] It should be noted here that different processes can be used to achieve a similar structure as shown in FIG. 6. For example, after creating a structure as shown in FIG. 5, instead of using the previously described isotropic etching technique to remove some of the exposed silicon surface, a thermal oxidation process can be used to grow the exposed silicon areas. Because the exposed silicon areas are somewhat narrow in horizontal distance, an oxide layer (such as thermal oxide) grown below the top surface of the silicon island can quickly fill the horizontal gap and provide a smooth close-up shape. However, the bulk silicon material under the cover of the pad nitride-3 layer 403 (spacer) is sufficiently protected and not over-oxidized to connect the semiconductor body regions of the transistors to the wafer substrate as robust pillar regions. This thermal oxide can then be removed using an isotropic etching technique to obtain a similar structure as shown in FIG. 6. One embodiment of the previously described thermal oxidation and etching process to remove silicon is presented below in Option B.

[0070] For step 40, see Fig. 7-8. See Fig. 7a and Fig. 7b. An isotropic etching technique is adopted to remove the pad nitride-3 layer 403 (spacer). A thermal oxidation process is used to grow a very thin oxide layer 701 (e.g. 1 nm) to adequately protect the freshly created and exposed silicon surface. Then, a suitable material can be selected that has a very high thermal conductivity but is an insulator in terms of electrical conductivity (such as Boron Nitride, BN (see [2], https: / / en.wikipedia.org / wiki / Boron_nitride), which is an electrical insulator but has a very high thermal conductivity, such as 600 W / m×K against 149 W / m×K for silicon material, Boron Nitride can be used to effectively fill the holes by a CVD process; or an Aluminum Nitride (AlN) material (see [4], https: / / en.wikipedia.org / wiki / Aluminium_nitride), which has a high thermal conductivity of 321 W / m×K, or other suitable materials to be used as the so-called Z material 702). Next, a CVD process is used to fill the hollow tunnel regions 601 created by the above processing results. Of course, the voids in the STI regions are filled with BN material (see FIG. 7, the top view and cross-sectional view are shown in FIG. 7a and FIG. 7b, respectively).

[0071] Then, the BN or Z material 702 on the pad nitride-1 layer 102 can be removed to a planar shape using CMP techniques, and anisotropic etching techniques can be further used to remove some of the BN or Z material 702 on the STI regions 201. Then, a layer of oxide 801 is deposited on top of the surface, flush with the pad nitride-1 layer 102. After removing the pad nitride-2 layer 301, the silicon surface is covered with the pad nitride-1 layer 102 and the STI regions 201 covered with oxide. Conventional processes can be continued to complete the MOS transistors in the remaining semiconductor active areas (see FIG. 8, top view 8a and cross-sectional view 8b, respectively).

[0072] Thus, some BN or Z material 702 is filled in the cavity tunnel region under the silicon body region of the FinFET / Tri-Gate device to protect it from the semiconductor body and wafer substrate, and is named as horizontal heat dissipation plate (HHDP), as shown in Figure 8. Some material is filled in the vertical cavity region of the STI, and is named as vertical heat dissipation column (VHDC). In the new device structure, the source / drain regions of the transistor are placed in both the HDDP and VHDC, which have a higher thermal conductivity than that of the silicon dioxide material surrounding the transistor in conventional designs. In fact, the hottest area of ​​the transistor during full operation is the center of the p / n junction areas between the drain and source regions, both of which are respectively connected to the channel region of the transistor, and these HDDP and VHDC structures are very effective at dissipating the heat generated in these p / n junction areas.

[0073] After describing the gist of the present invention, the variation of the design of HDDP and VHDC can be described in detail below. For example, the gist is to insert this high thermal conductivity material into the cavity tunnel region 601 after the BN material or Z material 702 is completed by the CVD process. Then, the bottom oxide material of the STI region 201 can also be removed or etched downwards using anisotropic etching technology (for example, only 20 nm thick oxide can be kept in the STI region without damaging the BN material already inserted horizontally into the cavity tunnel region 601). Then, the BN material or Z material 702 is deposited twice in the cavity of the STI region, and this two-step process of forming the BN material or Z material 702 is performed first for HHDP, and then to optimize the volume of the BN material or Z material 702 inside all of the STI region (see FIG. 9, the top view is shown in 9a and the cross-sectional view is shown in 9b, respectively).

[0074] Also note that the STI regions 201 extend over the entire wafer substrate. Since all the HHDP material is laid down under the body regions of the MOSFETs / transistors and connected to all the VHDC material in the STI regions 201, the high heat dissipation material network thus constructed acts as a connected heat dissipation sink from the operated PN junctions of the transistors. By utilizing the usual monolithic processing recipes to design the Z material heat dissipation sink inside the monolithic die and connect it all to the edge ring of the chip or die, the BN or Z material 702 inside the STI regions 201 is opened and contacted on its top surface. As a result, the heat dissipation sink of the entire die is connected to the outside edge of the chip / die, providing more direct and effective heat dissipation (see FIG. 10). For example, the lead frame can be designed to fulfill this function by directly connecting the BN or Z material 702 to a large area of ​​the lead frame material. Alternatively, the flip die connection method can be used to dissipate heat from all semiconductor circuits including the HHDP and VHDC structures proposed in this invention. Of course, there may be more than one body region in the semiconductor substrate, with each body region surrounded by BN or Z material 702 extending from one body region to another and even to the edge of the chip / die. Each body region may house a circuit element, such as a transistor.

[0075] In addition to the heat sink being connected from the top to the outside edge of the chip / die and to the VHDC (and / or HHDP) within the die / chip for heat dissipation (see FIG. 10), in another embodiment, the die / chip with the VHDC (and / or HHDP) can be first thinned and then opened to expose the VHDC (and / or HHDP) so that another substrate with thermal vias or a heat sink can be connected to the VHDC (and / or HHDP) from the bottom of the die / chip.

[0076] Another possibility is to use a similar method described in this embodiment to create not only a first HHDP structure but also a second HHDP structure at a deeper distance from the initial silicon surface within the monolithic transistor area, which allows extending more HHDPs to enlarge the heat dissipation area.

[0077] FIG. 11 shows the final transistor structure with HHDP and VHDC microstructures of the novel "Cool Transistor (CQT)", a term best used to describe one embodiment of the present invention. Such CQT structures can realize the scale-up (increase in transistor count) and scale-down (reduction in transistor dimensions) strategies from the current GSI (gigascale integration) to the near future TSI (terascale integration) era. The newly created heat dissipation path in the chip or die will directly generate a heating path from the transistor level to the whole die level. As mentioned above, there are designs that can connect the die-level heat dissipation path to the chip-level heat dissipation path, and it is certain that the die and package / heterogeneous integration module will be an effective heat sink for the chip package and / or heterogeneous integration module (e.g., via TSVs, TIVs, etc.) with the current cooling scheme.

[0078] In FIG. 11, the transistor comprises a gate structure including a gate metal region 1101 and a Hi-K dielectric 1102. The transistor also comprises a source region 1103 including a lightly doped region extending laterally from a sidewall of the substrate and a heavily doped region extending laterally from a sidewall of the lightly doped region. The lightly doped and heavily doped regions are formed by selective growth methods such as epitaxial growth methods. On top of the source region 1103 is a metal contact 1105 between the gate structure of the transistor and the STI region 201 / 801. It should be noted that the top surface of the STI region 801 is higher than the OSS, e.g., flush with the top surface of the gate structure, so that the metal contact 1105 is self-aligned with the source region 1103, such that the contact hole is automatically formed without using a photolithography process to form the contact hole. Furthermore, in another embodiment, the metal contact 1105 can be connected not only to the top of the source region 1103, but also to the outermost sidewall of the source region 1103. The transistor also includes a drain region 1104, the structure of which is the same as or substantially the same as that of the source region 1103, and so a description of which is omitted.

[0079] Furthermore, in another embodiment, the step of forming the horizontal heat dissipation plate (HHDP) can be omitted and only the vertical heat dissipation column (VHDC) can be constructed. Since the vertical heat dissipation column (VHDC) is in the STI region 201 distributed over the entire die / chip, the constructed VHDC is also thermally connected. Therefore, the constructed high heat dissipation VHDC network can act as a connected heat dissipation sink from the operated PN junctions of the transistors in the die / chip.

[0080] As mentioned above, the VHDC can be made of a single high heat dissipation material or can be made of a composite structure. For example, the VHDC comprises a layer of a first high heat dissipation material (BN, AlN, etc.) and another metal or metal-like column covered by the first high heat dissipation material. The metal-like material of the VHDC does not affect the operation of the transistors in the die / chip because the VHDC is in the STI region and the metal-like material is surrounded by the first high heat dissipation material, which is non-conductive during the operation of the transistors in the die / chip. In another embodiment, the VHDC comprises a layer (or thin layer) of a first high heat dissipation material (BN, AlN, etc.) and another non-conductive column (such as an oxide) covering the first high heat dissipation material. Such a layer of the first high heat dissipation material can further extend to the edge of the die / chip to form a heat dissipation network as mentioned above.

[0081] Vertical heat dissipation columns (VHDCs) are located within the STI regions 201 that are distributed across the die / chip, so these constructed VHDCs are also thermally connected. Thus, the high heat dissipation VHDC network thus constructed can act as a connected heat dissipation sink from the operated PN junctions of the transistors within the die / chip.

[0082] Furthermore, in another embodiment, only a horizontal heat dissipation plate (HHDP) may be constructed. The horizontal heat dissipation plate (HHDP) may extend outside the STI region 201 or may be connected to other high heat dissipation materials on the STI region 201. An oxide layer 801 may then be deposited above the surface, flush with the pad nitride-1 layer 102. It can be seen that the top of the STI region 201 is higher than the initial semiconductor surface of the semiconductor substrate (such as a Si substrate).

[0083] The horizontal heat dissipation plates (HHDPs) can extend to the STI regions 201 distributed across the die / chip, so that these constructed HHDPs are also thermally connected together. Thus, this constructed high heat dissipation HHDP network can act as a connected heat dissipation sink from the operated PN junctions of the transistors in the die / chip.

[0084] 2. Option B to implement HHR structure Hereinafter, another embodiment of the present invention based on the Option B process will be described. Based on the above Fig. 4a and Fig. 4b, the exposed oxide layer inside most of the STI region 201 is removed by a thickness of t3=160 nm using anisotropic etching technology. As a result, a planar oxide surface is formed with a distance from the top surface of the exposed oxide layer surface to the initial silicon surface of about 230 nm (t2+t3). Using an isotropic etching technique, the exposed thin oxide layer 401 is removed by a thickness of about 1.5 nm to expose the sidewall silicon (c).

[0085] As mentioned above, in option B, instead of directly etching the sidewall exposed silicon, a thermal oxidation process is used to grow the sidewall exposed silicon. The exposed silicon area may be rather narrow in horizontal distance (especially applicable for FinFETs where the transistor planar width is <20 nm), so the thermal oxide layer 602 grown under the silicon island or active area 103 can quickly fill the horizontal gaps to a smooth close-up shape. However, the bulk silicon material under the cover of the pad nitride layer-3 layer 403 (spacer) is sufficiently protected and can connect the transistor semiconductor body region to the wafer substrate as a strong pillar region without being too oxidized (see Figure B-6, top view is shown in Figure B-6a, cross section is shown in Figure B-6b, respectively; another cross section based on a different cut line is shown in Figure B-6c). (See FIG. B-7, where the top view is shown in FIG. B-7a and the cross-sectional view is shown in FIG. B-7b.) Next, an isotropic etching technique is used to remove the grown thermal oxide layer 602, resulting in horizontal halo or tunnel regions 603. An isotropic etching technique is employed to remove the Pad nitride-3 layer 403 (spacer) (See FIG. B-7, where the top view is shown in FIG. B-7a and the cross-sectional view is shown in FIG. B-7b.)

[0086] A thermal oxidation process is used to grow a very thin oxide layer 901 (e.g., 1 nm) that adequately protects the freshly prepared and exposed silicon surface (see FIG. B-8, with a top view in FIG. B-8a and a cross-sectional view in FIG. B-8b).

[0087] Next, a suitable material that has a very high thermal conductivity but is an insulator in terms of electrical conductivity (e.g., boron nitride (BN) is an electrical insulator, but has a very high thermal conductivity, such as 600 W / m×K, compared to 149 W / m×K for silicon material, and can be used to effectively fill the horizontal halo or tunnel region 603 by a CVD process. Aluminum nitride (AlN) material or other suitable Z material 902 with a high thermal conductivity of 321 W / m×K is used. Next, a CVD process is used to fill the horizontal halo or tunnel region 603 formed by the above-mentioned processing result, for example, BN is selected. Of course, the voids inside the STI region 201 are also filled with the BN material or Z material 902 (see Figure B-9, where the top view is shown in Figure B-9a and the cross-sectional view is shown in Figure B-9b, respectively). Of course, the suitable material can be tungsten or other highly thermally conductive metals, as long as it is separated from the silicon body of the transistor by an oxide layer 901.

[0088] Then, the BN or Z material 902 on the pad nitride-1 layer 102 is removed to a planar shape using a CMP technique, and an anisotropic etching technique can be further used to remove some of the BN or Z material 902 on the STI regions 201. Next, an oxide layer 903 is deposited above the surface to be flush with the pad nitride-1 layer 102 (see FIG. B-10, with a top view in FIG. B-10a and a cross-sectional view in FIG. B-10b). After removing the pad nitride layer-2 layer 301, the silicon surface is covered with the pad nitride layer-1 layer 201 and the oxide-covered STI regions 201, and normal processing can be continued to complete MOS transistors in the remaining semiconductor active areas 103.

[0089] As mentioned before, the STI region 201 extends above the wafer. Since all the HHDP material is laid under the body region of the MOSFETs / transistors and connected to all the VHDC VNs in the STI region 201, the high heat dissipation material network thus constructed acts as a connected heat dissipation sink from the operated junctions of the transistors. By designing such a Z material heat dissipation sink inside the monolithic die and connecting it all to the edge ring of the chip, and utilizing a normal monolithic processing recipe, the BN material or Z material 902 in the STI region 201 can be opened and contacted on its top surface to connect the heat dissipation sink of the entire die to the outside edge of the chip, and dissipate heat more directly and effectively (for example, the lead frame can be designed to fulfill this function by directly connecting the BN material or Z material 902 to a large area of ​​the lead frame material, or a flip die connection method can be used to dissipate heat from all the HHDP and VHDC structures proposed in this invention (see Figure B-11)).

[0090] FIG. B-12 shows another final transistor structure having the new "cool transistor (CQT)" HHDP and VHDC microstructure. Similarly, the transistor in FIG. B-12 can be identical or substantially identical to the transistor in FIG. 11, and therefore the description thereof is omitted. Furthermore, in another embodiment, the step of forming the horizontal heat dissipation plate (HHDP) can be omitted, and only the vertical heat dissipation column (VHDC) can be constructed. Furthermore, the VHDC in FIG. B-11 and FIG. B-12 can be made of a single high heat dissipation material, or can be made of a composite structure as described above.

[0091] The results of the operation simulation and heat generation model of the 3D cool transistor prove such an effective point disclosed in the present invention (see FIG. B-13). The structure of the 3D transistor is disclosed in the table at the bottom right of FIG. B-13. When the material of HHDP (corresponding to the region 1 shown in the left diagram of FIG. B-13) is BN and the material of VHDC (corresponding to the "STI material" shown in the first row of the table at the top right of FIG. B-13) is also BN, ΔT (the difference between the pn junction temperature T_junction and the ambient temperature T_ambient) is 53°C when T_ambient=40°C. On the other hand, when the material of region 1 is an oxide and the material of STI is also an oxide, ΔT is as high as 121°C when T_ambient=40°C. Thus, according to the present invention, T_junction is dramatically reduced. The table at the top right of FIG. B-13 also shows the combinations of different materials (oxide, Si, BN, etc.) of region 1 and STI and the results of their ΔT.

[0092] Furthermore, the present invention can be applied not only to the heat dissipation of transistors, but also to the heat dissipation of any circuit devices (resistors, capacitors, diodes, inductors, etc.) In the following, we will explain some advantages of the HSiD (heat sink within a die) of the present invention and provide a simulation demonstration using a 3D modeling tool.

[0093] (a) Current monolithic dies with many transistors only have a heat dissipation path through silicon material, oxide material, and metal wiring layers, none of which have high thermal conductivity. Therefore, in the current method, after the die or packaged chip is completed, a metal plate is placed near the die or package to realize the heat dissipation path, and an expensive heat sink is then installed. Then, expensive liquid cooling methods or electric fan systems are used to reduce the temperature. These methods are not only added after the monolithic die or chip is formed (not very effective), but are also very expensive. This new invention allows for the shortest path near the transistor junctions, which should be the most direct and effective cooling method. Because the heat sink is formed in a monolithic process, it is cheaper than using other methods that are not monolithic processes due to external materials or additives.

[0094] (2) The HHDP and VHDC can be connected together or formed in-situ by the Z material. This on-die heat sink covers nearly the entire die area, but allows the transistors to remain as bulk structures, as opposed to SOI structures.

[0095] (3) The connected heat sink network can be extended to the edge of the die by proper design methods, thus extending the heat dissipation path to the external bonding area, lead frame area, or other heterogeneous integration methods, and efficiently improving the electronic system environment. This invention is very effective in dissipating thermal power from the die to the system, and is expected to be a fundamental change for all future transistor and die / chip design structures.

[0096] (4) As thermal simulations show, the junction temperature of the transistors can be kept at a much lower temperature (e.g. 65°C) than current transistors can provide (e.g. 105°C). Better PPAC (performance, power, area, cost) is certainly expected to be achieved much better than expected. Thus, the transition to the TSI era shows a higher and closer probability. That is, multiple power-intensive applications using power transistors, or more transistors are expected to be realized.

[0097] (5) Because the Z material (such as BN) is deposited before the formation of transistors or circuit elements, the process of depositing the Z material (such as BN) does not affect the subsequent formation of transistors or circuit elements.

[0098] While the invention has been illustrated and described with reference to embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but rather, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. [Brief description of the drawings]

[0099] [Figure 1] 1 is a flow chart illustrating a method for manufacturing a heat removal (HHR) structure in a substrate or die according to one embodiment of the present invention. [Figure 2a] A top view is shown after forming active areas and shallow trench isolation (STI) regions. [Figure 2b] 3 shows a cross-sectional view after forming active areas and shallow trench isolation (STI) regions. [Figure 3a] A top view is shown after forming a nitride protective region over the center of the active area. [Figure 3b] 4 shows a cross-sectional view after forming a nitride protective region over the center of the active area. [Figure 4a] A top view is shown after vertical spacers have been formed covering the exposed silicon sidewalls. [Figure 4b] A cross-sectional view is shown after vertical spacers are formed covering the exposed silicon sidewalls. [Figure 5a] FIG. 13 is a top view after the deep silicon sidewalls are exposed. [Figure 5b] FIG. 2 is a cross-sectional view after the deep silicon sidewalls are exposed. [Figure 6a] A top view is shown after the hollow tunnel regions are formed. [Figure 6b] 1 shows a cross-sectional view after the cavity tunnel regions have been formed. [Figure 6c] 1 shows a cross-sectional view after the cavity tunnel regions have been formed. [Figure 7a] A top view is shown after the heat dissipation material has been deposited. [Figure 7b] 4 shows a cross-sectional view after a high thermal conductivity material has been deposited. [Figure 8a] A top view is shown after the horizontal heat dissipation plate (HHDP) and vertical heat dissipation column (VHDC) are formed. [Figure 8b] 1 shows a cross-sectional view after the horizontal heat dissipation plate (HHDP) and vertical heat dissipation column (VHDC) have been formed. [Figure 9a] 1 illustrates a top view of another embodiment after the HHDP and VHDC have been formed. [Figure 9b] 1 illustrates a cross-sectional view of another embodiment after the HHDP and VHDC are formed. [Figure 10] FIG. 13 shows that the HHDP and VHDC are connected and extend to the edge of the chip / die. [Figure 11] FIG. 2 shows a cool transistor according to the present invention. [Figure B-5a] 13 shows a top view of another embodiment after the deep silicon sidewalls are exposed. [Figure B-5b] 13 shows a cross-sectional view of another embodiment after the deep silicon sidewalls are exposed. [Figure B-6a] 4 shows a top view of another embodiment after thermal oxide has been formed along the deep silicon sidewalls. [Figure B-6b]4 illustrates a cross-sectional view of another embodiment after thermal oxide is formed along the deep silicon sidewalls. [Figure B-6c] 4 illustrates a cross-sectional view of another embodiment after thermal oxide is formed along the deep silicon sidewalls. [Figure B-7a] 13 illustrates a top view of another embodiment after cavity tunnel regions have been formed. [Figure B-7b] 13 illustrates a cross-sectional view of another embodiment after cavity tunnel regions have been formed. [Figure B-8a] 4 shows a top view of another embodiment after a thin thermal oxide layer has been formed. [Figure B-8b] 4 illustrates a cross-sectional view of another embodiment after a thin thermal oxide layer is formed. [Figure B-9a] 1 illustrates a top view of another embodiment after a high thermal dissipation material has been deposited. [Figure B-9b] 4 illustrates a cross-sectional view of another embodiment after a high thermal dissipation material has been deposited. [Figure B-10a] 1 illustrates a top view of another embodiment after horizontal heat dissipation plates (HHDPs) and vertical heat dissipation columns (VHDCs) have been formed. [Figure B-10b] 1 illustrates a cross-sectional view of another embodiment after horizontal heat dissipation plates (HHDPs) and vertical heat dissipation columns (VHDCs) have been formed. [Figure B-11] FIG. 13 shows another embodiment of the HHDP and VHDC connected and extending to the edge of the chip / die. [Figure B-12] FIG. 2 shows another embodiment of a cool transistor according to the present invention. [Figure B-13] 1A and 1B are diagrams showing the results of an operational simulation and a heat generation model of a three-dimensional cool transistor.

Claims

1. a semiconductor substrate having an initial semiconductor surface; a shallow trench isolation (STI) region (201) surrounding a semiconductor body region of the semiconductor substrate; circuit elements located within the semiconductor body region of the semiconductor substrate; a vertical heat sink column located within the semiconductor substrate and adjacent the semiconductor body region; The device structure, wherein the vertical heat dissipation columns include a heat dissipation material having a thermal conductivity greater than a thermal conductivity of the semiconductor substrate or a thermal conductivity of silicon oxide.

2. 2. The device structure of claim 1, wherein the semiconductor substrate has an edge region away from the circuit elements, and the vertical heat dissipation columns extend from a location adjacent the circuit elements to another location near the edge region of the semiconductor substrate.

3. The device structure of claim 1 , wherein the heat dissipation material is BN, AlN, or a metal.

4. The device structure of claim 1 , wherein the vertical heat dissipation columns comprise the layer of heat dissipation material and a thermally conductive column located above the layer of heat dissipation material.

5. The device structure of claim 1 , wherein the vertical heat dissipation columns comprise the layer of heat dissipation material and an insulating layer overlying the layer of heat dissipation material.

6. The device structure of claim 1 , wherein the vertical heat dissipation columns comprise the layer of heat dissipation material and an insulating layer underlying the layer of heat dissipation material.

7. The device structure of claim 1 , wherein the vertical heat dissipation columns are located within the STI regions and surround the semiconductor body regions.

8. The device structure of claim 7 , wherein the circuit element is a transistor, a resistor, a capacitor, a diode, or an inductor.

9. The device structure of claim 8 , wherein the transistor is a fin-structure transistor, a planar type transistor, a GAA transistor, or a sheet type transistor.

10. 2. The device structure of claim 1, wherein the semiconductor substrate has an edge region away from the circuit elements, the vertical heat dissipation columns extend from a location adjacent the circuit elements to another location near the edge region of the semiconductor substrate, and a heat dissipation sink is connected to the vertical heat dissipation columns near the edge region of the semiconductor substrate through a via above or below the vertical heat dissipation columns.

11. a semiconductor substrate having an initial semiconductor surface; a first transistor located in a first semiconductor body region of the semiconductor substrate; a second transistor located in a second semiconductor body region of the semiconductor substrate and spaced apart from but not adjacent to the first transistor; a shallow trench isolation (STI) region (201) located between the first semiconductor body region and the second semiconductor body region; a vertical heat spreader column located within the STI region and including a heat spreader material having a thermal conductivity greater than a thermal conductivity of the semiconductor substrate or a thermal conductivity of silicon oxide; The vertical heat dissipation column extends from the first semiconductor body region to the second semiconductor body region.

12. 12. The device structure of claim 11, wherein the semiconductor substrate comprises an edge region remote from the first transistor and the second transistor, and the vertical heat dissipation columns further extend closer to the edge region of the semiconductor substrate.

13. a first horizontal heat dissipation plate located directly below the first transistor; a second horizontal heat dissipation plate located directly below the second transistor; the vertical heat dissipation column is connected or thermally coupled to both the first horizontal heat dissipation plate and the second horizontal heat dissipation plate; and 12. The device structure of claim 11, wherein the first horizontal heat dissipation plate and / or the second horizontal heat dissipation plate further comprises another heat dissipation material having another thermal conductivity higher than the thermal conductivity of the semiconductor substrate or the thermal conductivity of silicon oxide.

14. the first horizontal heat dissipation plate is connected or thermally coupled to a bottom surface of a drain region and a source region of the first transistor, and the first horizontal heat dissipation plate is connected to the vertical heat dissipation column; 14. The device structure of claim 13, wherein the second horizontal heat dissipation plate is connected or thermally coupled to an underside of a drain region and a source region of the second transistor, and the second horizontal heat dissipation plate is connected to the vertical heat dissipation column.

15. 14. The device structure of claim 13, wherein the first horizontal heat dissipation plate and / or the second horizontal heat dissipation plate further comprise a thin oxide layer covering the other heat dissipation material, the other heat dissipation material being BN, AlN or a metal.

16. a semiconductor substrate having an initial semiconductor surface; a shallow trench isolation (STI) region (201) surrounding a semiconductor body region of the semiconductor substrate; circuit elements located within the semiconductor body region of the semiconductor substrate; a horizontal heat sink plate located within the semiconductor substrate and below the circuit elements; the horizontal heat dissipation plate includes a first heat dissipation material having a first thermal conductivity greater than a thermal conductivity of the semiconductor substrate or a thermal conductivity of silicon oxide; The horizontal heat sink plate extends outside the STI region.

17. 17. The device structure of claim 16, wherein the horizontal heat spreader plate further comprises a thin oxide layer covering the first heat spreader material, the first heat spreader material being BN, AlN, or a metal.

18. 17. The device structure of claim 16, wherein the semiconductor substrate comprises an edge region away from the circuit elements, the horizontal heat dissipation plate extends further near the edge region of the semiconductor substrate, and a heat dissipation sink is connected to the horizontal heat dissipation plate through a via above or below the horizontal heat dissipation plate.

19. 17. The device structure of claim 16, wherein the horizontal heat sink plate comprises a first horizontal heat sink plate and a second horizontal heat sink plate, a gap exists between the first horizontal heat sink plate and the second horizontal heat sink plate, the gap exists beneath the channel region of the transistor.

20. the circuit element is a transistor having a source region, a drain region and a channel region; the horizontal heat dissipation plate is connected to a lower surface of the source region and a lower surface of the drain region; 17. The device structure of claim 16, wherein a first PN junction exists between the source region and the channel region, and a second PN junction exists between the drain region and the channel region, both the first PN junction and the second PN junction existing directly above the horizontal heat sink plate.

21. 21. The device structure of claim 20, wherein the transistor is a fin-structure transistor, and a fin width of the fin-structure transistor is substantially the same as a width of the horizontal heat sink plate that is located directly underneath the fin-structure transistor.

Images