Method for manufacturing semiconductor device

Abstract

To provide a method for manufacturing a semiconductor device with high productivity.SOLUTION: A method for manufacturing a semiconductor device includes steps of: forming a first insulator 212, a second insulator 214, and a third insulator 216 in this order; forming a fourth insulator 222, a fifth insulator 224, a first oxide film, a second oxide film, and a third oxide film in this order; forming a conductive film (conductors 242a, 242b); processing the first oxide film, the second oxide film, the third oxide film, and the conductive film, thereby forming a first oxide 230a, a second oxide 230b, an oxide layer, and a conductive layer each having an island shape; forming a sixth insulator 280 and an insulating film in this order; planarizing the insulating film; forming, in the insulating film and the sixth insulator, an opening where the second oxide is exposed; forming seventh insulators 241a, 241b and the first conductors 240a, 240b; and forming an eighth insulator 283 and a ninth insulator 286 in this order.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. One embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor device and a module. Regarding placement.

[0002] In this specification and the like, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. This refers to semiconductor devices in general, including semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and memory devices. The device is one aspect of a semiconductor device. device, lighting device, electro-optical device, power storage device, storage device, semiconductor circuit, imaging device, electronic device etc. may be said to have a semiconductor device.

[0003] Note that one embodiment of the present invention is not limited to the above technical fields. One aspect of the present invention relates to an object, a method, or a manufacturing method. , process, machine, manufacture, or composition of matter (-) [Background technology]

[0004] A technology for constructing transistors using a semiconductor thin film formed on a substrate with an insulating surface. The transistor is used in integrated circuits (ICs) and image display devices (simply called display devices). It is widely used in electronic devices such as transistors. Silicon-based semiconductor materials are widely known as suitable semiconductor thin films, but other materials include oxides. Compound semiconductors have been attracting attention.

[0005] In oxide semiconductors, there are c-axis axial crystals (CAACs), which are neither single crystals nor amorphous. gned crystalline structure and nc (nanocrystalline) ) structure has been found (see Non-Patent Documents 1 and 2).

[0006] In Non-Patent Documents 1 and 2, a transistor was developed using an oxide semiconductor having a CAAC structure. A technique for fabricating a transistor is disclosed. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, p.183-186 [Non-Patent Document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, Number 4S, p.04ED18-1-04ED18-10 Summary of the Invention [Problem to be solved by the invention]

[0008] In recent years, semiconductor devices, such as semiconductor integrated circuits, have become more multifunctional, highly integrated, and faster. In order to meet these demands, there is a strong demand for semiconductor devices with higher speed and lower power consumption. It is necessary to miniaturize and highly integrate the transistors that make up the device.

[0009] One method for achieving high integration of semiconductor devices is stacking of semiconductor devices. In order to stack semiconductor devices, it is necessary to increase the productivity of semiconductor devices. In order to improve the reliability, the manufacturing process of the semiconductor device must be reduced, the time required for each process must be shortened, and the semiconductor device must be manufactured in a short period of time. It is important to shorten the path of substrate movement during the manufacturing process and to perform parallel processing of the processes.

[0010] An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. Another embodiment of the present invention is a semiconductor device with little variation in transistor characteristics. Another object of the present invention is to provide a semiconductor device having high reliability and a manufacturing method thereof. Another object of the present invention is to provide a good semiconductor device and a manufacturing method thereof. One aspect of the present invention is to provide a semiconductor device having good electrical characteristics and a manufacturing method thereof. Another object of one embodiment of the present invention is to provide a semiconductor device having a large on-state current and Another object of the present invention is to provide a method for manufacturing the semiconductor device. An object of the present invention is to provide a semiconductor device capable of high integration and a manufacturing method thereof. Another embodiment of the present invention is to provide a semiconductor device with low power consumption and a manufacturing method thereof. is one of the challenges.

[0011] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. Other issues can be extracted from the drawings, claims, etc. [Means for solving the problem]

[0012] One aspect of the present invention is a first method for depositing a first insulator, a second insulator, and a third insulator in this order. A fourth insulator, a fifth insulator, a first oxide film, a second oxide film, and a third oxide film are formed in this order. a second step of forming a conductive film on the first oxide film, a third step of forming a conductive film on the second oxide film, and By processing the third oxide film and the conductive film, the first oxide, the second oxide, and the third oxide are formed. A fourth step of forming an oxide layer and a conductive layer, and a sixth step of forming an insulator and an insulating film in sequence. A fifth step of planarizing the insulating film, a sixth step of forming a second insulating film on the insulating film and the sixth insulator, A seventh step of forming an opening exposing the oxide of the seventh insulator and the first conductor. and a ninth step of depositing an eighth insulator and a ninth insulator in that order. The first step is a method for manufacturing a semiconductor device using a first multi-chamber apparatus. The second step is carried out using a second multi-chamber apparatus. The fifth step is The ninth step is carried out using the fourth multi-chamber apparatus. This is done using a special device.

[0013] In one embodiment of the present invention, a first insulator, a second insulator, and a third insulator are sequentially formed. The first step, the fourth insulator, the fifth insulator, the first oxide film, the second oxide film, the third oxide film A second step of forming a film in this order, a third step of forming a conductive film, and a third step of forming a first oxide film, a second By processing the oxide film, the third oxide film, and the conductive film, the first oxide film, the second oxide film, and the conductive film are formed. The fourth step is to form an oxide, an oxide layer, and a conductive layer, and the sixth step is to form an insulator and an insulating film in this order. A fifth step of forming a film, a sixth step of planarizing the insulating film, and a sixth step of forming a sixth insulating film. a seventh step of forming an opening exposing the second oxide to the seventh insulator and the first conductor; An eighth step of forming an insulator, a ninth step of forming an eighth insulator, and The velum, the sixth insulator, the fifth insulator, the fourth insulator, the third insulator, and the second insulator The tenth step is to process the ninth insulator and the tenth step is to deposit the tenth insulator in sequence. The first step is a method for manufacturing a semiconductor device using a first multi-chamber apparatus. The second step is carried out using a second multi-chamber apparatus. The third step is carried out using a multi-chamber apparatus. The eleventh step is carried out using a fourth multi-chamber apparatus. This is done using a chamber apparatus.

[0014] In the method for manufacturing a semiconductor device, the fourth insulator, the fifth insulator, the first oxide film, the It is preferable that the second oxide film and the third oxide film are formed by a sputtering method. I wish.

[0015] In the method for manufacturing the semiconductor device, the first insulator, the second insulator, and the third insulator are Preferably, each of the bodies is deposited by a sputtering method.

[0016] In the method for manufacturing a semiconductor device, the sixth insulator and the insulating film are each formed of a spar. It is preferable to form the film by a tar-spraying method.

[0017] In the method for manufacturing a semiconductor device, the second oxide film is formed of an In-M-Zn oxide film. The film is formed using a target (M is gallium, aluminum, yttrium, or tin). It is preferable that:

[0018] In the method for manufacturing the semiconductor device, the first multi-chamber apparatus and the third multi-chamber apparatus are The first multi-chamber apparatus and the fourth multi-chamber apparatus are the same apparatus. is preferred. Effect of the Invention

[0019] According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics and In addition, according to one embodiment of the present invention, a semiconductor device having high reliability can be manufactured. According to one embodiment of the present invention, a semiconductor device and a manufacturing method thereof can be provided. It is possible to provide a semiconductor device having good electrical characteristics and a manufacturing method thereof. According to one embodiment of the present invention, a semiconductor device with a large on-state current and a manufacturing method thereof are provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. In addition, according to one embodiment of the present invention, a low power consumption It is possible to provide a semiconductor device having such a high power and a method for manufacturing the same.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these are described in the specification. The above will become apparent from the description, drawings, claims, etc. From the above description, it is possible to extract other effects. [Brief description of the drawings]

[0021] [Figure 1] Fig. 1A is a top view of the semiconductor device, and Fig. 1B to Fig. 1D are cross-sectional views of the semiconductor device. [Diagram 2] FIG. 2 is a cross-sectional view of the semiconductor device. [Diagram 3] Figure 3A is a diagram for explaining the classification of IGZO crystal structures, Figure 3B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film, and Figure 3C is a diagram for explaining the ultrafine electron beam diffraction pattern of a CAAC-IGZO film. [Figure 4] Fig. 4A is a top view of the semiconductor device, and Fig. 4B to Fig. 4D are cross-sectional views of the semiconductor device. [Diagram 5] 5A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 5B to 5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 6] 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 6B to 6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 7B to 7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B to 8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 9B to 9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 10B to 10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 11B to 11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12]12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 12B to 12D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13] 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 13B to 13D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 14B to 14D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 15B to 15D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 16B to 16D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 17B to 17D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 18B to 18D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 19B to 19D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 20B to 20D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 21B to 21D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] Fig. 22A is a top view of the semiconductor device, and Fig. 22B to Fig. 22D are cross-sectional views of the semiconductor device. [Figure 23] 23A and 23B are cross-sectional views of a semiconductor device. [Figure 24] FIG. 24 is a top view illustrating an apparatus for manufacturing a semiconductor device. [Diagram 25] FIG. 25 is a cross-sectional view showing the configuration of a storage device. [Figure 26] FIG. 26 is a cross-sectional view showing the configuration of a storage device. [Figure 27] FIG. 27 is a cross-sectional view of the semiconductor device. [Figure 28] FIG. 28 is a cross-sectional view of a semiconductor device. [Figure 29] Fig. 29A is a top view of the semiconductor device, and Fig. 29B is a cross-sectional view of the semiconductor device. [Diagram 30] FIG. 30 is a cross-sectional view of a semiconductor device. [Diagram 31] Fig. 31A is a block diagram showing a configuration example of a storage device, and Fig. 31B is a schematic diagram showing a configuration example of a storage device. [Diagram 32] 32A to 32H are circuit diagrams showing configuration examples of a memory device. [Diagram 33] FIG. 33 is a diagram showing various storage devices by hierarchy. [Diagram 34] Fig. 34A is a block diagram of the semiconductor device, and Fig. 34B is a schematic diagram of the semiconductor device. [Diagram 35] 35A and 35B are diagrams illustrating an example of an electronic component. [Diagram 36] 36A to 36E are schematic diagrams of a memory device. [Figure 37] 37A to 37H are diagrams showing electronic devices. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0022] Hereinafter, the embodiments will be described with reference to the drawings. It is understood that the present invention can be practiced in many different ways without departing from the spirit and scope of the present invention. It will be readily understood by those skilled in the art that various changes in form and details may be made. Therefore, the present invention should not be construed as being limited to the description of the following embodiment modes.

[0023] Also, in the drawings, the size, layer thickness, or area are exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. The examples are shown in schematic form, and are not limited to the shapes or values ​​shown in the drawings. For example, In the actual manufacturing process, layers and resist masks are damaged by etching and other processes. However, in order to make it easier to understand, this is not reflected in the diagram. In the drawings, the same parts or parts having similar functions are designated by the same reference numerals in different drawings. In addition, when referring to similar functions, In such cases, the hatch patterns may be the same and no particular reference numbers may be assigned.

[0024] In addition, the invention is easily understood, particularly in top views (also called "plan views") and perspective views. In order to simplify the description, some of the components may be omitted. The above information may be omitted.

[0025] In addition, in this specification, ordinal numbers such as 1st, 2nd, etc. are used for convenience. It does not indicate the order of processes or stacking. For example, "first" may be changed to "second "the" or "third" can be used as appropriate. The ordinal numbers described herein may not coincide with the ordinal numbers used to identify an aspect of the present invention. There are cases where this is the case.

[0026] In addition, in this specification, the terms "above" and "below" that indicate an arrangement are used to refer to the relationship between components. The positional relationship is used for convenience in describing the drawings. The relationship changes accordingly depending on the direction in which each configuration is depicted. The terms are not limited to those described above, and may be rephrased appropriately depending on the situation.

[0027] For example, in the present specification, it is explicitly stated that X and Y are connected. The cases are when X and Y are electrically connected and when X and Y are functionally connected. The case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification, etc. Therefore, the connection relationship is limited to a specific one, for example, the connection relationship shown in the figure or text. Connections other than those shown in the drawings or text are also disclosed in the drawings or text. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, etc.). , conductive film, layer, etc.).

[0028] In this specification, a transistor includes a gate, a drain, and a source. The drain terminal is a diode that has at least three terminals. Between the drain region or drain electrode and the source (source terminal, source region or source electrode) The channel forming region is formed in the channel. A current can be passed between the source and drain via the channel forming region. In this specification and the like, the channel formation region refers to a region through which current mainly flows.

[0029] In addition, the functions of the source and drain may differ depending on whether transistors of different polarities are used or the circuit In operation, when the direction of the current changes, the positions may be reversed. In the specification, the terms source and drain may be used interchangeably. do.

[0030] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is on, the gate electrode overlaps with the semiconductor (the part through which current flows). A source (source region or source electrode) in a region where the source is formed or a channel forming region This refers to the distance between the drain (drain region or drain electrode) and the transistor. In a transistor, the channel length does not necessarily have the same value in all regions. The channel length of the transistor may not be determined to a single value. In the above, the channel length is defined as any one value, maximum value, minimum value or is the average value.

[0031] The channel width is, for example, the width of the semiconductor (or transistor) in a top view of the transistor. The area where the gate electrode overlaps with the semiconductor (the part where current flows in the semiconductor when the transistor is on). In the channel forming region, the channel is formed in a direction perpendicular to the channel length direction. The length of the formation region. Note that in one transistor, the channel width is the entire region. In other words, the channel width of a transistor does not always take the same value. Therefore, in this specification, the channel width is determined based on the channel forming region. The value may be any one of the values, the maximum value, the minimum value or the average value.

[0032] In this specification and the like, depending on the structure of the transistor, the channel may not actually be formed. The channel width in the region where the transistor is The channel width shown in a top view of the star (hereinafter also referred to as the "apparent channel width") For example, if the gate electrode covers the side of the semiconductor, the effective When the channel width becomes larger than the apparent channel width and its effect cannot be ignored For example, in a transistor that is very small and has a gate electrode that covers the side of the semiconductor, The proportion of the channel formation region formed on the side may become large. In that case, the apparent The effective channel width is larger than the above channel width.

[0033] In such cases, it may be difficult to estimate the effective channel width through actual measurements. For example, to estimate the effective channel width from the design value, the shape of the semiconductor must be known. Therefore, if the shape of the semiconductor is not known accurately, Channel width is difficult to measure accurately.

[0034] In this specification, when the term "channel width" is used, it refers to the apparent channel width. In this specification, when the term "channel width" is used, it means an effective channel The channel length, channel width, effective channel width, apparent channel width, etc. The channel width and other parameters can be determined by analyzing cross-sectional TEM images, etc. can.

[0035] The impurities in a semiconductor are, for example, substances other than the main components that make up the semiconductor. Elements with a concentration of less than 0.1 atomic percent can be considered impurities. For example, This can cause problems such as an increase in the density of defect levels in semiconductors and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, , Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, oxide semiconductors There are transition metals other than the main component, such as hydrogen, lithium, sodium, silicon, These include boron, phosphorus, carbon, and nitrogen. Water can also act as an impurity. For example, impurities may cause oxygen vacancies (V O It may be written as .) may be formed.

[0036] In this specification and the like, silicon oxynitride refers to a material having a composition containing more oxygen than nitrogen. Silicon nitride oxide is a material that contains more oxygen than silicon. It has a high nitrogen content.

[0037] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." In addition, the term "conductor" can be replaced with "conductive film" or "conductive layer." In addition, the term "semiconductor" can be replaced with "semiconductor film" or "semiconductor layer." can.

[0038] In addition, in this specification, "parallel" means that two straight lines are at an angle of -10 degrees or more and 10 degrees or less. Therefore, it includes the case where the angle is between -5 degrees and 5 degrees. In addition, "approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state where two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it includes the case where the angle is between 85 degrees and 95 degrees. "Perpendicular" refers to two straight lines that form an angle between 60 degrees and 120 degrees.

[0039] In this specification, the term "metal oxide" refers to metals in a broad sense. Metal oxides are oxide insulators and oxide conductors (including transparent oxide conductors). ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used for the semiconductor layer of a transistor, Such a metal oxide may be called an oxide semiconductor. In this case, the transistor may be referred to as a transistor having a metal oxide or an oxide semiconductor. can be done.

[0040] In this specification and the like, normally off means that no potential is applied to the gate, or When a ground potential is applied to the gate, the drain current per 1 μm of channel width flows through the transistor. The input current is 1×10 -20 A or less, 1×10 at 85℃ -18 Below A , or 1×10 at 125°C -16 This means that it is A or lower.

[0041] (Embodiment 1) In this embodiment, a transistor 20 in this embodiment will be described with reference to FIGS. An example of a semiconductor device having 0 and a manufacturing method thereof will be described.

[0042] <Example of semiconductor device configuration> The structure of a semiconductor device including a transistor 200 will be described with reference to FIGS. 1A to 1D. 1A to 1D are top views and cross-sectional views of a semiconductor device including a transistor 200. FIG. 1A is a top view of the semiconductor device. FIG. 1B to FIG. 1D are 1B is a cross-sectional view of the body device shown in FIG. 1A at the portion indicated by the dashed line A1-A2. 1C is a cross-sectional view of transistor 200 taken along the channel length direction. 1A is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. FIG. 1D is a cross-sectional view in the width direction of the panel. In addition, in the top view of FIG. 1A, some elements are omitted for clarity. There are.

[0043] The semiconductor device in this embodiment is made up of an insulator 212 on a substrate (not shown) and an insulator 2 12, an insulator 214 on the insulator 214, an insulator 216 on the insulator 214, and an insulator 216 on the insulator 214 and an insulator A transistor 200 on an insulator 216, an insulator 254 on the transistor 200, and an insulator Insulator 280 on 254, insulator 282 on insulator 280, and insulator 282 on insulator 282. 283. The insulator 212, the insulator 214, the insulator 216, the insulator 254, the insulator The insulating layer 280, the insulator 282, and the insulator 283 function as an interlayer film. Conductor 240a and conductor 240b are electrically connected to the conductor 200 and function as plugs. In addition, the insulator 241 is in contact with the side surface of the conductor 240a that functions as a plug. a is provided, and an insulator 241b is provided in contact with the side surface of the conductor 240b which functions as a plug. In addition, a conductive layer is formed on the insulator 283, the conductor 240a, and the conductor 240b. A conductor 246a is provided which is electrically connected to the conductor 240a and functions as wiring. A conductor 246b is provided which is electrically connected to the conductor 240b and functions as wiring. An insulator 286 is provided on the conductor 246a, the conductor 246b, and the insulator 283. can be.

[0044] The insulators 254, 280, 282, and 283 are in contact with the side walls of the openings. An insulator 241a is provided on the conductor 240a, and the first conductor 240a is in contact with the side surface of the insulator 241a. A second conductor of the conductor 240a is provided on the inner side. In contact with the side walls of the openings of the insulators 254, 280, 282, and 283 An insulator 241b is provided, and a first conductive layer of the conductor 240b is in contact with a side surface of the insulator 241b. A second conductor of the conductor 240b is provided on the inner side. The height of the upper surface of the conductor 240a and the upper surface of the insulator 283 in the area overlapping with the conductor 246a The height of the upper surface of the conductor 240b and the height of the conductor 246b can be made approximately the same. The height of the upper surface of the insulator 283 in the region can be made to be approximately the same as that of the insulator 283. In the semiconductor device shown in FIG. 1, the first conductors of the conductors 240a and 240b are However, this embodiment is not limited to this configuration. For example, the conductor 240a and the conductor 240b may each be formed as a single layer, or The structure may have a laminated structure of three or more layers. In some cases, ordinal numbers are assigned to indicate the order of formation to distinguish them.

[0045] [Transistor 200] As shown in FIGS. 1A-1D, the transistor 200 includes an insulator 214 and / or The conductors 205 (conductors 205a and 205b) are disposed so as to be embedded in the insulator 216. conductor 205b), insulator 222 on insulator 216 and on conductor 205, and insulator 2 22, an insulator 224, an oxide 230a on the insulator 224, and an oxide 230a on the oxide 230a. The oxide 230b is covered with an oxide 243a, an oxide 243b, and an oxide 243c. 30c, conductor 242a on oxide 243a, and conductor 242b on oxide 243b. , an oxide 230d on the oxide 230c, an insulator 250 on the oxide 230d, and an insulator 2 Conductors 260 (conductors 260a and The oxide 230c is formed on the side of the oxide 243a. The side of the object 243b, the side of the conductor 242a, and the side of the conductor 242b are in contact with each other. , the insulator 282 includes the conductor 260, the insulator 250, the oxide 230d, the oxide 230c, and and contacts the upper surface of each of the insulators 280.

[0046] Insulator 280 and insulator 254 are provided with openings that reach down to oxide 230b. In the opening, an oxide 230c, an oxide 230d, an insulator 250, and a conductor 260 are formed. In addition, in the channel length direction of the transistor 200, the conductor 242a A conductor 242b is disposed between the oxide 243a and the conductor 242b and the oxide 243b. 60, an insulator 250, an oxide 230d, and an oxide 230c are provided. 250 has an area in contact with the side surface of the conductor 260 and an area in contact with the bottom surface of the conductor 260. In addition, the oxide 230c has a region in contact with the oxide 230b, a region in contact with the oxide 230d, and The region overlapping the side of the conductor 260 through the oxide 230d and the insulator 250, It has an area that overlaps with the bottom surface of the conductor 260 via the edge 250.

[0047] The oxide 230 is made up of an oxide 230a disposed on the insulator 224 and an oxide 230b. and a second oxide layer 230b disposed on the second oxide layer 230b, the second oxide layer 230b being at least partially oxide-coated. The oxide 230c is in contact with the oxide 230b, and the oxide 230 is disposed on the oxide 230c. d and

[0048] In the transistor 200, the oxide 230 is made up of oxide 230a, oxide 230b, The oxide 230c and the oxide 230d are stacked in four layers. The embodiment is not limited to this. For example, a single layer of oxide 230b, oxide 23 A two-layer structure of oxide 230a and oxide 230b, a two-layer structure of oxide 230b and oxide 230c, and an oxide A three-layer structure of oxide 230a, oxide 230b, and oxide 230c. 230b and oxide 230d, or a laminated structure of five or more layers. Alternatively, oxide 230a, oxide 230b, oxide 230c, and oxide 230 Each of d may have a laminate structure.

[0049] The conductor 260 functions as a first gate (also called a top gate) electrode. 205 functions as a second gate (also called a back gate) electrode. 250, insulator 224, and insulator 222 function as gate insulators. The conductor 242a serves as one of a source electrode or a drain electrode, and the conductor 242b serves as , which serves as the other of the source and drain electrodes. It serves as a formation region.

[0050] The transistor 200 includes an oxide 230 (oxide 230a, oxide The oxide 230b, oxide 230c, and oxide 230d) are provided with a metal oxide that functions as a semiconductor. It is preferable to use a semiconductor material other than the oxide semiconductor.

[0051] In addition, metal oxides that function as semiconductors must have a band gap of 2 eV or more. It is preferable that the band gap is 2.5 eV or more, and more preferable that the band gap is 2.5 eV or more. By using a thick metal oxide, the off-state current of a transistor can be reduced.

[0052] A transistor that uses an oxide semiconductor for a channel formation region has a leakage current when it is off. Since the current (off-state current) is extremely small, a semiconductor device with low power consumption can be provided. Since nitride semiconductors can be deposited using methods such as sputtering, they are ideal for the production of highly integrated semiconductor devices. The transistors can be used to form the semiconductor device.

[0053] The oxide 230 may be, for example, In-M-Zn having indium, element M, and zinc. Oxides (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, etc.) Sodium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lambda Tungsten, Cerium, Neodymium, Hafnium, Tantalum, Tungsten, Magnesium, Cobalt It is preferable to use a metal oxide such as one or more selected from the group consisting of gallium oxide, arsenic oxide, and the like. The oxide 230 is In-Ga oxide, In-Zn oxide, or indium oxide. This is also fine.

[0054] In a transistor using an oxide semiconductor, impurities and and oxygen deficiency (V O ) may cause electrical characteristics to fluctuate and reduce reliability. Examples of impurities in an oxide semiconductor include hydrogen, nitrogen, alkali metals, and alkali metals. These include earth metals, iron, nickel, silicon, etc.

[0055] In particular, hydrogen contained in oxide semiconductors reacts with oxygen that bonds with metal atoms to form HO, In addition, hydrogen atoms near the oxygen vacancies may form oxygen vacancies. The defect (hereinafter, V O H.) and generate electrons that act as carriers. In addition, some of the hydrogen may bond with oxygen that bonds with metal atoms to become carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen The transistor has a normally-on characteristic (a channel exists even when no voltage is applied to the gate electrode, and the transistor This tends to cause a current to flow through the transistor.

[0056] A defect in which hydrogen has entered an oxygen vacancy (V O H) can function as a metal oxide donor. However, it is difficult to quantitatively evaluate the defects. In some cases, the carrier concentration is used instead of the donor concentration. So, as a parameter of metal oxide, we consider not donor concentration but the state where no electric field is applied. In other words, the "carrier concentration" described in this specification may be used. " can be rephrased as "donor concentration." "Carrier concentration" can be rephrased as "carrier density."

[0057] From the above, hydrogen and oxygen vacancies are minimized in the channel formation region of the oxide semiconductor. Specifically, in the channel formation region of the oxide 230, Secondary ion mass spectrometry (SIMS) The hydrogen concentration obtained by CT is 1×10 20 atoms / cm 3 less than , preferably 1 x 10 19 atoms / cm 3 less than 5×10 18 ato ms / cm 3 less than 1×10 18 atoms / cm 3 Less than. In the channel formation region in the oxide semiconductor, the carrier concentration is reduced and the region becomes i-type (intrinsic). It is preferable that the polysaccharide is substantially i-type.

[0058] In the process of manufacturing a semiconductor device, a substrate on which a film is formed is removed from the device in which the film was formed. When the substrate is transported from one equipment to another, it may be exposed to the air environment. Impurities or moisture from the atmospheric environment may adhere to the film. Impurities or moisture attached to the film may be mixed into the oxide semiconductor in a later process, resulting in the oxide semiconductor There is a high possibility that the hydrogen concentration in the body will increase. A process for reducing or removing impurities or moisture adhering to the film, such as heat treatment, is performed. This may increase the number of defects and reduce the productivity of the semiconductor device.

[0059] Therefore, in the process of manufacturing the semiconductor device according to the present embodiment, the material or chemical composition When laminating films having different compositions, it is preferable to deposit the films successively. It is more preferable to form the films successively without exposing the films to the heat treatment. It is preferable that at least a part of the layer structure is continuously formed in the same apparatus, without being exposed to the atmosphere. It is more preferable to form the films continuously in the same equipment without forming the oxide film. The compound semiconductor and the layered structure provided in the vicinity thereof are successively formed without being exposed to the air environment. In this specification, the case where the films are continuously formed without being exposed to the air environment is considered. This method may also be simply referred to as continuous film formation.

[0060] For example, when a first film and a second film on the first film are continuously formed, By depositing the first and second films in succession without exposing them to the air, impurities from the air environment are prevented from being deposited on the first film. Therefore, impurities or moisture can be prevented from adhering to the channel. It is possible to suppress the inclusion of the oxide 230 in the formation region, and thus the transistor with good electrical properties can be obtained. In addition, impurities or moisture adhering to the film can be removed by heat treatment, etc. Reducing the number of steps required to reduce or eliminate the problem, or shortening the time required for such steps This allows the productivity of the semiconductor device to be improved. Therefore, the vicinity of the interface between the first film and the second film can be kept clean. In addition, the continuous film formation simplifies the manufacturing process of the semiconductor device. This makes it possible to improve the productivity of the semiconductor device.

[0061] The continuous film formation is not limited to a two-layer laminate structure, but can be applied to a three-layer or more laminate structure. For the continuous film formation, for example, a multi-chamber type apparatus may be used. In a multi-chamber system, different processing chambers are parallelly arranged in each of the processing chambers. This is preferable because it allows for continuous film formation. do.

[0062] Furthermore, in the semiconductor device having the transistor according to the present embodiment, The oxide film that becomes the oxide 230 including the oxide region is preferably formed by sputtering. The sputtering method is preferable because it is possible to form a film having a low hydrogen concentration. By forming the oxide film by sputtering, the hydrogen concentration in the channel formation region is Therefore, it is possible to fabricate a transistor with a low resistance. It can be suppressed.

[0063] In addition, the structure constituting the transistor other than the oxide 230 including the channel formation region For example, the hydrogen concentration in the oxide layer including the channel formation region is preferably as low as possible. A part of the structure constituting the transistor other than 230 is formed by using a sputtering method. This prevents hydrogen that may diffuse from the structure to the channel formation region. Therefore, a transistor having a channel formation region with a low hydrogen concentration can be manufactured.

[0064] In addition, the hydrogen concentration in the structure provided around the transistor is also as low as possible. It is preferable to reduce the hydrogen concentration in the structure provided around the transistor. This can prevent hydrogen from entering the transistor. For example, a structure provided around the transistor can be fabricated. A part of the film may be formed by sputtering.

[0065] Specifically, in the semiconductor device shown in FIGS. 1A to 1D, the insulator 212 and the insulator 21 4 and the insulator 216 are preferably formed successively, and are successively formed by a sputtering method. It is more preferable to perform the subsequent film formation. By performing the subsequent film formation, the insulating layer 212 and the insulating layer 2 14, impurities or moisture from the atmospheric environment can be prevented from adhering to the insulator 21. 2 and the insulator 214 and the vicinity of the interface between the insulator 214 and the insulator 216 The interface and its vicinity can be kept clean. This makes it possible to form a film with a low hydrogen concentration.

[0066] In addition, the insulator 222, the insulator 224, the oxide film that becomes the oxide 230a, the oxide 230b, The oxide film that becomes the oxide 243a and the oxide film that becomes the oxide 243b are successively formed. It is preferable to form the films successively by a sputtering method. By this, the oxide film on the insulator 222, the insulator 224, the oxide film that becomes the oxide 230a, and Prevent impurities or moisture from the atmospheric environment from adhering to the oxide film that will become oxide 230b. The interface between the insulator 222 and the insulator 224 and the vicinity of the interface, the insulator 224 and The interface with the oxide film that becomes the oxide 230a and the vicinity of the interface, the oxide film that becomes the oxide 230a, The interface with the oxide film that becomes the oxide 230b and the vicinity of the interface, and the oxide film that becomes the oxide 230b The interface and the vicinity of the interface between the oxide film and the oxide film that becomes the oxide 243a and the oxide 243b are In addition, the sputtering method can be used to produce a film with a low hydrogen concentration. In particular, the insulator 224, as well as the oxide 243a and the oxide 243b can be formed. The oxide films 43b are in contact with the oxides 230a and 230b, respectively. The insulator 224 and the oxide film that becomes the oxide 243a and the oxide 243b are formed in the presence of hydrogen. It is preferable that the degree of the light is reduced.

[0067] The conductive film that becomes the conductor 242a and the conductor 242b is formed by removing the oxide 243a and the oxide After the oxide film that becomes the oxide 243b is formed, the oxide film may be formed continuously. It is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film, and the oxide The interface between the film and the conductive film and the vicinity of the interface can be kept clean. By using this deposition method, a film with a low hydrogen concentration can be formed.

[0068] In addition, it is preferable that the insulating film that becomes the insulator 254 and the insulator 280 be continuously formed. By continuously forming the films, impurities or moisture from the atmospheric environment adhere to the insulator 254. This can prevent the interface between the insulator 254 and the insulating film that becomes the insulator 280 and the interface The vicinity can be kept clean. In addition, the hydrogen concentration is low by using the sputtering method. In particular, the insulator 254 is made of oxide 230a and oxide 230b. Since it comes into contact with 30b, it is preferable that the hydrogen concentration is reduced in this manner.

[0069] The insulator 282 and the insulator 283 are preferably formed successively. This prevents impurities or moisture from the atmospheric environment from adhering to the insulator 282. As a result, the interface between the insulator 282 and the insulator 283 and the vicinity of the interface can be kept clean. In addition, by using the sputtering method, it is possible to form a film with a low hydrogen concentration. do.

[0070] The conductive film and insulator that form the conductor 205 (conductor 205a and conductor 205b) The insulating film that becomes 250, the conductive film that becomes the conductor 242a and the conductor 242b, the conductor 260 The conductive film (conductor 260a and conductor 260b) is also formed by sputtering. The film may be formed by using the above method.

[0071] With the above structure, a transistor with a low hydrogen concentration can be manufactured. For example, The hydrogen concentration of the transistor 200 measured by SIMS was 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 It has an area that is less than Specifically, the region includes an insulator 224, an oxide 230a, an oxide 230b, and an oxide 230c. That is, the insulator 224, the oxide 230a, the oxide 230b, and the oxide c are included. At least one of the compounds 230c has a hydrogen concentration of 1×10 20 a toms / cm 3 Less than 1 x 10 19 atoms / cm 3 Areas where The region is not limited to the inside of the transistor 200, but may be the periphery of the transistor 200. In some cases, the structure may include an insulator 280. .

[0072] As a result, a semiconductor device with high productivity can be provided. It is possible to provide a semiconductor device having little variation in the characteristics. It is also possible to provide a semiconductor device having good electrical characteristics. can.

[0073] The oxide 230 preferably has a layered structure of multiple oxide layers with different chemical compositions. In addition, the oxide 230 is a mixture of a plurality of oxides having a common element other than oxygen (main component). It is preferable that the layer has a laminated structure.

[0074] Specifically, in the metal oxide used for the oxide 230a or the oxide 230d, In The atomic ratio of element M to the metal oxide used in oxide 230b or oxide 230c is It is preferable that the atomic ratio of element M to In is larger than the atomic ratio of element M to In in the above formula. The larger the atomic ratio of M, the easier it is to suppress the diffusion of impurities or oxygen. By having the oxide 230a under the oxide 230b, the oxide 230a is formed below the oxide 230a. The diffusion of impurities from the structure to the oxide 230b can be suppressed. By having an oxide 230d on the object 230c, the oxide 230d is formed above the oxide 230d. The diffusion of impurities from the structure into the oxide 230c can be suppressed.

[0075] In other words, the element in the metal oxide used for the oxide 230b or the oxide 230c The atomic ratio of In to M is the same as that of the metal oxide used for the oxide 230a or the oxide 230d. In this case, the atomic ratio of In to the element M is preferably larger than that of the carrier. The main path of the oxide 230 is through the oxide 230b, the oxide 230c or its vicinity, for example, the oxide 230b. The interface between the oxide 230b and the oxide 230c. However, because they have a common element other than oxygen (as the main component), oxide 230b and oxide 2 The defect density at the interface with 30c can be reduced, which reduces the capacitance caused by interface scattering. The effect on rear conduction is small, and a high on-current can be obtained.

[0076] In order to make the oxide 230c the main path of the carriers, the oxide 230c is The atomic ratio of indium to the main component metal element is It is preferable that the atomic ratio of indium to the metal element is greater than the atomic ratio of indium to the metal element. By using a metal oxide with a high content of , the on-current of the transistor is can be increased.

[0077] In order to make the oxide 230c the main carrier path, the oxide 230c must be in the conduction band below the conduction band. The edge is lower than the vacuum level of the conduction band minimum of the oxide 230a, the oxide 230b, and the oxide 230d. In other words, the electron affinity of the oxide 230c is It is preferable that the electron affinity of the oxide 230a, the oxide 230b, and the oxide 230d is greater than that of the oxide 230a. It is nice.

[0078] It is preferable that the oxide 230b and the oxide 230c each have crystallinity. The oxide 230b and the oxide 230c are the CAAC-OS (c-axi s aligned crystalline oxide semiconductor It is preferable to use the oxide 230d. Also, the oxide 230d may have a crystalline structure. .

[0079] By using CAAC-OS for the oxide 230b and the oxide 230c, an oxide semiconductor It is possible to reduce impurities and oxygen deficiencies in the areas where channels are formed throughout the body. This suppresses fluctuations in electrical characteristics, realizing stable electrical characteristics and reliability. It is possible to provide a transistor having improved characteristics.

[0080] Also, the extraction of oxygen from the oxide 230b by the source electrode or the drain electrode This can suppress the oxygen from being removed from the oxide 230b even when a heat treatment is performed. Since the transistor 200 can be manufactured at high temperatures ( It is stable against the so-called thermal budget.

[0081] In addition, CAAC-OS has the property of easily transferring oxygen in the direction perpendicular to the c-axis of the CAAC structure. Therefore, the oxygen contained in the oxide 230c is efficiently supplied to the oxide 230b. It is possible.

[0082] CAAC-OS has a highly crystalline and dense structure and is free of impurities and defects (oxygen vacancies). In particular, after the formation of the metal oxide, the metal oxide is polycrystallized. By heat-treating at a temperature that does not cause the CAA This allows the C-OS to have a more crystalline and dense structure. By increasing the density of the C-OS, the diffusion of impurities or oxygen in the CAAC-OS can be suppressed. It is possible to further reduce the

[0083] Here, an enlarged view of the vicinity of the channel formation region in FIG. 1B is shown in FIG. 2. The oxide 230 is then formed into a region 234 which functions as a channel forming region of the transistor 200. and a region that functions as a source region or a drain region and is provided so as to sandwich the region 234. The region 234 has a conductive layer 236a and a conductive layer 236b. 60. A conductor 242a and a conductor 242b are provided on the oxide 230b. The conductor 242a in the region 236a and the conductor 242b in the region 236b are Nearby, a region of lower resistance is formed.

[0084] The regions 236a and 236b, which function as source and drain regions, are The carrier concentration is increased due to low concentration of hydrogen, nitrogen, metal elements, and other impurities. In other words, the regions 236a and 236b are regions in which the resistance is reduced. 34, this region has a higher carrier concentration and a lower resistance. The region 234 acting as a filter has a higher oxygen concentration than the regions 236a and 236b. Due to low impurity concentration, the carrier concentration is low and the resistance is high. Between the region 234 and the region 236a (region 236b), the oxygen concentration is b) is equal to or higher than the oxygen concentration in region 234; A region lower than this may be formed.

[0085] Also, in FIG. 2, the width of the region 234 in the channel length direction is the same as the width of the conductor 260. However, the present embodiment is not limited to this. In some cases, the width of region 234 may be narrower or wider than the width of conductor 260 .

[0086] In addition, it may be difficult to clearly detect the boundaries between the regions of the oxide 230. The concentrations of impurities such as hydrogen, nitrogen, and metal elements detected in each region are graded by region. The change is not limited to a simple change, but may be continuous within each region. The closer the region is to the above, the lower the concentration of impurities such as hydrogen, nitrogen, and metal elements. .

[0087] In order to increase the oxygen concentration in the region 234, the oxygen desorption An insulator containing oxygen that causes the oxide to be generated (hereinafter, sometimes referred to as excess oxygen) is provided, and heat treatment is performed. In this case, the insulator may be configured to supply oxygen to the oxide semiconductor. The oxygen vacancies in the channel formation region of the nitride semiconductor are repaired by the supplied oxygen. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide semiconductor. This allows the hydrogen to be removed as H2O (dehydration). Semiconductor V O The formation of H can be suppressed.

[0088] However, if an excessive amount of oxygen is provided to the source or drain region, The carrier concentration in the source or drain region is reduced, resulting in a reduction in the on-current of the transistor 200. In addition, the source region or drain region may be damaged. The oxygen supplied to the drain region varies across the substrate surface, causing semiconductor devices with transistors to This results in variations in the characteristics of the device.

[0089] Therefore, in the oxide semiconductor, the region 234 functioning as a channel formation region is It is preferable that the carrier concentration is reduced to be i-type or substantially i-type. Regions 236a and 236b function as source and drain regions. It is preferable that the concentration is high and the oxide semiconductor region 234 is n-type. and not to supply an excessive amount of oxygen to the regions 236a and 236b. It is preferable that

[0090] For example, the insulator 254 can be formed by a sputtering method. Oxygen can be injected. The oxygen injected into the insulator 224 is then transported through the oxide 230c. 230b. This causes the oxide 230 that occupies most of the region 234 to c, and selectively supplying oxygen to a region of the oxide 230b adjacent to the oxide 230c. can be done.

[0091] In addition, the oxide 230b is made of CAAC-OS having a dense structure as described above. This can reduce the diffusion of impurities and oxygen in the oxide 230b. Thus, the oxygen supplied to the region 234 of the oxide 230b is converted into the oxygen supplied to the region 236a of the oxide 230b. and can reduce diffusion into region 236b.

[0092] In this manner, oxygen is selectively supplied to the region 234 that functions as a channel forming region. In this way, the region 234 is made i-type or substantially i-type, and the source region or drain region is made i-type. The oxygen diffusion into the region 236a and the region 236b that function as the region is suppressed, and the region 23 6a and region 236b can be maintained as n-type. The variation in the electrical characteristics of the transistor 200 is suppressed, and the variation in the electrical characteristics of the transistor 200 within the substrate surface is suppressed. can be suppressed.

[0093] As a parameter for evaluating the reliability of a transistor, for example, Shift measured by GBT (Gate Bias Temperature) stress test Vsh is the drain current (Id) minus the gate voltage of the transistor. (Vg) The tangent to the point where the slope of the curve is maximum is Id=1pA The change in Vsh is defined as Vg at which the line crosses the line. The change in Vsh is expressed as ΔVsh.

[0094] In the +GBT stress test of a transistor, ΔVsh becomes negative over time. Also, ΔVsh may fluctuate in the negative direction (e.g., in the negative direction). In this specification, the term "positive" refers to a state in which the positive and negative directions of the voltage are changed. In this case, the above behavior is called the jagged behavior of ΔVsh in the +GBT stress test. There is a match.

[0095] The oxide 230c may be a metal oxide that does not contain the element M as a main component or a metal oxide that contains a small proportion of the element M. For example, by using a low-temperature metal oxide, ΔVsh can be reduced and the jagged behavior of ΔVsh can be suppressed. This can improve the reliability of the transistor.

[0096] The oxide 230d is a metal element constituting the metal oxide used in the oxide 230c. It is preferable that the metal element contains at least one of the above metal elements, and it is more preferable that the metal element contains all of the above metal elements. For example, the oxide 230c may be an In-M-Zn oxide, an In-Zn oxide, or an oxide. Indium is used as the oxide 230d, and In-M-Zn oxide, M-Zn oxide, or Alternatively, an oxide of element M may be used. This allows the oxide 230c and the oxide 230d to be The defect state density at the interface can be reduced.

[0097] In addition, the oxide 230d is a metal that suppresses the diffusion or permeation of oxygen more than the oxide 230c. It is preferable that the oxide 230d is provided between the insulator 250 and the oxide 230c. By providing the insulating layer 230c, oxygen contained in the oxide 230c or the insulator 280 is diffused into the insulator 250. Therefore, the oxygen can be prevented from diffusing through the oxide 230c. The oxygen can be efficiently supplied to the oxide 230b. This allows the conductor 260 to be prevented from being oxidized.

[0098] In addition, in the metal oxide used for oxide 230d, the I The atomic ratio of n is the main component metal element in the metal oxide used for oxide 230c. By making the atomic ratio of In smaller than that of In, the diffusion of In into the insulator 250 is suppressed. The insulator 250 functions as a gate insulator, so that In is 50, it will cause the transistor characteristics to deteriorate. By providing an oxide 230d between the insulating material 250 and the insulating layer 250, a highly reliable semiconductor device can be provided. It becomes possible to do so.

[0099] Here, the oxides 230a, 230b, 230c, and 230d are In other words, the conduction band edge changes gradually at the junction. The conduction band minimum at the junction of the oxide 230b, the oxide 230c, and the oxide 230d is In order to achieve this, the oxide 230a and oxide 230b, the interface between oxide 230b and oxide 230c, and The defect level density of the mixed layer formed at the interface between the oxide 230c and the oxide 230d is reduced. It is good.

[0100] For example, oxide 230a and oxide 230b, oxide 230b and oxide 230c, oxide 230c and oxide 230d have a common element other than oxygen as the main component, so that defects For example, the oxide 230b is an In-MZ layer. In the case of n-oxide, oxide 230a, oxide 230c, and oxide 230d are In -M-Zn oxide, M-Zn oxide, oxide of element M, In-Zn oxide, indium oxide It is a good idea to use something like this.

[0101] Specifically, the oxide 230a is In:M:Zn=1:3:4 [atomic ratio] or or a composition close to that, or In:M:Zn=1:1:0.5 [atomic ratio] or close to that A metal oxide having a composition close to the above may be used. 1:1:1 [atomic ratio] or a composition close to that, or In:M:Zn=4:2:3 [ The metal oxide having a composition of 230c or a composition close to the atomic ratio may be used. The composition is In:M:Zn=4:2:3 [atomic ratio] or close thereto, In:M: Zn=5:1:3 [atomic ratio] or a composition close to that, or In:M:Zn=10: Uses metal oxide or indium oxide with a composition of 1:3 [atomic ratio] or close to that. In addition, the oxide 230d may have an atomic ratio of In:M:Zn=1:3:4. or a composition close thereto, M:Zn=2:1 [atomic ratio] or a composition close thereto, or Metal oxides with a composition of M:Zn=2:5 [atomic ratio] or close to that, or elements M The oxide may be used. The nearby composition includes the range of the desired atomic ratio by ±30%. It is also preferable to use gallium as the element M.

[0102] The oxide 230a, the oxide 230b, the oxide 230c, and the oxide 230d are formed as described above. By forming the oxide 230a and the oxide 230b, the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230b are The defect density at the interface between oxide 230c and oxide 230d. Therefore, the effect of interface scattering on carrier conduction is reduced. Thus, the transistor 200 can achieve a large on-current and high frequency characteristics.

[0103] In addition, in a cross-sectional view in the channel length direction of the transistor, a groove is provided in the oxide 230b. It is preferable to fill the groove with an oxide 230c having a CAAC-OS. At this time, the oxide 230c is disposed so as to cover the inner wall (side wall and bottom surface) of the groove. .

[0104] Also, it is preferable that the depth of the grooves in the oxide 230b approximately coincides with the thickness of the oxide 230c. In other words, the upper surface of the oxide 230c in the region overlapping with the oxide 230b is preferably 230b and the oxide 243a or 243b. For example, when the bottom surface of the insulator 222 is taken as a reference, the oxide 230b and the oxide 24 3a or oxide 243b and the height of the interface between oxide 230c and oxide 230d. The height difference is preferably equal to or less than the thickness of the oxide 230c. It is more preferable that it is half or less.

[0105] By using the above configuration, the transistor V O Reduces the effects of defects and impurities such as H By reducing the thickness of the oxide 230c, a channel can be formed in the oxide 230c. Furthermore, the variation in transistor characteristics is small. Therefore, it is possible to provide a semiconductor device with good reliability.

[0106] In addition, impurities at the interface between the oxide 230b and the oxide 230c and in the vicinity thereof are reduced. It is preferred that the element M is reduced or eliminated. If the element M is not aluminum, it is especially preferred that the element M is aluminum. Impurities such as aluminum and silicon affect the crystallinity or the crystallinity of the oxide 230c and the oxide 230b. Since hinders the improvement of the c-axis orientation, it is preferable to reduce or eliminate it. For example, , aluminum atoms at and near the interface between oxide 230b and oxide 230c The concentration of is preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, and more preferably 1.0 atomic % or less. % or less is even more preferable.

[0107] In addition, impurities such as aluminum and silicon hinder the improvement of crystallinity or c-axis orientation. The amorphous oxide semiconductor (a-like OS) The region of the metal oxide that became a non-CAAC In the non-CAAC region, it is called the V O A large amount of H is formed, and the transistor Therefore, the non-CAAC region is likely to be reduced or eliminated. It is preferable that the ion exchange layer is removed.

[0108] In contrast, in the oxide 230b and the oxide 230c having the CAAC structure, Since a dense crystal structure is formed, V O H becomes less stable. In the oxygen addition process described below, excess oxygen is supplied to the oxide 230b and the oxide 230c. By this, V in oxide 230b and oxide 230c O H, and V O To reduce In this way, the oxide 230b and the oxide 230c have a CAAC structure. In this way, it is possible to suppress the transistor from becoming normally on.

[0109] In FIG. 2, the side of the opening in which the conductor 260 and the like are embedded includes the groove of the oxide 230b. First, the configuration in which the oxide 230b is approximately perpendicular to the surface on which it is formed has been shown. The shape of the opening is not limited to this. It may also have the shape of:

[0110] The oxides consisting of the non-CAAC regions are oxide 230b, oxide 243a, and oxide 243b. The oxide 23 may be formed so as to be surrounded by the oxide 230c and the oxide 230d. In some cases, it may be formed sandwiched between oxide 230b and oxide 230c.

[0111] In addition, as shown in FIG. 1C, in a cross-sectional view of the transistor 200 in the channel width direction, The oxide 230b may have a curved surface between the side surface and the top surface of the oxide 230b. The end of the side surface and the end of the top surface may be curved (hereinafter, also referred to as rounded). .

[0112] The radius of curvature of the curved surface is greater than 0 nm, and the conductor 242a or the conductor 242b The thickness of the oxide 230b in the region overlapping the upper surface of the oxide 230b is smaller than the thickness of the oxide 230b in the region overlapping the upper surface of the oxide 230b. It is preferable that the length of the curved surface is less than half the length of the region not having the curved surface. Specifically, the diameter is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm. More preferably, the thickness is 2 nm or more and 10 nm or less. The insulating material 250 and the conductor 260 formed in the process can be improved in coverage of the groove portion. In addition, the length of the region of the upper surface of the oxide 230b that does not have the curved surface can be prevented from decreasing. This can suppress the decrease in the on-state current and mobility of the transistor 200. A semiconductor device having good electrical characteristics can be provided.

[0113] The oxide 230c may be provided for each transistor 200. The oxide 230c of the transistor 200 and the oxide 230b of the transistor 200 adjacent to the transistor 200 The oxide 230c of the transistor 200 may not be in contact with the oxide 230c. and the oxide 230c of the transistor 200 adjacent to the transistor 200. In other words, the oxide 230c may separate the transistor 200 from the It is also possible to adopt a configuration in which the second transistor 200 is not disposed between the adjacent transistors 200 .

[0114] In a semiconductor device in which a plurality of transistors 200 are arranged in a channel width direction, By adopting the above configuration, the oxide 230c is independently provided in the transistor 200. Therefore, the transistor 200 and the transistor 2 adjacent to the transistor 200 00, the occurrence of a parasitic transistor is suppressed, and a leakage path along the conductor 260 is prevented. Therefore, it is possible to suppress the occurrence of defects. Alternatively, a semiconductor device that can be highly integrated can be provided.

[0115] For example, transistors 200 facing each other in the channel width direction The side edge of the oxide 230c of the transistor 200 and the transistor adjacent to the transistor 200 If the distance between the side end of the oxide 230c of the capacitor 200 and the oxide 230c is represented as L1, L1 is set to be greater than 0 nm. In addition, in the channel width direction of the transistor 200, the transistors facing each other The side edge of the oxide 230a of the transistor 200 and the transistor adjacent to the transistor 200 If the distance between the side end of the oxide 230a of the transistor 200 and the side end of the oxide 230a is represented as L2, the L The value of the ratio (L1 / L2) is preferably greater than 0 and less than 1, more preferably 0.1 or less. The L2 is preferably from 0.2 to 0.8. The side edge of the oxide 230b of the transistor 200 and the It may be the distance between the side edges of the oxide 230b of the adjacent transistor 200.

[0116] By reducing the ratio of L1 to L2 (L1 / L2), the oxide 230c Between a transistor 200 and a transistor 200 adjacent to the transistor 200 Even if the non-placed region is misaligned, the oxide 230c of the transistor 200 and the The oxide 230c of the transistor 200 adjacent to the transistor 200 is separated. This can be done.

[0117] In addition, by increasing the ratio of L1 to L2 (L1 / L2), the transistor Even if the distance between the transistor 200 and the transistor 200 adjacent to the transistor 200 is narrowed, This allows the minimum processing dimension to be secured, facilitating further miniaturization and high integration of semiconductor devices. It is possible to plan this.

[0118] The conductor 260 and the insulator 250 are shared between adjacent transistors 200. That is, the conductor 260 of the transistor 200 may be used The conductor 260 of the adjacent transistor 200 is continuous with the conductor 260 of the adjacent transistor 200. In addition, the insulator 250 of the transistor 200 is It has a region that is continuous with the insulator 250 of the transistor 200 .

[0119] In addition, by adopting the above-mentioned configuration, the oxide 230d is a transistor 200 and The transistor 200 has a region in contact with the insulator 224 between the adjacent transistors 200. The oxide 230d of the transistor 200 is adjacent to the transistor 200. The oxide 230d of the transistor 200 may be separated from the oxide 230d of the transistor 200. 250 is a transistor 200 and a transistor 20 adjacent to the transistor 200 0, there is a region in contact with the insulator 224.

[0120] Insulator 212, insulator 214, insulator 254, insulator 282, insulator 283, and insulator The insulator 286 is a barrier for impurities such as water and hydrogen to enter the transistor 200 from the substrate side or the top surface of the transistor 200. It is preferable that the insulating film functions as a barrier insulating film that suppresses diffusion of the insulating film from the outside into the transistor 200. Therefore, the insulators 212, 214, 254, 282, and The body 283 and the insulator 286 are hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, Function to suppress the diffusion of impurities such as nitrogen oxide molecules (N2O, NO, NO2, etc.) and copper atoms It is preferable to use an insulating material having the above properties (which is difficult for the impurities to permeate). It has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use an insulating material that is difficult for oxygen to permeate.

[0121] In this specification, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the term "barrier property" refers to a function of suppressing the diffusion of a corresponding substance (i.e., low permeability). Alternatively, the corresponding substance is captured and fixed (also called gettering). (c) Function.

[0122] For example, silicon nitride or the like is used as the insulator 212 and the insulator 283. 214, insulator 254, and insulator 282 may be made of aluminum oxide or the like. This is preferable because impurities such as water and hydrogen can penetrate the insulators 212 and 214. It is possible to suppress diffusion from the substrate side to the transistor 200 side through the Oxygen contained in the insulator 224 etc. is transferred to the substrate through the insulator 212 and the insulator 214. In this way, the transistor 200 can be prevented from being diffused to the outside by water, hydrogen, etc. The insulators 212 and 214 have the function of suppressing the diffusion of impurities and oxygen. It is preferable to have a structure surrounded by edge 254, insulator 282, and insulator 283.

[0123] It is also preferable to reduce the resistivity of the insulators 212, 283, and 286. For example, the resistivity of the insulator 212, the insulator 283, and the insulator 286 may be 1×1013 By setting the resistance to Ωcm, the processing using plasma, etc. in the semiconductor device manufacturing process can be performed. In the embodiment, the insulator 212, the insulator 283, and the insulator 286 are 242a, conductor 242b, conductor 260, conductor 246a, or conductor 246b. In some cases, it may be possible to reduce the charge-up. The resistivity of the insulator 286 is preferably greater than 1×10 10 Ωcm or more 1×10 15 Ωcm or less Let us assume that.

[0124] The insulators 216 and 280 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. For example, the insulator 216 and the insulator 280 may be made of silicon oxide or silicon oxynitride. Silicon, silicon oxide nitride, silicon nitride, silicon oxide doped with fluorine, carbon doped Silicon oxide doped with carbon and nitrogen, silicon oxide with vacancies In particular, silicon oxide and silicon oxynitride are thermally stable. In particular, silicon oxide, silicon oxynitride, and silicon oxide having voids are preferred. Such materials are preferred because they can easily form regions containing oxygen that is desorbed by heating. I wish.

[0125] The conductor 205 (the conductor 205a and the conductor 205b) serves as a second gate electrode. In this case, the potential applied to the conductor 205 may be changed to the potential applied to the conductor 260. By changing the threshold voltage of the transistor 200 independently of the potential of the transistor 202, In particular, by applying a negative potential to the conductor 205, This makes it possible to increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 increases the conductor current more than not applying a negative potential. When the potential applied to the body 260 is 0 V, the drain current can be reduced.

[0126] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260 .

[0127] As shown in FIG. 1A, the conductor 205 is a conductor 242a of the oxide 230 and a conductor It is preferable that the area is larger than the area that does not overlap with the conductive material 242b. As shown in FIG. 1, the conductor 205 intersects with the channel width direction of the oxide 230a and the oxide 230b. It is preferable that the oxide 2 extends beyond the outer edge of the oxide film. On the outer side of the side surface of the channel width direction of the semiconductor device 30, the conductor 205 and the conductor 260 are It is preferable that the first gate electrode and the second gate electrode overlap each other via an insulator. The electric field of the conductor 260 acting as an electrode and the electric field of the conductor 20 acting as a second gate electrode The electric field of 5 can electrically surround the channel forming region of oxide 230. In this specification, the electric field of the first gate and the second gate forms a channel forming region. The structure of a transistor that electrically surrounds the region is called a surrounded channel. This is called the S-channel structure.

[0128] In this specification, a transistor having an S-channel structure is a transistor having a pair of gates. The electric field of one and the other of the transistor electrodes electrically surrounds the channel forming region. The S-channel structure disclosed in this specification is a fin type structure. The S-channel structure is different from the planar structure. In other words, the transistor is less susceptible to short channel effects. It is possible.

[0129] As shown in FIG. 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided under the conductor 205. Also, the conductor 205 does not necessarily have to be provided for each transistor. For example, the conductor 205 may be shared by multiple transistors. stomach.

[0130] Here, the conductor 205a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, an oxide, It has the function of suppressing the diffusion of impurities such as nitrogen molecules (N2O, NO, NO2, etc.) and copper atoms. It is preferable to use a conductive material that can absorb oxygen (e.g., oxygen atoms, oxygen molecules, etc.). It is preferable to use a conductive material having a function of suppressing the diffusion of at least one of the above.

[0131] By using a conductive material having a function of suppressing the diffusion of oxygen for the conductor 205a, Therefore, it is possible to prevent the conductor 205b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing the above include tantalum, tantalum nitride, and ruthenium. It is preferable to use ruthenium, ruthenium oxide, or the like. The conductive material may be a single layer or a multilayer. For example, the conductive material 205a may be made of tantalum, nitride, or the like. Lamination of tantalum oxide, ruthenium, or ruthenium oxide with titanium or titanium nitride; You may do so.

[0132] The conductor 205b is a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205b is illustrated as a single layer, it may have a laminated structure. For example, a laminate of titanium or titanium nitride and the conductive material may be used. .

[0133] In the transistor 200, the conductor 205 is made up of a conductor 205a and a conductor 205b. However, the present embodiment is not limited to this. For example, the conductor 205 may be configured as a single layer or a laminated structure of three or more layers. When the structure has a layered structure, the layers may be distinguished by giving ordinal numbers in the order of formation.

[0134] The insulator 222 suppresses the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). In addition, the insulator 222 preferably has a function of suppressing oxygen (for example, oxygen atom, It is preferable that the material has a function of suppressing the diffusion of at least one of oxygen molecules. For example, The insulator 222 inhibits the diffusion of hydrogen and / or oxygen more than the insulator 224. It is preferable that the function be

[0135] The insulator 222 is made of one or both of aluminum and hafnium, which are insulating materials. It is recommended to use an insulator containing oxide. The insulator containing oxide has a barrier property against oxygen, hydrogen, and water. Examples of the oxides include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium. It is preferable to use materials such as hafnium aluminate. When the insulating body 222 is formed, the insulating body 222 prevents oxygen from being released from the oxide 230 to the substrate side, A layer that suppresses the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Therefore, by providing the insulator 222, impurities such as hydrogen can be prevented from entering the transistor. 200 and suppress the formation of oxygen vacancies in the oxide 230. In addition, the conductor 205 reacts with the oxygen contained in the insulator 224 and the oxide 230. This can prevent the above from happening.

[0136] Alternatively, the insulator may be, for example, aluminum oxide, bismuth oxide, or germanium oxide. , niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, oxide Zirconium may be added. Alternatively, these insulators may be nitrided. The insulator 222 may be silicon oxide, silicon oxynitride, or silicon nitride. may be used in a laminated form.

[0137] The insulator 222 may be, for example, aluminum oxide, hafnium oxide, tantalum oxide, Zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrT Insulating materials, including so-called high-k materials such as (Ba,Sr)TiO3 (BST) The insulator may be a single layer or a multilayer. However, thinning the gate insulator may cause problems such as leakage current. By using a high-k material as an insulator that functions as a barrier, the thickness of the This makes it possible to reduce the gate potential during transistor operation.

[0138] It is preferable that the insulator 224 in contact with the oxide 230 desorbs oxygen when heated. For example, the insulator 224 may be made of silicon oxide, silicon oxynitride, or the like. By providing an insulator containing the compound in contact with the oxide 230, oxygen vacancies in the oxide 230 are reduced. This can reduce the resistance of the transistor 200 and improve the reliability of the transistor 200.

[0139] Specifically, the insulator 224 is a region where oxygen is present in excess of the stoichiometric composition ( It is preferable to use an insulating material containing an excess oxygen region (hereinafter, also referred to as an excess oxygen region) or an excess oxygen. Excess oxygen regions or oxide films containing excess oxygen are called TDS (Thermal Deso rption spectroscopy analysis revealed that the amount of desorbed oxygen molecules was 1.0 × 10 18 molecules / cm 3 More than 1.0×10 19 Molecules / cm 3 More preferably, 2.0×10 19 molecules / cm 3 That's all. or 3.0×10 20 molecules / cm 3 The oxide film is as described above. The surface temperature of the membrane during the TDS analysis is 100°C to 700°C or 100°C to 400°C. A range of 00°C or less is preferred.

[0140] In addition, a heat treatment is performed while the insulator having the excess oxygen region is in contact with the oxide 230, One or more of microwave processing and / or RF processing may be performed. By carrying out the treatment, the water or hydrogen in the oxide 230 can be removed. A part of the conductor 242a or conductor 242b is diffused or captured (also called gettered). (c) may be used.

[0141] The microwave treatment may be carried out, for example, using a device having a power source that generates high-density plasma, or For example, it is preferable to use an apparatus having a power source for applying RF to the substrate side. By using a gas containing oxygen and high-density plasma, high-density oxygen radicals are generated. By applying RF to the substrate side, oxygen laminations generated by high-density plasma can be It is possible to efficiently introduce the hydroxide into the oxide 230 or into the insulator adjacent to the oxide 230. The microwave treatment can be carried out at a pressure of 133 Pa or more, preferably 200 Pa or less. More preferably, the pressure is 400 Pa or more. For example, oxygen and argon are used as the gases to be introduced into the It is recommended to carry out microwave treatment with an Ar+Ar ratio of 50% or less, preferably 10% to 30%. stomach.

[0142] In addition, by performing an oxygen addition process on the oxide 230, oxygen vacancies in the oxide 230 can be filled by the supply of oxygen. The oxygen in the oxide 230 can promote the repair reaction. The remaining hydrogen reacts with the supplied oxygen, removing the hydrogen as H2O (desorption). This converts the hydrogen remaining in the oxide 230 into oxygen vacancies. Recombined to V O The formation of H can be suppressed.

[0143] Each of the insulators 222 and 224 has a laminated structure of two or more layers. In this case, the laminated structure is not limited to the same material, and may be made of different materials. It may also have a layered structure.

[0144] The oxide 243a and the oxide 243b preferably have a function of suppressing oxygen permeation. The conductor 242a (conductor 242b) functioning as a source electrode or a drain electrode is preferably Between the oxide 230b and the oxide 243a (oxide 243b) is formed a layer having a function of suppressing oxygen permeation. 3b) is disposed between the conductor 242a (conductor 242b) and the oxide 230b. This is preferable because the electrical resistance of the transistor 20 is reduced. The electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved. When the electrical resistance between the body 242a (the conductor 242b) and the oxide 230b can be sufficiently reduced, The oxide 243a (oxide 243b) may not be provided.

[0145] The oxide 243a and the oxide 243b may be a metal oxide having an element M. In particular, the element M may be aluminum, gallium, yttrium, or tin. The oxide 243a and the oxide 243b have a higher concentration of element M than the oxide 230b. It is preferable to use gallium oxide as the oxide 243a and the oxide 243b. In addition, the oxide 243a and the oxide 243b may be an In-M-Zn oxide or the like. Specifically, the oxide 243a and the oxide 243b may be made of a metal oxide. In the metal oxide, the atomic ratio of element M to In is It is preferable that the atomic ratio of element M to In in the oxide is larger than that of element In. The thickness of the oxide 243b and the oxide 243a is preferably 0.5 nm or more and 5 nm or less. The thickness is preferably 1 nm or more and 3 nm or less, and more preferably 1 nm or more and 2 nm or less. It is preferable that the oxide 243a and the oxide 243b have crystallinity. In addition, when the oxide 243b has crystallinity, the release of oxygen in the oxide 230 is suitably suppressed. For example, the oxide 243a and the oxide 243b may be formed in a crystal structure such as a hexagonal crystal structure. The structure may suppress the release of oxygen in the oxide 230.

[0146] The conductor 242a is provided on the oxide 243a, and the conductor 242b is provided on the oxide 243b. It will be established.

[0147] The conductor 242a and the conductor 242b may be, for example, a nitride containing tantalum, a titanium nitride, or the like. Nitrides containing lanthanum, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and Nitrides containing aluminum, nitrides containing titanium and aluminum, etc. can be used. In this embodiment, a nitride containing tantalum is particularly preferable. For example, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, lanthanum Oxides containing tungsten and nickel may also be used. These materials have low oxidation resistance and are conductive. It is preferable because it is a material that maintains its conductivity even when it absorbs oxygen.

[0148] Between the side surface of the conductor 242a and the upper surface of the conductor 242a, and between the side surface of the conductor 242b and the top surface of the conductor 242b may each have a curved surface. The ends of the conductors 242a and the ends of the top surface may be curved. At the end of the conductor 242b, the radius of curvature is 3 nm or more and 10 nm or less, preferably The thickness of the film is set to 5 nm or more and 6 nm or less. The coverage is improved.

[0149] In addition, when the oxide 243a (the oxide 243b) is not provided, the conductor 242a (the conductor 2 42b) comes into contact with the oxide 230b or the oxide 230c. Alternatively, oxygen in the oxide 230c diffuses into the conductor 242a (conductor 242b), and the conductor 24 2a (conductor 242b) may be oxidized. There is a high possibility that the electrical conductivity of the conductor 242a and the conductor 242b will decrease due to oxidation. In addition, the oxygen in the oxide 230b or the oxide 230c is mixed with the conductor 242a and the conductor 242b. The conductors 242a and 242b are diffusing into the oxide 230b or 42b. In other words, it absorbs the oxygen in the oxide 230c.

[0150] In addition, oxygen in the oxide 230b or the oxide 230c is mixed with the conductor 242a and the conductor 242b. 42b, the oxide 230b is diffused between the conductor 242a and the oxide 230b, and between the conductor 242a and the oxide 230b. 2b and oxide 230b, or between conductor 242a and oxide 230c, and A layer may form between the conductor 242b and the oxide 230c. Since the layer contains more oxygen than the conductive material 242a or the conductive material 242b, the layer has insulating properties. At this time, the conductor 242a or the conductor 242b, the layer, and the oxide 23 The three-layer structure with 0b or oxide 230c is considered to be a three-layer structure consisting of metal-insulator-semiconductor. It is possible to make MIS (Metal-Insulator-Semiconductor r) structure, or a diode junction structure mainly based on an MIS structure.

[0151] In addition, hydrogen contained in the oxide 230b, the oxide 230c, etc. is converted into the conductor 242a or In particular, the conductive material 242a and the conductive material 242b may diffuse into the conductive material 242a and the conductive material 242b. By using a nitride containing tantalum, the oxide 230b, the oxide 230c, etc. Hydrogen is likely to diffuse into the conductor 242a or the conductor 242b. The oxide 23 may bond with nitrogen contained in the oxide 242a or the conductor 242b. Hydrogen contained in the oxide 230b, the oxide 230c, etc. is absorbed by the conductor 242a or the conductor 242b. It may be taken away.

[0152] The insulator 254 is formed on the side of the oxide 230a, the side of the oxide 230b, and the side of the oxide 243a. the surface of the oxide 243b, the side surface of the conductor 242a, the top surface of the conductor 242a, the conductor 24 2b and the top surface of conductor 242b.

[0153] The insulator 254 preferably has a function of suppressing the diffusion of oxygen. For example, It is preferable that the insulator 254 has a function of suppressing the diffusion of oxygen more than the insulator 280. The body 254 may include, for example, an oxide of one or both of aluminum and hafnium. It is preferable to form a film of an insulating material having a thickness of 100 nm or more.

[0154] The insulator 254 is formed by bias sputtering in an oxygen-containing atmosphere. It is preferable to deposit a film of aluminum oxide or hafnium oxide. The sputtering method is a method in which RF power is applied to the substrate while sputtering. By applying power, the potential of the substrate becomes negative relative to the plasma potential (called the bias potential). ) and the + ions in the plasma are accelerated by this bias potential and injected into the substrate. The bias potential can be controlled by the magnitude of the RF power applied to the substrate. Therefore, aluminum oxide and Alternatively, oxygen can be implanted into the insulator 224 by depositing hafnium oxide.

[0155] In the bias sputtering method, the insulation layer is formed by applying RF power to the substrate. It is possible to control the amount of oxygen injected into the insulator 224 that is the base of the insulator 254. For example, the RF power density is 0.31 W / cm 2 More than 0.62 W / cm 2 More preferably, 1.86 W / cm 2 The above bias should be applied to the substrate. In other words, the RF power used to form the insulator 254 determines the amount of oxygen that is suitable for the characteristics of the transistor. The amount of oxygen can be changed and injected. The RF frequency is preferably 10 MHz or higher. The higher the RF frequency, the less damage it causes to the board. Therefore, by adjusting the RF power applied to the substrate, the insulator 22 Since the amount of oxygen implanted into the insulator 4 can be controlled, the amount of oxygen implanted into the insulator 224 can be optimized.

[0156] In the bias sputtering method, the bias applied to the substrate is not limited to RF power. It can be a DC voltage as well.

[0157] As described above, the insulator 254 has a function of injecting oxygen into the underlying film. The insulator 254 itself has a function of suppressing oxygen permeation. When oxygen is diffused from the insulator 280, the insulator 280 to the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductive layer 242B. This can prevent oxygen from diffusing directly.

[0158] By providing the insulator 254 as described above, the oxide 230a, the oxide 230b, and the oxide 243a, oxide 243b, conductor 242a, and conductor 242b are removed from insulator 280. Therefore, the oxide 230a, the oxide 230b, the oxide 243a, Oxygen is directly transferred from the insulator 280 to the oxide 243b, the conductor 242a, and the conductor 242b. This prevents the source and drain regions of the oxide 230 from being diffused. Excessive oxygen is supplied to the drain region, causing the carrier concentration in the source and drain regions to In addition, the conductor 242a and the conductor 242b can be prevented from being excessively oxidized. It is possible to suppress the on-current from decreasing due to the increase in resistivity caused by the oxidization.

[0159] An insulator 250 is preferably disposed in contact with at least a portion of the oxide 230d. The insulator 250 may be silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen Silicon oxide with voids, silicon oxide with voids, etc. can be used. Silicon and silicon oxynitride are preferred because they are thermally stable.

[0160] The insulator 250 is made of an insulator that releases oxygen when heated, similar to the insulator 224. It is preferable to form the insulating material 250 as an insulating material from which oxygen is released by heating. By providing the oxide 230 in contact with at least a portion of the oxide 230d, the channel shape of the oxide 230 This effectively supplies oxygen to the channel formation region of the oxide 230, thereby reducing oxygen vacancies in the channel formation region of the oxide 230. Therefore, the fluctuation of the electrical characteristics is suppressed, and stable electrical characteristics are realized. In addition, a transistor with improved reliability can be provided. Similarly, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 250 is reduced. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0161] Although the insulator 250 is illustrated as a single layer in FIGS. 1B and 1C, it may have a laminated structure of two or more layers. When the insulator 250 has a two-layer laminate structure, the lower layer of the insulator 250 is The insulating material 250 is formed by using an insulating material that releases oxygen by heat, and the upper layer of the insulating material 250 is formed by using an insulating material that prevents the diffusion of oxygen. It is preferable to form the insulating layer using an insulating material having a function of suppressing the electric field. As a result, oxygen contained in the lower layer of the insulator 250 is prevented from diffusing into the conductor 260. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, the oxidation of the conductor 260 due to the oxygen contained in the lower layer of the insulator 250 can be suppressed. For example, the lower layer of the insulator 250 may be made of the material that can be used for the insulator 250 described above. The upper layer of the insulator 250 may be formed using a material similar to that of the insulator 222. do.

[0162] In addition, when silicon oxide or silicon oxynitride is used as the lower layer of the insulator 250, The upper layer of the body 250 may be an insulating material, such as a high-k material having a high dielectric constant. The gate insulator has a laminated structure of a lower layer of the insulator 250 and an upper layer of the insulator 250. It is possible to obtain a laminated structure that is stable against heat and has a high relative dielectric constant. The gate potential applied during transistor operation can be reduced while maintaining the physical thickness of the insulator. In addition, the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator can be reduced. It becomes possible to

[0163] Specifically, the upper layer of the insulator 250 may be made of hafnium, aluminum, gallium, yttrium, or the like. Thorium, zirconium, tungsten, titanium, tantalum, nickel, germanium, A metal oxide or acid containing one or more metals selected from magnesium, etc. Metal oxides that can be used as the oxide 230 can be used. It is preferable to use an insulator containing oxides of one or both of tungsten and hafnium.

[0164] By forming the insulator 250 into a two-layer laminate structure, the physical thickness of the insulator 250 can improve the conductivity. The distance between the conductor 260 and the oxide 230 is maintained, and the distance between the conductor 260 and the oxide 230 is maintained. In addition, the leakage current between the conductor 260 and the oxide 230 can be suppressed. The distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily adjusted appropriately. It is possible.

[0165] A metal oxide may be provided between the insulator 250 and the conductor 260. The material preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses diffusion, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, the decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. In addition, oxidation of the conductor 260 due to oxygen in the insulator 250 can be suppressed.

[0166] The metal oxide preferably functions as a part of the first gate electrode. By including the above metal oxide, the effect of the electric field from the conductor 260 is not weakened, The on-state current of the transistor 200 can be improved. For example, the oxide 230 may be Any usable metal oxide can be used as the above-mentioned metal oxide. By forming the conductor 260a by a sputtering method, the electrical resistance value of the metal oxide is This is called OC (Oxide Conductor). It can be called an electrode.

[0167] The conductor 260 includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a has a bottom surface and a bottom surface of the conductor 260b. It is preferable that the side surface is wrapped around the substrate. Also, as shown in FIG. 1B and FIG. 1C, The top surface of the conductor 260 is connected to the top surface of the insulator 250, the top surface of the oxide 230d, and the top surface of the oxide 23 1B and 1C, the conductor 260 is disposed so as to be substantially aligned with the upper surface of the conductor 260. Although the two-layer structure of the conductor 260a and the conductor 260b is shown, a single-layer structure is also acceptable. It may have a laminated structure of three or more layers.

[0168] The conductor 260a is a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, or a nitrogen oxide molecule. It is preferable to use a conductive material that has a function of suppressing the diffusion of impurities such as copper atoms. Or, the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.) It is preferable to use a conductive material having the above-mentioned properties.

[0169] In addition, the conductor 260a has a function of suppressing the diffusion of oxygen, so that the insulator 250 The oxygen contained therein can suppress the conductor 260b from being oxidized and the conductivity from decreasing. Examples of conductive materials that have the function of suppressing oxygen diffusion include tantalum, nitride, and the like. It is preferable to use tantalum chloride, ruthenium, ruthenium oxide, or the like.

[0170] In addition, since the conductor 260 also functions as wiring, a conductor with high conductivity should be used. For example, the conductor 260b is preferably made of tungsten, copper, or aluminum. The conductor 260b may have a laminated structure. For example, a laminated structure of titanium or titanium nitride and the above conductive material may be used.

[0171] In addition, in the transistor 200, the conductor 260 is formed in the insulator 280, etc. The conductor 260 is formed in a self-aligned manner to fill the opening. Thus, the conductor 260 is aligned in the region between the conductors 242a and 242b. It can be positioned reliably without any

[0172] As shown in FIG. 1C, in the channel width direction of the transistor 200, the conductor 2 The bottom surface of the region of 60 where the conductor 260 and the oxide 230b do not overlap is the oxide 230b. A conductor 260 that functions as a gate electrode is disposed between the insulator 250 and the bottom surface of the insulator 250. The side and top surfaces of the channel formation region of the oxide 230b are covered via the insulating layer 230b. This makes it easier for the electric field of the conductor 260 to act on the entire channel formation region of the oxide 230b. As a result, the on-state current of the transistor 200 can be increased, and the frequency characteristics can be improved. When the bottom surface of the insulator 222 is taken as a reference, the oxide 230a and the oxide 230b are , the height of the bottom surface of the conductor 260 in the region where the conductor 260 does not overlap with the oxide 23 The difference between the height of the bottom surface of 0b and is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. nm or less, and more preferably, 5 nm to 20 nm.

[0173] The insulator 280 is provided on the insulator 254. The upper surface of the insulator 280 is planarized. It may be possible.

[0174] It is also preferable that the concentration of impurities such as water and hydrogen in insulator 280 be reduced. Additionally, the insulator 280 preferably has a low hydrogen concentration and an excess oxygen region or region. Preferably, for example, the insulator 280 may be made of the same material as the insulator 216. The above-mentioned materials may be laminated, for example, an oxide film formed by sputtering. The silicon is then subjected to chemical vapor deposition (CVD) on the silicon. A laminated structure of silicon oxynitride formed by the SiO2 film forming method may be used. Silicon nitride may be laminated on the insulating layer.

[0175] The conductor 240a and the conductor 240b are made of tungsten, copper, or aluminum. It is preferable to use a conductive material as the main component.

[0176] Moreover, each of the conductor 240a and the conductor 240b may have a laminated structure. When the conductive body 240a and the conductive body 240b each have a laminated structure, the insulator 283 and the insulating layer 284 are The conductor in contact with the insulator 282, the insulator 280, and the insulator 254 is free of impurities such as water and hydrogen. It is preferable to use a conductive material that has a function of suppressing the permeation of pure substances. For example, tantalum Ruthenium, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having the function of suppressing the permeation of impurities such as water and hydrogen is preferably It may be used as a single layer or a laminate. In addition, water, hydrogen, etc. contained in the layer above the insulator 283 Impurities are prevented from entering the oxide 230 through the conductors 240a and 240b. It can be controlled.

[0177] The insulators 241a and 241b may be, for example, silicon nitride or aluminum oxide. The insulator 241a and the insulator 244 may be made of an insulator such as silicon nitride oxide. Since the insulating layer 1b is provided in contact with the insulator 254, water, hydrogen, etc. contained in the insulator 280, etc. What impurities are mixed into the oxide 230 through the conductors 240a and 240b? In particular, silicon nitride has a high blocking effect against hydrogen. In addition, the oxygen contained in the insulator 280 is preferably can prevent it from being absorbed into the

[0178] In addition, a conductor 246a that functions as wiring in contact with the upper surface of the conductor 240a and a conductor A conductor 246b that functions as wiring may be disposed in contact with the upper surface of the conductor 240b. The body 246a and the conductor 246b are made of tungsten, copper, or aluminum. It is preferable to use a conductive material having a layered structure. For example, a laminate of titanium or titanium nitride and the conductive material may be used. The body may be formed to fit into an opening in the insulator.

[0179] The insulator 286 is provided on the conductor 246a, the conductor 246b, and the insulator 283. As a result, the upper surface of the conductor 246a, the side surface of the conductor 246a, and the The upper surface and the side surface of the conductor 246b are in contact with the insulator 286, and the lower surface and The bottom surfaces of the conductor 246a and the conductor 246b are in contact with the insulator 283. The conductive body 246b may be configured to be surrounded by an insulator 283 and an insulator 286. With this configuration, the permeation of oxygen from the outside is suppressed, and the oxidation of the conductor 246 is prevented. In addition, it is possible to prevent water, hydrogen, etc. from conductor 246a and conductor 246b. This is preferable because it can prevent impurities from diffusing to the outside.

[0180] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0181] [substrate] The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or A conductive substrate may be used. Examples of insulating substrates include glass substrates, quartz substrates, and silicon substrates. Fire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.), resin substrate Semiconductor substrates are made of, for example, silicon or germanium. Semiconductor substrates, or silicon carbide, silicon germanium, gallium arsenide, indium phosphide Compound semiconductor substrates made of gallium oxide, zinc oxide, and gallium oxide are also available. A semiconductor substrate having an insulating region inside the semiconductor substrate, for example, SOI (Silicon on Insulator) Conductive substrates include graphite substrates and metal substrates. , alloy substrates, conductive resin substrates, etc. Also, substrates with metal nitrides, metal oxides, etc. Furthermore, there are substrates in which a conductor or semiconductor is provided on an insulating substrate. Substrate, substrate with conductor or insulator provided on semiconductor substrate, substrate with semiconductor or insulator provided on conductive substrate There are also substrates with elements on them. The elements provided on the substrate may include a capacitance element, a resistance element, a switch element, a light-emitting element, and the like. These include elements such as memory elements.

[0182] [Insulator] Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. These include metal oxide nitrides, metal oxynitrides, and metal oxynitrides.

[0183] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. The material should be selected accordingly.

[0184] Insulators with high relative dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. Oxides containing aluminum, aluminum and hafnium, and oxides containing aluminum and hafnium oxide-nitride having silicon and hafnium; oxide-nitride having silicon and hafnium; Examples of suitable materials include oxynitrides with hafnium, or nitrides with silicon and hafnium.

[0185] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, Silicon oxide doped with carbon and nitrogen, silicon oxide with voids, or resin, etc. be.

[0186] In addition, transistors using metal oxides suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of stabilizing the electrical characteristics of the transistor, Insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include: For example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, Phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum Insulators containing tantalum, neodymium, hafnium, or tantalum are used in single or multilayer configurations. Specifically, an insulating material that has a function of suppressing the permeation of impurities such as hydrogen and oxygen is used. As bodies, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, oxide Yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Metal oxides such as tantalum nitride, aluminum nitride, silicon oxynitride, silicon nitride, etc. Metal nitrides of the following metals can be used.

[0187] In addition, the insulator that functions as the gate insulator has a region that contains oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, The oxygen deficiency of 230 can be compensated for.

[0188] [conductor] Conductive materials include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sium, zirconium, beryllium, indium, ruthenium, iridium, strontium Metal elements selected from aluminum, lanthanum, etc., or alloys containing the above-mentioned metal elements It is preferable to use an alloy or the like that combines the above-mentioned metal elements. For example, tantalum nitride titanium nitride, tungsten, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitrides, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use an oxide containing lanthanum and nickel. Tantalum, titanium nitride, nitrides containing titanium and aluminum, tantalum and aluminum Ruthenium nitride, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium Oxides containing lanthanum and nickel are conductive materials that are difficult to oxidize or absorb oxygen. It is preferable because it is a material that maintains its conductivity even if it is oxidized. In addition, it does not contain impurity elements such as phosphorus. Highly conductive semiconductors, such as polycrystalline silicon, nickel silicide, etc. Silicide may also be used.

[0189] In addition, a plurality of conductive layers made of the above materials may be laminated. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated material that combines the above-mentioned material containing a metal element and a conductive material containing nitrogen is In addition, the above-mentioned metal element-containing material, the conductive material containing oxygen, and the nitrogen A laminated structure in which the conductive material containing the element is combined with the conductive material containing the element may be used.

[0190] In the case where an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminate structure in which an oxygen-containing conductive material is used as the It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0191] In particular, the metal oxide in which the channel is formed is a conductor that functions as a gate electrode. It is preferable to use a conductive material containing oxygen and a metal element contained in the metal. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. In addition, a conductive material containing nitrogen such as indium tin oxide or tungsten oxide may be used. Indium zinc oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, Silicon-doped indium tin oxide may also be used. The use of such a material may be used to form a channel. In some cases, the metal oxides surrounding the outer insulator can trap hydrogen. In some cases, it may be possible to capture hydrogen that is mixed in from sources such as

[0192] [Metal oxides] The oxide 230 is a metal oxide (oxide semiconductor) that functions as a semiconductor. The following describes metal oxides that can be used as the oxide 230 according to the present invention. do.

[0193] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that the material contains yttrium, tin, etc. Also, boron, titanium, iron, nickel, etc. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, halide One selected from among fluorine, tantalum, tungsten, magnesium, cobalt, etc. Or multiple types may be included.

[0194] In this specification, metal oxides containing nitrogen are also referred to as metal oxides. Metal oxides containing nitrogen are also called metal oxynitrides (MEs). It may also be called tal oxynitride.

[0195] <<Crystal structure classification>> First, classification of crystal structures in oxide semiconductors will be described with reference to FIG. 3A. FIG. 3A shows an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga, and Zn). FIG. 1 is a diagram explaining the classification of crystal structures of quartz crystals.

[0196] As shown in Figure 3A, oxide semiconductors are broadly divided into "amorphous" ", "Crystalline" and "Crystal" In addition, "Amorphous" includes completely amorp hous is included. Also, "Crystalline" includes CAAC (c-ax is-aligned crystalline), nc(nanocrystalli ne), and cloud-aligned composite (CAC). The classification of "Crystalline" includes single crystal, pol y crystal and completely amorphous are excluded. "Crystal" includes single crystal and poly crystal. Contains stal.

[0197] The structures in the bold frame in Figure 3A are classified into two types: "Amorphous" and "Cryptozotocin". It is an intermediate state between "crystal" and "new crystal" This structure belongs to the line phase. Completely different from the stable "Amorphous" and "Crystal" This can be rephrased as a structure in which

[0198] The crystal structure of the film or substrate was determined by X-ray diffraction (XRD). The crystallinity can be evaluated using the crystallinity spectrum. CAAC-IGZO films classified as "Grazing-Incidence The XRD spectrum obtained by the GIXD measurement is shown in Figure 3B. This is also called the Seemann-Bohlin method. The obtained XRD spectrum is simply referred to as the XRD spectrum. The composition of the C-IGZO film is approximately In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 3B is 500 nm.

[0199] In FIG. 3B, the horizontal axis is 2θ [deg.], and the vertical axis is intensity [a As shown in Figure 3B, the XRD spectrum of the CAAC-IGZO film shows A clear peak indicating crystallinity was detected. In the spectrum, a peak indicating the c-axis orientation is detected near 2θ=31°. As shown in Fig. 1, the peak near 2θ = 31° is nonlinear on the left and right of the angle at which the peak intensity was detected. It is symmetrical.

[0200] The crystal structure of the film or substrate was also analyzed by nano-beam electron diffraction (NBED). Diffraction patterns observed by electron diffraction (ultra-small The diffraction pattern of the CAAC-IGZO film can be evaluated by the electron beam diffraction pattern. The folding pattern is shown in FIG. 3C. FIG. 3C shows the NBED in which the electron beam is incident parallel to the substrate. The diffraction pattern observed by the CAAC-IGZO film shown in Fig. 3C is The composition is approximately In:Ga:Zn=4:2:3 [atomic ratio]. Here, electron diffraction is performed with a probe diameter of 1 nm.

[0201] As shown in Figure 3C, the diffraction pattern of the CAAC-IGZO film shows multiple c-axis orientations. Spots of 100 nm are observed.

[0202] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 3A. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As examples of non-single-crystal oxide semiconductors, the above-mentioned CAAC-OS, Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, Al These include ike OS, amorphous oxide semiconductors, etc.

[0203] Here, the details of CAAC-OS, nc-OS, and a-like OS mentioned above are , and provide an explanation.

[0204] [CAAC-OS] CAAC-OS has multiple crystalline regions, and the multiple crystalline regions have c-axes oriented in a specific direction. The specific direction is the thickness direction of the CAAC-OS film. , in the normal direction to the surface on which the CAAC-OS film is formed, or in the normal direction to the surface of the CAAC-OS film. A crystalline region is a region in which the atomic arrangement has periodicity. When considered as a child arrangement, a crystalline region is also a region with a uniform lattice arrangement. The OS has a region in which multiple crystal regions are connected in the ab-plane direction, and this region is strained. The distortion may occur when the lattice arrangement is distorted in a region where multiple crystal regions are connected. The area where the orientation of the lattice array changes between an area with one lattice array and an area with a different lattice array. In other words, the CAAC-OS has a c-axis orientation and no clear orientation in the ab-plane direction. It is an oxide semiconductor that has no

[0205] Each of the multiple crystalline regions is made up of one or more minute crystals (maximum diameter 10 When a crystalline region is made up of a single tiny crystal, the crystal size is less than 1 nm. The maximum diameter of the crystalline region is less than 10 nm. When such a crystal region is formed, the size of the crystal region may be approximately several tens of nm.

[0206] In-M-Zn oxide (where element M is aluminum, gallium, yttrium, or sulphur) CAAC-OS is one or more selected from the group consisting of aluminum, titanium, etc. A layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as the In layer) are A layered crystal structure (also called a layered structure) is formed by stacking a layer having an element (hereinafter, an (M,Zn) layer) and a layer having an element having an element (hereinafter, an (M,Zn) layer). Indium and element M are mutually substitutable. The (M,Zn) layer may contain indium. The In layer contains the element M. The In layer may contain Zn. The layered structure may be, for example, In high-resolution TEM images, this is observed as a lattice image.

[0207] For example, when the structure of the CAAC-OS film is analyzed using an XRD device, the θ / 2θ shift In the out-of-plane XRD measurement using a can, two peaks indicating the c-axis orientation were observed. The peak position indicating the c-axis orientation (value of 2θ) is detected at or near θ=31°. ) may vary depending on the type and composition of the metal elements that make up the CAAC-OS.

[0208] For example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots (spots) Note that one spot and another spot are the electron beams that have passed through the sample. The spot (also called the direct spot) is the center of symmetry, and the points are observed at point-symmetric positions. can be.

[0209] When the crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is a hexagonal lattice. However, the unit cell is not necessarily a regular hexagon, and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. -In the OS, clear grain boundaries were confirmed even in the vicinity of the distortion. In other words, the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the arrangement of oxygen atoms in the CAAC-OS is dense in the ab-plane direction. The metal atoms are replaced by other metals, and the bond distance between the atoms changes. , it is believed that this is because distortion can be tolerated.

[0210] The crystal structure in which clear grain boundaries are observed is called polycrystal. The grain boundaries act as recombination centers, trapping carriers and forming transistor structures. It is highly likely that this will cause a decrease in on-state current and a decrease in field effect mobility. CAAC-OS, which has no visible grain boundaries, has a crystal structure suitable for the semiconductor layer of a transistor. CAAC-OS is one of the crystalline oxides that contain Zn. For example, In-Zn oxide and In-Ga-Zn oxide are In oxides. This is preferable since it can suppress the generation of grain boundaries more effectively than oxides.

[0211] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, the CAAC-OS is less susceptible to the decrease in electron mobility caused by grain boundaries. In addition, the crystallinity of an oxide semiconductor may be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS is an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, the physical properties of the oxide semiconductor having the CAAC-OS are stable. Therefore, oxide semiconductors having CAAC-OS are resistant to heat and have high reliability. C-OS is stable even under high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using CAAC-OS for OS transistors can expand the flexibility of the manufacturing process. It is possible to

[0212] [nc-OS] nc-OS is a material that is used in microscopic regions (e.g., regions between 1 nm and 10 nm, especially regions between 1 nm and In other words, the nc-OS has a periodic atomic arrangement in the region of 3 nm or less. The size of the minute crystals is, for example, 1 nm or more and 10 nm or less. Since the size of the crystals is between 1 nm and 3 nm, these very small crystals are also called nanocrystals. In the case of nc-OS, the crystal orientation of different nanocrystals is not regular. Therefore, depending on the analysis method, the nc-OS may be a-like In some cases, it may be difficult to distinguish between OS and amorphous oxide semiconductors. For example, The structure was analyzed using an XRD device, and the out-of-phase structure was analyzed using θ / 2θ scan. In the XRD measurement, no peaks indicating crystallinity were detected. In addition, electron beam circuits using electron beams with probe diameters larger than nanocrystals (e.g., 50 nm or more) are used. When electron diffraction (also called selected area electron diffraction) is performed, a diffraction pattern resembling a halo pattern appears. On the other hand, for the nc-OS film, the size of the nanocrystals is close to or smaller than that of the nanocrystals. Electron beam diffraction (nanobeam) using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) When electron diffraction is performed, a ring-shaped region is formed around the direct spot. An electron diffraction pattern may be obtained in which multiple spots are observed.

[0213] [a-like OS] The a-like OS is an oxide semiconductor that has a structure between the nc-OS and the amorphous oxide semiconductor. A-like OS is a semiconductor. It has voids or low density regions. The OS has lower crystallinity than the nc-OS and CAAC-OS. The OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0214] <<Oxide semiconductor structure>> Next, the details of the above-mentioned CAC-OS will be explained. Concerning formation.

[0215] [CAC-OS] CAC-OS is a type of metal oxide in which the elements constituting the metal oxide are 0.5 nm to 10 nm in diameter. Preferably, the material is unevenly distributed in a size range of 1 nm to 3 nm or less, or in the vicinity thereof. In the following, it is assumed that one or more metal elements are unevenly distributed in the metal oxide. The region having the metal element has a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm. A state where the mixture is smaller than m or close to that size is called a mosaic or patch pattern. .

[0216] Furthermore, CAC-OS is a material that is separated into a first region and a second region. The first region has a structure in which the first region is distributed throughout the film (hereinafter, also referred to as a cloud-like structure). ) In other words, the CAC-OS is a mixture of the first and second regions. It is a composite metal oxide having a structure in which

[0217] Here, the I ratio for the metal elements constituting the CAC-OS in the In-Ga-Zn oxide is The atomic ratios of n, Ga, and Zn are expressed as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS of In-Ga-Zn oxide, the first region is In this region, [In] is larger than [In] in the composition of the CAC-OS film. The second region is where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Or, for example, the first region has a higher [In] than the second region. The first region is larger than the second region, and [Ga] is smaller than [Ga] in the first region. In the second region, [Ga] is larger than [Ga] in the first region, and [In ] is a region smaller than [In] in the first region.

[0218] Specifically, the first region is mainly composed of indium oxide, indium zinc oxide, etc. The second region is a region in which gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region in which In is the main component. The second region can be rephrased as a region containing Ga as a main component. can be done.

[0219] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed. .

[0220] For example, in the case of CAC-OS of In-Ga-Zn oxide, Optical method (EDX:Energy Dispersive X-ray spectrosc) The EDX mapping obtained using the opy revealed that the region containing In as the main component (the first region) The structure has a structure in which a first region (a region mainly made of Ga) and a region mainly made of Ga (a second region) are unevenly distributed and mixed. It can be confirmed that.

[0221] When the CAC-OS is used in a transistor, the conductivity due to the first region and the conductivity due to the second region are different. The insulating properties due to the region of the gate insulating film act complementary to each other to provide a switching function (On In other words, CAC-OS and has a conductive function in a part of the material and an insulating function in a part of the material, and By separating the conductive function from the insulating function, Therefore, by using CAC-OS in transistors, This allows for a high on-state current (I on ), high field-effect mobility (μ), and good switching It is possible to realize a switching operation.

[0222] Oxide semiconductors have a variety of structures, each of which has different characteristics. Oxide semiconductors include amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, and CA Two or more of C-OS, nc-OS, and CAAC-OS may be included.

[0223] <<Transistors containing oxide semiconductors>> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0224] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility can be obtained. In addition, a highly reliable transistor can be realized.

[0225] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, , the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 c m -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm - 3 In addition, in order to reduce the carrier concentration of the oxide semiconductor film, The impurity concentration in the semiconductor film may be reduced to reduce the defect state density. A low impurity concentration and a low defect level density are called high purity intrinsic or substantially high purity intrinsic. In addition, the oxide semiconductor having a low carrier concentration is treated with a high-purity intrinsic or substantially high-purity intrinsic oxide. In this specification, the metal oxide semiconductor in the channel formation region is The carrier concentration of the compound is 1×10 16 cm -3 The following are defined as essentially high purity genuine: do.

[0226] In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states. Therefore, the trap level density may be low.

[0227] In addition, the time required for the charge trapped in the trap level of the oxide semiconductor to disappear is Therefore, the trap level density is high. A transistor in which a channel formation region is formed in an oxide semiconductor has unstable electrical characteristics. There may be cases where this occurs.

[0228] In addition, in a transistor using an oxide semiconductor, insufficient charge is generated in a channel formation region in the oxide semiconductor. When a pure substance or oxygen vacancies are present, the resistance of the oxide semiconductor may be reduced. The electrical characteristics are prone to fluctuation, which may result in poor reliability.

[0229] In a transistor in which an oxide semiconductor is used for a channel formation region, When a low resistance region is formed in the low resistance region, the source electrode and drain electrode of the transistor are connected to the low resistance region. A leakage current (parasitic channel) between the electrodes is easily generated. As a result, the transistor becomes normally on, leakage current increases, and the threshold voltage decreases due to stress application. This can lead to voltage shifts and other transistor characteristic defects. If the processing accuracy of the transistor is low, the parasitic channel will vary from transistor to transistor. This causes variations in the transistor characteristics.

[0230] Therefore, in order to stabilize the electrical characteristics of a transistor, the impurity concentration in the oxide semiconductor In order to reduce the impurity concentration in the oxide semiconductor, It is preferable to also reduce the impurity concentration in adjacent films.

[0231] <<Impurities>> Here, the influence of each impurity in an oxide semiconductor will be described.

[0232] When impurities are introduced into an oxide semiconductor, defect states or oxygen vacancies may be formed. Therefore, when impurities are mixed into the channel formation region of the oxide semiconductor, The electrical characteristics of the transistors used are likely to fluctuate, which may result in poor reliability. If there is oxygen vacancy in the channel formation region, the transistor will have normally-on characteristics (gate (The property that a channel exists and current flows through the transistor even when no voltage is applied to the gate electrodes) It's easy to become.

[0233] Transistors using metal oxides are subject to the effects of impurities and oxygen vacancies in the metal oxides. In addition, the electrical properties of the metal oxide change and the metal oxide tends to become normally-on. When the transistor is operated in a state where excess oxygen exceeds The valence may change, and the electrical characteristics of the transistor may fluctuate, resulting in a decrease in reliability. do.

[0234] Furthermore, when impurities are present in a channel formation region of an oxide semiconductor, the junction The crystallinity of the oxide provided in contact with the channel formation region may be reduced. If the crystallinity of the channel formation region is low, the stability or In addition, the oxide formed in contact with the channel forming region tends to deteriorate the reliability. Poor crystallinity may result in the formation of interface states, which may deteriorate the stability or reliability of the transistor. There is.

[0235] Impurities in metal oxides include, for example, hydrogen, nitrogen, alkali metals, and alkaline earth metals. metals, iron, nickel, silicon, etc.

[0236] When oxide semiconductors contain silicon or carbon, which is one of the group 14 elements, they become oxidized. Defect levels are formed in oxide semiconductors. The concentration of silicon and carbon near the interface with the oxide semiconductor (obtained by SIMS) The concentration of 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0237] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, a defect level is formed. Therefore, when alkali metals or alkaline earth metals are included, Transistors using oxide semiconductors, which are widely used in semiconductor manufacturing, tend to be normally on. Therefore, the concentration of alkali metals or alkaline earth metals in oxide semiconductors obtained by SIMS Degrees, 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 To the following:

[0238] In addition, when nitrogen is contained in an oxide semiconductor, electrons that serve as carriers are generated, and As a result, the nitrogen-containing oxide semiconductor is easily converted to n-type. The transistor used for the oxide semiconductor tends to be normally on. In addition, when nitrogen is contained, trap states may be formed. Therefore, the electrical properties of the oxide semiconductor obtained by SIMS may become unstable. The nitrogen concentration in 19 atoms / cm 3 Less than 5 x 10 18 ato ms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 The following is more preferable: 5×10 17 atoms / cm 3 To the following:

[0239] By using an oxide semiconductor in which impurities are sufficiently reduced for a channel formation region of a transistor, This makes it possible to impart stable electrical characteristics.

[0240] <Modification 1 of the semiconductor device> An example of a semiconductor device will be described below with reference to FIGS. 4A to 4D.

[0241] Fig. 4A shows a top view of the semiconductor device. Fig. 4B shows the area along the dashed line A1-A2 in Fig. 4A. FIG. 4C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in FIG. 4A. 4D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in FIG. In the top view of FIG. 4A, some elements are omitted for clarity. It is omitted.

[0242] In the semiconductor device shown in FIG. 4A to FIG. 4D, The structures constituting the semiconductor device and having the same functions are denoted by the same reference numerals. The materials constituting the semiconductor device are described in detail in <Examples of the configuration of the semiconductor device>. Materials can be used.

[0243] The semiconductor device shown in FIGS. 4A to 4D is a modified example of the semiconductor device shown in FIGS. 1A to 1D. The semiconductor device shown in FIG. 4A to FIG. 4D is the same as the semiconductor device shown in FIG. 1A to FIG. 1D. The shape of the insulator 283 is different. is different.

[0244] In the semiconductor device shown in FIGS. 4A to 4D, the insulators 214, 216, and 222 , insulator 224, insulator 254, insulator 280, and insulator 282 are patterned. In addition, the insulator 287 and the insulator 283 are insulators 214, 216, and A structure covering the edge 222, the insulator 224, the insulator 254, the insulator 280, and the insulator 282 That is, the insulator 287 is formed on the top surface of the insulator 212, the side surface of the insulator 214, A side of the insulator 216, a side of the insulator 222, a side of the insulator 224, a side of the insulator 254, The insulator 280 is in contact with a side surface of the insulator 282 and a top surface of the insulator 282. 83 contacts the top and side surfaces of the insulator 287. 14, insulator 216, insulator 222, insulator 224, insulator 254, insulator 280, and The insulators 282 and 287 are formed by the insulators 283 and 212. In other words, the transistor 200 is isolated from the outside by the insulator 287 and the insulator 2 It is disposed within the area sealed by 83 and insulator 212.

[0245] For example, insulators 214, 282, and 287 may be configured to trap and store hydrogen. The insulators 212 and 283 are formed using a material having a function of adhering the insulators to each other. It is preferable to form the insulating layer using a material having a function of suppressing the diffusion of oxygen. Specifically, aluminum oxide is used as the insulator 214, the insulator 282, and the insulator 287. Typically, the insulator 212 and the insulator 283 can be made of nitrogen. Silicon carbide can be used.

[0246] With the above configuration, hydrogen contained outside the sealed region is absorbed into the sealed region. Therefore, the hydrogen concentration in the transistor can be kept low. can be held.

[0247] In the transistor 200 shown in FIGS. 4A to 4D, the insulator 212, the insulator 287, 283 is provided as a single layer. For example, the insulator 212, the insulator 287, and the insulator 28 Each of the components 3 may be provided as a laminated structure of two or more layers.

[0248] In addition, the insulator 287 may not be provided. 0 is disposed within the area sealed by the insulator 212 and the insulator 283. This prevents hydrogen contained outside the sealed area from mixing into the sealed area. Therefore, the hydrogen concentration in the transistor can be kept low. It is possible.

[0249] The insulator 274 functions as an interlayer film. The insulator 274 has a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance between wirings is reduced. The insulator 274 may be made of the same material as the insulator 280. It can be established as follows.

[0250] In addition, the insulating film that becomes the insulator 274 is preferably formed by a sputtering method. A film formed by sputtering is preferable because the hydrogen concentration in the film is low. Therefore, in the process of forming the insulating film, the hydrogen concentration in the transistor increases. can be suppressed.

[0251] In addition, the insulator 287, the insulator 283, and the insulating film are continuously heated without being exposed to the air environment. It is preferable to deposit the film in a continuous manner without exposing it to the air environment. 87 and the insulator 283 from the atmospheric environment. The interface and the vicinity of the interface between the insulator 287 and the insulator 283, and the insulator 2 The interface between the insulating film 83 and the insulating film and the vicinity of the interface can be kept clean. The manufacturing process can be simplified.

[0252] <Method for manufacturing semiconductor device> Next, a manufacturing method of a semiconductor device according to one embodiment of the present invention shown in FIGS. This will be explained with reference to FIG.

[0253] Figures 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, and 13A , Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, and Fig. 21A shows a top view. Also, FIG. 5B, FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, FIG. 10B, FIG. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, 20B, and 21B are respectively similar to FIGS. 5A, 6A, 7A, 8A, and 9. A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17 A, the area indicated by the dashed lines A1-A2 in Figs. 18A, 19A, 20A, and 21A 1 is a cross-sectional view of the transistor 200 taken along the channel length direction. , FIG. 5C, FIG. 6C, FIG. 7C, FIG. 8C, FIG. 9C, FIG. 10C, FIG. 11C, FIG. 12C, FIG. 13C , Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C, Fig. 18C, Fig. 19C, Fig. 20C, and Fig. 21C are respectively Figs. 5A, 6A, 7A, 8A, 9A, 10A, 11A, and Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A and 21A are cross-sectional views corresponding to the area indicated by the dashed line A3-A4 in FIG. 5D, 6D, 7D, and 8 are cross-sectional views of the transistor 200 in the channel width direction. Fig. 8D, Fig. 9D, Fig. 10D, Fig. 11D, Fig. 12D, Fig. 13D, Fig. 14D, Fig. 15D, Fig. 1 6D, 17D, 18D, 19D, 20D, and 21D are respectively similar to FIG. Figures 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, and 14A 15A, 16A, 17A, 18A, 19A, 20A, and 21A 5A, 6A, 7A, and 7B are cross-sectional views corresponding to the portion indicated by the dashed line in FIG. ,Fig. 8A,Fig. 9A,Fig. 10A,Fig. 11A,Fig. 12A,Fig. 13A,Fig. 14A,Fig. 15A,Fig. In the top views of Figs. 16A, 17A, 18A, 19A, 20A, and 21A, Some elements have been omitted for clarity.

[0254] First, a substrate (not shown) is prepared, and an insulator 212, an insulator 214, an insulator 215, and an insulator 216 are formed on the substrate. The insulating layer 212 and the insulating layer 216 are then formed in sequence (see FIG. 5A to FIG. 5D). 14 and insulator 216 are preferably deposited in succession without exposure to an atmospheric environment. By successively depositing the films, impurities from the atmospheric environment are removed from the insulators 212 and 214. In addition, the interface between the insulator 212 and the insulator 214 and the Keeping the vicinity of the interface, and the interface and vicinity of the interface between the insulator 214 and the insulator 216 clean It is possible.

[0255] The insulators 212, 214, and 216 are formed by a sputtering method. CVD method, molecular beam epitaxy (MBE) y) method, Pulsed Laser Deposition (PLD) ) method, atomic layer deposition (ALD) method, etc. This can be done using:

[0256] The CVD method is a process that uses plasma (PECVD). Enhanced CVD method, Thermal CVD (TCVD) These methods are further classified into the VD method, which uses light, and the Photo CVD method, which uses light. Depending on the source gas, metal CVD (MCVD: Metal CVD) method, metal organic CVD method (MOCVD: Metal Organic CVD) method.

[0257] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can reduce plasma damage to the workpiece because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device ) may become charged up by receiving an electric charge from the plasma. When accumulated electric charges destroy wiring, electrodes, elements, etc., contained in a semiconductor device. On the other hand, in the case of thermal CVD, which does not use plasma, such plasma damage occurs. Since the thermal CVD method does not require any heat treatment, the yield of the semiconductor device can be increased. Since no plasma damage occurs in the film, a film with few defects can be obtained.

[0258] In addition, the ALD method uses only thermal energy to react with the precursor and reactant. Thermal ALD method, which uses plasma-excited reactants The EALD (Plasma Enhanced ALD) method, for example, can be used.

[0259] In addition, the ALD method utilizes the self-regulating nature of atoms to deposit atoms one layer at a time. This allows for extremely thin film deposition, film deposition on structures with high aspect ratios, and pinhole It is possible to form films with few defects such as holes, it is possible to form films with excellent coverage, it is possible to form films at low temperatures, etc. In the PEALD (Plasma Enhanced ALD) method, The use of Zuma may be preferable because it allows deposition at lower temperatures. Some precursors used in the ALD method contain impurities such as carbon. The film formed by this method contains more impurities such as carbon than the films formed by other deposition methods. The amount of impurities may be determined by X-ray photoelectron spectroscopy (XPS). This can be done using photoelectron spectroscopy.

[0260] The CVD and ALD methods are deposition methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is not easily affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it ideal for achieving high aspect ratios. However, the ALD method is relatively slow in forming a film. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a faster deposition rate. may be preferred.

[0261] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, the film formation By changing the flow rate ratio of the source gas while heating, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gas, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transportation or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0262] In this embodiment, the insulator 212 is made of silicon nitride formed by sputtering. This allows the formation of silicon nitride with a low hydrogen concentration. By using an insulator that is difficult for copper to penetrate, such as silicon nitride, as the body 212, the insulation Even if a metal that easily diffuses, such as copper, is used for the conductor in the layer below the body 212 (not shown), the metal The metal can be prevented from diffusing upward through the insulator 212. By using an insulator that is difficult for impurities such as water and hydrogen to penetrate, 2. It is possible to suppress the diffusion of impurities such as water and hydrogen contained in the lower layer.

[0263] In this embodiment, the insulator 214 is made of aluminum oxide by sputtering. This results in an aluminum oxide film with a lower hydrogen concentration than the insulator 212. can be formed.

[0264] In this embodiment, the insulator 216 is formed of silicon oxide by sputtering. This allows the formation of silicon oxide with a low hydrogen concentration.

[0265] Next, an opening is formed in the insulator 216 so as to reach the insulator 214. The opening may be, for example, a groove or This also includes slits. The area where an opening is formed may also be referred to as an opening. The openings may be formed by wet etching, but it is more preferable to use dry etching. Insulator 214 is preferably formed by etching insulator 216. It is preferable to select an insulator that functions as an etching stopper film when etching. For example, In the case where silicon oxide or silicon oxynitride is used for the insulator 216 forming the groove, the insulating The insulator 214 may be made of silicon nitride, aluminum oxide, or hafnium oxide.

[0266] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. : Capacitively Coupled Plasma (CAP) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency voltage may be applied to one of the parallel plate type electrodes. A configuration in which a plurality of different high-frequency voltages are applied to the electrodes may be used. Alternatively, a high-frequency voltage of the same frequency may be applied to each of the parallel plate electrodes. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching apparatus or the like can be used.

[0267] After the opening is formed, a conductive film that will become the conductor 205a is formed. The conductive film has a property that prevents oxygen from passing through. It is preferable to include a conductor having a function of suppressing the electric field. For example, tantalum nitride, tantalum Alternatively, a material that has the function of suppressing oxygen permeation can be used. Conductors having the above properties and tantalum, tungsten, titanium, molybdenum, aluminum, copper, molybdenum, The conductive film can be formed by laminating a tungsten alloy with a tungsten alloy. This can be performed using a ring method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0268] In this embodiment, the conductive film that becomes the conductor 205a has a multi-layer structure. A tantalum nitride film is formed by a photolithography method, and a titanium nitride film is laminated on the tantalum nitride film. By using such a metal nitride film as the lower layer of the conductor 205b, Even if a metal that easily diffuses, such as copper, is used for the conductive film that becomes the body 205b, the metal This can prevent the gas from diffusing out of 205a.

[0269] Next, a conductive film that will become the conductor 205b is formed. The conductive film can be formed by a plating method, a sputtering method, or the like. This can be performed using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film is formed of a low resistance conductive material such as copper.

[0270] Next, a CMP process is performed to form a conductive film that will become the conductor 205a and a conductive film that will become the conductor 205b. The conductive film is then partially removed to expose the insulator 216. As a result, the conductive film is left only in the opening. Thus, the conductive body 205a and the conductive body 205b remain. (See FIG. 6A to FIG. 6D.) In addition, the CMP process can form an insulating film. A portion of the edge 216 may be removed.

[0271] In the above, the conductor 205 is formed so as to be embedded in the opening of the insulator 216. However, one embodiment of the present invention is not limited to this. For example, a conductor 2 is formed on an insulator 214. 05 is formed, an insulator 216 is formed on the conductor 205, and the insulator 216 is subjected to CMP processing. By this, a part of the insulator 216 is removed and the surface of the conductor 205 is exposed. In this case, it is preferable to deposit the insulators 212 and 214 successively without exposing them to the air environment. stomach.

[0272] Next, an insulator 222, an insulator 224, and an oxide film 225 are formed on the insulator 216 and the conductor 205. 30A, an oxide film 230B, and an oxide film 243A are formed in this order (see FIGS. 7A to 7D). In addition, the insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 2 It is preferable to deposit 43A continuously without exposing it to the air environment. By successively forming the oxide film 230A on the insulator 222, the insulator 224, and the oxide film 230A, In addition, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the oxide film 230B. , the interface between the insulator 222 and the insulator 224 and the vicinity of the interface, the insulator 224 and the oxide film 230A the interface and vicinity of the interface between the oxide film 230A and the oxide film 230B, In addition, the interface between the oxide film 230B and the oxide film 243A and the vicinity of the interface can be kept clean. Cut.

[0273] The insulator 222, the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A are Each film is formed using the sputtering method, CVD method, MBE method, PLD method, ALD method, etc. This can be done.

[0274] Note that heat treatment may be performed after the insulator 222 is formed. or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, more preferably 320°C or higher The heat treatment may be performed at a temperature of 450° C. or less. The heat treatment conditions described below are used for the heat treatment. Alternatively, you can perform RTA (Rapid Thermal Annealing) as described below. The heat treatment can improve the crystallinity of the insulator 222.

[0275] In this embodiment, the insulator 222 is made of aluminum and An insulator containing oxides of one or both of cerium and hafnium is deposited.

[0276] In this embodiment, the insulator 224 is formed of silicon oxide by sputtering. This can reduce the hydrogen concentration in the insulator 224.

[0277] When the oxide film 230A and the oxide film 230B are formed by a sputtering method, The sputtering gas used is oxygen or a mixture of oxygen and a rare gas. By increasing the ratio of oxygen in the etching gas, the excess oxygen in the oxide film is increased. In addition, when the oxide film is formed by a sputtering method, the above An In-M-Zn oxide target or the like can be used.

[0278] In particular, when the oxide film 230A is formed, a part of the oxygen contained in the sputtering gas becomes an insulator. Therefore, the oxygen contained in the sputtering gas may be The ratio is 70% or more, preferably 80% or more, and more preferably 100%.

[0279] In addition, when the oxide film 230B is formed by a sputtering method, the oxide film 230B is formed by sputtering. The ratio of oxygen to be added is set to more than 30% and not more than 100%, preferably 70% or more and not more than 100%. When the oxide semiconductor is formed in the above-mentioned manner, an oxygen-excess oxide semiconductor is formed. The transistor used in the channel formation region has relatively high reliability. In one embodiment, the oxide film 230B is formed by a sputtering method. The ratio of oxygen contained in the sputtering gas is 1% or more and 30% or less, preferably 5% or more and 20% or less. When the concentration is 0% or less, an oxygen-deficient oxide semiconductor is formed. Transistors that use semiconductors in the channel formation region have a relatively high field effect mobility. In addition, by forming the film while heating the substrate, the crystallinity of the oxide film is improved. It is possible to do so.

[0280] In this embodiment, the oxide film 230A is formed by sputtering In:Ga:Zn The oxide film 230B is formed using an oxide target with an atomic ratio of 1:3:4. The oxide was then oxidized by sputtering to a ratio of In:Ga:Zn=4:2:4.1 [atomic ratio]. The oxide film 243A is formed by sputtering using a metal target. The film is formed using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. By appropriately selecting the film formation conditions and the atomic ratio of each oxide film, the oxide 230a, the oxide The material 230b, the oxide 243a, and the oxide 243b are formed according to the desired properties. good.

[0281] Next, it is preferable to perform a heat treatment. The temperature range is set to 250° C. to 650° C., and the oxide film 243A does not become polycrystalline. The heat treatment is preferably performed at a temperature of 400° C. to 600° C. Or in an inert gas atmosphere, or oxidizing gas is 10 ppm or more, 1% or more, or For example, heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas. In this case, the oxygen gas should be about 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in a nitrogen gas or inert gas atmosphere, followed by desorption. To compensate for the lost oxygen, an atmosphere containing oxidizing gas at 10 ppm or more, 1% or more, or 10% or more Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or After heat treatment in an atmosphere containing 10% or more of The heat treatment may be performed in an oxygen atmosphere. By supplying oxygen to the substrate, oxygen vacancies can be reduced.

[0282] In addition, it is preferable that the gas used in the heat treatment is highly purified. The moisture content of the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less. The concentration of the purified gas is preferably 0.05 ppb or less. By performing the treatment, moisture and the like are removed from the oxide film 230A, the oxide film 230B, the oxide film 243A, etc. It is possible to prevent intrusion as much as possible.

[0283] The heat treatment can also be performed using a gas bake furnace, an electric furnace, an RTA device, or the like. By using the TA device, it is possible to perform heat treatment at a temperature above the distortion point of the substrate for a short period of time. Therefore, it is possible to shorten the heating time. Furthermore, it is possible to perform continuous film formation. The apparatus can be configured to perform RTA in one of its processing chambers. In this way, the heat treatment can be performed during the continuous film formation. This simplifies the process. This makes it possible to improve the productivity of semiconductor devices.

[0284] The heat treatment by RTA is performed at a temperature of, for example, 400° C. or higher and 750° C. or lower, preferably 500° C. or higher. The heat treatment may be performed at a temperature of 650° C. or less in an oxygen atmosphere. The treatment time is 600 seconds or less, preferably 180 seconds or less.

[0285] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at a temperature of 550° C. for one hour. After that, the heating is continued in an oxygen atmosphere at 550° C. for 1 hour. According to the theory, water and hydrogen in the oxide film 230A, the oxide film 230B, and the oxide film 243A are Furthermore, the heat treatment can remove impurities such as oxide film 23. It is possible to improve the crystallinity of 0B and create a denser, more compact structure. This can suppress the diffusion of oxygen or impurities in the oxide film 230B.

[0286] Next, a conductive film 242A is formed on the oxide film 243A (see FIGS. 7A to 7D). The deposition of the conductive film 242A is performed by sputtering, CVD, MBE, PLD, ALD, etc. Note that, before the conductive film 242A is formed, a heat treatment may be performed. The heat treatment is performed under reduced pressure, and the conductive film 242A is continuously formed without being exposed to the atmosphere. By carrying out such a treatment, the oxide film 243A may be adsorbed on the surface thereof. The moisture and hydrogen in the oxide film 230A, the oxide film 230B, and the The moisture concentration and hydrogen concentration in the oxide film 243A can be reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is set to 200 °C.

[0287] In addition, when the conductive film 242A is formed by a sputtering method, the insulator 222 and the insulating The body 224, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are It is preferable to form the films continuously without exposing them to the air environment. This can prevent moisture and hydrogen from being adsorbed on the surface. Therefore, the manufacturing process of the semiconductor device can be simplified, and the productivity of the semiconductor device can be improved. It is possible.

[0288] Next, the oxide film 230A, the oxide film 230B, and the oxide film 243A are formed by lithography. , and the conductive film 242A is processed into an island shape.

[0289] First, a resist is formed on the conductive film 242A, and the resist is exposed to light through a mask. The exposed areas are then removed or left behind using a developer to form a resist mask. do.

[0290] For example, KrF excimer laser light, ArF excimer laser light, EUV (Extreme UV) The resist is exposed to ultraviolet light to form a resist mask. In addition, exposure may be performed by filling the space between the substrate and the projection lens with liquid (e.g., water). Alternatively, an immersion technique may be used, in which an electron beam or an ion beam is used instead of the light described above. If an electron beam or an ion beam is used, the mask is not necessary. .

[0291] Here, the heat resistance and dry etching resistance of the resist mask may be improved. In the document, improving the heat resistance and dry etching resistance of the resist mask is called resist masking. This may mean hardening the mask.

[0292] For example, by irradiating a resist mask with ultraviolet light, the resist molecules are cross-linked, The heat resistance and dry etching resistance of the mask can be improved. Near ultraviolet light (ultraviolet light with a wavelength of 200 nm or more and 380 nm or less), or far ultraviolet light ( It is ultraviolet light with a wavelength of 10 nm or more and 200 nm or less, also called vacuum ultraviolet light. It is preferable to use ultraviolet light having a wavelength of 250 nm or more and 300 nm or less. After the irradiation with ultraviolet light, a high-temperature heat treatment may be performed.

[0293] In addition, for example, the resist mask is exposed to plasma to modify the film quality on the resist surface side. By doing so, the heat resistance and dry etching resistance of the resist mask can be improved. The plasma includes H2 gas, a mixture of H2 and Ar, a mixture of CF4 and O2, and C2H A mixture of Cl3 and O2 gas may be used.

[0294] Next, an etching process is performed through a resist mask to form oxide film 230A and oxide film 2 30B, the oxide film 243A, and the conductive film 242A are processed into islands to form the oxide 230a, the oxide 8A to 8D, a silicide layer 230b, an oxide layer 243B, and a conductive layer 242B are formed. (See page 11.) This processing can be done using dry etching or wet etching. Dry etching is suitable for fine processing. A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed differently. In this step, the oxide 230a of the insulator 224 may be overlapped. The thickness of the film in the non-existent areas may be reduced.

[0295] Here, oxide 230a, oxide 230b, oxide layer 243B, and conductive layer 242B The oxide 230a is formed so as to overlap at least a part of the conductor 205. The sides of the oxide layer 230b, the oxide layer 243B, and the conductive layer 242B are aligned with the top surface of the insulator 222. It is preferable that the oxide layer 230a, the oxide layer 230b, and the oxide layer 230b are substantially perpendicular to each other. 43B and the side surface of the conductive layer 242B are approximately perpendicular to the upper surface of the insulator 222. This allows a reduction in area and a high density when providing a plurality of transistors 200. The oxide 230a, the oxide 230b, the oxide layer 243B, and the side surface of the conductive layer 242B are The angle between the upper surface of the insulator 222 and the upper surface of the insulator 222 may be small. By doing so, the covering property of the insulator 254 etc. is improved in the subsequent steps, and porosity etc. Defects can be reduced.

[0296] In addition, a curved surface is provided between the side surface and the upper surface of the conductive layer 242B. It is preferable that the end of the side surface and the end of the top surface are curved. For example, the radius of curvature at the end of the conductive layer 242B is 3 nm or more and 10 nm or less, preferably The thickness of the film is set to 5 nm or more and 6 nm or less. The coverage is improved.

[0297] By the above processing, the insulator 224, the oxide 230a, the oxide 230b, and the oxide layer 243B are formed. A layer (not shown) may be formed on the conductive layer 242B. A part of the conductive layer 242B is etched and floats up into the chamber, where it is deposited again to form Therefore, the layer is an oxide containing the main component of the conductive layer 242B. For example, when tantalum nitride is used for the conductive layer 242B, the layer becomes an oxide containing tantalum. .

[0298] When the layer has a function of suppressing oxygen diffusion, the layer is formed on the insulator 224. By this, the oxygen in the insulator 224 due to the formation of the insulator 254 by the sputtering method can be prevented. The amount of injection is reduced.

[0299] Therefore, by performing anisotropic etching after the above processing, the insulating layer 224 and the conductive layer 2 The layer on 42B is removed. At this time, a part of the layer is removed from the side of the oxide 230a, the oxide The side of the oxide 243a, the side of the oxide 243b, and the side of the conductor 242a The above layer may remain on the side of the conductive material 242b and the side of the conductive material 242c. When the oxide layer 230a has a function of forming a thin film on the surface of the oxide 230b, a part of the oxide layer 230a may be formed on the side of the oxide 230b. By remaining on the side surface, oxygen is prevented from being mixed into the regions 236a and 236b. Therefore, the low resistance region can be maintained.

[0300] Thus, the conductor 242a and the conductor 242b function as a source electrode and a drain electrode. The side of the oxide 230a and the side of the oxide 230b overlapping the inductor 242b are made n-type. As a result, the on-state current of the transistor 200 can be increased.

[0301] In some cases, the above-mentioned layers can be detected using EDX. The elemental analysis was performed using EDX on the side of the oxide 230b in the region overlapping with the conductor 242b. The concentration of the main components (excluding oxygen) in the above layer obtained by elementary analysis is 1.0 atm or more than the detection limit. In addition, the area where the concentration of the conductor 242a or the conductor 242b is less than omic% is detected. The concentration of the main components (except oxygen) of the layer on the side of the oxide 230b in the region overlapping with The main component of the layer on the top surface of the insulator 224 in the area not overlapping the oxide 230b (excluding oxygen) is lower.

[0302] After the anisotropic etching, the resist mask may remain. The mask is used for dry etching such as ashing, or for wet etching. A wet etching process is performed after a dry etching process, or The insulating layer can be removed by performing a dry etching process after the coating process.

[0303] In addition, the resist mask is hardened, and the oxide film 230A, the oxide film 230B, the oxide film 243A, and The island-shaped processing of the conductive film 242A and the anisotropic etching of the above layers are all performed in one dot. It is preferable to carry out the anisotropic etching continuously using a laser etching apparatus. If the resist mask remains after etching, the resist mask is hardened, the oxide film 230A, and the oxide film 230B are removed. The insulating film 230B, the oxide film 243A, and the conductive film 242A are processed into islands, and the anisotropic etching of the above layers is performed. The etching, etching, and removal of the resist mask (also called resist stripping) are all performed in one process. It is preferable to carry out these steps continuously using a laser etching apparatus. By performing the above process, the process can be simplified. During the separation, a process of removing deposits from the inner walls of the processing chamber of the dry etching device (so-called chamfering) is performed. A bar cleaning process may be performed.

[0304] Next, the insulator 254 and the insulating film 280A are formed on the insulator 224 and the conductive layer 242B. The insulating film 280A is formed in this order (see FIG. 9B to FIG. 9D). It is preferable to deposit the films continuously without exposing them to the air environment. Impurities or moisture from the atmospheric environment can be prevented from adhering to the insulating body 254. The interface between the insulating film 254 and the insulating film 280A and the vicinity of the interface can be kept clean. can be simplified.

[0305] The insulator 254 and the insulating film 280A are formed by sputtering, CVD, M This can be performed using a BE method, a PLD method, an ALD method, or the like.

[0306] In this embodiment, the insulator 254 is made of aluminum oxide by sputtering. The insulator 254 is formed in an oxygen-containing atmosphere by sputtering. This allows oxygen to be added to the insulator 224 during deposition.

[0307] In the present embodiment, the insulating film 280A is formed by sputtering an oxide film. A silicon film is formed, which can reduce the hydrogen concentration in the insulating film 280A.

[0308] Next, the insulating film 280A is subjected to CMP processing to form an insulator 280 having a flat upper surface. On the insulating film 280A, for example, an aluminum oxide film is formed by a sputtering method. However, CMP processing may be performed until an insulator 280 with a flat upper surface is formed. The insulator 254, the insulating film 280A, and the aluminum oxide are then dried without being exposed to the air environment. In this way, impurities from the atmospheric environment or the like are prevented from being deposited on the insulating film 280A. It is possible to prevent moisture from adhering to the insulating film 280A during the formation of the aluminum oxide film. The reduction in the amount of added oxygen can be suppressed.

[0309] Here, a microwave treatment may be performed. The microwave treatment is performed in an oxygen-containing atmosphere. It is preferable to carry out the microwave treatment under reduced pressure. An electric field is applied to the insulator 280, the oxide 230b, the oxide 230a, etc., and the oxide 230 b and V in oxide 230a O H can be split into oxygen vacancies and hydrogen. Some of the hydrogen that is split off during the reaction combines with oxygen in the insulator 280 and is removed as water molecules. In addition, some of the hydrogen may flow through the insulator 254 to the conductor 242a and the conductor In some cases, the ions may be gettered by the dielectric 242b.

[0310] In addition, after the microwave treatment, a heat treatment may be performed while maintaining the reduced pressure state. By such a process, the insulator 280, the oxide 230b, and the oxide 230a are Hydrogen can be removed efficiently. The heat treatment temperature is 300℃ to 500℃. It is preferable to set it to lower.

[0311] In addition, by performing microwave treatment, the film quality of the insulator 280 is modified, so that hydrogen Therefore, the diffusion of water, impurities, etc. can be suppressed. Hydrogen, water, impurities, etc. are absorbed through the insulator 280 by a post-process or heat treatment, etc. Therefore, diffusion into the compound 230 can be suppressed.

[0312] Next, a portion of the insulator 280, a portion of the insulator 254, a portion of the conductive layer 242B, and the oxide A part of the material layer 243B is processed to form an opening that reaches the oxide 230b. It is preferable that the opening is formed so as to overlap the conductor 205. 242a, conductor 242b, oxide 243a, and oxide 243b are formed (FIG. 10 See Figures 10A to 10D.

[0313] When forming the opening, the upper part of the oxide 230b is removed. By removing the oxide 230b, a groove is formed in the oxide 230b. Depending on the depth of the groove, The groove may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening. It may be formed by

[0314] In addition, a part of the insulator 280, a part of the insulator 254, a part of the conductive layer 242B, and the oxide layer 2 The processing of a part of 43B and a part of the oxide 230b is performed by dry etching or wafer etching. The hot etching method can be used. The processing is performed under different conditions. For example, a part of the insulator 280 may be processed by dry etching to remove the insulator 254. A part of the oxide layer 243B and a part of the conductive layer 242B are processed by wet etching. , and a part of the oxide 230b may be processed by a dry etching method. Processing of a part of 243B and a part of the conductive layer 242B and processing of a part of the oxide 230b , may be carried out under different conditions.

[0315] Here, a part of the oxide 230b is removed by dry etching to form a groove. When performing the above-mentioned treatment, it is preferable to increase the bias power. The power density is 0.03 W / cm 2 It is preferable to set it to 0.06 W / cm or more. 2 More than It is more preferable that the dry etching time is appropriately set according to the depth of the groove. Just do that.

[0316] When forming the opening, the surface of the oxide 230b at the bottom of the opening may be damaged. In the damaged region of the oxide 230b, crystal defects such as oxygen vacancies are formed, and impurities are formed. Damage may occur if metals such as hydrogen, nitrogen, silicon, and aluminum are present. In the V region, oxygen vacancies and impurities such as hydrogen are likely to exist. O +H→V O H Thus, in the damaged area, V O H is formed in large quantities. Thus, the damaged area of ​​the oxide 230b is left, and the oxide 230c is formed on it. Even if the damage region is large, the transistor tends to have normally-on characteristics. Variations within the surface will cause variations in the characteristics of semiconductor devices that have transistors. become.

[0317] Here, impurities attached to the surface of the oxide 230a, the oxide 230b, etc. or diffused inside the oxide 230a, etc. It is preferable to remove the oxide 230b formed on the surface by the dry etching. It is preferable to remove the damaged area. 254, and the components contained in the conductive layer 242B, and the apparatus used in forming the opening. Components contained in the materials used in the product, and components contained in the gas or liquid used in etching Examples of such impurities include aluminum, silicon, etc. Examples include zinc, tantalum, fluorine, and chlorine.

[0318] In order to remove the damaged area, the impurities, etc., a cleaning process is performed. The cleaning method includes the following steps: Wet cleaning using cleaning fluids, plasma processing using plasma, cleaning by heat treatment, etc. The above cleaning steps may be combined as appropriate. The grooves may become deeper.

[0319] For wet cleaning, ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, etc. are mixed with carbonated water. Alternatively, the cleaning treatment may be performed using an aqueous solution diluted with pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using an aqueous solution of these, pure water, or carbonated water. These cleaning methods may be combined as appropriate.

[0320] In this specification and the like, an aqueous solution of commercially available hydrofluoric acid diluted with pure water is referred to as diluted hydrofluoric acid. Ammonia is called an acid, and commercially available aqueous ammonia diluted with pure water is called diluted aqueous ammonia. The concentration and temperature of the aqueous solution depend on the impurities to be removed and the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water is 0.0 The concentration is 1% to 5%, preferably 0.1% to 0.5%. The hydrogen fluoride concentration of the hydrofluoric acid is 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or less. It should be between pm and 10 ppm.

[0321] For ultrasonic cleaning, a frequency of 200 kHz or more, preferably 900 kHz or more, should be used. By using this frequency, damage to the oxide 230b and the like can be reduced. Cut.

[0322] The above cleaning process may be carried out multiple times, and the cleaning solution may be changed for each cleaning process. For example, the first cleaning process may be a process using diluted hydrofluoric acid or diluted aqueous ammonia. A first cleaning treatment may be performed, and a second cleaning treatment may be performed using pure water or carbonated water.

[0323] In the present embodiment, the cleaning process is performed by wet cleaning using diluted hydrofluoric acid. Then, wet cleaning is performed using pure water or carbonated water. , removing impurities attached to the surface of the oxide 230a, the oxide 230b, etc. or diffused therein. Furthermore, the crystallinity of the oxide 230c formed on the oxide 230b can be improved. It can be done.

[0324] The above-mentioned opening and overlapping portions are formed by the conventional processing such as dry etching or the above-mentioned cleaning process. The thickness of the insulator 224 in the region that does not overlap with the oxide 230b is smaller than that of the oxide 230b. In some cases, the thickness of the insulator 224 may be thinner than the thickness of the insulator 224 in the overlapping area.

[0325] After the etching or cleaning, a heat treatment may be performed. The heating temperature may be from 350° C. to 400° C., preferably from 350° C. to 400° C. The atmosphere is nitrogen gas or inert gas, or oxidizing gas is 10 ppm or more, 1% For example, heat treatment should be performed in an oxygen atmosphere. This is preferable. Oxygen is supplied to the oxide 230a and the oxide 230b, In addition, by performing such a heat treatment, the oxide 230 The crystallinity of oxide 230b is improved, and the crystallinity of oxide 230c formed in the groove of oxide 230b is also improved. The heat treatment may be carried out under reduced pressure or in an oxygen atmosphere. After the heat treatment at 200° C., a heat treatment may be successively performed in a nitrogen atmosphere without exposure to the air.

[0326] By removing the damaged region, the CAA is formed in the groove of the oxide 230b from which the damaged region has been removed. The oxide 230c having the C-OS can be formed. In a cross-sectional view in the channel length direction of the transistor, a groove is provided on the upper part of the oxide 230b. , may be removed.

[0327] Next, an oxide film 230C is formed (see FIGS. 11A to 11D). Heat treatment may be performed before the deposition, and the heat treatment is performed under reduced pressure without exposure to the atmosphere. It is preferable to form the oxide film 230C in succession to the heat treatment. By carrying out such a treatment, the oxide 230b The moisture and hydrogen adsorbed on the surface of the oxide 230a and the oxide The water concentration and hydrogen concentration in the SiO 230b can be reduced. In the present embodiment, the temperature of the heat treatment is set to 200° C. do.

[0328] Here, the oxide film 230C is formed on at least the inner wall of the groove formed in the oxide 230b, a part of a side surface of the object 243a, a part of a side surface of the oxide 243b, a part of a side surface of the conductor 242a, A part of the side of the conductor 242b, a part of the side of the insulator 254, and a part of the side of the insulator 280 It is preferable that the conductor 242a (conductor 242b) is provided so as to be in contact with a part of the conductor 242a. The oxide 243a (oxide 243b), the insulator 254, and the oxide film 230C are surrounded by the oxide 243a (oxide 243b). As a result, the conductivity of the conductor 242a (conductor 242b) decreases due to oxidation in the subsequent steps. can be suppressed.

[0329] In this embodiment, the oxide film 230C is formed by sputtering In:Ga:Zn The film is formed using an oxide target with an atomic ratio of 4:2:3.

[0330] During the formation of the oxide film 230C, part of the oxygen contained in the sputtering gas is converted into the oxide 230C. a and oxide 230b. A portion of the oxygen contained in the sputtering gas may be supplied to the insulator 280. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230C is preferably 70% or more. The oxygen content is preferably 80% or more, and more preferably 100%. By forming the oxide film 230C in an atmosphere containing SiO 2 , the oxide film 230C can be easily converted into CAAC-OS. It becomes.

[0331] The oxide film 230C is preferably formed while the substrate is heated. By setting the temperature at 200° C. or higher, oxygen vacancies in the oxide film 230C and the oxide 230b are reduced. By forming the film while heating the substrate, the oxide film 230C and the oxide The crystallinity of 230b can be improved.

[0332] Next, a mask is formed on the oxide film 230C by lithography. As the mask, a hard mask or a resist mask may be used.

[0333] Next, a part of the oxide film 230C is selectively removed using the mask. A part of 230C may be removed by using a wet etching method or the like. The oxide film 230C is removed from the transistors 200 adjacent to each other in the channel width direction. It can be removed.

[0334] In the region where the oxide film 230C has been partially removed by the above process, the insulator 224 At this time, the thickness and thickness of the insulator 224 in the region are In addition, the insulator 224 in the region may be removed. In addition, the step of forming the mask may be performed by oxidizing the insulating material 222. This may also serve as a step of removing a portion of film 230C.

[0335] Next, the mask is removed (see Figures 12A, 12C and 12D). The mask may be removed by etching or the like.

[0336] Next, an oxide film 230D is formed (see FIGS. 13A to 13D). The oxide film 230D is formed by sputtering In:Ga:Zn=1:3:4 [original The film is formed using an oxide target with a [atomic ratio].

[0337] During the formation of the oxide film 230D, part of the oxygen contained in the sputtering gas is In addition, when the oxide film 230D is formed, the oxide gas may be supplied to the sputtering gas. Some of the oxygen contained in the oxide film 230D may be supplied to the insulator 280. The proportion of oxygen contained in the sputtering gas is 70% or more, preferably 80% or more, and more preferably Preferably, it should be set to 100%.

[0338] Next, an insulating film 250A is formed (see FIGS. 13A to 13D). Heat treatment may be performed before the reaction, and the heat treatment is performed under reduced pressure and without exposure to air. The insulating film 250A may be formed in succession. By carrying out such a treatment, the surface of the oxide film 230D, etc. The moisture and hydrogen adsorbed in the oxide 230a and the oxide 230b are removed. Reducing the moisture concentration and hydrogen concentration in the oxide film 230C and the oxide film 230D The temperature for the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0339] The insulating film 250A is formed by a method such as sputtering, CVD, MBE, PLD, or ALD. The insulating film 250A can be formed by using a method in which hydrogen atoms are reduced or removed. It is preferable to form the insulating film 250A by a film forming method using a gas containing the above-mentioned gas. The insulating film 250A is in contact with the oxide 230d in a later process. Since this will become the insulator 250, it is preferable that the hydrogen concentration is reduced in this manner.

[0340] In addition, when the insulator 250 has a two-layer laminated structure, the insulating film and the The insulating film that is the upper layer of the insulator 250 can be formed in succession without being exposed to the air environment. It is preferable that the film is formed without exposure to the atmosphere, so that the insulating film underlying the insulator 250 is not exposed to the atmosphere. This prevents impurities or moisture from adhering to the insulating layer 250. The vicinity of the interface between the insulating film and the insulating film that is the upper layer of insulator 250 can be kept clean.

[0341] After the insulating film 250A is formed, the insulating film 250A is heated under an oxygen-containing atmosphere and under reduced pressure. Microwave treatment may be performed. By performing microwave treatment, the electric field generated by microwaves is insulated. The border film 250A, the oxide film 230D, the oxide film 230C, the oxide 230b, the oxide 230a, etc. , and in oxide film 230D, in oxide film 230C, in oxide 230b, and in oxide 230C. V in 30a O H to V O At this time, part of the hydrogen is split into hydrogen and hydrogen. is combined with oxygen to form H2O, and the oxide film 250A, the oxide film 230D, the oxide film 230C, The hydrogen may be removed from the oxide 230b and the oxide 230a. , conductor 242a, and conductor 242b. By performing microwave treatment, the insulating film 250A, the oxide film 230D, and the oxide film 230C The hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide 230a can be reduced. Also, in the oxide 230a, in the oxide 230b, in the oxide film 230C, and in the oxide film 230D V O H to V O V that can exist after splitting into and hydrogen O Oxygen is supplied to V O of Can be repaired or compensated for.

[0342] In addition, after the microwave treatment, a heat treatment may be performed while maintaining the reduced pressure state. By carrying out such a process, the oxide film 230C is formed in the insulating film 250A, the oxide film 230D, and the oxide film 230C. Hydrogen in the oxide 230a and the oxide 230b can be efficiently removed. Some of the hydrogen may be gettered to the conductor 242a and the conductor 242b. Alternatively, multiple steps of heat treatment may be performed while maintaining the reduced pressure after microwave treatment. By repeatedly performing the heat treatment, the oxide film in the insulating film 250A is removed. Hydrogen in oxide film 230D, oxide film 230C, oxide 230b, and oxide 230a are further The heat treatment temperature is 300°C or higher and 500°C or lower. It is preferable to set the above.

[0343] In addition, by performing microwave processing, the film quality of the insulating film 250A is modified, so that the water Therefore, the diffusion of hydrogen, water, impurities, etc. can be suppressed. By a post-process such as film formation or a post-treatment such as heat treatment, hydrogen, water, etc. are introduced through the insulator 250. Therefore, it is possible to suppress the diffusion of impurities into the oxide 230b, the oxide 230a, etc. Cut.

[0344] Next, a conductive film 260A and a conductive film 260B are formed in this order (see FIGS. 14A to 14D). The conductive film 260A and the conductive film 260B are formed by a sputtering method, a CVD method, an MB method, etc. This can be done by using the E method, the PLD method, the ALD method, etc. In this embodiment, the ALD method The conductive film 260A is formed using the method, and the conductive film 260B is formed using the CVD method.

[0345] Next, the oxide film 230C, the oxide film 230D, the insulating film 250A, and the conductive The film 260A and the conductive film 260B are polished until the insulator 280 is exposed. , oxide 230c, oxide 230d, insulator 250, and conductor 260 (conductor 260 a, and conductor 260b) are formed (see FIGS. 15A to 15D). The oxide 230c is formed on the inner wall (side wall) of the opening that reaches the oxide 230b and the groove of the oxide 230b. The oxide 230d is disposed so as to cover a part of the oxide 23 The insulating material 2 is disposed so as to cover the opening and the inner wall of the groove through the insulating material 2c. 50 is formed on the inner wall of the opening and the groove through oxide 230c and oxide 230d. The conductor 260 is disposed so as to cover the oxide 230c, the oxide 230d, and The insulating material 250 is disposed so as to fill the opening and the groove.

[0346] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The heat treatment is carried out for 1 hour. The moisture concentration in the insulators 250 and 280 is reduced by the heat treatment. After the heat treatment, the temperature and hydrogen concentration can be reduced. The insulator 282 may be deposited immediately after the above process.

[0347] Next, on the oxide 230c, on the oxide 230d, on the insulator 250, on the conductor 260, and An insulator 282 is formed on the insulator 280 (see FIGS. 16B to 16D). The deposition of 282 is done by sputtering, CVD, MBE, PLD, ALD, etc. The insulator 282 can be formed by, for example, sputtering. It is preferable to form an aluminum film by sputtering in an oxygen-containing atmosphere. By forming the insulator 282 in the above manner, oxygen can be added to the insulator 280 during the film formation. At this time, it is preferable to form the insulator 282 while heating the substrate. In addition, by forming an insulator 282 in contact with the upper surface of the conductor 260, In this case, it is possible to suppress the oxygen contained in the insulator 280 from being absorbed into the conductor 260. Cut.

[0348] Next, a part of the insulator 282, a part of the insulator 280, a part of the insulator 254, and the insulator 224 are A part of the insulating material 222, a part of the insulating material 216, and a part of the insulating material 214 are processed. 17A to 17D, an opening is formed that reaches the insulator 212. The opening may be formed so as to surround the transistor 200. Alternatively, the opening may be formed so as to surround a plurality of In some cases, the transistor 200 is formed so as to be surrounded by an insulator 2. 82, a portion of a side of the insulator 280, a portion of a side of the insulator 254, and the insulator 22 4, a portion of a side of the insulator 222, a portion of a side of the insulator 216, and the insulator Part of the side of 214 is exposed.

[0349] A part of the insulator 282, a part of the insulator 280, a part of the insulator 254, and a part of the insulator 224 , a part of the insulator 222, a part of the insulator 216, and a part of the insulator 214 are processed by a drum. The etching method may be a wet etching method. In this process, the above opening of the insulator 212 may be performed under different conditions. The thickness of the film may be reduced in the area overlapping the mouth.

[0350] Next, the insulator 282, the insulator 280, the insulator 254, the insulator 224, the insulator 222, the insulator Covering the edge 216 and the insulator 214, an insulator 287, an insulator 283, and an insulating film 274 are provided. A are formed in this order (see FIG. 18B to FIG. 18D). It is preferable that the insulating film 274A and the insulating film 274B are successively formed without being exposed to the air environment. By the diagenesis, impurities or other substances from the atmospheric environment are removed from the insulator 287 and the insulator 283. The insulator 287 and the insulator 283 can prevent moisture from adhering to the insulator 287 and the insulator 283. The surface and the vicinity thereof, as well as the interface and the vicinity thereof between the insulator 283 and the insulating film 274A are kept clean. In addition, the process can be simplified.

[0351] The insulator 287, the insulator 283, and the insulating film 274A are formed by sputtering. The deposition can be performed by using a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0352] In this embodiment, the insulator 287 is made of aluminum oxide by sputtering. The insulator 287 is deposited in an oxygen-containing atmosphere by sputtering. This allows oxygen to be added to the insulator 280 during deposition.

[0353] In this embodiment, the insulator 283 is formed of silicon nitride by sputtering. A film of kon is formed.

[0354] As shown in FIG. 18B to FIG. 18D, the insulator 287 is an insulating material at the bottom surface of the opening. The insulator 283 contacts the insulator 287. That is, the transistor 200 The upper surface and side surfaces are wrapped in the insulator 287 and the insulator 283, and the lower surface is wrapped in the insulator 212. In this way, the insulator 287 with high barrier properties, the insulator 283, and the insulator The transistor 200 is enclosed in the body 212, so that moisture and hydrogen can be prevented from entering from the outside. It is possible to prevent the above.

[0355] In the present embodiment, the insulating film 274A is formed by sputtering an oxide film. A silicon film is formed.

[0356] In addition, when the insulator 287 is not provided, the insulator 283 and the insulating film 274A are exposed to the atmosphere. It is advisable to deposit the films continuously without exposing them to a boundary.

[0357] Next, the insulating film 274A is subjected to CMP processing to form an insulator 274 with a flat upper surface ( See Figures 19B to 19D.)

[0358] Next, heat treatment may be performed. In this embodiment, heat treatment is performed in a nitrogen atmosphere at a temperature of 400° C. The treatment is carried out for 1 hour. The oxygen added to the insulator 280 is converted to an oxide by the heat treatment. 230c to the oxide 230a and the oxide 230b. The heat treatment may be performed not only after the formation of the insulator 274 but also after the formation of the insulator 282. This is also fine.

[0359] Next, insulator 254, insulator 280, insulator 282, insulator 287, and insulator 28 3, an opening reaching the conductor 242a and an opening reaching the conductor 242b are formed (FIG. 2 0A and 20B. The openings can be formed by using a lithography method. In addition, although the shape of the opening is circular when viewed from above in FIG. 20A, it is not limited to this. For example, the opening may be substantially circular, such as an ellipse, or rectangular when viewed from above. or a polygonal shape such as a square with rounded corners.

[0360] Next, an insulating film that will become the insulators 241a and 241b is formed, and the insulating film is anisotropically Reactive etching is performed to form insulators 241a and 241b (FIGS. 20A and 2 0B.) The insulating film is formed by sputtering, CVD, MBE, and PLD methods. The insulating film may be formed by using an ALD method or the like. For example, an insulating film having an aluminum oxide film can be formed by the ALD method. Alternatively, a silicon nitride film is formed by using the PEALD method. Silicon nitride is preferred because it has a high blocking property against hydrogen.

[0361] The anisotropic etching of the insulating film may be performed by using, for example, a dry etching method. By providing the insulators 241a and 241b on the side walls of the opening, the insulators 241a and 241b can prevent the inflow of oxygen from the outside. This suppresses the permeation of oxygen and prevents the oxidation of the conductors 240a and 240b that will be formed next. In addition, impurities such as water and hydrogen can be removed from the conductors 240a and 240b. can be prevented from spreading to the outside.

[0362] Next, a conductive film that will become the conductor 240a and the conductor 240b is formed. It is desirable to have a laminated structure that includes a conductor that has the function of suppressing the permeation of impurities such as water and hydrogen. For example, tantalum nitride, titanium nitride, etc., and tungsten, molybdenum, copper, etc. The conductive film can be formed by a sputtering method, a CVD method, etc. The deposition can be performed by using an MBE method, a PLD method, an ALD method, or the like.

[0363] Next, a part of the conductive film is removed by CMP processing, and the insulator 283 and the insulating film are removed. As a result, the conductive film remains only in the opening, and the upper surface of the substrate 274 is exposed. Planar conductors 240a and 240b can be formed (FIGS. 20A and 20B). (See FIG. 20B.) Note that, due to the CMP process, a part of the upper surface of the insulator 283 and the insulating film A portion of the top surface of the rim 274 may be removed.

[0364] Next, a conductive film that will become the conductor 246a and the conductor 246b is formed. The film can be formed by sputtering, CVD, MBE, PLD, ALD, etc. This can be done.

[0365] Next, a conductive film that will become the conductor 246a and the conductor 246b is formed by lithography. The conductor 246a is in contact with the upper surface of the conductor 240a, and the upper surface of the conductor 240b is in contact with the upper surface of the conductor 246b. At this time, the conductor 246a and the conductor 246b are insulated from each other. A part of the insulator 283 in a region where the insulator 283 does not overlap with the edge 283, the conductor 246a, and the conductor 24 6b and a portion of the insulator 274 in the area where the insulator 274 does not overlap may be removed. (See Figures 21B to 21D.)

[0366] Next, on the conductor 246a, on the conductor 246b, on the insulator 274, and on the insulator 283 Next, an insulator 286 is deposited (see FIGS. 4A to 4D). This can be done using a deposition method, a CVD method, an MBE method, a PLD method, an ALD method, etc. The insulator 286 may also be multi-layered. For example, a nitride layer may be formed by sputtering. Even if a silicon film is formed and a silicon nitride film is formed on the silicon nitride film by using a CVD method, good.

[0367] In this manner, a semiconductor device including the transistor 200 shown in FIGS. 4A to 4D is manufactured. As shown in FIGS. 5 to 21, the method for manufacturing the semiconductor device described in this embodiment can be performed. The transistor 200 can be manufactured by using the method.

[0368] Note that when a semiconductor device including the transistor 200 shown in FIGS. 1A to 1D is manufactured, 17A to 17D, an insulator 287 and an insulating film 274A are formed. 19A to 19D. At this time, the insulators 282 and 283 are formed continuously without being exposed to the air environment. It is preferable to coat the substrate with a film.

[0369] <Modification 2 of Semiconductor Device> An example of a semiconductor device according to this embodiment will be described below with reference to FIGS. 22A to 22D. We will explain about this.

[0370] FIG. 22A is a top view of a semiconductor device including a transistor 200A. FIG. 22 is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in FIG. 22C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in FIG. 2D is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in FIG. In the top view of FIG. 1, some elements have been omitted for clarity.

[0371] In the semiconductor device shown in FIG. 22A to FIG. 22D, and a structure having the same function as the structure constituting the semiconductor device shown in <Modification 1 of the semiconductor device>. In this section, the constituent materials of the semiconductor device are also Use the materials described in detail in <Configuration Example of Semiconductor Device> and <Modification 1 of Semiconductor Device>. can be done.

[0372] The semiconductor device shown in FIGS. 22A to 22D is a variation of the semiconductor device shown in FIGS. 4A to 4D. The semiconductor device shown in FIGS. 22A to 22D is an example. The device is different from the device shown in FIG. 1 in that it has an insulator 271a and an insulator 271b. 230c, and oxide 230d.

[0373] In the semiconductor device shown in FIG. 22A to FIG. 22D, An insulator 271a is provided, and an insulator 271b is provided between the conductor 242b and the insulator 254. It is being done.

[0374] Here, the insulators 271a and 271b have a function of suppressing the diffusion of oxygen. This makes it possible to form a conductive material 2 that functions as a source electrode or a drain electrode. The absorption of excess oxygen from the insulator 280 by the conductor 242a and the conductor 242b is suppressed. In addition, by suppressing the oxidation of the conductor 242a and the conductor 242b, It is possible to suppress an increase in the contact resistance between the transistor and the wiring. The insulator 271a and the insulator 271b can provide the insulator 200A with good electrical properties and reliability. The insulator 271b can be formed using, for example, a material similar to that of the insulator 254. .

[0375] In the method for manufacturing the semiconductor device shown in FIGS. 22A to 22D, the insulator 271a and The insulating layer that becomes the insulator 271b and the conductive layer provided on the insulating layer are called a conductive film 242. By using the mask A, the conductors 242a and 242b are The ends where the surfaces intersect are angular. The conductors 242a and 242b are formed in a square shape at the end portions, so that the conductors 242a and 242b are formed in a square shape at the end portions, compared to when the end portions have a curved surface. The cross-sectional areas of the conductors 242a and 242b are increased. Since the resistance of 2b is reduced, the on-current of the transistor 200A can be increased. do.

[0376] In addition, by not providing the oxide 230c and the oxide 230d, the transistor Between the transistor 200A and the transistor 200A adjacent to the transistor 200A, Suppresses the occurrence of parasitic transistors and suppresses the occurrence of leakage paths along the conductor 260 Therefore, it is possible to obtain a semiconductor device having good electrical characteristics and capable of being miniaturized or highly integrated. It is possible to provide a semiconductor device capable of performing the above.

[0377] <Applications of semiconductor devices> In the following, the above-mentioned <Configuration Example of Semiconductor Device> and the above-mentioned A transistor according to the present embodiment, which is different from that shown in <Modification 1 of the semiconductor device> An example of a semiconductor device having the semiconductor device 200 will be described. In the semiconductor device, the semiconductor device shown in <Modification 1 of the semiconductor device> (FIGS. 4A to 4 D.) and structures having the same functions are given the same symbols. Regarding the material of the transistor 200, see <Configuration Example of Semiconductor Device> and <Semiconductor The materials explained in detail in the section "Modification 1 of the semiconductor device" can be used.

[0378] 23A and 23B show a plurality of transistors (transistors 200_1 to 200_3). The resistor 200_n is collectively referred to as an insulator 287, an insulator 283, and an insulator 212. In addition, in FIG. 23A and FIG. 23B, the plurality of transistors are sealed. The transistors appear to be aligned along the channel length, but this is not necessarily the case. The multiple transistors may be arranged in the channel width direction or in a matrix. Also, they may be arranged without any regularity depending on the design.

[0379] As shown in FIG. 23A, a plurality of transistors (transistors 200_1 to On the outside of the heater 200_n, the insulator 287 and the insulator 283 are connected to the insulator 212. The sealing portion 265 is formed in such a manner that the sealing portion 265 is sealed by the sealing member 265. , which is formed to surround the plurality of transistors (also referred to as a transistor group). By using such a structure, multiple transistors are connected to the insulators 287 and 283. The transistors can be wrapped in the insulator 212. , a plurality of them will be provided on the substrate.

[0380] In addition, a dicing line (scribe line, dividing line, or The substrate may be divided at the dicing line. Since the semiconductor device is cut, the group of transistors enclosed by the sealing portion 265 can be extracted as one chip. It becomes.

[0381] In addition, in FIG. 23A, a plurality of transistors (transistors 200_1 to 200_n) is surrounded by one sealing portion 265, but the present invention is not limited to this. As shown in FIG. 23B, the plurality of transistors are surrounded by a plurality of sealing portions. In FIG. 23B, the plurality of transistors are surrounded by a sealing portion 265a, and The sealing portion 265b also surrounds the semiconductor device.

[0382] In this manner, a plurality of transistors (transistors 200_1 to 200_3) are sealed in a plurality of sealing portions. By surrounding the resistor 200_n, the insulator 287 and the insulator 283 Since the contact area of ​​the insulator 287 and the insulator 283 with the insulator 212 increases, This can improve adhesion, and therefore seal multiple transistors more reliably. It can be stopped.

[0383] In this case, even if a dicing line is provided overlapping the sealing portion 265a or the sealing portion 265b, Alternatively, a dicing line may be provided between the sealing portion 265a and the sealing portion 265b.

[0384] It should be noted that the insulator 287 does not necessarily have to be provided.

[0385] According to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics and In addition, according to one embodiment of the present invention, a semiconductor device having high reliability can be manufactured. According to one embodiment of the present invention, a semiconductor device and a manufacturing method thereof can be provided. It is possible to provide a semiconductor device having good electrical characteristics and a manufacturing method thereof. According to one embodiment of the present invention, a semiconductor device with a large on-state current and a manufacturing method thereof are provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. In addition, according to one embodiment of the present invention, a low power consumption It is possible to provide a semiconductor device having such a high power and a method for manufacturing the same.

[0386] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0387] (Embodiment 2) The semiconductor device in this embodiment mode can be used to manufacture the semiconductor device shown in the other embodiment modes. The device will be described with reference to FIG.

[0388] When manufacturing a semiconductor device according to another embodiment, different types of films can be successively formed. It is preferable to use a so-called multi-chamber apparatus having a plurality of processing chambers. can be subjected to film formation processing by sputtering, CVD, ALD, etc. .

[0389] In addition, each processing chamber performs substrate cleaning, plasma processing, and reverse sputtering processing. In each processing chamber, etching, ashing, heating, etc. may be performed. By performing different processes as appropriate, insulating films, conductive films, and semiconductor films can be formed without exposing them to the atmosphere. A film can be formed.

[0390] A typical example of a semiconductor film used in one embodiment of the present invention is an oxide semiconductor film. In particular, an oxide semiconductor film having a low impurity concentration and a low density of defect states (few oxygen vacancies) has the following properties: A transistor having excellent electrical characteristics can be manufactured. A material having a low density of defect states is called high purity intrinsic or substantially high purity intrinsic.

[0391] A highly-purified intrinsic or substantially highly-purified intrinsic oxide semiconductor film has a small carrier generation source. Therefore, the carrier concentration can be reduced. The transistor in which the junction region is formed has electrical characteristics in which the threshold voltage is negative (normal Also, it is rare for the product to become intrinsic or substantially intrinsic. In some oxide semiconductor films, the density of defect states is low, and therefore the density of trap states may also be low. In addition, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a significantly low off-state current. It is very small and has a channel width of 1×10 6 μm and the channel length L is 10 μm. When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, The off-state current is below the measurement limit of the semiconductor parameter analyzer, i.e., 1×10 -13 After A The following characteristics can be obtained.

[0392] Typical examples of impurities in the oxide semiconductor film include water and hydrogen. In addition, in this specification and the like, the reduction or removal of water and hydrogen from an oxide semiconductor film The addition of oxygen to the oxide semiconductor film may be referred to as dehydration or dehydrogenation. , or oxygenated, which is oxygenated and has an excess of oxygen over the stoichiometric composition The condition is sometimes referred to as hyperoxia.

[0393] Here, the oxide semiconductor, the insulator or conductor located under the oxide semiconductor, and and / or an insulator or conductor located on the oxide semiconductor, and By continuously depositing the film without any additional steps, the concentration of impurities (especially hydrogen and water) is reduced, resulting in a substantially high An oxide semiconductor film with intrinsic purity can be formed.

[0394] Further, a stacked structure formed before the formation of the oxide semiconductor film or a stacked structure formed after the formation of the oxide semiconductor film The laminated structure formed after processing should also be formed continuously without exposing to the atmosphere. The concentration of impurities (particularly hydrogen and water) in the stacked structure is reduced, and the impurities are absorbed in the oxide semiconductor. Diffusion into the membrane can be suppressed.

[0395] First, a configuration of an apparatus that can be used for manufacturing a semiconductor device shown in another embodiment will be described. The details of the example will be described with reference to FIG. 24. By using the device shown in FIG. A semiconductor film and an insulating or conductive material located under the semiconductor film and / or a semiconductor film on the semiconductor film. The insulating film or conductive film located in the semiconductor film can be formed continuously. This can suppress impurities (especially hydrogen and water) that may enter the inside of the filter. The device is not limited to continuous deposition of a laminated structure having a semiconductor film, but can also continuously deposit insulating films of different materials. It is possible to continuously deposit conductive films made of different materials, and continuously deposit laminated structures of insulating and conductive films. It becomes.

[0396] FIG. 24 is a schematic top view of a single-wafer type multi-chamber apparatus 4000.

[0397] The apparatus 4000 includes an atmospheric substrate supply chamber 4010 and a substrate supply chamber 4020. The atmospheric side substrate transfer chamber 4012 transfers the substrate, and the atmospheric side substrate transfer chamber 4013 transfers the substrate and changes the pressure in the chamber from atmospheric pressure to A load lock chamber 4020a for switching from reduced pressure to atmospheric pressure and a load lock chamber 4020b for transferring the substrate Unloading is performed by switching the pressure in the room from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure. A lock chamber 4020b, a transfer chamber 4029 for transferring a substrate in a vacuum, and a transfer chamber 403 9, a transfer chamber 4030 connecting the transfer chamber 4029 and the transfer chamber 4039, and a film forming or heating The process chambers 4024a, 4024b, 4024c, and 4024d are It has a processing chamber 4034a, a processing chamber 4034b, and a processing chamber 4034c.

[0398] The multiple processing chambers can each perform different processes in parallel. It is possible to easily fabricate a laminated structure of different film types. For example, the apparatus 4000 shown in FIG. 24 has seven processing chambers. Therefore, using one device (also referred to as in-situ in this specification), Seven film deposition processes can be performed consecutively without being exposed to the atmosphere.

[0399] On the other hand, in a laminated structure, the number of layers that can be produced without exposing to the atmosphere does not necessarily depend on the number of processing chambers. For example, if the desired laminate structure has multiple layers of the same material, Since the layers can be formed in one processing chamber, the number of stacked layers can be greater than the number of processing chambers installed. It is possible to fabricate a multi-layer structure.

[0400] The atmospheric side substrate supply chamber 4010 has a cassette port 4014 for accommodating substrates and an arranging port for arranging the substrates. The cassette port 401 is provided with an alignment port 4016 for alignment. The number 4 may be multiple (for example, three in FIG. 24).

[0401] The atmospheric substrate transfer chamber 4012 includes a load lock chamber 4020a and an unload lock chamber 4020b. The transfer chamber 4029 is connected to the load lock chamber 4020a and the unload lock chamber 4020b. The transfer chamber 4030, the processing chamber 4024a, the processing chamber 4024b, the processing chamber 402 The transfer chamber 4030 is connected to the transfer chamber 4029 and the processing chamber 4024d. The transfer chamber 4039 is connected to the transfer chamber 4030, the processing chamber 4034a, and the transfer chamber 4039. , processing chamber 4034b, and processing chamber 4034c.

[0402] A gate valve 4028 or a gate valve 4038 is provided at the connection between the chambers. Each chamber is independent except for the atmospheric substrate supply chamber 4010 and the atmospheric substrate transfer chamber 4012. The vacuum can be maintained by the vacuum pump.

[0403] The atmospheric substrate transfer chamber 4012 also includes a transfer robot 4018. The transfer chamber 4039 has a transfer robot 4036 . The transport robot 4018, the transport robot 4026, and the transport robot 4036 are It has a movable part and an arm that holds a substrate, and can transport the substrate to each chamber.

[0404] The transfer chamber, the processing chamber, the load lock chamber, the unload lock chamber and the transfer chamber are the same as those described above. There is no limit to the number of units, so you can set the optimal number according to the installation space and process conditions. can.

[0405] In FIG. 24, one transfer chamber (transfer chamber 4030), but is not limited to this. When there are multiple transfer chambers, It is preferable to have two or more transfer chambers between one transfer chamber and another transfer chamber. For example, in the case where the transfer chamber 4029 and the transfer chamber 4039 are provided, the transfer chamber 4029 and the transfer chamber 40 It is preferable that two transfer chambers (not shown in FIG. 24) are arranged in parallel between the transfer chamber 39 and the transfer chamber 39. It is nice.

[0406] By arranging two transfer chambers in parallel, for example, the transfer robot 4026 can a step of loading a substrate into the transfer chamber, and a step of the transfer robot 4036 loading the substrate into the other transfer chamber; The transfer robot 4026 can simultaneously pick up the substrate from the other transfer chamber. The transfer robot 4036 transfers the substrate from one of the transfer chambers. In other words, by driving multiple transport robots simultaneously, production efficiency can be improved. will improve.

[0407] In addition, in FIG. 24, one transfer chamber has one transfer robot and is connected to multiple processing chambers. Although an example of connecting multiple transport robots is shown, this is not limited to this structure. The ion exchange resin may have a fluorine atom.

[0408] In addition, one or both of the transfer chambers 4029 and 4039 are connected via a valve. It is connected to a vacuum pump and a cryopump. The delivery chamber 4039 uses a vacuum pump to change the pressure from atmospheric pressure to low or medium vacuum (several hundred Pa or less). After evacuating the chamber to about 0.1 Pa, switch the valve and use a cryopump to evacuate the chamber. From air to high or ultra-high vacuum (0.1 Pa to 1×10 -7 The exhaust pressure must be reduced to approximately 1 Pa. can be done.

[0409] Also, for example, two or more cryopumps may be connected in parallel to one transfer chamber. By having multiple cryopumps, even if one cryopump is in regeneration, It is possible to pump the gas using another cryopump. This is the process of releasing the molecules (or atoms) stored in the ion pump. If too many molecules (or atoms) accumulate in the filter, its exhaust capacity will decrease, so it is recommended to periodically refill the filter. It is a good idea to do this.

[0410] Processing chamber 4024a, processing chamber 4024b, processing chamber 4024c, processing chamber 4024d, processing chamber The processing chambers 4034a, 4034b, and 4034c are each used for performing different processes in parallel. That is, sputtering can be performed on the substrates placed in each processing chamber. , CVD, MBE, PLD, ALD, etc., heat treatment, or plasma treatment In addition, in the treatment chamber, after a heat treatment or a plasma treatment, a formation A membrane treatment may also be carried out.

[0411] The apparatus 4000 has a plurality of processing chambers, so that the substrate is exposed to the atmosphere between processing. Since the substrate can be transported without being damaged, it is possible to prevent impurities from being adsorbed on the substrate. Each processing chamber can perform a different type of film deposition process, a heat treatment, or a plasma treatment. Therefore, the order of film formation, heat treatment, etc. can be freely configured.

[0412] Each processing chamber may be connected to a vacuum pump via a valve. For example, a dry pump, a mechanical booster pump, etc. can be used.

[0413] Each processing chamber may be connected to a power source capable of generating plasma. As a power source, a DC power source, an AC power source, or a high frequency (RF, microwave, etc.) power source can be provided. Alternatively, a pulse generator may be connected to the DC power supply.

[0414] The processing chamber is connected to a gas supply device and a gas purification device connected to the gas supply device. The number of gas supply devices and gas purification devices may be the same as the number of gas types. .

[0415] For example, when a film formation process is performed by sputtering in a processing chamber, the processing chamber is A backing plate connected to the target and a target via the backing plate. The apparatus may also include a cathode arranged opposite the get, an adhesion prevention plate, a substrate stage, and the like. For example, the substrate stage may include a substrate holding mechanism for holding the substrate, a substrate heating mechanism for heating the substrate from the rear surface, and a The substrate may also be equipped with a rear heater, a power supply for applying a bias to the substrate, and the like.

[0416] The substrate stage is held approximately perpendicular to the floor during film formation. At times, the substrate stage is held in a substantially horizontal position relative to the floor surface. By making it nearly vertical, the probability that dust or particles that may be mixed in during film formation will adhere to the substrate is reduced. However, the substrate stage can be moved relative to the floor surface. If the substrate is held vertically (90°), the substrate may fall. It is preferable that the angle with respect to the floor surface is greater than or equal to 80° and less than 90°.

[0417] The configuration of the substrate stage is not limited to the above configuration. For example, In this case, the substrate stage may be arranged so as to be approximately horizontal to the floor surface. A target is placed below, and a substrate is placed between the target and the substrate stage. The substrate stage is equipped with a jig to hold the substrate in place so that it does not fall off, or a The device may be provided with a mechanism for determining whether the

[0418] In addition, by providing a shield in the processing chamber, particles sputtered from the target are prevented from being generated. The deposition of the spatter can be prevented in the desired area. It is desirable to process the ring particles so that they do not peel off. For example, by increasing the surface roughness, Alternatively, the surface of the adhesion prevention plate may be roughened by blasting.

[0419] The backing plate has a function of holding the target, and the cathode is It has the function of applying a voltage (for example, a negative voltage).

[0420] The target may be a conductor, an insulator, or a semiconductor. For example, When the target is an oxide semiconductor such as a metal oxide, an oxide semiconductor film is formed in the treatment chamber. In addition, even when the target is a metal oxide, the deposition gas can be nitrogen. If a nitrogen gas is used, an oxynitride semiconductor film can also be formed.

[0421] In addition, each processing chamber may be connected to a gas supply device via a gas heating mechanism. The system is connected to a gas purification device via a gas supply device. The temperature is -80°C or lower, preferably -100°C or lower, and more preferably -120°C or lower. For example, oxygen gas, nitrogen gas, and rare gas (argon gas, etc.) can be used. ) can be used. In addition, the gas introduced into the processing chamber can be heated to 40°C by a gas heating mechanism. The temperature can be increased to 400° C. or lower, preferably 50° C. or higher and 200° C. or lower. It is advisable to provide as many gas heating mechanisms, gas supply devices, and gas purification devices as there are types of gas.

[0422] Each processing chamber may be connected to a turbomolecular pump and a vacuum pump via a valve. Each processing chamber may be provided with a cryotrap.

[0423] In addition, cryotraps adsorb molecules (or atoms) with relatively high melting points, such as water. Turbomolecular pumps are a mechanism that can stabilise large molecules (or atoms). The system is highly productive because it requires little maintenance, but it also requires little effort to exhaust hydrogen or water. The capacity is low. Therefore, in order to improve the pumping capacity for water, etc., a cryotrap is used. The temperature of the cryotrap refrigerator is 100K or less, preferably 80K or less. In addition, if the cryotrap has multiple refrigerators, the temperature of each refrigerator should be changed. For example, the temperature of the first stage refrigerator is should be set to 100K or less, and the temperature of the second stage refrigerator should be set to 20K or less.

[0424] The exhaust method of the processing chamber is not limited to this, and may be the exhaust method (clamp method) shown in the transfer chamber connected to the processing chamber. The same configuration as the exhaust method of the ion pump and the vacuum pump may be used. The method may be the same as that of the processing chamber (a turbo molecular pump and a vacuum pump). .

[0425] In particular, a vacuum pump and a cryostat are used as a method for evacuating a processing chamber in which an oxide semiconductor film is formed. A wrap may be combined with the oxide semiconductor film. As an exhaust method, it is preferable that the exhaust gas has a function of at least adsorbing water molecules. .

[0426] In addition, the partial pressure of hydrogen molecules in the treatment chamber for forming the oxide semiconductor film was 1×10 -2 Below Pa And the partial pressure of water molecules is 1×10 -4 It is preferable that the resistance of the oxide semiconductor is less than 1 Pa. The pressure in the waiting state of the treatment chamber for forming the solid film is 8.0×10 -5 Pa or less, preferably 5.0×10 -5 Pa or less, more preferably 1.0×10 -5 Pa or less. The partial pressure of hydrogen molecules and the partial pressure of water molecules were measured while the sputtering chamber was in standby. The values ​​are for both the non-discharge state and the film-forming state (plasma discharge state).

[0427] The total pressure and partial pressure of the process chamber can be measured using a mass spectrometer. , ULVAC, Inc., Quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 can be used.

[0428] The partial pressure of hydrogen molecules, the partial pressure of water molecules, and the pressure in the standby state in the treatment chamber are set within the above ranges. By this, the concentration of impurities in the oxide semiconductor film to be formed can be reduced. .

[0429] In addition, for example, when a heat treatment is performed in the treatment chamber, the treatment chamber can accommodate a substrate. The heating stage may be a multi-stage structure. By increasing the number of heating stages, multiple substrates can be heated simultaneously, improving productivity. It can be improved.

[0430] The heating mechanism that can be used in the processing chamber is, for example, a heating mechanism using a resistance heating element. Alternatively, the heating mechanism may be a heat transfer mechanism, such as a heated gas or other medium. For example, a heating mechanism that uses GRTA (Gas Rapid Transient Atomic Energy Thermal Anneal), LRTA(Lamp Rapid Thermal By using RTA (Rapid Thermal Anneal) etc. LRTA can be used with halogen lamps, metal halide lamps, and xenon arc lamps. The radiation emitted from lamps such as high-pressure sodium lamps, carbon arc lamps, and high-pressure mercury lamps The GRTA uses high-temperature gas to heat the material being treated. Heat treatment is performed using an inert gas.

[0431] The apparatus 4000 is capable of performing a film formation process by sputtering in six processing chambers. It is preferable to configure the processing chamber so that the heat treatment can be performed in one processing chamber. A laminated structure in which a part of the configuration of the semiconductor device shown in the embodiment is successively formed in-situ When the heat treatment is performed in an apparatus other than the apparatus 4000, The apparatus 4000 is configured so that all of the processing chambers can perform film formation by sputtering. It may be possible to make it.

[0432] In a method for manufacturing a semiconductor device having a transistor 200, 14 and the insulator 216 are successively deposited using the apparatus 4000. In addition, the insulator 222 , the insulator 224, the oxide film 230A, the oxide film 230B, and the oxide film 243A are 00, the insulator 254 and the insulating film 280A are successively formed. 0 are successively deposited. Insulator 282 and insulator 283, or insulator 2 87, the insulator 283, and the insulating film 274A are successively formed using the apparatus 4000.

[0433] That is, the insulators 212, 214, and 216 are connected together without being exposed to the atmosphere. The insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B can be formed successively. The oxide film 230B and the oxide film 243A can be formed continuously without exposure to the atmosphere. In addition, the insulator 254 and the insulating film 280A can be formed in succession without exposure to the atmosphere. In addition, the insulator 282 and the insulator 283 or the insulator 287, The insulator 283 and the insulating film 274A can be formed continuously without exposure to the atmosphere. Cut.

[0434] The above structure allows the lamination to be made with a structure that thoroughly removes impurities (typically water, hydrogen, etc.). In addition, since the interfaces of the laminated film are not exposed to the atmosphere, The impurity concentration is reduced.

[0435] The load lock chamber 4020a includes a substrate delivery stage and a back surface heating device for heating the substrate from the back surface. The load lock chamber 4020a may be equipped with a heater or the like. The pressure is increased, and when the pressure in the load lock chamber 4020a becomes atmospheric pressure, the atmospheric side substrate transfer The substrate transfer stage transfers the substrate from the transfer robot 4018 provided in the transfer chamber 4012. After that, the load lock chamber 4020a is evacuated to a reduced pressure, and then the A transfer robot 4026 provided in the chamber 4029 receives the substrate from the substrate delivery stage. Take.

[0436] The load lock chamber 4020a is connected to a vacuum pump and a cryopump via a valve. The unload lock chamber 4020b is connected to the load lock chamber 4020. It is sufficient to use a similar configuration to a.

[0437] The atmospheric substrate transfer chamber 4012 has a transfer robot 4018. 18, the transfer of the substrate between the cassette port 4014 and the load lock chamber 4020a is performed. In addition, the atmosphere side substrate transfer chamber 4012 and the atmosphere side substrate supply chamber 4010 Above the filter is a High Efficiency Particulate Air (HEPA) filter. e) Air Filter) to prevent the intrusion of dust or particles. Also, the cassette port 4014 can store multiple substrates.

[0438] Using the above-mentioned apparatus 4000, an insulating film, a semiconductor film, and a conductive film are formed without being exposed to the atmosphere. By forming the films successively, the intrusion of impurities into the semiconductor film can be suitably suppressed.

[0439] As described above, by using the device of this embodiment mode, a stacked structure having a semiconductor film and a semiconductor The laminated structure near the conductor film can be fabricated by successive film formation. The aim is to create a semiconductor film that suppresses the incorporation of impurities such as hydrogen and water and has a low defect level density. It is possible.

[0440] The structures, methods, etc. described in this embodiment may be combined as appropriate with the structures, methods, etc. described in other embodiments. They can be used in combination.

[0441] (Embodiment 3) In this embodiment, one mode of a semiconductor device will be described with reference to FIGS.

[0442] [Storage device 1] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIG. In the semiconductor device, the transistor 200 is provided above the transistor 300, and the capacitance element The transistor 100 is provided above the transistor 300 and the transistor 200. In this case, the transistor 200 described in the previous embodiment is used as the transistor 200. This can be done.

[0443] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This makes it possible to retain the memory contents for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0444] In the semiconductor device shown in FIG. 25, a wiring 1001 is electrically connected to the source of a transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200. 006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to a capacitor. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. It is electrically connected to the other.

[0445] In addition, the memory device shown in FIG. 25 has a memory cell array arranged in a matrix. It can be configured.

[0446] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 that functions as a gate. 3, an insulator 315 serving as a gate insulator, and a semiconductor region 31 3, and a low resistance region 314a serving as a source region or a drain region, and The transistor 300 may be a p-channel or an n-channel Any type is acceptable.

[0447] Here, the transistor 300 shown in FIG. 25 has a semiconductor region 313 ( A part of the substrate 311 has a convex shape. The side and top surfaces of the semiconductor region 313 are insulated. The conductor 316 is provided so as to cover the edge 315. Materials for adjusting the work function may be used. Since it uses a protruding part, it is also called a FIN type transistor. In addition, the insulating layer may have an insulating material that functions as a mask for forming the protrusions. Here, a case where a protrusion is formed by processing a part of a semiconductor substrate is shown, but a SOI substrate is also processed. A semiconductor film having a convex shape may be formed by the above-mentioned method.

[0448] Note that the transistor 300 shown in FIG. 25 is just an example, and the present invention is not limited to this structure. Appropriate transistors may be used depending on the configuration and driving method.

[0449] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. A conductor 110 functions as the first electrode, a conductor 120 functions as the second electrode, and a dielectric The insulator 130 functions as a dielectric. It is preferable to use an insulator that can be used as insulator 286 shown.

[0450] Also, for example, the conductor 112 provided on the conductor 240 and the conductor 110 are formed at the same time. Note that the conductor 112 can be used for the capacitor 100, the transistor 200, and has a function as a plug or wiring that is electrically connected to the transistor 300 .

[0451] In FIG. 25, the conductor 112 and the conductor 110 are shown as having a single-layer structure. However, the present invention is not limited to this, and may be a laminated structure of two or more layers. For example, Conductors that have barrier properties between weak conductors and those with high electrical conductivity have good adhesion to conductors with high electrical conductivity. may form a highly conductive material.

[0452] The insulator 130 may be, for example, silicon oxide, silicon oxynitride, or silicon nitride oxide. , silicon nitride, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, nitrogen Aluminum oxide, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium The conductive layer may be formed as a laminate or a single layer.

[0453] For example, the insulator 130 may be made of a material with high dielectric strength, such as silicon oxynitride, or a material with high dielectric strength. It is preferable to use a laminated structure with a high-k material. The semiconductor device 100 has a high dielectric constant (high-k) insulator, so that it can ensure sufficient capacitance. By using an insulator having a large dielectric strength, the dielectric strength is improved, and the electrostatic breakdown of the capacitance element 100 is prevented. This can suppress the destruction.

[0454] Gallium oxide is an example of a high-dielectric-constant (high-k) material. , hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, Oxynitride with aluminum and hafnium, Oxynitride with silicon and hafnium Oxide, oxynitride with silicon and hafnium or silicon and hafnium and nitrides having the formula:

[0455] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide and oxynitride. Silicon oxide, silicon nitride, silicon nitride, silicon oxide doped with fluorine, carbon Doped silicon oxide, carbon and nitrogen doped silicon oxide, vacancy-containing silicon oxide Examples include concrete or resin.

[0456] <Wiring layer> Between each structure, a wiring layer is provided in which an interlayer film, wiring, plugs, etc. are provided. Also, a plurality of wiring layers may be provided according to the design. Conductors that function as wiring or wiring may be grouped together and given the same symbol. In addition, in the present specification and the like, the wiring and the plug that are electrically connected to the wiring may be integrated. That is, when a part of the conductor functions as a wiring, or when the conductor In some cases, some parts also function as plugs.

[0457] For example, an insulator 320, an insulator 322, and an insulator 323 are provided on the transistor 300 as an interlayer film. The edge member 324 and the insulator 326 are laminated in this order. The insulators 322, 324, and 326 are connected to the capacitive element 100 or the transistor. A conductor 328 and a conductor 330 are embedded in the conductive layer 200. The conductor 328 and the conductor 330 function as plugs or wiring.

[0458] In addition, the insulator that functions as an interlayer film acts as a flattening film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be chemically mechanically polished ( The surface may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like.

[0459] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. In the insulating layer 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed on the insulators 350, 352, and 354. The conductor 356 functions as a plug or a wiring.

[0460] Similarly, the insulators 210, 212, 214, and 216 are each provided with a conductive The conductive body 218 and the conductive body (conductive body 205) constituting the transistor 200 are embedded. Note that the conductor 218 is electrically connected to the capacitor 100 or the transistor 300. The conductor 120 and the insulator 130 function as a plug or wiring for connecting the conductor 120 and the insulator 130. On top of 130 is an insulator 150 .

[0461] Here, similarly to the insulator 241a and the insulator 241b shown in the above embodiment, The insulator 217 is provided in contact with the side surface of the conductor 218 which functions as a , the openings formed in the insulators 210, 212, 214, and 216. That is, the insulator 217 is provided in contact with the side wall. , and the insulator 212, the insulator 214, and the insulator 216. The conductor 205 can be formed in parallel with the conductor 218, so that the side of the conductor 205 In some cases, an insulator 217 may be formed in contact with the substrate.

[0462] The insulator 217 may be, for example, silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 217 may be an insulator such as silicon. Since the insulating member 222 is provided in contact with the insulating member 210 or the insulating member 216, water is prevented from entering the insulating member 222. Alternatively, impurities such as hydrogen are prevented from being mixed into the oxide 230 through the conductor 218. In particular, silicon nitride is suitable because it has a high blocking property against hydrogen. In addition, oxygen contained in the insulator 210 or the insulator 216 is absorbed into the conductor 218. This can be prevented.

[0463] Insulator 217 may be formed in a manner similar to insulators 241a and 241b. For example, a silicon nitride film can be formed using the PEALD method and then anisotropically etched. An opening reaching the conductor 356 may be formed.

[0464] Insulators that can be used as the interlayer film include oxides, nitrides, and oxides having insulating properties. These include metal nitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0465] For example, by using a material with a low relative dielectric constant for the insulator that functions as an interlayer film, Therefore, depending on the function of the insulator, the material It is recommended to select:

[0466] For example, the insulators 150, 210, 352, and 354 have relatively low resistance. It is preferable to have an insulator with a low dielectric constant, for example silicon oxynitride. , silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, carbon and and silicon oxide with added nitrogen, silicon oxide or resin with voids. Alternatively, the insulator is preferably silicon oxide, silicon oxynitride, or silicon nitride oxide. Silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, carbon Lamination of silicon oxide doped with silicon and nitrogen or silicon oxide having voids and resin It is preferable that the silicon oxide and silicon oxynitride have the structure. Therefore, by combining it with resin, it is possible to create a laminated structure that is thermally stable and has a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon), etc. Examples include polyimide, polycarbonate, and acrylic.

[0467] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the Therefore, the insulators 214, 212, and 350 can be made of hydrogen or the like. Any insulator that has the function of suppressing the permeation of impurities and oxygen may be used.

[0468] Examples of insulators that have a function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, the following insulators have the function of suppressing the permeation of impurities such as hydrogen and oxygen: Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tungsten oxide Metal oxides such as talc, silicon oxide nitride, silicon nitride, etc. can be used. .

[0469] Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, Gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium Sodium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium Materials containing one or more metal elements selected from the group consisting of ruthenium and lithium can be used. Semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as arsenic, A silicide such as nickel silicide may also be used.

[0470] For example, conductor 328, conductor 330, conductor 356, conductor 218, and conductor 1 12, etc., may be a metal material, an alloy material, a metal nitride material, or the like formed from the above-mentioned materials. Conductive materials such as metal oxide materials can be used in a single layer or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that is also electrically conductive. It is particularly preferable to use tungsten. Alternatively, a low resistance conductive material such as aluminum or copper may be used. It is preferable to form the wiring from a low-resistance conductive material. It is possible.

[0471] <Wiring or plug of layer provided with oxide semiconductor> When an oxide semiconductor is used for the transistor 200, excess An insulator having an oxygen region may be provided. In that case, the insulator having the excess oxygen region and an insulator having a barrier property is provided between the conductor and the insulator having the excess oxygen region. It is preferable to provide such a function.

[0472] For example, in FIG. 25, insulator 224 and insulator 280 have excess oxygen, and conductor 2 40, an insulator 241 may be provided between the insulator 241 and the insulator 222 and the insulator 240. 82 and the insulator 283 are provided in contact with each other, The star 200 can be structured to be sealed with an insulator having barrier properties.

[0473] In other words, by providing the insulator 241, the excess of the insulators 224 and 280 It is possible to suppress the absorption of oxygen into the conductor 240. By having the above, hydrogen, which is an impurity, diffuses into the transistor 200 through the conductor 240. This can suppress the occurrence of

[0474] The insulator 241 is made of a material that suppresses the diffusion of impurities such as water or hydrogen, and oxygen. For example, silicon nitride, silicon oxide nitride, It is preferable to use aluminum oxide or hafnium oxide. In particular, silicon nitride is Magnesium oxide is preferred because it has a high blocking ability against hydrogen. Nesium, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, acid Metal oxides such as lanthanum oxide, neodymium oxide, or tantalum oxide can be used. do.

[0475] As in the above embodiment, the transistor 200 includes an insulator 212 and an insulator 214. It is preferable that the insulating material 282 and the insulating material 283 are sealed. By this, impurities (especially hydrogen and water) contained in the insulators 274 and 150 are absorbed into the insulators. In addition, the transistor 200 and the insulator 280 can be prevented from being mixed with each other. An insulator 287 may be provided between the first and second terminals 83 .

[0476] Here, the insulator 283 and the insulator 282 are connected to the conductor 240, the insulator 214 and the The conductor 218 penetrates the insulator 212, but as described above, the insulator 241 is the conductor. The insulator 217 is provided in contact with the conductor 218. Thus, the insulator 212, the insulator 214, the insulator 282 and the insulator 283. The insulators 212, 214, 282, 283, 241, and The transistor 200 is more securely sealed with the insulator 217, and the water contained in the insulator 274, etc. This can reduce the amount of impurities such as silicon that enter the transistor 200 .

[0477] Also, the insulators 216, 224, 280, 250, and 27 4 is a film formation method using a gas in which hydrogen atoms are reduced or removed, as shown in the previous embodiment. It is preferable that the insulators 216, 224, and 226 are formed by the method described above. 80, insulator 250, and insulator 274 may have reduced hydrogen concentrations.

[0478] In this way, the hydrogen concentration in the silicon-based insulating film in the vicinity of the transistor 200 is reduced, and the hydrogen concentration in the silicon-based insulating film in the vicinity of the transistor 200 is reduced. The hydrogen concentration in the compound 230 can be reduced.

[0479] <Dicing line> In the following, a large-area substrate is divided into individual semiconductor elements to produce multiple semiconductor devices. Dicing lines (scribe lines, dividing lines) are provided when extracting chips. The following describes the method of cutting the wire. First, grooves (dicing lines) for dividing the semiconductor elements are formed on the substrate, and then the dicing In some cases, the substrate is cut at a grinding line and divided (divided) into a plurality of semiconductor devices.

[0480] Here, for example, as shown in FIG. 25, the area where the insulator 283 and the insulator 212 contact each other It is preferable to design the dicing line so that the dicing line overlaps the dicing line. In the vicinity of the region that will become the dicing line provided on the outer edge of the memory cell having the data buffer 200, The insulator 282, the insulator 280, the insulator 254, the insulator 224, the insulator 222, the insulator 216, and an opening is provided in the insulator 214.

[0481] That is, the insulator 282, the insulator 280, the insulator 254, the insulator 224, the insulator 222, Insulator 216 and the openings in insulator 214 are connected to insulator 212 and insulator 214. For example, the insulator 212 and the insulator 283 are made of the same material. The insulator 212 and the insulator 283 may be formed using the same material and the same method. By providing the film by a method such as silicon nitride, the adhesion can be improved. is preferred.

[0482] With this structure, the insulators 212, 214, 282, and 283 , which can encapsulate the transistor 200. At least one of the insulating material 282 and the insulating material 283 has a function of suppressing the diffusion of oxygen, hydrogen, and water. Therefore, the substrate is divided into circuit regions each having a semiconductor element as shown in this embodiment mode. By dividing the substrate into multiple chips, hydrogen or other impurities can be easily absorbed from the side of the divided substrate. This can prevent impurities such as water from entering and diffusing into the transistor 200.

[0483] In addition, this structure prevents excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 can be prevented from The oxide is then efficiently applied to the transistor 200, forming the channel therein. The oxygen vacancies in the oxide in which the channel of the transistor 200 is formed are reduced by the use of the nitrogen atom. This allows the oxide in which the channel in the transistor 200 is formed to be formed. The oxide semiconductor can have a low density of defect states and stable characteristics. The fluctuation of the electrical characteristics of the transistor 200 can be suppressed and the reliability can be improved. do.

[0484] In the memory device shown in FIG. 25, the shape of the capacitor element 100 is a planar type. The storage device shown in the embodiment is not limited to this. For example, as shown in FIG. Alternatively, the shape of the capacitive element 100 may be a cylinder. The configuration below the edge 150 is similar to that of the semiconductor device shown in FIG.

[0485] An insulator 150 is provided on the insulator 130, and an insulator 142 is provided on the insulator 150. Note that openings are formed in the insulator 150 and the insulator 142.

[0486] The capacitance element 100 shown in FIG. 26 includes a conductor 115 and an insulator 142 on the conductor 115. The opening has an insulator 145 on the upper surface and a conductor 125 on the insulator 145. The conductor 115, the insulator 145, and at least a portion of the conductor 125 are disposed therein.

[0487] The conductor 115 functions as a lower electrode of the capacitor 100, and the conductor 125 functions as a lower electrode of the capacitor 100. 0, and insulator 145 serves as a dielectric for capacitive element 100. In the openings of the insulator 150 and the insulator 142, the capacitance element 100 is provided with a bottom surface, The upper and lower electrodes are also opposed to each other on the side with a dielectric material between them. The capacitance per area can be increased. In this way, the capacitance of the capacitance element 100 can be increased. By increasing the capacitance per unit area, miniaturization or high integration of semiconductor devices can be achieved. can be promoted.

[0488] An insulator 152 is provided on the conductor 125 and on the insulator 145 .

[0489] The insulator 152 may be made of any insulator that can be used for the insulator 280. The edge 142 acts as an etch stop when forming the opening in the insulator 150. It is preferable to use an insulator that can be used for the insulator 214.

[0490] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above is rectangular. Alternatively, the shape may be a polygon other than a rectangle, or the corners of the polygon may be rounded. Here, when viewed from above, the opening may be in a circular shape including an ellipse. It is preferable that the overlapping area between the gate and the transistor 200 is large. As a result, the area occupied by the semiconductor device having the capacitor element 100 and the transistor 200 can be reduced. This can be done.

[0491] The conductor 115 is disposed in contact with an opening formed in the insulator 142 and the insulator 150. It is preferable that the upper surface of the conductor 115 is substantially flush with the upper surface of the insulator 142. The lower surface of the conductor 115 contacts the conductor 110 through the opening of the insulator 130. The conductive layer 5 is preferably formed by ALD or CVD. Any conductor that can be used for 05 may be used.

[0492] The insulator 145 is disposed to cover the conductor 115 and the insulator 142. For example, It is preferable to form the insulator 145 by using an ALD method or a CVD method. 45 is, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, Zirconium oxide, aluminum oxide, aluminum oxide nitride, aluminum oxide nitride, Aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium oxynitride, hafnium nitride For example, the insulator 1 may be made of fluorine or the like, and may be formed as a laminate or a single layer. 45, zirconium oxide, aluminum oxide, zirconium oxide are layered in this order. An insulating film having such a structure can be used.

[0493] The insulator 145 is made of a material with high dielectric strength, such as silicon oxide nitride, or a material with high dielectric strength. It is preferable to use high-k materials. Alternatively, materials with high dielectric strength and high A stack of dielectric (high-k) materials may also be used.

[0494] Gallium oxide is an example of a high-dielectric-constant (high-k) material. , hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, Oxynitride with aluminum and hafnium, Oxynitride with silicon and hafnium oxide, oxide-nitride having silicon and hafnium, oxide-nitride having silicon and hafnium By using such high-k materials, the insulator 145 can be made thick. Even if the insulator 145 is made thicker, the capacitance of the capacitance element 100 can be sufficiently secured. This makes it possible to suppress leakage current occurring between the conductor 115 and the conductor 125. Cut.

[0495] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, silicon oxide with fluorine, silicon oxide with carbon, Examples include silicon oxide doped with carbon and nitrogen, silicon oxide having voids, and resin. For example, silicon nitride film formed by ALD method, silicon oxide film formed by PEALD method The insulating film is made of a silicon nitride film formed by the ALD method. By using such an insulator with high dielectric strength, the dielectric strength is improved and the capacity is increased. Therefore, electrostatic damage to the capacitor 100 can be suppressed.

[0496] The conductor 125 is disposed so as to fill the openings formed in the insulators 142 and 150. The conductor 125 is connected to the wiring 10 via the conductor 140 and the conductor 153. The conductor 125 is formed by using the ALD method or the CVD method. For example, a conductive material that can be used for the conductive material 205 may be used. stomach.

[0497] The conductor 153 is provided on an insulator 154 and is covered with an insulator 156. The conductor 153 may be made of any conductor that can be used for the conductor 112. The insulator 156 may be an insulator that can be used for the insulator 152. 53 is in contact with the upper surface of the conductor 140, and It serves as a terminal of transistor 300 .

[0498] The configurations, methods, etc. described in this embodiment may be different from the configurations, methods, etc. described in other embodiments. They can be used in appropriate combination.

[0499] (Embodiment 4) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0500] [Storage device 2] An example of a semiconductor device (memory device) in this embodiment mode is shown in FIG.

[0501] <Memory device configuration example> FIG. 27 is a cross-sectional view of a semiconductor device having a memory device 290. The memory device 290 is a capacitive device in addition to the transistor 200 shown in FIGS. 4A-4D. FIG. 27 corresponds to a cross-sectional view of the transistor 200 in the channel length direction. do.

[0502] In the semiconductor device shown in FIG. 27, the semiconductor device shown in the previous embodiment is The same reference numerals are used for structures having the same functions as those of the structures described above. The materials used to construct the device can be the same as those described in detail in the previous embodiment.

[0503] As shown in FIG. 27, the memory device 290 is sealed with an insulator 283 and an insulator 212. By adopting such a configuration, impurities in the memory device 290 are prevented from being In addition, as shown in the above embodiment, the inclusion of foreign matters (especially hydrogen and water) can be suppressed. An insulator 287 may be provided between the memory device 290 and the insulator 283 .

[0504] The capacitance device 292 is made up of a conductor 242b and an insulator 29 provided on the conductor 242b. 3 and a conductor 294 provided on an insulator 293. That is, the capacitance device 292 is made up of MIM (Metal-Insulator-Metal) capacitors. One of the pair of electrodes of the capacitance device 292, that is, the conductor 242b, is a The source electrode or drain electrode of the transistor can be used as well. In the manufacturing process of the device 292, a part of the manufacturing process of the transistor can be used. Therefore, a semiconductor device with high productivity can be obtained. This makes it possible to reduce the area in which the chairs are arranged.

[0505] For the conductor 294, for example, a material that can be used for the conductor 240 is used. That's good.

[0506] The insulator 293 may be, for example, zirconium oxide, aluminum oxide, or zirconium oxide. For example, a laminated structure with Cr and Cu may be used for the insulator 130. Any suitable material may be used, and the insulating layer may be provided as a laminate or a single layer.

[0507] Also, a wiring layer may be provided on the memory device 290. For example, as shown in FIG. , on the transistor 200 and on the capacitance device 292, an insulator serving as an interlayer film The insulator 283 and the insulator 160 are provided with a transistor 2 00. The conductor 166 is embedded in the plug. , or function as wiring.

[0508] A wiring layer may be provided on the insulator 160 and the conductor 166. For example, as shown in FIG. As shown in FIG. 1, the insulator 162 and the insulator 164 are laminated in this order. A conductor 168 is embedded in the edge 162 and the insulator 164. 168 functions as a plug or wiring.

[0509] It is preferable that the insulator 160 and the insulator 164 have a low dielectric constant. For example, the insulator 160 and the insulator 164 may be used for the insulator 352. Any suitable insulator can be used.

[0510] The insulator 162 has a function of suppressing the permeation of impurities such as hydrogen and oxygen. For example, the insulator 162 may be an insulating material that can be used for the insulator 350. A peripheral body may be used.

[0511] The memory device 290 may be configured to be stacked. 28 shows a cross-sectional view of a memory device having five layers each having a thickness of 290. Device 290 is connected to different memory devices via electrical conductors 240 and electrical conductors 166. 290 and electrically connected.

[0512] As shown in FIG. 28, a plurality of memory devices (memory devices 290_1 to The memory device 290_5 may be enclosed and sealed with the insulator 283 and the insulator 212. By packaging and sealing multiple memory devices, the manufacturing process of the memory device can be simplified. In addition, a part of the structure constituting the transistor 200 and the transistor 20 A part of the structure around the transistor is formed by sputtering. Therefore, the hydrogen concentration in the transistor 200 can be reduced. Even when a different transistor 200 is manufactured, the transistor 2 located below 00 hydrogen concentration can be kept low. In this configuration, multiple memory devices can be packaged together without sealing the memory devices 290 individually. By enclosing and sealing the transistor 200, the hydrogen concentration in the transistor 200 can be reduced.

[0513] The sealing of the multiple memory devices by the insulator 283 and the insulator 212 is This may be performed comprehensively for all memory devices, or may be performed comprehensively for some devices.

[0514] In addition, when the same material is used for the insulator 214 and the insulator 282, Either of the edge members 282 may not be provided. This reduces the number of steps for manufacturing the memory device. It can be reduced.

[0515] As shown in FIG. 28, a plurality of memory devices (memory devices 290_1 to By stacking the memory devices (290_5), the occupied area of ​​the memory device is not increased. In other words, a 3D memory device can be constructed. It is possible.

[0516] In addition, although FIG. 28 illustrates a configuration in which each layer has one memory device, the present invention is not limited to this. As shown in the previous section "Applications of Semiconductor Devices," each layer is made up of multiple memories. The memory devices may be arranged in a channel length direction. They may be arranged in the channel width direction or in a matrix. Also, they may be arranged without any regularity depending on the design.

[0517] <Modifications of memory device> In the following, the configuration of the memory device described above will be explained with reference to Figs. 29A, 29B, and 30. The transistor 200 in this embodiment is different from the semiconductor device shown in Example 1. An example of a semiconductor device having a capacitance device 292 will be described. 9B and the semiconductor device shown in FIG. 30, the semiconductor device shown in the previous embodiment and FIG. The same reference numerals are used to designate structures having the same functions as those constituting the semiconductor device. In the present embodiment, the materials constituting the transistor 200 and the capacitance device 292 are the same as those in the previous embodiment. The materials described in detail in the embodiment and in the previous <Configuration Example of Memory Device> can be used. Cut.

[0518] <<Memory Device Variation 1>> An example of a semiconductor device having a memory device 600 will be described below with reference to FIG. 29A and FIG. The memory device 600 includes a transistor 200a, a transistor The capacitor 200b includes a capacitive device 292a and a capacitive device 292b.

[0519] FIG. 29A is a top view of a semiconductor device having a memory device 600. 29A is a cross-sectional view of the transistor 200 shown in FIG. 29A and 29B are cross-sectional views of the transistor 200b in the channel length direction. In the top view, some elements have been omitted for clarity.

[0520] As shown in FIG. 29B, the memory device 600 is symmetrical about the dashed line A3-A4. The source electrode or drain electrode of the transistor 200a is One of the electrodes and one of the source electrode and drain electrode of the transistor 200b is connected to the conductor 242. Also, the transistor 200a is electrically connected to the plug. a conductor that functions as a plug and is electrically connected to the transistor 200b; The conductor 240c also serves as the conductor. An insulator 241c is provided.

[0521] In this way, two transistors, two capacitance devices, and connections between wiring and plugs are By adopting the above-mentioned configuration, it is possible to provide a semiconductor device that can be miniaturized or highly integrated. Cut.

[0522] The transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device The configuration and effect of each of the vices 292b are shown in FIG. 4A to FIG. 4D and FIG. 7 can be referred to.

[0523] <<Memory Device Modification 2>> FIG. 30 illustrates a memory unit 470 including a transistor layer 4 having a transistor 200T. 13, and four memory device layers 415 (memory device layers 415_1 to 415_2). An example having a silicon layer 415_4 is shown.

[0524] The memory device layers 415_1 to 415_4 each include a plurality of memory The memory device 420 includes, for example, a memory device shown in FIG. 29A and 29B. can be done.

[0525] The memory device 420 is connected to different memory cells via electrical conductors 424 and electrical conductors 166. The device layer 415 includes a memory device 420, and the transistor layer 413 includes Electrically connected to transistor 200T.

[0526] The memory unit 470 includes an insulator 212, an insulator 214, an insulator 282, and an insulator The insulating body 283 is sealed (hereinafter, referred to as a sealing structure for convenience). The insulator 274 is provided between the insulator 274, the insulator 283, and the insulator 212. A conductor 440 is provided on the memory unit 411 and is electrically connected to the element layer 411. An insulator 287 may be provided between 470 and the insulator 283 .

[0527] The insulators 212 and 283 are made of a material that has high blocking properties against hydrogen. In addition, the insulator 214 and the insulator 282 are preferably configured to capture hydrogen or It is preferable that the material has a function of fixing hydrogen.

[0528] For example, the material having high blocking properties against hydrogen is silicon nitride or oxynitride. Silicon oxide and the like can be used. In addition, the above-mentioned hydrogen capturing or hydrogen fixing function can be used. Materials that can be used include aluminum oxide, hafnium oxide, and aluminum and hafnium oxide. Examples include oxides containing hafnium (hafnium aluminate).

[0529] The materials used for the insulators 212, 214, 282, and 283 are The crystal structure of the compound is not particularly limited, but may be either amorphous or crystalline. For example, amorphous oxides have been used as materials that can capture or fix hydrogen. It is preferable to use an aluminum film. Amorphous aluminum oxide is a highly crystalline oxide. It may capture and adhere to a greater amount of hydrogen than aluminum.

[0530] In addition, between the transistor layer 413 and the memory device layer 415_1, or between each memory device Preferably, an insulator 282 and an insulator 214 are also provided between the seat layers 415. In addition, it is preferable that an insulator 296 is provided between the insulator 282 and the insulator 214. The insulator 296 can be made of the same material as the insulator 283. Silicon or silicon oxynitride can be used. Alternatively, a known insulating material can be used. Good too.

[0531] An insulator 280 is provided inside the sealing structure. The insulator 280 is heated. The insulator 280 has a function of releasing oxygen, or has an excess oxygen region.

[0532] Here, the excess oxygen in the insulator 280 is converted to hydrogen in the oxide semiconductor in contact with the insulator 280. The following model for diffusion can be considered:

[0533] Hydrogen present in the oxide semiconductor is absorbed by other The hydrogen diffuses into the structure. The hydrogen forms an OH bond with the excess oxygen in the insulator 280, forming an OH bond. The hydrogen atoms with OH bonds diffuse through the insulator 280 as hydrogen atoms. When the material that has the function of adhering the element (typically, the insulator 282) is reached, the insulator 2 reacts with oxygen atoms bonded to atoms (e.g., metal atoms) in 82, and enters the insulator 282 On the other hand, excess oxygen with OH bonds is captured or fixed. In other words, the excess oxygen in the insulator 280 is diffused into the insulator 280. There is a high probability that Mo will play a bridging role.

[0534] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors. .

[0535] As an example, an insulator 280 having excess oxygen is formed on an oxide semiconductor, and then an insulating After that, a heat treatment is preferably performed. Specifically, in an atmosphere containing oxygen, an atmosphere containing nitrogen, or a mixture of oxygen and nitrogen, The temperature is 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or more. The time is preferably 4 hours or more, and more preferably 8 hours or more.

[0536] By the heat treatment, hydrogen in the oxide semiconductor is converted into the insulator 280 and the insulator 28 2. That is, the oxide semiconductor and the oxide semiconductor The absolute amount of hydrogen present in the vicinity of the body can be reduced.

[0537] After the heat treatment, the insulator 283 is formed. The insulator 283 is a blocking material for hydrogen. Since it is a material with high anti-corrosion properties, hydrogen that has diffused outward or hydrogen that is present outside can be It is possible to suppress the penetration of the oxide semiconductor or the insulator 280 into the interior, specifically, can.

[0538] Regarding the above heat treatment, the following is performed after the insulator 282 is formed: For example, after the formation of the transistor layer 413 or after the memory After the formation of the re-device layer 415_1 to the memory device layer 415_3, the above-mentioned heating In addition, when hydrogen is diffused outward by the above-mentioned heat treatment, Hydrogen is diffused upward or laterally into the transistor layer 413. Similarly, the memory device layer In the case where heat treatment is performed after forming the memory device layers 415_1 to 415_3, water The elements are diffused upwards or laterally.

[0539] By using the above-mentioned manufacturing process, the insulator 212 and the insulator 283 are bonded to each other. In this way, the above-mentioned sealing structure is formed.

[0540] As described above, a highly reliable semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device having favorable electrical characteristics and a manufacturing method thereof can be provided.

[0541] The configuration, structure, method, etc. described in this embodiment may be the same as the configuration, structure, method, etc. described in other embodiments. It can be used in appropriate combination.

[0542] (Embodiment 5) In this embodiment, the present invention will be described with reference to FIGS. 31A, 31B, and 32A to 32H. According to one embodiment of the present invention, a transistor using an oxide as a semiconductor (hereinafter referred to as an OS transistor) ) and a storage device to which a capacitive element is applied (hereinafter referred to as an OS memory device) The OS memory device includes at least a capacitive element and a The memory device has an OS transistor that controls the charging and discharging of the semiconductor. Since the flash current is extremely small, the OS memory device has excellent retention characteristics and is a non-volatile memory. It can be made to function as such.

[0543] <Storage device configuration example> FIG. 31A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 141. 1, and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, It has a column circuit 1430, an output circuit 1440, and a control logic circuit 1460. .

[0544] The column circuits 1430 include, for example, column decoders, precharge circuits, sense amplifiers, write The precharge circuit has a function of precharging the wiring. The amplifier has a function of amplifying the data signal read from the memory cell. The lines are wirings connected to memory cells in the memory cell array 1470. The amplified data signal is output via an output circuit 1440 as a data signal RDA TA to the outside of the memory device 1400. It has a decoder, a word line driver circuit, etc., and can select a row to be accessed.

[0545] The storage device 1400 is supplied with a low power supply voltage (VSS) from the outside as a power supply voltage, and a peripheral circuit 14 The high power supply voltage (VDD) for the 11 and the high power supply voltage (VIL) for the memory cell array 1470 are The storage device 1400 also receives control signals (CE, WE, RE), address signals, and The address signal ADDR and the data signal WDATA are input from the outside. The data signal WDATA is input to the write circuit. do.

[0546] The control logic circuit 1460 receives control signals (CE, WE, R E) to generate control signals for the row decoder and column decoder. The control signal WE is a write enable signal, and the control signal R E is a read enable signal. The signal is not limited to this, and other control signals may be input as necessary.

[0547] The memory cell array 1470 includes a plurality of memory cells MC arranged in a matrix and a plurality of The wiring connecting the memory cell array 1470 and the row circuit 1420 is The number of lines is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is It is determined by the configuration of the recell MC, the number of memory cells MC in one row, etc.

[0548] In FIG. 31A, the peripheral circuit 1411 and the memory cell array 1470 are arranged on the same plane. However, the present embodiment is not limited to this. For example, As shown in FIG. 31B, a memory cell array 1470 is overlapped on a part of the peripheral circuit 1411. For example, the memory cell array 1470 may be provided so as to overlap the memory cell array 1470. A sense amplifier may be provided.

[0549] 32A to 32H show examples of memory cell configurations that can be applied to the above-mentioned memory cell MC. He explains.

[0550] [DOSRAM] 32A to 32C show examples of circuit configurations of memory cells in a DRAM. A DRAM using a one-transistor, one-capacitor type memory cell is called a DOSRAM. (Dynamic Oxide Semiconductor Random Acce. The memory cell 1471 shown in FIG. The transistor M1 has a gate (top It has a gate, sometimes called a push gate, and a back gate.

[0551] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, and the transistor M The second terminal of the transistor M1 is connected to the wiring BIL, and the gate of the transistor M1 is connected to the wiring WOL. The back gate of the transistor M1 is connected to the wiring BGL. The second terminal of A is connected to the wiring CAL.

[0552] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitive element CA. When writing and reading data, a low level potential is applied to the wiring CAL. The wiring BGL is preferably used for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, The threshold voltage of M1 can be increased or decreased.

[0553] Here, the memory cell 1471 shown in FIG. 32A corresponds to the memory device shown in FIG. That is, the transistor M1 corresponds to the transistor 200, and the capacitive element CA corresponds to the capacitive device 29. Corresponds to 2.

[0554] In addition, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration may be changed. For example, the memory cell MC can be a memory cell 1472 shown in FIG. The back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 1473 shown in FIG. As described above, a transistor with a single gate structure, i.e., a transistor without a back gate, The memory cell may be configured with M1.

[0555] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, The transistor 200 is used as M1, and the capacitance element 100 is used as the capacitance element CA. By using an OS transistor as the transistor M1, This makes it possible to make the leakage current of the transistor M1 very small. The transistor M1 allows the data to be retained for a long time, reducing the frequency of refreshing the memory cells. Alternatively, the refresh operation of the memory cells can be eliminated. In addition, since the leakage current is very small, the memory cell 1471 and the memory cell 14 72, the memory cell 1473 can hold multi-value data or analog data. Cut.

[0556] In addition, in the DOSRAM, as described above, By providing a sense amplifier as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0557] [NOSRAM] FIG. 32D to FIG. 32G show a circuit diagram of a gain cell type memory cell having two transistors and one capacitance element. FIG. 32D shows an example of a circuit configuration. The memory cell 1474 shown in FIG. The transistor M2 has a top gate ( In this specification, the term "transistor" refers to a transistor having a gate. A memory device having a gain cell type memory cell using an OS transistor as the transistor M2 , NOSRAM(Nonvolatile Oxide Semiconductor It is sometimes called RAM.

[0558] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, and the transistor M The second terminal of the transistor M2 is connected to the wiring WBL, and the gate of the transistor M3 is connected to the wiring WOL. The back gate of the transistor M2 is connected to the wiring BGL. The second terminal of the transistor M1 is connected to the wiring CAL. The first terminal of the transistor M2 is connected to the wiring R BL, the second terminal of the transistor M3 is connected to the line SL, and the second terminal of the transistor M The gate of 3 is connected to a first terminal of the capacitance element CB.

[0559] The wiring WBL functions as a write bit line, and the wiring RBL functions as a read bit line. The wiring WOL functions as a word line. The wiring CAL is connected to the second It functions as a wiring for applying a specific potential to the terminal. During the data read operation, a low level potential is applied to the wiring CAL. The wiring BGL is a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, The threshold voltage can be increased or decreased.

[0560] Here, the memory cell 1474 shown in FIG. 32D corresponds to the memory device shown in FIG. That is, the transistor M2 is connected to the transistor 200, and the capacitance element CB is connected to the capacitance element 100. , the transistor M3 is connected to the transistor 300, the wiring WBL is connected to the wiring 1003, and the wiring WOL is connected to the wiring 1004, the wiring BGL is connected to the wiring 1006, the wiring CAL is connected to the wiring 1005, and the wiring R The line BL corresponds to the line 1002 , and the line SL corresponds to the line 1001 .

[0561] In addition, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration may be appropriately changed. For example, the memory cell MC can be a memory cell 1475 shown in FIG. In addition, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell 1476 shown in FIG. As shown in the figure, a transistor with a single gate structure, i.e., a transistor without a back gate, For example, the memory cell MC may be configured as shown in FIG. As shown in FIG. 2G, the wiring WBL and the wiring RBL are connected to one wiring BIL. The configuration may be such that the above-mentioned components are combined together.

[0562] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor 200 is used as M2, and the transistor 300 is used as M3. The capacitance element CB can be a capacitance element 100. By using an OS transistor, the leakage current of transistor M2 is made very small. This allows the written data to be stored for a long time by the transistor M2. Since the memory cells can be maintained at a constant level, the frequency of refreshing the memory cells can be reduced. Alternatively, the refresh operation of the memory cell can be eliminated. Because it is so small, the memory cell 1474 can store multi-value data or analog data. The same can be said for memory cells 1475 to 1477.

[0563] The transistor M3 is a transistor having silicon in the channel formation region (hereinafter The conductivity type of the Si transistor may be The Si transistor may be an n-channel type or a p-channel type. In some cases, the field effect mobility is higher than that of the read transistor. A Si transistor may be used as the transistor M3 that functions as the By using a Si transistor for transistor M3, a transistor Since the memory cell can be provided with a transistor M2, the area occupied by the memory cell can be reduced, and the memory device can be made more efficient. Integration can be achieved.

[0564] The transistor M3 may be an OS transistor. When an OS transistor is used for the transistor M3, the memory cell array 1470 is The circuit can be constructed using only transistors.

[0565] FIG. 32H shows an example of a gain cell type memory cell having three transistors and one capacitor. The memory cell 1478 shown in FIG. 32H includes transistors M4 through M6, and The memory cell 1478 includes a wiring and a capacitor CC. The capacitor CC is provided appropriately. Electrically connected to BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL The wiring GNDL is a wiring for applying a low-level potential. , may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

[0566] The transistor M4 is an OS transistor having a back gate. The back gate and gate of the transistor M4 are electrically connected to the wiring BGL. Alternatively, the transistor M4 may have a back gate. It's not necessary.

[0567] The transistors M5 and M6 are n-channel Si transistors. Alternatively, the transistors M4 to M5 may be p-channel Si transistors. In this case, the memory cell array 1470 may be an n-type transistor. The circuit can be constructed using only transistors.

[0568] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor M The transistor M4 is a transistor 200, and the transistors M5 and M6 are transistors The transistor 300 can be used as the capacitance element CC, and the capacitance element 100 can be used as the capacitance element CC. By using an OS transistor as transistor M4, the leakage current of transistor M4 is The flow can be very small.

[0569] The configurations of the peripheral circui...

Claims

[Claim 1] a first step of depositing a first insulator, a second insulator, and a third insulator in that order; a second step of sequentially depositing a fourth insulator, a fifth insulator, a first oxide film, a second oxide film, and a third oxide film; a third step of depositing a conductive film; a fourth step of processing the first oxide film, the second oxide film, the third oxide film, and the conductive film to form an island-shaped first oxide, an island-shaped second oxide, an island-shaped oxide layer, and an island-shaped conductive layer; a fifth step of depositing a sixth insulator and an insulating film in that order; a sixth step of planarizing the insulating film; a seventh step of forming an opening in the insulating film and the sixth insulator to expose the second oxide; an eighth step of forming a seventh insulator and a first conductor; a ninth step of depositing an eighth insulator and a ninth insulator in that order; The first step is carried out using a first multi-chamber apparatus; The second step is carried out using a second multi-chamber apparatus; The fifth step is carried out using a third multi-chamber apparatus; The method for manufacturing a semiconductor device, wherein the ninth step is performed using a fourth multi-chamber apparatus.

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