Wiring board and semiconductor package

Abstract

To provide a method for manufacturing a wiring board that has a wiring part and an insulating material layer with sufficient adhesion and heat resistance, and has sufficient insulation reliability.SOLUTION: A method for manufacturing a wiring board includes steps of: (A) forming a first insulating material layer on a support substrate; (B) forming a first opening in the first insulating material layer; (C) forming a seed layer on the first insulating material layer; (D) providing a resist pattern on a surface of the seed layer; (E) forming a wiring part including a pad and wiring; (F) removing the resist pattern; (G) removing the seed layer; (H) executing first surface treatment on a surface of the pad; (I) forming a second insulating material layer; (J) forming a second opening in the second insulating material layer; (K) executing second surface treatment on the surface of the pad; and (L) heating the second insulating material layer to a temperature equal to or more than the glass-transition temperature of the second insulating material layer.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present disclosure relates to a method for manufacturing a wiring board. [Background technology]

[0002] In order to increase the density and performance of semiconductor packages, mounting forms in which chips with different performance are mixed in a single package have been proposed, and cost-effective high-density interconnect technology between chips is becoming important (see, for example, Patent Document 1).

[0003] Package-on-package, which connects different packages by stacking them on top of one another through flip-chip mounting, is widely used in smartphones and tablet terminals (see, for example, Non-Patent Documents 1 and 2). As forms for mounting at higher density, packaging technology using an organic substrate with high-density wiring (organic interposer), fan-out type packaging technology with through-mold vias (TMV) (FO-WLP), packaging technology using silicon or glass interposers, packaging technology using through-silicon vias (TSV), packaging technology using chips embedded in a substrate for inter-chip transmission, etc. have been proposed. In particular, in the case of organic interposers and FO-WLP, when semiconductor chips are mounted in parallel, a fine wiring layer is required for high-density conduction (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2003-318519 A [Patent Document 2] US Patent Application Publication No. 2001 / 0221071 [Non-patent literature]

[0005] [Non-Patent Document 1] Application of Through Mold Via(TMV) as PoP Base Package, Electronic Components and Technology Conference(ECTC),2008 [Non-Patent Document 2] Advanced Low Profile PoP Solution with Embedded Wafer Level PoP(eWLB-PoP)Technology,ECTC,2012 Summary of the Invention [Problem to be solved by the invention]

[0006] In the technique described in Patent Document 1, after desmearing, wiring is formed through the steps of electroless plating, resist patterning, electrolytic plating, resist stripping, seed etching, and insulating material formation. In order to ensure adhesion between the wiring and the insulating material, it is necessary to make the wiring surface appropriately rough by etching or the like, and to firmly fix the insulating material to the wiring by the anchor effect.

[0007] In recent years, wiring boards are required to have reduced transmission loss in the high frequency band. As described above, roughening the wiring surface increases the transmission loss due to the skin effect. However, in a method for manufacturing a wiring board, if an insulating material layer is formed without a process for roughening the wiring surface, another problem occurs in that the electrical insulation deteriorates due to poor adhesion with the wiring surface. Therefore, the problem is to manufacture a wiring board that exhibits excellent electrical insulation while ensuring adhesion between the wiring and the insulating material.

[0008] Even when the wiring and the insulating material are in close contact immediately after the wiring board is assembled, a thick oxide layer (e.g., a CuO layer) is formed on the wiring surface by long-term heat resistance tests such as a high-temperature storage test, a moisture absorption resistance test, a reflow resistance test, and an accelerated test, which reduces the adhesion between the wiring and the insulating material. As a result, the electrical insulation deteriorates. An example of an accelerated test is the Highly Accelerated Stress Test (HAST).

[0009] The present disclosure has been made in consideration of the above-mentioned problems, and aims to provide a method for manufacturing a wiring board in which a wiring portion and an insulating material layer have sufficient adhesion and heat resistance as well as sufficient insulation reliability. [Means for solving the problem]

[0010] The method for manufacturing a wiring board according to the present disclosure includes the following steps. (A) forming a first insulating material layer on a supporting substrate (B) forming a first opening in the first insulating material layer; (C) forming a seed layer on the surface of the first insulating material layer by electroless plating; (D) A step of providing a resist pattern for forming a wiring portion on the surface of the seed layer (E) A step of forming a wiring portion including a pad and a wiring by electrolytic plating in an area of ​​the surface of the seed layer that is exposed from the resist pattern. (F) Step of removing the resist pattern (G) A step of removing the seed layer exposed by removing the resist pattern. (H) A step of performing a first surface treatment on the surface of the wiring portion (I) forming a second insulating material layer so as to cover the wiring portion; (J) forming a second opening in the second insulating material layer at a position corresponding to the pad; (K) A process of performing a second surface treatment on the surface of the pad (L) heating the second insulating material layer to a temperature equal to or greater than the glass transition temperature of the second insulating material layer.

[0011] In the above step (H), the adhesion between the wiring part and the second insulating material layer can be improved by performing a treatment (first surface treatment) on the surface of the wiring part that improves the adhesion between the wiring part made of a metal material and the second insulating material layer. A specific example of the first surface treatment is a treatment using a surface treatment agent containing an organic component that improves the adhesion between the wiring part made of a metal material and the second insulating material layer. The average roughness Ra of the surface of the wiring part that has been subjected to the first surface treatment is, for example, 40 to 80 nm. By performing the first surface treatment on the surface of the wiring part, the adhesion between the wiring part and the second insulating material layer can be sufficiently increased without excessively roughening the surface of the wiring part. After the step (J), the peel strength of the second insulating material layer against the wiring is, for example, 0.2 to 0.7 kN / m. In addition, since the surface of the wiring part is not excessively rough, the transmission loss can be sufficiently reduced. When a fine wiring pattern is formed on the first insulating layer, a resist pattern having a groove-shaped opening with a line width of, for example, 0.5 to 20 μm may be formed in the above step (D).

[0012] According to the present disclosure, by performing the second surface treatment on the surface of the pad in the above step (K), excellent conductivity of the pad can be obtained. That is, even if a surface treatment layer is formed on the surface of the pad by the first surface treatment in the above step (H), and this layer reduces the conductivity of the pad, for example, by performing a process to remove this layer in the above step (K), the conductivity of the pad can be restored. Furthermore, according to the present disclosure, by performing both the above step (H) and the above step (L), the adhesion between the wiring portion and the second insulating material layer can be further improved, and a wiring board with excellent insulation reliability can be manufactured.

[0013] The above manufacturing method may further include a step of removing residues on the first insulating material layer and / or in the first opening between steps (B) and (C). The process of removing residues is sometimes called a desmear process. At least one of the first insulating material layer and the second insulating material layer may contain a photosensitive resin. When the insulating material layer contains a photosensitive resin, the opening can be formed by, for example, a photolithography process.

[0014] The second opening is preferably formed at a position corresponding to the pad. In this case, the manufacturing method may further include a step of performing a second surface treatment on the surface of the pad in the second opening. When a surface treatment agent containing an organic component as described above is used in the step of performing the first surface treatment, the surface treatment agent can be removed from the surface of the pad by the second surface treatment. The second surface treatment is, for example, at least one selected from the group consisting of an oxygen plasma treatment, an argon plasma treatment, and a desmear treatment. Effect of the Invention

[0015] According to the present disclosure, there is provided a method for manufacturing a wiring board in which a wiring portion and an insulating material layer have sufficient adhesion and heat resistance as well as sufficient insulation reliability. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1(a) is a cross-sectional view showing a schematic state of a first insulating material layer formed on a supporting substrate, FIG. 1(b) is a cross-sectional view showing a schematic state of a first opening provided in the first insulating material layer, FIG. 1(c) is a cross-sectional view showing a schematic state of a desmear treatment performed on the first insulating material layer and the first opening, and FIG. 1(d) is a cross-sectional view showing a schematic state of a seed layer formed on the first insulating material layer. [Diagram 2] Figure 2(a) is a cross-sectional view showing a schematic state in which a resist pattern for forming a wiring portion has been formed on a seed layer, Figure 2(b) is a cross-sectional view showing a schematic state in which a wiring portion has been formed by electrolytic plating, Figure 2(c) is a cross-sectional view showing a schematic state in which the resist pattern has been removed, and Figure 2(d) is a cross-sectional view showing a schematic state in which the seed layer exposed by removing the resist pattern has been removed. [Diagram 3] Figure 3(a) is a cross-sectional view showing a schematic state in which a first surface treatment has been applied to the surface of the wiring portion, Figure 3(b) is a cross-sectional view showing a schematic state in which a second insulating material layer having a second opening has been formed on the first insulating material layer, and Figure 3(c) is a cross-sectional view showing a schematic state in which a second surface treatment has been applied to the surface of the pad. [Figure 4] FIG. 4 is a cross-sectional view that typically shows a state in which a fired layer is formed between the second insulating material layer and the wiring portion by heating the second insulating material layer to a temperature equal to or higher than the glass transition temperature of the second insulating material layer. [Diagram 5] FIG. 5 is a cross-sectional view that illustrates a schematic diagram of an embodiment of a wiring board having multilayered wiring layers. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] Hereinafter, an embodiment of the present disclosure will be described in detail with reference to the drawings. In the following description, the same or equivalent parts are given the same reference numerals, and duplicated descriptions will be omitted. In addition, unless otherwise specified, the positional relationships such as up, down, left, and right are based on the positional relationships shown in the drawings. The dimensional ratios of the drawings are not limited to the illustrated ratios.

[0018] When terms such as "left", "right", "front", "back", "top", "bottom", "upper" and "lower" are used in the description and claims of this specification, they are intended to be explanatory and do not necessarily mean that the relative positions are permanent. Furthermore, the term "layer" includes a structure having a shape formed on the entire surface as well as a structure having a shape formed on a part of the surface when observed in a plan view. "A or B" may include either A or B, or may include both.

[0019] In this specification, the term "process" includes not only an independent process, but also a process that cannot be clearly distinguished from other processes, as long as the intended effect of the process is achieved. In addition, a numerical range indicated using "~" indicates a range that includes the numerical values ​​before and after "~" as the minimum and maximum values, respectively.

[0020] In this specification, the content of each component in the composition means the total amount of the multiple substances present in the composition when the composition contains multiple substances corresponding to each component, unless otherwise specified. In addition, the exemplified materials may be used alone or in combination of two or more types, unless otherwise specified. In addition, in the numerical ranges described in stages in this specification, the upper limit or lower limit of a certain numerical range may be replaced by the upper limit or lower limit of the numerical range of another stage. In addition, in the numerical ranges described in this specification, the upper limit or lower limit of the numerical range may be replaced by the value shown in the examples.

[0021] A method for manufacturing a wiring board according to an embodiment of the present disclosure will be described with reference to the drawings. The method for manufacturing a wiring board according to the embodiment includes at least the following steps. (A) Step of forming a first insulating material layer 1 on a supporting substrate S (B) Step of forming a first opening H1 in the first insulating material layer 1 (C) A step of forming a seed layer T on the surface of the first insulating material layer 1 by electroless plating. (D) A step of providing a resist pattern R for forming a wiring portion on the surface of the seed layer T (E) A step of forming a wiring portion C including a pad C1 and a wiring C2 by electrolytic plating in an area on the surface of the seed layer T that is exposed from the resist pattern R. (F) Step of removing the resist pattern R (G) A step of removing the seed layer T exposed by removing the resist pattern R. (H) A step of performing a first surface treatment on the surfaces of the pads C1 and the wiring C2 (I) A step of forming a second insulating material layer 2 so as to cover the pads C1 and the wiring C2. (J) Step of forming a second opening H2 in the second insulating material layer 2 (K) A step of performing a second surface treatment on the surface of the pad C1 in the second opening H2 (L) a step of heating the second insulating material layer 2 to a temperature equal to or higher than the glass transition temperature of the second insulating material layer 2.

[0022] The wiring board according to this embodiment is suitable for a form requiring miniaturization and a large number of pins, and is particularly suitable for a package form requiring an interposer for mounting different types of chips together. More specifically, the manufacturing method according to this embodiment is suitable for a package form in which the pin interval is 200 μm or less (for example, 30 to 100 μm in the case of finer) and the number of pins is 500 or more (for example, 1000 to 10000 in the case of finer). Each process will be described below.

[0023] <Step of forming a first insulating material layer on a supporting substrate> A first insulating material layer 1 is formed on a support substrate S (FIG. 1(a)). The support substrate S is not particularly limited, but may be a silicon plate, a glass plate, a SUS plate, a substrate containing glass cloth, a sealing resin containing a semiconductor element, or the like, and a substrate having high rigidity is preferable. As shown in FIG. 1(a), the support substrate S may have a conductive layer Sa formed on the surface on the side on which the insulating material layer is to be formed. The support substrate S may have wiring and / or pads on its surface instead of the conductive layer Sa.

[0024] The thickness of the support substrate S is preferably in the range of 0.2 mm to 2.0 mm. If it is thinner than 0.2 mm, handling becomes difficult, while if it is thicker than 2.0 mm, the material cost tends to be high. The support substrate S may be in the form of a wafer or a panel. The size is not particularly limited, but a wafer with a diameter of 200 mm, 300 mm, or 450 mm, or a rectangular panel with one side of 300 to 700 mm is preferably used.

[0025] It is preferable to adopt a photosensitive resin material as a material constituting the first insulating material layer 1. The photosensitive insulating material may be in the form of a liquid or film, and a film-like photosensitive insulating material is preferable from the viewpoint of film thickness flatness and cost. In addition, in order to form fine wiring, it is preferable that the photosensitive insulating material contains a filler (filling material) having an average particle size of 500 nm or less (more preferably 50 to 200 nm). The filler content of the photosensitive insulating material is preferably 0 to 70 parts by mass, more preferably 10 to 50 parts by mass, per 100 parts by mass of the photosensitive insulating material excluding the filler.

[0026] When using a film-type photosensitive insulating material, it is preferable to carry out the lamination process at as low a temperature as possible, and it is preferable to employ a photosensitive insulating film that can be laminated at 40° C. to 120° C. Photosensitive insulating films that can be laminated at temperatures below 40° C. tend to have strong tack at room temperature (about 25° C.) and are difficult to handle, while photosensitive insulating films that can be laminated at temperatures above 120° C. tend to warp significantly after lamination.

[0027] The thermal expansion coefficient of the first insulating material layer 1 after curing is set to 80×10 -6 / K or less is preferable, and 70×10 -6 / K or less. In addition, in terms of the stress relaxation of the insulating material and the ability to obtain a highly precise pattern, -6 It is preferable that the ratio is 1 / K or more.

[0028] The thickness of the first insulating material layer 1 is preferably 10 μm or less, more preferably 5 μm or less, and even more preferably 3 μm or less. From the viewpoint of insulation reliability, the thickness of the first insulating material layer 1 is preferably within the above range.

[0029] <Step of forming a first opening in the surface of the first insulating material layer> A first opening H1 is formed in the surface of the first insulating material layer 1, reaching the support substrate S or the conductive layer Sa (FIG. 1(b)). In this embodiment, the first opening H1 is formed so as to penetrate the first insulating material layer 1 in its thickness direction, and is composed of a bottom surface (the surface of the conductive layer Sa) and a side surface (the insulating material layer 1). When the first insulating material layer 1 is made of a photosensitive resin material, the first opening H1 can be formed by a photolithography process (exposure and development).

[0030] The exposure method for the photosensitive resin material can be a normal projection exposure method, contact exposure method, direct drawing exposure method, etc. The development method is preferably an alkaline aqueous solution of sodium carbonate or TMAH (tetramethylammonium hydroxide). After the first opening H1 is formed, the first insulating material layer 1 may be further heated and cured. For example, the heating temperature is 100°C to 200°C, and the heating time is between 30 minutes and 3 hours.

[0031] The first opening H1 may be formed in the first insulating material layer 1 by a method other than the photolithography process (for example, laser ablation, sandblasting, water blasting, imprinting). For example, when the first insulating material layer 1 is formed of a thermosetting resin material, laser ablation is preferred because it is possible to form the first opening H1. The opening method by laser ablation can be formed by a CO2 laser, a UV-YAG laser, or the like, but from the viewpoint of cost, an opening method using a CO2 laser is preferred. Resin residue on the surface of the conductive layer Sa exposed from the first opening H1 may be removed by a desmear process. The surface of the first insulating material layer 1 may be roughened by this desmear process. Surface F shown in FIG. 1(c) shows the surface that has been subjected to the desmear process.

[0032] <Step of forming a seed layer on the surface of the first insulating material layer> A seed layer T is formed on the surface of the first insulating material layer 1 by electroless plating (FIG. 1(d)). In this embodiment, first, in order to adsorb palladium, which is a catalyst for electroless copper plating, on the surface of the first insulating material layer 1, the surface of the first insulating material layer 1 is washed with a pretreatment liquid. The pretreatment liquid may be a commercially available alkaline pretreatment liquid containing sodium hydroxide or potassium hydroxide. The concentration of sodium hydroxide or potassium hydroxide is between 1% and 30%. The immersion time in the pretreatment liquid is between 1 minute and 60 minutes. The immersion temperature in the pretreatment liquid is between 25° C. and 80° C. After the pretreatment, in order to remove excess pretreatment liquid, washing with city water, pure water, ultrapure water, or an organic solvent may be performed. Note that, before forming the seed layer T on the surface of the first insulating material layer 1, the surface of the first insulating material layer 1 may be modified by a method such as ultraviolet irradiation, electron beam irradiation, ozone water treatment, corona discharge treatment, plasma treatment, or the like.

[0033] After removing the pretreatment solution, the surface of the first insulating material layer 1 is immersed and washed in an acidic aqueous solution to remove alkaline ions from the surface. The acidic aqueous solution may be a sulfuric acid aqueous solution with a concentration of 1% to 20%, and the immersion time is between 1 minute and 60 minutes. To remove the acidic aqueous solution, washing with city water, pure water, ultrapure water, or an organic solvent may be used.

[0034] Subsequently, palladium is attached to the surface of the first insulating material layer 1 after immersion cleaning in an acidic aqueous solution. The palladium may be a commercially available palladium-tin colloidal solution, an aqueous solution containing palladium ions, a palladium ion suspension, or the like, but an aqueous solution containing palladium ions that are effectively adsorbed to the modified layer is preferred.

[0035] When immersing in the aqueous solution containing palladium ions, the temperature of the aqueous solution containing palladium ions is 25° C. to 80° C., and the immersion time for adsorption is between 1 minute and 60 minutes. After the palladium ions are adsorbed, the substrate may be washed with city water, pure water, ultrapure water, or an organic solvent to remove excess palladium ions.

[0036] After the palladium ions are adsorbed, activation is performed to allow the palladium ions to act as a catalyst. The reagent for activating the palladium ions may be a commercially available activator (activation treatment solution). The temperature of the activator in which the palladium ions are immersed to activate them is 25°C to 80°C, and the immersion time for activation is between 1 minute and 60 minutes. After the activation of the palladium ions, the palladium ions may be washed with city water, pure water, ultrapure water, or an organic solvent to remove excess activator.

[0037] Subsequently, the surface of the first insulating material layer 1 is electrolessly plated with copper to form a seed layer T. This seed layer T serves as a power supply layer for electrolytic plating. Examples of electroless copper plating include electroless pure copper plating (purity of 99% by mass or more), electroless copper nickel phosphorus plating (nickel content: 1% by mass to 10% by mass, phosphorus content: 1% by mass to 13% by mass), and the like. From the viewpoint of adhesion, however, electroless copper nickel phosphorus plating is preferred. The electroless copper nickel phosphorus plating solution may be a commercially available plating solution, and for example, an electroless copper nickel phosphorus plating solution (manufactured by JCU Corporation, product name "AISL-570") can be used. The electroless copper nickel phosphorus plating is carried out in an electroless copper nickel phosphorus plating solution at 60°C to 90°C. The thickness of the seed layer T is preferably 20nm to 200nm, more preferably 40nm to 200nm, and even more preferably 60nm to 200nm.

[0038] After electroless copper plating, excess plating solution may be removed by washing with tap water, pure water, ultrapure water, or an organic solvent. After electroless copper plating, heat curing (annealing: age hardening treatment by heating) may be performed to increase the adhesion between the seed layer T and the first insulating material layer 1. The heat curing temperature is preferably 80°C to 200°C. To accelerate the reactivity, heating at 120°C to 200°C is more preferable, and heating at 120°C to 180°C is even more preferable. The heat curing time is preferably 5 minutes to 60 minutes, more preferably 10 minutes to 60 minutes, and even more preferably 20 minutes to 60 minutes.

[0039] <Process of forming resist pattern for forming wiring portion> A resist pattern R for forming a wiring portion is formed on the seed layer T (FIG. 2(a)). The resist pattern R may be a commercially available resist, for example, a negative film-like photosensitive resist (Photec RY-5107UT, manufactured by Hitachi Chemical Co., Ltd.). The resist pattern R has openings R1 and R2 as shown in FIG. 2(a). The opening R1 is provided at a position corresponding to the opening H1 of the first insulating material layer 1, and is for forming the pad C1. The first opening H1 and the opening R1 form an opening H. The opening R2 is, for example, a groove-shaped opening with a line width of 0.5 to 20 μm, and is for forming the wiring C2.

[0040] The resist pattern R can be formed through the following steps. First, a resist is formed using a roll laminator, then a phototool with a pattern is attached to the resist, exposure is performed using an exposure machine, and then spray development is performed using an aqueous sodium carbonate solution. Note that a positive photosensitive resist may be used instead of a negative one.

[0041] <Process for forming wiring part> Using the seed layer T as a power supply layer, for example, electrolytic copper plating is performed to form a wiring portion C including a pad C1 and a wiring C2 (FIG. 2(b)). The thickness of the wiring portion C is preferably 1 to 10 μm, more preferably 3 to 10 μm, and further preferably 5 to 10 μm. The wiring portion C may be formed by electrolytic plating other than electrolytic copper plating.

[0042] <Step of removing the resist pattern> After the electrolytic copper plating, the resist pattern R is removed (Figure 2(c)). The resist pattern R can be peeled off using a commercially available peeling solution.

[0043] <Seed layer removal process> After removing the resist pattern R, the seed layer T is removed (FIG. 2(d)). Along with removing the seed layer T, the palladium remaining under the seed layer T may be removed. This removal may be performed using a commercially available removal solution (etching solution), and specific examples include acidic etching solutions (manufactured by JCU Corporation, BB-20, PJ-10, SAC-700W3C).

[0044] <Step of performing first surface treatment on surfaces of pads C1 and wiring C2> A first surface treatment is performed on the surfaces of the pad C1 and the wiring C2 to form a surface treatment layer 5 on these surfaces (FIG. 3(a)). The first surface treatment can be performed using a commercially available surface treatment liquid. As the surface treatment liquid, for example, a liquid containing an organic component that improves the adhesion between the wiring portion C and the second insulating material layer 2 formed in a later process (for example, Shikoku Chemical Industry Co., Ltd., product name "GliCAP"), or a liquid that finely etches the surface of the wiring portion C and contains an organic component that improves the adhesion between the wiring portion C and the second insulating material layer 2 (for example, Atotech Japan KK, product name "Novabond" and MEC Co., Ltd., product names "CZ8401" and "CZ-8402") can be used.

[0045] The average roughness Ra of the surface of the wiring portion C (pads C1 and wiring C2) after the first surface treatment is, for example, 40 to 80 nm, and may be 50 to 80 nm or 60 to 80 nm. When the average roughness Ra of the surface of the wiring portion C is 40 nm or more, the adhesion between the wiring portion C and the second insulating material layer 2 can be sufficiently ensured, while when it is 80 nm or less, the transmission loss of the wiring board can be sufficiently reduced.

[0046] <Step of forming second insulating material layer> The second insulating material layer 2 is formed so as to cover the wiring portion C. The material constituting the second insulating material layer 2 may be the same as that of the first insulating material layer 1, or may be different.

[0047] <Step of forming second opening in second insulating material layer> A second opening H2 is formed in the second insulating material layer 2 (FIG. 3(b)). The second opening H2 is provided at a position corresponding to the pad C1. The method for forming the second opening H2 may be the same as or different from the method for forming the first opening H1. After this process, the peel strength of the second insulating material layer 2 with respect to the wiring C2 is, for example, 0.2 to 0.7 kN / m, and may be 0.4 to 0.65 kN / m or 0.5 to 0.6 kN / m. The peel strength here means a value measured under the conditions of a peel angle of 90° and a peel speed of 10 mm / min. Through these steps, the wiring board 10 shown in FIG. 3(b) is obtained. The wiring board 10 includes a support substrate S, a pad C1 provided so as to penetrate the first insulating material layer 1 and the second insulating material layer 2, and a wiring layer 8A having a wiring C2 embedded in the second insulating material layer 2.

[0048] <Process of performing second surface treatment on the surface of the pad> The surface of the pad C1 in the second opening H2 is subjected to a second surface treatment to remove the surface treatment layer 5 (FIG. 3(c)). As described above, the surface treatment layer 5 contains, for example, an organic component, and may impair the conductivity of the pad C1. By removing at least a part of the surface treatment layer 5, that is, by providing a surface treatment agent removal section 6 on the surface of the pad C1 as shown in FIG. 3(c), the decrease in the conductivity of the pad C1 due to the surface treatment layer 5 can be improved. Examples of the treatment for removing the surface treatment layer 5 include plasma treatment and desmear treatment (treatment using an alkaline solution). The types of gas used in the plasma treatment are, for example, oxygen, argon, nitrogen, and a mixed gas of these. Through this process, a wiring board 20 having a configuration shown in FIG. 3(c) is obtained. The wiring board 20 differs from the wiring board 10 shown in FIG. 3(b) in that the surface treatment agent removal section 6 is provided on the surface of the pad C1.

[0049] <Step of Heating the Second Insulating Material Layer> By heating the second insulating material layer 2 to a temperature equal to or higher than the glass transition temperature (Tg) of the second insulating material layer 2, a fired layer 7 is formed at the interface between the wiring portion C and the second insulating material layer 2 (FIG. 4). This further improves the adhesion between the wiring portion C and the second insulating material layer 2. The fired layer 7 is a layer formed, for example, by the surface treatment agent contained in the surface treatment layer 5 being altered by reaction with the second insulating material layer 2. The heating temperature is equal to or higher than the glass transition temperature (Tg) of the second insulating material layer 2, and is, for example, equal to or lower than 250° C. The heating time is preferably 30 minutes to 3 hours. By setting the heating temperature to equal to or higher than Tg and the heating time to equal to or higher than 30 minutes, the effect of improving the adhesion between the wiring portion C and the second insulating material layer 2 is sufficiently exhibited. On the other hand, by setting the heating temperature to equal to or lower than 250° C. and equal to or lower than 3 hours, the surface treatment agent remaining between the wiring portion C and the second insulating material layer 2 is suppressed from being decomposed, and excellent adhesion between the wiring portion C and the second insulating material layer 2 can be maintained. Furthermore, by keeping the heating temperature at 250° C. or less, warping of the wiring board can be suppressed. Through this process, a wiring board 30 having the configuration shown in Fig. 4 is obtained. The wiring board 30 differs from the wiring board 20 shown in Fig. 3(c) in that a fired layer 7 is formed at the interface between the wiring portion C and the second insulating material layer 2.

[0050] The glass transition temperature of the second insulating material layer referred to here is the midpoint glass transition temperature value when the second insulating material layer after curing is measured using a differential scanning calorimetry (DSC, for example, "Thermo Plus 2" manufactured by Rigaku Corporation). Specifically, the glass transition temperature is the midpoint glass transition temperature calculated by measuring the change in heat quantity under conditions of a temperature rise rate of 10°C / min and a measurement temperature of 30 to 250°C according to a method in accordance with JIS K 7121:1987.

[0051] Although one embodiment of the method for manufacturing a wiring board has been described above, the present invention is not necessarily limited to the above embodiment, and appropriate modifications may be made within the scope of the present invention. For example, in the above embodiment, a method for manufacturing a wiring board having a single wiring layer 8A has been illustrated, but a wiring board having a multi-layered wiring layer may be manufactured. The multilayer wiring board 40 shown in FIG. 5 includes a wiring layer 8B including a third insulating material layer 3 and a wiring C2 embedded in the third insulating material layer 3 in addition to the configuration of the wiring board 30. The pad C1 of the multilayer wiring board 40 is provided so as to penetrate the first insulating material layer 1, the second insulating material layer 2, and the third insulating material layer 3. EXAMPLES

[0052] The present disclosure will be described in more detail with reference to the following examples, but the present invention is not limited to these examples.

[0053] [Example 1] <Preparation of photosensitive resin film> A photosensitive resin composition used to form the insulating material layer was prepared using the following components. Photoreactive resin containing a carboxyl group and an ethylenically unsaturated group: 50 parts by mass of acid-modified cresol novolac epoxy acrylate (CCR-1219H, product name, manufactured by Nippon Kayaku Co., Ltd.) Photopolymerization initiator component: 2,4,6-trimethylbenzoyl-diphenyl-phosphine oxide (Darocur TPO, product name, manufactured by BASF Japan Ltd.) and ethanone, 1-[9-ethyl-6-(2-methylbenzoyl)-9H-carbazol-3-yl]-, 1-(o-acetyloxime) (Irgacure OXE-02, product name, manufactured by BASF Japan Ltd.) 5 parts by mass Heat curing agent component: 10 parts by weight of biphenol-type epoxy resin (YX-4000, product name, manufactured by Mitsubishi Chemical Corporation) Inorganic filler component: (average particle size: 50 nm, silane coupling treatment with vinyl silane)

[0054] The inorganic filler component was mixed at 10 parts by volume per 100 parts by volume of the resin. The particle size distribution was measured using a dynamic light scattering nanotrack particle size distribution meter "UPA-EX150" (manufactured by Nikkiso Co., Ltd.) and a laser diffraction scattering microtrack particle size distribution meter "MT-3100" (manufactured by Nikkiso Co., Ltd.), and it was confirmed that the maximum particle size was 1 μm or less.

[0055] The solution of the photosensitive resin composition having the above composition was applied onto the surface of a polyethylene terephthalate film (G2-16, Teijin Limited, product name, thickness: 16 μm). It was dried at 100° C. for about 10 minutes using a hot air convection dryer. The thickness of the photosensitive resin film formed in this way was 10 μm.

[0056] <Formation of wiring layer having fine wiring> A glass cloth-containing wiring board (size: 200 mm square, thickness: 1.5 mm) was prepared as a support board. A copper layer was formed on the surface of this wiring board, and its thickness was 20 μm.

[0057] ·Process (A) The photosensitive resin film (first insulating material layer) was laminated on the surface of the copper layer of the wiring board. In detail, the photosensitive resin film was first placed on the surface of the copper layer of the wiring board. Then, pressing was performed using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho Co., Ltd.). The pressing conditions were: press hot plate temperature 80°C, vacuuming time 20 seconds, lamination pressing time 60 seconds, atmospheric pressure 4 kPa or less, and pressure bonding pressure 0.4 MPa.

[0058] ·Process (B) The insulating material layer after pressing was subjected to exposure and development processes to provide an opening (first opening) in the first insulating material layer that reached the copper layer of the wiring board. Exposure was performed by closely contacting a phototool with a pattern formed on the insulating material layer and using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Therma Precision Co., Ltd.) at 30 mJ / cm. 2The insulating material layer was exposed to light with an energy amount of 2000 mJ / cm using a mask exposure machine (EXM-1201 exposure machine, manufactured by Oak Manufacturing Co., Ltd.) after development. 2 The post-UV exposure was performed with an energy amount of 10 ...

[0059] ·Process (C) A seed layer was formed on the surface of the insulating material layer by electroless copper plating. That is, first, as an alkaline cleaning, the substrate was immersed in a 110 mL / L aqueous solution of an alkaline cleaner (manufactured by JCU Corporation, product name: EC-B) at 50°C for 5 minutes, and then immersed in pure water for 1 minute. Next, as a conditioner, the substrate was immersed in a mixed solution of a conditioning solution (manufactured by JCU Corporation, product name: PB-200) and EC-B (PB-200 concentration: 70 mL / L, EC-B concentration: 2 mL / L) at 50°C for 5 minutes, and then immersed in pure water for 1 minute. Next, as a soft etching, the substrate was immersed in a mixed solution of a soft etching solution (manufactured by JCU Corporation, product name: PB-228) and 98% sulfuric acid (PB-228 concentration: 100 g / L, sulfuric acid concentration: 50 mL / L) at 30°C for 2 minutes, and then immersed in pure water for 1 minute. Next, as a desmutting, the substrate was immersed in 10% sulfuric acid at room temperature for 1 minute. Next, as a catalyzer, the catalyst was immersed in a mixture of a catalyzer reagent 1 (manufactured by JCU Corporation, product name: PC-BA), a catalyzer reagent 2 (manufactured by JCU Corporation, product name: PB-333), and EC-B (PC-BA concentration: 5 g / L, PB-333 concentration: 40 mL / L, EC-B concentration: 9 mL / L) at 60 ° C for 5 minutes, and then immersed in pure water for 1 minute. Next, as an accelerator, the catalyst was immersed in a mixture of an accelerator reagent (manufactured by JCU Corporation, product name: PC-66H) and PC-BA (PC-66H concentration: 10 mL / L, PC-BA concentration: 5 g / L) at 30 ° C for 5 minutes, and then immersed in pure water for 1 minute. Next, the substrate was immersed in a mixture of electroless copper plating solution (manufactured by JCU Corporation, product names: AISL-570B, AISL-570C, AISL-570MU) and PC-BA (AISL-570B concentration: 70mL / L, AISL-570C concentration: 24mL / L, AISL-570MU concentration: 50mL / L, PC-BA concentration: 13g / L) at 60°C for 7 minutes, and then immersed in pure water for 1 minute. The substrate was then dried on a hot plate at 85°C for 5 minutes. The substrate was then thermally annealed in an oven at 180°C for 1 hour.

[0060] ·Process (D) Using a vacuum laminator (V-160, manufactured by Nichigo-Morton Co., Ltd.), a resist for wiring formation (RY-5107UT, manufactured by Hitachi Chemical Co., Ltd.) was vacuum laminated onto a 200 mm square substrate on which electroless copper had been formed. The lamination temperature was 110°C, the lamination time was 60 seconds, and the lamination pressure was 0.5 MPa.

[0061] After vacuum lamination, the substrate was left for one day, and then the resist for forming wiring was exposed using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Therma Precision Co., Ltd.). The exposure dose was 140 mJ / cm 2 The exposure time was 100 s, and the focus was -15 μm. After exposure, the resist was left for one day, the protective film for the wiring formation resist was peeled off, and the resist was developed using a spray developer (Mikasa Co., Ltd., AD-3000). The developer was a 1.0% aqueous sodium carbonate solution, the development temperature was 30°C, and the spray pressure was 0.14 MPa. As a result, a resist pattern for forming the following L / S (line / space) wiring was formed on the seed layer. ·L / S=20μm / 20μm (number of wires: 10) ·L / S=15μm / 15μm (number of wires: 10) ·L / S=10μm / 10μm (number of wires: 10) ·L / S=7μm / 7μm (number of wires: 10) ·L / S=5μm / 5μm (number of wires: 10) ·L / S=3μm / 3μm (number of wires: 10) ·L / S=2μm / 2μm (number of wires: 10)

[0062] ·Process (E) The sample was immersed in a 100 mL / L aqueous solution of a cleaner (manufactured by Okuno Chemical Industries Co., Ltd., product name: ICP Clean S-135) at 50° C. for 1 minute, in pure water at 50° C. for 1 minute, in pure water at 25° C. for 1 minute, and in a 10% aqueous sulfuric acid solution at 25° C. for 1 minute. Next, the sample was immersed in an aqueous solution of 7.3 L of 120 g / L copper sulfate pentahydrate and 220 g / L 96% sulfuric acid, to which 0.25 mL of hydrochloric acid, 10 mL of Top Lucina GT-3 (manufactured by Okuno Chemical Industries Co., Ltd., product name: Top Lucina GT-2) were added, and the current density was set at 1.5 A / dm 2 After that, the plate was immersed in pure water at 25°C for 5 minutes and dried on a hot plate at 80°C for 5 minutes.

[0063] ·Process (F) The resist for forming wiring was stripped using a spray developer (Mikasa AD-3000). The stripping solution was a 2.38% TMAH aqueous solution, the stripping temperature was 40°C, and the spray pressure was 0.2 MPa.

[0064] ·Process (G) The electroless copper seed layer and palladium catalyst were removed. For electroless Cu etching, the specimen was immersed in an etching solution (JCU Corporation, SAC-700W3C) and an aqueous solution of 98% sulfuric acid, 35% hydrogen peroxide, and copper sulfate pentahydrate (SAC-700W3C concentration: 5% by volume, sulfuric acid concentration: 4% by volume, hydrogen peroxide concentration: 5% by volume, copper sulfate pentahydrate concentration: 30 g / L) at 35°C for 1 minute. Next, to remove the palladium catalyst, the specimen was immersed in an FL aqueous solution (JCU Corporation, FL-A 500 mL / L, FL-B 40 mL / L) at 50°C for 1 minute. After that, the specimen was immersed in pure water at 25°C for 5 minutes and dried on a hot plate at 80°C for 5 minutes.

[0065] ·Process (H) The surfaces of the pads and wiring were subjected to a surface treatment (first surface treatment) using GliCAP (manufactured by Shikoku Chemical Industry Co., Ltd.). For acid cleaning, the substrate was immersed in a 3.5% hydrochloric acid aqueous solution at 25°C for 1 minute. Then, the substrate was washed with running pure water at 25°C for 1 minute. Then, the substrate was immersed in a soft etching solution (GB-1000, manufactured by Shikoku Chemical Industry Co., Ltd.) at 30°C for 1 minute. Then, the substrate was washed with running pure water at 25°C for 1 minute. Then, the substrate was immersed in a surface treatment agent (GliCAP, manufactured by Shikoku Chemical Industry Co., Ltd.) at 30°C for 15 minutes. Then, the substrate was washed with running pure water at 25°C for 1 minute. Then, the substrate was dried on a hot plate at 100°C for 5 minutes.

[0066] ·Process (I) A photosensitive resin film (second insulating material layer) was laminated so as to cover the pads and wiring that had been surface-treated through step (H). In detail, a photosensitive resin film was first placed on the first insulating material layer so as to cover the pads and wiring. Then, pressing was performed using a press-type vacuum laminator (MVLP-500, manufactured by Meiki Seisakusho Co., Ltd.). The pressing conditions were a press hot plate temperature of 80°C, a vacuuming time of 20 seconds, a lamination pressing time of 60 seconds, an atmospheric pressure of 4 kPa or less, and a pressure bonding pressure of 0.4 MPa.

[0067] ·Process (J) The insulating material layer after pressing was subjected to exposure and development processes to provide an opening (second opening) that reached the pad in the second insulating material layer. Exposure was performed by placing a phototool with a pattern formed on the insulating material layer in close contact with the surface, and using an i-line stepper exposure machine (product name: S6CK type exposure machine, lens: ASC3(Ck), manufactured by Therma Precision Co., Ltd.) at 30 mJ / cm. 2 The insulating material layer was exposed to light with an energy amount of 2000 mJ / cm using a mask exposure machine (EXM-1201 exposure machine, manufactured by Oak Manufacturing Co., Ltd.) after development. 2 The post-UV exposure was performed with an energy amount of 1.0 μm. Then, heat curing was performed in a clean oven at 170°C for 1 hour. The glass transition temperature (Tg) of the cured second insulating material layer was 160°C.

[0068] [Example 2] A wiring board was obtained in the same manner as in Example 1, except that in step (H), the surface was treated with Novabond (manufactured by Atotech Japan Co., Ltd.) instead of GliCAP. That is, first, it was immersed in a 15 mL / L aqueous solution of Novabond IT Stabilizer (manufactured by Atotech Japan Co., Ltd.) at 50° C. for 1 minute. Then, it was washed with running pure water at 25° C. for 1 minute. Then, it was immersed in a 30 mL / L aqueous solution of Novabond IT (manufactured by Atotech Japan Co., Ltd.) at 50° C. for 1 minute. Then, it was washed with running pure water at 25° C. for 1 minute. Then, it was immersed in a 20 mL / L aqueous solution of Novabond IT Reducer (manufactured by Atotech Japan Co., Ltd.) at 30° C. for 5 minutes. Then, it was washed with running pure water at 25° C. for 1 minute. Then, it was immersed in a 10 mL / L aqueous solution of Novabond IT Protector MK (manufactured by Atotech Japan Co., Ltd.) at 35° C. for 1 minute. Then, it was washed with running pure water at 25° C. for 1 minute. Then, it was dried on a hot plate at 100°C for 5 minutes.

[0069] [Example 3] A wiring board was obtained in the same manner as in Example 1, except that in step (H), the surface was treated with CZ8401 (manufactured by MEC Co., Ltd.) instead of GliCAP. That is, first, as an acid cleaning, spray cleaning was performed with a 5% hydrochloric acid aqueous solution at 25°C for 30 seconds at a water pressure of 0.2 MPa. Next, it was washed with running pure water at 25°C for 1 minute. Next, it was spray treated with a CZ8401 treatment solution at 25°C for 1 minute at a water pressure of 0.2 MPa. Next, it was washed with running pure water at 25°C for 1 minute. Next, it was spray treated with a 10% sulfuric acid aqueous solution at 25°C for 20 seconds at a water pressure of 0.1 MPa. Next, it was washed with running pure water at 25°C for 1 minute. Then, it was dried on a hot plate at 100°C for 5 minutes.

[0070] [Example 4] A wiring board was obtained in the same manner as in Example 1, except that in step (H), the surface was treated with CZ8402 (manufactured by MEC Co., Ltd.) instead of GliCAP. That is, first, as an acid cleaning, spray cleaning was performed with a 5% hydrochloric acid aqueous solution at 25°C for 30 seconds at a water pressure of 0.2 MPa. Next, it was washed with running pure water at 25°C for 1 minute. Next, it was spray treated with a CZ8402 treatment solution at 25°C for 1 minute at a water pressure of 0.2 MPa. Next, it was washed with running pure water at 25°C for 1 minute. Next, it was spray treated with a 10% sulfuric acid aqueous solution at 25°C for 20 seconds at a water pressure of 0.1 MPa. Next, it was washed with running pure water at 25°C for 1 minute. Then, it was dried on a hot plate at 100°C for 5 minutes.

[0071] [Comparative Example 1] A wiring board was obtained in the same manner as in Example 1, except that no surface treatment agent was used in step (H). That is, first, as an acid cleaning, the board was spray-cleaned with a 5% hydrochloric acid aqueous solution at 25°C for 30 seconds at a water pressure of 0.2 MPa. Next, the board was washed with running pure water at 25°C for 1 minute. Then, the board was dried on a hot plate at 100°C for 5 minutes.

[0072] [Comparative Example 2] A wiring board was obtained in the same manner as in Example 1, except that in step (H), the surface was treated with CZ8101 (manufactured by MEC Co., Ltd.) instead of GliCAP. That is, first, as an acid cleaning, spray cleaning was performed with a 5% hydrochloric acid aqueous solution at 25°C for 30 seconds at a water pressure of 0.2 MPa. Next, it was washed with running pure water at 25°C for 1 minute. Next, it was sprayed with a CZ8101 treatment solution at 25°C for 1 minute at a water pressure of 0.2 MPa. Next, it was washed with running pure water at 25°C for 1 minute. Next, it was sprayed with a 10% sulfuric acid aqueous solution at 25°C for 20 seconds at a water pressure of 0.1 MPa. Next, it was washed with running pure water at 25°C for 1 minute. Next, it was immersed in a CL-8300 (manufactured by MEC Co., Ltd.) treatment solution at 25°C for 30 seconds as a rust prevention treatment. Next, it was washed with running pure water at 25°C for 1 minute. Then, it was dried on a hot plate at 100°C for 5 minutes.

[0073] <Measurement of average roughness Ra of copper layer surface> The average roughness Ra of the copper layer surface in Example 1 (surface treatment with Glicap), Example 2 (surface treatment with Novabond), Example 3 (surface treatment with CZ-8401), Example 4 (surface treatment with CZ-8402), Comparative Example 1 (no surface treatment agent), and Comparative Example 2 (CZ-8101) was measured using a surface roughness meter (OLS-4000, manufactured by Olympus Corporation). The results are shown in Table 1.

[0074] <Peel strength measurement of the interface between copper layer and insulating material layer> The peel strength of the interface between the copper layer and the insulating material layer in Example 1 (surface treatment with Glicap), Example 2 (surface treatment with Novabond), Example 3 (surface treatment with CZ-8401), Example 4 (surface treatment with CZ-8402), Comparative Example 1 (no surface treatment agent), and Comparative Example 2 (CZ-8101) was measured using a peel strength measuring device (ES-Z, manufactured by Shimadzu Corporation). The measurement conditions were a peel angle of 90° and a peel speed of 10 mm / min. The results are shown in Table 1.

[0075] <Evaluation of wiring formability> Regarding the wiring formability with L / S of 20μm / 20μm, 15μm / 15μm, 10μm / 10μm, 7μm / 7μm, 5μm / 5μm, 3μm / 3μm and 2μm / 2μm, the cases where 0 out of 10 wirings had collapsed, peeled or broken wires were rated as "A", 1-2 cases were rated as "B", and 3 or more cases were rated as "C". The results are shown in Table 1.

[0076] [Table 1]

[0077] ·Process (K) The pad surfaces of the wiring boards according to Examples 1 to 4 and Comparative Examples 1 and 2 were subjected to a desmear treatment (second surface treatment). That is, first, for swelling treatment, the pads were immersed in 40 mL / L of a swera (Cleaner Securigant 902, manufactured by Atotech) at 70°C for 5 minutes. Then, the pads were immersed in pure water for 1 minute. Next, for removing the surface treatment agent, the pads were immersed in 40 mL / L of a desmear solution (Compact CP, manufactured by Atotech) at 70°C for 3 minutes. Next, the pads were immersed in pure water for 1 minute. Then, the pads were dried on a hot plate at 80°C for 5 minutes.

[0078] <Evaluation of surface treatment agent removal> The removability of the surface treatment agent was evaluated according to Examples 1 to 4 and Comparative Examples 1 and 2. For the openings of Φ100 μm, Φ50 μm, Φ30 μm, Φ20 μm, and Φ10 μm, the exposed copper surface was observed at 900 cm using a Raman microscope (product name: DXR2 Microscope, manufactured by Thermo Fisher Scientific Co., Ltd.). -1 The presence or absence of peaks was checked, and pads with zero peaks (residues) out of 10 were rated as "A", pads with one or two peaks were rated as "B", and pads with three or more peaks were rated as "C". The results are shown in Table 2.

[0079] [Table 2]

[0080] [Examples 1a to 4d and Comparative Examples 1a to 2d] ·Process (L) A plurality of wiring boards according to Examples 1 to 4 and Comparative Examples 1 and 2 were prepared, and as shown in Table 3, were heated at 200° C. or 250° C. for 30 minutes or 3 hours, respectively.

[0081] <Evaluation of electrical insulation> The electrical insulation of the wiring boards according to Examples 1a to 4d and Comparative Examples 1a to 2d was evaluated. Wirings with L / S of 20 μm / 20 μm, 15 μm / 15 μm, 10 μm / 10 μm, 7 μm / 7 μm, 5 μm / 5 μm, 3 μm / 3 μm, and 2 μm / 2 μm were tested under the conditions of electrical insulation at 130° C., relative humidity of 85%, and applied voltage of 3.3 V using a HAST chamber (EHS-222MD, manufactured by ESPEC) and an ion migration evaluation system (AM-150-U-5, manufactured by ESPEC). Of the 10 wirings, the electrical resistance value was 1×10 6 When there were 10 wires with an insulation retention time of 200 hours or more in Ω, it was rated as "A", when there were 7 or more, it was rated as "B", and when there were 5 or more, it was rated as "C". The results are shown in Table 3.

[0082] [Table 3]

[0083] <Evaluation of heat resistance> The heat resistance of the wiring boards according to Examples 1a to 4d and Comparative Examples 1a to 2d was evaluated. The wirings with L / S of 20 μm / 20 μm, 15 μm / 15 μm, 10 μm / 10 μm, 7 μm / 7 μm, 5 μm / 5 μm, 3 μm / 3 μm, and 2 μm / 2 μm were tested using a HAST chamber (EHS-222MD, manufactured by ESPEC) at a holding temperature of 130° C., a relative humidity of 85%, and a holding time of 500 hours. After the heat resistance test, the cross section of the wiring was observed with a scanning electron microscope (manufactured by Hitachi High-Tech Corporation, Regulus8230) to observe the thickness of the copper oxide (CuO) on the wiring surface and the presence or absence of peeling between the wiring and the insulating material. When the thickness of the copper oxide (CuO) was 50 nm or less, it was rated as "A", when it was 80 nm or less, it was rated as "B", and when it was 150 nm or less, it was rated as "C". The evaluation results for the thickness of the copper oxide are shown in Table 4. After the heat resistance test, if 10 out of 10 wires had no peeling, it was rated as "A", if 7 or more had no peeling, it was rated as "B", and if 5 or more had no peeling, it was rated as "C". The evaluation results for peeling are shown in Table 5.

[0084] [Table 4]

[0085] [Table 5] [Industrial Applicability]

[0086] According to the present disclosure, there is provided a method for manufacturing a wiring board in which a wiring portion and an insulating material layer have sufficient adhesion and heat resistance as well as sufficient insulation reliability. [Explanation of symbols]

[0087] 1...first insulating material layer, 2...second insulating material layer, 3...third insulating material layer, 5...surface treatment layer, 6...surface treatment agent removal portion, 7...fired layer, 8A, 8B...wiring layer, 10, 20, 30...wiring board, 40...multilayer wiring board, C...wiring portion, C1...pad, C2...wiring, F...desmeared surface, H...opening, H1...first opening, H2...second opening, R...resist pattern, R1, R2...openings, S...supporting board, Sa...conductive layer, T...seed layer

Claims

1. A support substrate having a first surface and a second surface; a first layer of insulating material formed on the first surface of the support substrate; a first wiring formed on a surface of the first insulating material layer; a second insulating material layer formed to cover the surface of the first insulating material layer and the first wiring; a first fired layer formed between the first wiring and the second insulating material layer; Equipped with A wiring board, wherein the first fired layer is a layer in which a surface treatment agent containing an organic component that improves adhesion between the first wiring and the second insulating material layer has been altered by reaction with the second insulating material layer.

2. A first opening formed in the first insulating material layer; a second opening formed in the second insulating material layer and communicating with the first opening; a pad formed by a conductive material filled in the first opening and the second opening; and a second fired layer formed between the pad and the second layer of insulating material; Further comprising:

2. The wiring board according to claim 1, wherein the second fired layer is a layer formed by a reaction of a surface treatment agent containing an organic component that improves adhesion between the pad and the second insulating material layer with the second insulating material layer.

3. A second wiring formed on a surface of the second insulating material layer; a third insulating material layer formed to cover the surface of the second insulating material layer and the second wiring; a third fired layer formed between the second wiring and the third insulating material layer; Further comprising:

3. The wiring board according to claim 1, wherein the third fired layer is a layer formed by a surface treatment agent containing an organic component that improves adhesion between the second wiring and the third insulating material layer being altered by reaction with the third insulating material layer.

4. A wiring board described in any one of claims 1 to 3, wherein the first wiring has a surface with an average roughness Ra of 40 to 80 nm.

5. A wiring board described in any one of claims 1 to 4, wherein the width of the first wiring is 0.5 to 20 μm.

6. A wiring board described in any one of claims 1 to 5, further comprising a conductive layer provided between the support substrate and the first insulating material layer.

7. A wiring board according to any one of claims 1 to 6, A semiconductor chip mounted on the wiring substrate; A semiconductor package comprising:

8. A wiring board according to any one of claims 1 to 6, A plurality of semiconductor chips mounted on the wiring substrate; Equipped with The semiconductor package, wherein the plurality of semiconductor chips have different capabilities.

9. A semiconductor package as described in claim 7 or 8, wherein the semiconductor chip is flip-chip mounted to the wiring substrate.

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