Wiring board and method of manufacturing the same

Abstract

To improve the connection reliability.SOLUTION: A wiring board includes a wiring layer, an insulating layer laminated on the wiring layer, an opening that penetrates the insulating layer to the wiring layer, and a conductor film formed in the opening of the insulating layer. The surface of the insulating layer includes a smooth portion exposed from the conductor film, and a roughened portion including an inner wall surface of the opening covered with the conductor film and having a surface roughness larger than that of the smooth portion.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a wiring board and a method for manufacturing a wiring board. [Background technology]

[0002] Conventionally, wiring boards on which semiconductor chips are mounted have a multilayer wiring structure formed using, for example, a semi-additive process. Specifically, a wiring layer is formed on an insulating layer by electroless plating and electrolytic plating, and an insulating layer is further formed to cover this wiring layer. In this way, a wiring board with a multilayer wiring structure is formed by repeatedly stacking insulating layers and wiring layers.

[0003] In such wiring boards, vias are provided through the insulating layers as needed to electrically connect the wiring patterns of different wiring layers. The outermost wiring layer of the multilayer wiring structure is covered with an insulating solder resist layer. Connection terminals are provided through the solder resist layer as needed, allowing electrical connection between the outermost wiring layer and electronic components such as semiconductor chips mounted on the solder resist layer.

[0004] These vias and connection terminals are formed by forming openings in an insulating layer or a solder resist layer, forming a seed layer by electroless plating on the surface of the insulating layer or the solder resist layer, including the inner wall surface of the opening, and then performing electrolytic plating on the seed layer. Electrolytic plating is performed by masking areas other than those where the vias or connection terminals will be formed with, for example, dry film resist (DFR). After electrolytic plating, the DFR is removed, and the seed layer exposed in unnecessary areas is removed by etching. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2019-125709 [Patent Document 2] Japanese Patent Application Publication No. 2019-186243 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the above-mentioned wiring board has a problem in that the connection reliability of the vias and the connection terminals is insufficient. Specifically, when the unnecessary portions of the seed layer are removed by etching, the seed layer at the bases of the vias and the connection terminals is etched from the sides by side etching, resulting in undercuts. This is because the etching solution used to etch the seed layer is isotropic, and the unnecessary portions of the seed layer are etched in the thickness direction and also in the direction along the surface, dissolving the bases of the vias and the connection terminals from the sides.

[0007] Because the amount of undercut varies depending on the etching time, it is possible to reduce the undercut by shortening the etching time. However, in this case, the unnecessary seed layer may not be sufficiently removed, which may cause short circuits in the wiring pattern. Therefore, the etching time is generally set longer than the time required to completely remove the unnecessary seed layer in the thickness direction to reliably prevent short circuits in the wiring pattern. As a result, side etching increases and the undercut becomes larger.

[0008] Furthermore, as the undercut increases, the range of movement of the vias and connection terminals increases, making the electrical connection between the vias and connection terminals and the wiring layer unstable, which reduces the reliability of the connection between the vias and connection terminals and the wiring layer of the wiring board.

[0009] The disclosed technology has been made in view of the above points, and aims to provide a wiring board and a method for manufacturing a wiring board that can improve connection reliability. [Means for solving the problem]

[0010] In one aspect, the wiring board disclosed in the present application comprises a wiring layer, an insulating layer stacked on the wiring layer, an opening that penetrates the insulating layer to the wiring layer, and a conductive film formed in the opening of the insulating layer, wherein the surface of the insulating layer has a smooth portion exposed from the conductive film and a roughened portion that includes an inner wall surface of the opening that is covered by the conductive film and has a surface roughness greater than that of the smooth portion. [Effects of the Invention]

[0011] According to one aspect of the wiring board and the method for manufacturing the wiring board disclosed in the present application, it is possible to achieve an effect of improving connection reliability. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a diagram showing a configuration of a wiring board according to an embodiment. [Figure 2] FIG. 2 is an enlarged view of a part of the connection terminal. [Figure 3] FIG. 3 is an enlarged view of the periphery of the via. [Figure 4] FIG. 4 is a flow diagram showing a method for manufacturing a semiconductor device according to one embodiment. [Figure 5] FIG. 5 is a diagram showing a specific example of a core substrate forming step. [Figure 6] FIG. 6 is a diagram showing a specific example of the insulating layer forming step. [Figure 7] FIG. 7 is a diagram showing a specific example of the opening forming step. [Figure 8] FIG. 8 is a diagram showing a specific example of the wiring layer forming step. [Figure 9] FIG. 9 is a diagram showing a specific example of a multilayer wiring structure. [Figure 10] FIG. 10 is a diagram showing a specific example of the solder resist layer forming step. [Figure 11] FIG. 11 is a diagram showing a specific example of the connection terminal forming step. [Figure 12] FIG. 12 is a diagram showing a specific example of a semiconductor chip mounting process. [Figure 13]FIG. 13 is a flow chart showing the connection terminal forming step. [Figure 14] FIG. 14 is an enlarged view of a part of the solder resist layer. [Figure 15] FIG. 15 is a diagram showing a specific example of the opening forming step. [Figure 16] FIG. 16 is a diagram showing a specific example of the desmearing process. [Figure 17] FIG. 17 is a diagram showing a specific example of an electroless plating process. [Figure 18] FIG. 18 is a diagram showing the appearance of the surface of the seed layer. [Figure 19] FIG. 19 is a diagram showing a specific example of the DFR layer forming step. [Figure 20] FIG. 20 is a diagram showing a specific example of an electrolytic plating process. [Figure 21] FIG. 21 is a diagram showing a specific example of the DFR layer removal step. [Figure 22] FIG. 22 is a diagram showing a specific example of the etching process. [Figure 23] FIG. 23 is a diagram showing a specific example of the masking process. [Figure 24] FIG. 24 is a diagram showing a specific example of the dry desmear treatment process. [Figure 25] FIG. 25 is a diagram showing a specific example of the mask removal process. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, an embodiment of a wiring board and a method for manufacturing a wiring board disclosed in the present application will be described in detail with reference to the drawings. However, the present invention is not limited to this embodiment.

[0014] Fig. 1 is a diagram showing a configuration of a wiring board 100 according to one embodiment. Fig. 1 schematically shows a cross section of the wiring board 100. The wiring board 100 shown in Fig. 1 can be used, for example, as a substrate for a semiconductor device on which a semiconductor chip is mounted.

[0015] The wiring board 100 has a layered structure and includes a core substrate 110, a multilayer wiring structure 120, and solder resist layers 130 and 140. In the following description, the solder resist layer 140 is the bottom layer and the solder resist layer 130 is the top layer, as shown in Fig. 1, but the wiring board 100 may be used, for example, upside down, or in any position.

[0016] Core substrate 110 is made by forming wiring layers 113 by metal plating on both sides of base material 111, which is a plate-shaped insulator. Wiring layers 113 on both sides are connected by through-wires 112 that penetrate base material 111 as necessary.

[0017] The multilayer wiring structure 120 is formed by stacking layers including an insulating layer 121 and a conductive wiring layer 122. The insulating layer 121 is formed using a heat-resistant, non-photosensitive, thermosetting insulating resin, such as epoxy resin, polyimide resin, or cyanate resin. The wiring layer 122 is formed using a metal, such as copper or a copper alloy. In FIG. 1, two layers are stacked in the multilayer wiring structure 120 above the core substrate 110, and two layers are stacked in the multilayer wiring structure 120 below the core substrate 110. However, the number of stacked layers may be one or three or more. Adjacent wiring layers 113 and 122, separated by the insulating layer 121, are connected by vias 123 that penetrate the insulating layer 121 as necessary. Because the insulating layer 121 is formed using a non-photosensitive thermosetting resin, openings for forming the vias 123 can be formed by laser processing. As will be described later, the surface of the insulating layer 121 is roughened on the inner wall surface of the opening where the via 123 is formed and in the vicinity of the via 123.

[0018] The solder resist layer 130 is a layer that covers the uppermost wiring layer 122 of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 130 is a layer made of a heat-resistant, non-photosensitive, thermosetting insulating resin such as epoxy resin, polyimide resin, or cyanate resin, and is one of the insulating layers.

[0019] The solder resist layer 130 side of the wiring substrate 100 is the surface on which electronic components such as semiconductor chips are mounted. Openings 131 are formed in the solder resist layer 130 at positions where the semiconductor chips are to be mounted. Because the solder resist layer 130 is formed using a non-photosensitive thermosetting resin, the openings 131 can be formed by laser processing. Connection terminals 150 that connect the wiring layer 122 of the multilayer wiring structure 120 to electrodes of the semiconductor chips are formed in the openings 131. As will be described later, the surface of the solder resist layer 130 is roughened on the inner wall surfaces of the openings 131 and in the vicinity of the connection terminals 150.

[0020] Like the solder resist layer 130, the solder resist layer 140 is a layer that covers the wiring layer 122 on the surface of the multilayer wiring structure 120 and protects the wiring. The solder resist layer 140 is a layer made of a heat-resistant, non-photosensitive, thermosetting insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin, and is a type of insulating layer.

[0021] The solder resist layer 140 side of the wiring board 100 is the surface that is connected to external components, devices, etc. At positions where external connection terminals for electrical connection to external components or devices will be formed, openings 141 are formed in the solder resist layer 140, and the wiring layer 122 of the multilayer wiring structure 120 is exposed through the openings 141. External connection terminals, such as solder balls, are formed in the openings 141. Because the solder resist layer 140 is formed using a non-photosensitive thermosetting resin, the openings 141 can be formed by laser processing.

[0022] Fig. 2 is an enlarged view of part A in Fig. 1. In this figure, the vicinity of the boundary between the connection terminal 150 and the solder resist layer 130 is shown in enlargement.

[0023] As shown in FIG. 2, the connection terminal 150 has a seed layer 151, which is an electroless plated film formed by electroless plating, and a post 152, which is an electrolytic plated film formed on the seed layer 151 by electrolytic plating. Near the position where the connection terminal 150 is to be formed, the surface of the solder resist layer 130 is roughened to form a roughened portion 130a. In other positions, the surface of the solder resist layer 130 is smooth, forming a smooth portion 130b. The seed layer 151 forming the connection terminal 150 is formed in the roughened portion 130a by electroless plating. The roughened portion 130a has a longer creepage distance per unit length in a direction parallel to the surface of the solder resist layer 130 than the smooth portion 130b. This reduces the amount of side etching of the seed layer 151, and also reduces the undercut around the post 152.

[0024] That is, the unnecessary portion of the seed layer is formed on the smooth portion 130b, and when this seed layer is removed by etching, the seed layer 151 that forms the connection terminal 150 is side-etched. At this time, because the creeping distance of the roughened portion 130a on which the seed layer 151 is formed is long, the side etching progresses relatively slowly in a direction parallel to the surface of the solder resist layer 130, and only a small amount of the lower portion of the post 152 and the seed layer 151 is dissolved. As a result, the undercut of the connection terminal 150 is small, and the connection reliability between the connection terminal 150 and the wiring layer 122 can be improved.

[0025] Although the structure of the connection terminal 150 has been described above, the via 123 penetrating the insulating layer 121 and the surrounding wiring layer 122 are also made of a seed layer and an electroplated layer, just like the connection terminal 150. Specifically, as shown in FIG. 3, the wiring layer 122 is made of a seed layer 122a and an electroplated layer 122b at the position where the via 123 is to be formed. The via 123 is formed by filling the seed layer 122a with electroplating in the opening of the insulating layer 121. Such wiring layer 122 and via 123 are formed, for example, by a semi-additive method.

[0026] A roughened portion is formed on the surface of the insulating layer 121 near the position where the via 123 is to be formed. That is, the inner wall surface of the opening of the insulating layer 121 where the via 123 is to be formed is roughened, and the seed layer 122a is formed so as to cover the roughened portion. Since the via 123 is formed by electrolytic plating on this seed layer 122a, the undercut of the via 123 can be reduced, and the connection reliability between the via 123 and the wiring layer 113 (or the underlying wiring layer 122) can be improved.

[0027] Next, a method for manufacturing a semiconductor device having wiring substrate 100 configured as described above will be described with reference to a flow chart in FIG. 4, using a specific example.

[0028] First, a core substrate 110 serving as a support member for the wiring board 100 is formed (step S101). Specifically, as shown in FIG. 5, for example, through-hole wiring 112 is formed in a base material 111, which is a plate-shaped insulator, and wiring layers 113 made of metal such as copper or a copper alloy are formed on both sides of the base material 111 by, for example, copper foil or copper plating. The wiring layers 113 on both sides of the base material 111 are connected by through-hole wiring 112 formed by plating of metal such as copper or a copper alloy, as necessary. The base material 111 can be made of a reinforcing material such as a woven glass fabric impregnated with an insulating resin such as an epoxy resin. In addition to the woven glass fabric, other reinforcing materials such as a nonwoven glass fabric, a woven aramid fabric, or a nonwoven aramid fabric can also be used. In addition to the epoxy resin, other insulating resins such as a polyimide resin or a cyanate resin can also be used.

[0029] Then, a multilayer wiring structure 120 is formed by a build-up method on the upper and lower surfaces of the core substrate 110. Specifically, as shown in Fig. 6, for example, an insulating layer 121 is first formed on the upper and lower surfaces of the core substrate 110 (step S102). That is, an insulating layer 121 made of a heat-resistant, non-photosensitive, thermosetting resin such as an epoxy resin, a polyimide resin, or a cyanate resin is laminated on the wiring layer 113 of the core substrate 110.

[0030] An opening is formed in the insulating layer 121 at a position where the via 123 is to be formed (step S103). That is, as shown in FIG. 7, for example, an opening 121a is formed that penetrates the insulating layer 121 and exposes the wiring layer 113 at the bottom. At this time, since the insulating layer 121 is formed of a non-photosensitive resin, the opening 121a is formed by laser processing. For example, a CO laser or a UV laser is used for the laser processing, and the laser is irradiated onto the surface of the insulating layer 121 so that the surface temperature of the insulating layer 121 is at least equal to or higher than the glass transition temperature of the resin that makes up the insulating layer 121. That is, when the opening 121a is formed, a laser having energy that alters the material of the insulating layer 121 is irradiated onto the inner wall surface and periphery of the opening 121a, and the inner wall surface and periphery of the opening 121a become embrittled.

[0031] Once the opening 121a is formed in the insulating layer 121, a desmear process is performed to remove resin residue. That is, the resin residue remaining in and around the opening 121a is removed using, for example, a potassium permanganate solution. At this time, the inner wall surface and periphery of the opening 121a are embrittled, so when these parts are immersed in the chemical solution used for the desmear process, the surface of the insulating layer 121 is roughened and the surface roughness increases. The surface roughness of the inner wall surface and periphery of the opening 121a is, for example, about 3 to 10 times larger than the surface roughness of the part that has not been embrittled by laser irradiation.

[0032] Then, the wiring layer 122 is formed on the insulating layer 121 with the openings 121a formed therein (step S104). The wiring layer 122 is formed by, for example, a semi-additive method. In this case, a seed layer is formed on the surface of the insulating layer 121, including the inner wall surfaces of the openings 121a, by, for example, electroless copper plating. Next, a plating resist layer having openings in areas where wiring patterns are to be formed is formed on the seed layer. Next, electrolytic copper plating is performed on the seed layer exposed from the openings in the plating resist layer to form an electrolytic plated layer. Next, the plating resist layer is removed. Thereafter, the seed layer exposed from the electrolytic plated layer is removed by etching, thereby forming the wiring layer 122 having the desired wiring pattern.

[0033] At this time, as shown in FIG. 8 , for example, openings 121a of insulating layer 121 are filled with electrolytic copper plating to form vias 123 penetrating insulating layer 121, electrically connecting wiring layer 113 and wiring layer 122 of core substrate 110. After the wiring pattern is formed by electrolytic copper plating, unnecessary portions of the seed layer where the wiring pattern is not formed are removed by etching. However, because the surface of insulating layer 121 is roughened around via 123, the amount of side etching of the seed layer forming via 123 is small. This reduces undercuts around via 123, improving the connection reliability of via 123. The seed layer may be formed by sputtering a metal such as copper. A seed layer formed by electroless plating or sputtering, or an electrolytic plating layer are examples of conductive films.

[0034] By repeating the above-described formation of insulating layer 121, formation of openings 121a, and formation of wiring layer 122 a desired number of times, insulating layers 121 and wiring layers 122 are sequentially stacked to form multilayer wiring structure 120. In the following, the explanation will be continued assuming that two insulating layers 121 and two wiring layers 122 are formed on the top and bottom surfaces of core substrate 110, for example, as shown in Fig. 9. Around each via 123 shown in Fig. 9, the surface of insulating layer 121 is roughened, so that undercuts around via 123 are small, improving connection reliability.

[0035] When the multilayer wiring structure 120 is formed by the build-up method, the wiring layer 122 on the surface of the multilayer wiring structure 120 is covered with solder resist layers 130 and 140 (step S105). That is, the wiring layer 122 on the surface of the multilayer wiring structure 120 laminated on the upper surface of the core substrate 110 is covered with the solder resist layer 130, and the wiring layer 122 on the surface of the multilayer wiring structure 120 laminated on the lower surface of the core substrate 110 is covered with the solder resist layer 140. The solder resist layers 130 and 140 are formed from a heat-resistant, non-photosensitive, thermosetting resin material such as epoxy resin, polyimide resin, and cyanate resin.

[0036] 10, for example, openings 131 are formed in the solder resist layer 130 on the side on which the semiconductor chip is mounted at positions where connection terminals 150 for connecting to the semiconductor chip are to be provided (step S106). The uppermost wiring layer 122 of the multilayer wiring structure 120 is exposed at the bottom of the openings 131. Meanwhile, openings 141 are formed in the solder resist layer 140 on the side connected to external components or devices at positions where external connection terminals are to be provided. The lowermost wiring layer 122 of the multilayer wiring structure 120 is exposed at the bottom of the openings 141.

[0037] Because the solder resist layers 130, 140 are formed from a non-photosensitive resin, the openings 131, 141 are formed by laser processing. For example, a CO2 laser or a UV laser is used for the laser processing, and the laser is irradiated onto the surfaces of the solder resist layers 130, 140 so that the surface temperature of the solder resist layers 130, 140 is at least equal to or higher than the glass transition temperature of the resin that makes up the solder resist layers 130, 140. In other words, when the openings 131, 141 are formed, the inner wall surfaces and surrounding areas of the openings 131, 141 are irradiated with a laser having energy that alters the material of the solder resist layers 130, 140, causing the inner wall surfaces and surrounding areas of the openings 131, 141 to become embrittled.

[0038] Once the openings 131, 141 are formed in the solder resist layers 130, 140, a desmear process is performed to remove resin residue. That is, the resin residue remaining in and around the openings 131, 141 is removed using, for example, a potassium permanganate solution. At this time, the inner wall surfaces and peripheries of the openings 131, 141 are embrittled, so when these parts are immersed in the chemical solution used for the desmear process, the surfaces of the solder resist layers 130, 140 are roughened, increasing the surface roughness. The surface roughness of the inner wall surfaces and peripheries of the openings 131, 141 is, for example, about 3 to 10 times larger than the surface roughness of the parts that have not been embrittled by laser irradiation.

[0039] Then, the connection terminals 150 are formed in the openings 131 of the solder resist layer 130 (step S107). That is, a seed layer is formed on the surface of the solder resist layer 130 by, for example, electroless copper plating, and then, at the positions of the openings 131, electrolytic copper plating is applied to the seed layer, thereby forming the connection terminals 150 each consisting of the seed layer 151 and a post 152. The connection terminals 150 are connected to the uppermost wiring layer 122 of the multilayer wiring structure 120 at the positions of the openings 131 of the solder resist layer 130, as shown in FIG. 11 , for example. The seed layer may be formed by sputtering a metal such as copper. A seed layer formed by electroless plating or sputtering, or an electrolytic plating layer is an example of a conductive film.

[0040] When forming the connection terminals 150, the posts 152 are formed on the seed layer 151 by electrolytic copper plating, and then unnecessary portions of the seed layer are removed by etching. However, because the surface of the solder resist layer 130 is roughened around the openings 131, the amount of side etching of the seed layer 151 is small. This reduces undercuts around the connection terminals 150, improving the connection reliability of the connection terminals 150. The formation of the connection terminals 150 will be described in detail later.

[0041] The formation of connection terminals 150 completes wiring board 100. Then, a semiconductor chip is mounted on the solder resist layer 130 side of wiring board 100 (step S108), and connection terminals 150 and electrodes of the semiconductor chip are connected.

[0042] 12, for example, the semiconductor chip 180 is mounted above the connection terminals 150. The semiconductor chip 180 is mounted on the wiring substrate 100 by joining the electrodes 181 to the connection terminals 150 with, for example, solder, and sealing the joints between the electrodes 181 and the connection terminals 150 with underfill resin 182. Next, external connection terminals such as solder balls 170 are formed in the openings 141 of the solder resist layer 140 (step 109). Note that the order of the step of mounting the semiconductor chip 180 and the step of forming the external connection terminals may be reversed. Alternatively, the solder balls 170 may not be provided, and the portions of the wiring layer 122 exposed from the openings 141 of the solder resist layer 140 may serve as the external connection terminals.

[0043] Next, the process of forming the connection terminal 150 will be described more specifically with reference to the flow chart shown in Fig. 13. Here, a method of forming the connection terminal 150 on the solder resist layer 130 that covers the uppermost wiring layer 122 of the multilayer wiring structure 120 will be described, for example, as shown in Fig. 14. However, a similar method can also be applied to the case of forming a via 123 in the insulating layer 121.

[0044] When the solder resist layer 130 is formed using a non-photosensitive insulating resin, openings 131 are formed in the solder resist layer 130 (step S201). Specifically, as shown in FIG. 15, for example, a laser such as a CO laser or UV laser is irradiated at a position where the wiring pattern of the wiring layer 122 will be disposed, thereby forming openings 131 in the solder resist layer 130. At this time, a relatively high-energy laser is irradiated so that the surface temperature of the solder resist layer 130 is at least equal to or higher than the glass transition temperature of the resin that constitutes the solder resist layer 130, and therefore the resin on the inner wall surface 131a of the opening 131 and around it is altered and becomes embrittled. In FIG. 15, the portion where the resin is altered is indicated by a thick line.

[0045] Then, a desmearing process is performed to remove resin residue remaining on the bottom surface and inner wall surface 131a of opening 131 and their surroundings (step S202). That is, the inside of opening 131 and its surroundings are cleaned with a chemical solution such as a potassium permanganate solution. Because the inner wall surface 131a of opening 131 and its surroundings have been embrittled by the laser irradiation, they are roughened when immersed in the chemical solution, as shown in FIG. 16, for example. That is, around opening 131, roughened portion 130a is formed on the surface of solder resist layer 130, and the surface roughness is greater than that of other smooth portion 130b.

[0046] Specifically, the arithmetic mean roughness Ra, which represents the surface roughness of the smooth portion 130b, is, for example, about 60 to 100 nm, while the arithmetic mean roughness Ra of the roughened portion 130a is, for example, about 300 to 600 nm. Therefore, the surface roughness of the roughened portion 130a is, for example, about 3 to 10 times larger than the surface roughness of the smooth portion 130b. While this ratio of the surface roughnesses of the roughened portion 130a and the smooth portion 130b is merely an example, the surface roughness of the roughened portion 130a is preferably in the range of about 1.5 to 50 times larger than the surface roughness of the smooth portion 130b. As the surface roughness of the roughened portion 130a increases, the creepage distance per unit length in the direction parallel to the surface of the solder resist layer 130 increases in the roughened portion 130a. That is, the creepage distance per unit length in the roughened portion 130a is, for example, 3 to 10 times the creepage distance per unit length in the smooth portion 130b.

[0047] Once the roughened portion 130a is formed around the opening 131 in this manner, a seed layer 151 is formed by electroless plating (step S203). Specifically, as shown in Fig. 17, the surface of the solder resist layer 130 including the roughened portion 130a and the smooth portion 130b is subjected to, for example, electroless copper plating to form the seed layer 151. The thickness of the seed layer 151 is, for example, about 0.5 to 1.5 µm.

[0048] The seed layer 151 covers the upper surface of the wiring layer 122, the roughened portion 130a, and the smooth portion 130b. When viewed from above, the seed layer 151 has an appearance as shown in FIG. 18, for example. That is, a portion covering the roughened portion 130a, including the inner wall surface of the opening 131, extends around the central portion covering the upper surface of the wiring layer 122, and a portion covering the smooth portion 130b extends around that portion. The seed layer 151 may be formed by sputtering a metal such as copper.

[0049] After the seed layer 151 is formed, a dry film resist (DFR) layer that serves as a mask for electrolytic plating is formed (step S204). That is, the DFR is laminated on the seed layer 151, and exposure and development are performed according to the positions of the connection terminals 150, thereby forming a DFR 210 on the seed layer 151 in a portion other than the position where the connection terminals 150 are to be formed, as shown in FIG.

[0050] Then, electrolytic plating is performed to form posts 152 on the seed layer 151 (step S205). Specifically, electrolytic copper plating is performed using, for example, a copper sulfate plating solution, so that copper is deposited in the portions where the DFR 210 is not formed, and posts 152 are formed on the seed layer 151, as shown in Fig. 20 . At this time, the openings 131 are filled with electrolytic plating.

[0051] Once the posts 152 are formed, the DFR 210 is removed (step S206). To remove the DFR 210, for example, a caustic soda or amine-based alkaline stripper is used. By removing the DFR 210, the posts 152 protrude from the solder resist layer 130 and connect to the wiring layer 122 via the seed layer 151, as shown in FIG. 21 . At this stage, the seed layer 151 remains on the entire surface, and the posts 152 are short-circuited with other posts. Therefore, it is necessary to remove the unnecessary portions of the seed layer 151 that do not overlap with the posts 152.

[0052] Therefore, the seed layer 151 is etched using the posts 152 as a mask (step S207). Specifically, the seed layer 151 formed on the upper surface of the solder resist layer 130 is immersed in an etching solution that selectively dissolves copper, for example, and unnecessary portions of the seed layer 151 that do not overlap with the posts 152 are removed, as shown in Fig. 22. This forms connection terminals 150 that are connected to the wiring layer 122 and are made up of the seed layer 151 and the posts 152.

[0053] During etching of the seed layer 151, unnecessary portions of the seed layer 151 are dissolved, and at the same time, side etching progresses, dissolving the seed layer 151 overlapping the posts 152 from the sides. However, in the regions overlapping the posts 152, the seed layer 151 is formed on the roughened portion 130a of the solder resist layer 130, so the side etching progresses relatively slowly. That is, the long creeping distance of the roughened portion 130a prevents the etching solution from penetrating the seed layer 151 on the roughened portion 130a, reducing the amount of side etching of the seed layer 151. As a result, only a small amount of the seed layer 151 overlapping the posts 152 is dissolved, reducing the undercut of the connection terminals 150. Therefore, the connection terminals 150 are securely fixed to the surface of the solder resist layer 130, improving the connection reliability between the connection terminals 150 and the wiring layer 122.

[0054] As described above, according to this embodiment, when an opening is formed in an insulating layer made of resin by laser processing, the resin around the opening is altered by laser irradiation, and the altered area around the opening is roughened when the resin residue is removed by desmearing. A seed layer is then formed on the surface of the insulating layer, including the area around the opening, and electrolytic plating is performed on the seed layer to form a connection terminal or via, and unnecessary portions of the seed layer are removed by etching. Therefore, when the unnecessary portions of the seed layer are etched, the intrusion of the etching solution into the roughened area around the opening is prevented, thereby reducing the amount of side etching of the seed layer in the area overlapping the electrolytic plating. As a result, the connection terminal or via can be reliably fixed to the surface of the insulating layer, improving the connection reliability of the connection terminal or via.

[0055] In the above embodiment, the resin around the opening of the insulating layer is altered by laser irradiation, and the surface of the insulating layer is roughened by desmearing the altered area around the opening. However, the method for roughening the surface of the insulating layer is not limited to the above method. For example, after forming an opening in the insulating layer, the area to be smooth other than the area around the opening may be masked with, for example, DFR, and the unmasked area around the opening may be roughened by, for example, dry desmearing.

[0056] In this case, when the solder resist layer 130 is formed using, for example, an insulating resin, an opening 131 is formed in the solder resist layer 130, and a mask is formed around the opening 131 using, for example, DFR. That is, as shown in Fig. 23 , for example, the surface of the solder resist layer 130 except for the inner wall surface 131a of the opening 131 and its periphery is masked by DFR 220.

[0057] Then, a dry desmear process is performed to remove resin residue remaining on the bottom surface, inner wall surface 131a, and the surrounding area of ​​opening 131. Dry desmear process is a type of plasma process that uses, for example, CF4 (carbon tetrafluoride) gas to micro-etch the resin on the surface of the insulating layer. Therefore, by the dry desmear process, the surface of solder resist layer 130 is roughened on inner wall surface 131a of opening 131 exposed from DFR 220 and the surrounding area, as shown in FIG. 24, for example.

[0058] 25, for example, when the mask made of DFR 220 is removed, roughened portion 130a and smooth portion 130b are formed on the surface of solder resist layer 130. In other words, roughened portion 130a is formed on the surface of solder resist layer 130 around opening 131, and the surface roughness is greater than that of other smooth portion 130b.

[0059] Although this method adds the steps of masking using DFR and removing the mask, it also makes it possible to roughen the area around the opening when forming an opening in an insulating layer by exposure and development, and allows the use of a photosensitive resin as the material for the insulating layer.

[0060] Furthermore, in the above embodiment, the connection terminal 150 is made up of the seed layer 151 and the post 152, but a surface treatment layer such as nickel / palladium / gold plating may be formed on the upper surface of the connection terminal 150. By forming a surface treatment layer on the upper surface of the connection terminal 150, it is possible to improve the wettability of the solder when, for example, the electrode 181 of the semiconductor chip 180 is joined to the connection terminal 150 by solder.

[0061] In the above embodiment, the wiring board 100 is described as having the multilayer wiring structure 120 formed on the core substrate 110 by a build-up method. However, the present invention may be applied to a coreless wiring board that does not have the core substrate 110. [Explanation of symbols]

[0062] 110 Core Board 111 Base material 112 Through-hole wiring 113, 122 wiring layer 120 Multilayer wiring structure 121 Insulating layer 121a, 131, 141 opening 123 Beer 130, 140 Solder resist layer 130a Roughening section 130b Smooth part 150 connection terminal 151 seed layer 152 posts 180 semiconductor chips

Claims

1. a wiring layer; an insulating layer laminated on the wiring layer; an opening that penetrates the insulating layer to the wiring layer; a conductive film formed in the opening of the insulating layer, The surface of the insulating layer is a smooth portion exposed from the conductive film; a roughened portion including an inner wall surface of the opening covered with the conductive film and having a surface roughness greater than that of the smooth portion; and The roughened portion is provided on the surface of the insulating layer around the opening and on the inner wall surface of the opening, The conductive film is a surface of the insulating layer around the opening, an inner wall surface of the opening, and a surface of the wiring layer exposed through the opening; The side surface of the conductor film on the surface of the insulating layer around the opening is a portion of the insulating layer surrounding the opening that is located radially inside the opening and further inside than a periphery of the roughened portion; A part of the roughened portion is the conductive film extends outward from the side surface of the conductive film in a plan view and is exposed from the conductive film; The conductive film is a first conductor film covering a surface of the insulating layer around the opening, an inner wall surface of the opening, and a surface of the wiring layer exposed through the opening; a second conductor film laminated on the first conductor film; and The side surface of the first conductor film on the surface of the insulating layer around the opening is a portion of the insulating layer that is located radially inward of the opening and the side surface of the second conductive film; A wiring board characterized by:

2. The roughened portion is 2. The wiring board according to claim 1, wherein the surface roughness of the smooth portion is 1.5 to 50 times greater than the surface roughness of the smooth portion.

3. The conductive film is 2. The wiring board according to claim 1, wherein a connecting terminal is formed by connecting to the wiring layer and projecting from the opening of the insulating layer.

4. The conductive film is 2. The wiring board according to claim 1, wherein a via is formed to connect the wiring layer to another wiring layer formed on the insulating layer.

5. laminating an insulating layer on the wiring layer; forming an opening in the insulating layer that penetrates to the wiring layer; roughening a portion of the surface of the insulating layer including the inner wall surface of the opening; forming a conductive film on the surface of the insulating layer; removing unnecessary portions of the conductor film by etching; and The roughening step includes: a surface of the insulating layer around the opening and an inner wall surface of the opening are roughened to form a roughened portion; The conductive film after the removing step is a surface of the insulating layer around the opening, an inner wall surface of the opening, and a surface of the wiring layer exposed through the opening; The side surface of the conductor film on the surface of the insulating layer around the opening is a portion of the insulating layer surrounding the opening that is located radially inside the opening and further inside than a periphery of the roughened portion; A part of the roughened portion is the conductive film extends outward from the side surface of the conductive film in a plan view and is exposed from the conductive film; The conductive film is a first conductor film covering a surface of the insulating layer around the opening, an inner wall surface of the opening, and a surface of the wiring layer exposed through the opening; a second conductor film laminated on the first conductor film; and The side surface of the first conductor film on the surface of the insulating layer around the opening is a portion of the insulating layer that is located radially inward of the opening and the side surface of the second conductive film; 10. A method for manufacturing a wiring board comprising:

6. The step of forming the opening includes: forming the opening by irradiating the insulating layer with a laser and modifying a part of the surface of the insulating layer including the inner wall surface of the opening; The roughening step includes: A part of the surface of the altered insulating layer is roughened by a desmear treatment using a chemical solution.

6. The method for manufacturing a wiring board according to claim 5.

7. The step of forming the opening includes: The insulating layer is irradiated with a laser so that the surface temperature of the insulating layer is equal to or higher than the glass transition temperature of the resin constituting the insulating layer, thereby altering the inner wall surface of the opening and the surface of the insulating layer around the opening.

7. The method for manufacturing a wiring board according to claim 6.

8. The roughening step includes: forming a mask on the surface of the insulating layer excluding the portion; a step of micro-etching the surface of the insulating layer by a dry desmear treatment using plasma to roughen the portion; removing the mask; 6. The method for manufacturing a wiring board according to claim 5, further comprising the steps of:

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