Semiconductor switching element driving circuit

Abstract

To provide a semiconductor switching element driving circuit capable of both suppressing a surge voltage equal to or higher than a breakdown voltage between a pair of main terminals and maintaining a stable OFF state.SOLUTION: Provided is a driving circuit including a driving unit that switches a semiconductor switching element between an ON state and an OFF state in accordance with a control signal, a timing adjustment circuit that performs a process of delaying switching timings of a first state and a second state of the control signal by a prescribed time, a voltage detection circuit that detects a voltage between the pair of main terminals of the semiconductor switching element, and a current injection circuit that injects current to a control terminal in accordance with the magnitude of the voltage between the pair of main terminals at the time of switching from the ON state to the OFF state of the semiconductor switching element. The timing adjusting circuit delays the switching timing of the processed control signal until the OFF state is established when the current injection circuit operates.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] An embodiment of the present invention relates to a drive circuit for a semiconductor switching element. [Background technology]

[0002] There is a drive circuit that drives a semiconductor switching element. The semiconductor switching element has a pair of main terminals and a control terminal, and has an on state in which a current flows between the pair of main terminals, and an off state in which the flow of current between the pair of main terminals is blocked. The drive circuit is connected to the control terminal of the semiconductor switching element, and switches between the on state and the off state by a voltage applied to the control terminal. The drive circuit sets the switching element to the on state by applying a first voltage to the control terminal, and sets the switching element to the off state by applying a second voltage different from the first voltage to the control terminal.

[0003] It has been proposed to provide such a drive circuit with a current injection circuit for suppressing the generation of an excessive surge voltage exceeding the withstand voltage of the semiconductor switching element between a pair of main terminals when the semiconductor switching element is switched from an on state to an off state. The current injection circuit injects a current into the control terminal according to the voltage between the pair of main terminals when the semiconductor switching element is switched from an on state to an off state, thereby slowing down the switching speed and suppressing the generation of an excessive surge voltage exceeding the withstand voltage between the pair of main terminals.

[0004] Also proposed is a two-stage drive method in which a drive circuit applies a second voltage to a control terminal via a resistive element to switch a semiconductor switching element from an on state to an off state, and then applies the second voltage to the control terminal in a lower resistance state. Compared to a one-stage drive method in which the second voltage is only applied to the control terminal via a resistive element, the two-stage drive method can maintain the semiconductor switching element in an off state in a more stable state while suppressing abrupt changes from an on state to an off state of the semiconductor switching element. For example, it can suppress the voltage of the control terminal from fluctuating due to the influence of the operation of another element connected to the semiconductor switching element, causing the state of the semiconductor switching element to become unstable.

[0005] However, when a two-stage drive method is adopted in a drive circuit provided with a current injection circuit, even if a current is injected from the current injection circuit to the control terminal, the application of the second voltage in a low resistance state makes it difficult for the voltage of the control terminal to change from the second voltage, and it may become impossible to suppress the occurrence of a surge voltage exceeding the withstand voltage between the pair of main terminals.

[0006] Thus, in the drive circuits for semiconductor switching elements, there remains room for improvement in terms of both suppressing surge voltages exceeding the withstand voltage using a current injection circuit and maintaining a stable off state using a two-stage drive method. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent No. 366843 [Patent Document 2] JP 2001-238432 A [Patent Document 3] International Publication No. 2009 / 054143 Summary of the Invention [Problem to be solved by the invention]

[0008] An embodiment of the present invention provides a drive circuit for a semiconductor switching element that can simultaneously suppress a surge voltage exceeding a withstand voltage between a pair of main terminals and maintain a stable off state. [Means for solving the problem]

[0009] According to an embodiment of the present invention, there is provided a drive circuit for a semiconductor switching element, the drive circuit having a pair of main terminals and a control terminal, and switching between an on state and an off state of a semiconductor switching element having an on state in which a current flows between the pair of main terminals and an off state in which a current flow between the pair of main terminals is interrupted, the drive circuit including: a drive unit that receives an input of a control signal having a first state in which the semiconductor switching element is set to the on state and a second state in which the semiconductor switching element is set to the off state, the drive unit being connected to the control terminal of the semiconductor switching element and switching between the on state and the off state of the semiconductor switching element based on the control signal; a timing adjustment circuit that receives an input of the control signal, performs a process of delaying, for a predetermined time, the timing of the control signal switching from the first state to the second state and the timing of the control signal switching from the second state to the first state, and inputs the processed control signal to the drive unit; a voltage detection circuit that detects a voltage between the pair of main terminals of the semiconductor switching element; a current injection circuit connected to the control terminal of the semiconductor switching element, and injecting a current into the control terminal according to a magnitude of a voltage between the pair of main terminals detected by the voltage detection circuit when the semiconductor switching element is switched from the on state to the off state, thereby suppressing an increase in the voltage between the pair of main terminals to a first set voltage or more, wherein the drive unit has a first input terminal for receiving a supply of a first control power source for applying a first voltage to the control terminal, and a second input terminal for receiving a supply of a second control power source for applying a second voltage different from the first voltage to the control terminal, and sets the semiconductor switching element to the on state by applying the first voltage to the control terminal, and sets the semiconductor switching element to the off state by applying the second voltage to the control terminal, anda third application state in which the second voltage is applied to the control terminal, and a fourth application state in which the second voltage is applied to the control terminal in a state in which a resistance between the second input terminal and the control terminal is lower than that in the third application state, and by switching to the third application state in response to switching of the control signal from the first state to the second state, the semiconductor switching element is switched from the on state to the off state, and then, by switching from the third application state to the fourth application state in response to switching of the control signal after the processing of the timing adjustment circuit from the first state to the second state, the semiconductor switching element is switched to the first application state in response to switching of the control signal from the second state to the first state. There is provided a drive circuit for a semiconductor switching element, which switches from the first application state to the second application state in response to a switching of the processed control signal of the timing adjustment circuit from the second state to the first state after switching from the off state to the on state, and when the control signal switches from the first state to the second state and the drive unit switches to the third application state, and the current injection circuit operates, the timing adjustment circuit delays the timing of switching the processed control signal from the first state to the second state until the semiconductor switching element reaches the off state if it is assumed that the semiconductor switching element is in a state between the on state and the off state even after the predetermined time has elapsed. Effect of the Invention

[0010] A drive circuit for a semiconductor switching element is provided that can simultaneously suppress a surge voltage exceeding the withstand voltage between a pair of main terminals and maintain a stable off state. [Brief description of the drawings]

[0011] [Figure 1] FIG. 2 is a block diagram illustrating a drive circuit according to an embodiment of the present invention. [Diagram 2] FIG. 2 is a block diagram illustrating an example of a drive unit. [Diagram 3]4 is a timing chart illustrating an example of the operation of a drive unit and a timing adjustment circuit. [Figure 4] 4 is a timing chart illustrating an example of an operation of the drive circuit according to the embodiment. [Diagram 5] 10 is a timing chart illustrating a modified example of the operation of the drive circuit according to the embodiment. [Figure 6] 10 is a timing chart illustrating a modified example of the operation of the drive circuit according to the embodiment. [Figure 7] FIG. 13 is a block diagram illustrating a modified example of a drive circuit according to the embodiment. [Figure 8] FIG. 13 is a block diagram illustrating a modified example of a drive circuit according to the embodiment. [Figure 9] FIG. 13 is a block diagram illustrating a modified example of a drive circuit according to the embodiment. [Figure 10] FIG. 13 is a block diagram illustrating a modified example of the drive unit. [Figure 11] FIG. 13 is a block diagram illustrating a modified example of the drive unit.

[0012] Each embodiment will be described below with reference to the drawings. In this specification and each drawing, elements similar to those described above with reference to the previous drawings are given the same reference numerals and detailed descriptions thereof will be omitted as appropriate.

[0013] FIG. 1 is a block diagram illustrating a drive circuit according to an embodiment. As shown in FIG. 1, the drive circuit 10 is a drive circuit for the semiconductor switching element 2 that is connected to the semiconductor switching element 2 when used. The semiconductor switching element 2 and the drive circuit 10 are used, for example, in a power conversion device that converts power by switching a plurality of semiconductor switching elements 2. When the semiconductor switching element 2 and the drive circuit 10 are applied to a power conversion device, for example, a rectifier element 4 is connected in inverse parallel to the semiconductor switching element 2. The rectifier element 4 is, for example, a free wheel diode. However, the semiconductor switching element 2 and the drive circuit 10 are not limited to being applied to a power conversion device, and can be applied to any device that requires the semiconductor switching element 2.

[0014] The semiconductor switching element 2 has a pair of main terminals 2a, 2b and a control terminal 2c, and has an ON state in which a current flows between the pair of main terminals 2a, 2b, and an OFF state in which the current flow between the pair of main terminals 2a, 2b is interrupted. Note that the OFF state is not limited to a state in which no current flows between the pair of main terminals 2a, 2b, but may be a state in which a weak current flows between the pair of main terminals 2a, 2b within a range that does not affect the operation of the semiconductor switching element 2 and a device (e.g., a power conversion device) to which the semiconductor switching element 2 is applied.

[0015] The drive circuit 10 is connected to the control terminal 2c of the semiconductor switching element 2, and switches the semiconductor switching element 2 between an on state and an off state by a voltage applied to the control terminal 2c. The drive circuit 10 sets the semiconductor switching element 2 to an on state by applying a first voltage to the control terminal 2c, and sets the semiconductor switching element 2 to an off state by applying a second voltage different from the first voltage to the control terminal 2c.

[0016] The second voltage is, for example, lower than the first voltage. The semiconductor switching element 2 is turned on when the potential of the control terminal 2c relative to the potential of the low-potential side main terminal 2b becomes higher than a threshold voltage between the main terminal 2b and the control terminal 2c of the semiconductor switching element 2, and is turned off when the potential becomes lower than the threshold voltage. The first voltage is, for example, a positive bias voltage in which the potential of the control terminal 2c is higher than the potential of the low-potential side main terminal 2b. The second voltage is, for example, a negative bias voltage in which the potential of the control terminal 2c is lower than the potential of the low-potential side main terminal 2b.

[0017] The semiconductor switching element 2 is, for example, a self-excited semiconductor switching element such as a MOSFET, an IGBT, or an IEGT. More specifically, the semiconductor switching element 2 is an insulated gate type semiconductor switching element. However, the semiconductor switching element 2 is not limited to the above and may be any semiconductor switching element that can be switched between an on state and an off state by the drive circuit 10.

[0018] The drive circuit 10 includes a drive section 12, a timing adjustment circuit 14, a voltage detection circuit 16, and a current injection circuit 18.

[0019] The driver 12 is connected to the control terminal 2c of the semiconductor switching element 2. The driver 12 also receives an input of a control signal. The driver 12 receives an input of a control signal from, for example, a higher-level controller. The driver 12 switches the semiconductor switching element 2 between an ON state and an OFF state based on the input control signal.

[0020] The control signal has a first state for setting the semiconductor switching element 2 to an on state and a second state for setting the semiconductor switching element 2 to an off state. The drive unit 12 switches the semiconductor switching element 2 from an off state to an on state in response to the switching of the control signal from the second state to the first state, and switches the semiconductor switching element 2 from an on state to an off state in response to the switching of the control signal from the first state to the second state.

[0021] The control signal is, for example, a pulse signal (PWM signal). The first state is, for example, a high state of the pulse signal, and the second state is, for example, a low state of the pulse signal. However, the control signal is not limited to the above, and may be any signal that can appropriately switch the on state and off state of the semiconductor switching element 2 in the drive unit 12.

[0022] Moreover, the drive unit 12 applies the second voltage to the control terminal 2c in response to the switching of the control signal from the first state to the second state, thereby switching the semiconductor switching element 2 from the on state to the off state, and then applies the second voltage to the control terminal 2c in a lower resistance state. Furthermore, the drive unit 12 applies the first voltage to the control terminal 2c in response to the switching of the control signal from the second state to the first state, thereby switching the semiconductor switching element 2 from the off state to the on state, and then applies the first voltage to the control terminal 2c in a lower resistance state. In this way, the drive unit 12 switches the semiconductor switching element 2 between the on state and the off state by a two-stage drive method.

[0023] The timing adjustment circuit 14, like the drive unit 12, receives a control signal from a higher-level controller or the like. The timing adjustment circuit 14 performs processing to delay the timing at which the control signal switches from the first state to the second state and the timing at which the control signal switches from the second state to the first state by a predetermined time. In other words, the timing adjustment circuit 14 is a delay circuit. The timing adjustment circuit 14 inputs the processed control signal to the drive unit 12.

[0024] The timing adjustment circuit 14 generates a second control signal in which the timing of switching of the first control signal input from a higher-level controller or the like is delayed by a predetermined time from the first state to the second state, and a third control signal in which the timing of switching of the first control signal from the second state to the first state is delayed by a predetermined time, and inputs the generated second control signal and third control signal to the drive unit 12.

[0025] The predetermined time is set to a time longer than the time required for switching of the semiconductor switching element 2 when the driving unit 12 applies the first or second voltage to the control terminal 2c of the semiconductor switching element 2 in a state where the resistance value is high (first stage of a two-stage driving method). If the driving unit 12 applies the first or second voltage to the control terminal 2c of the semiconductor switching element 2 in a state where the resistance value is low (second stage of a two-stage driving method) during switching of the semiconductor switching element 2, the voltage of the control terminal 2c may suddenly drop or rise, and the switching speed of the semiconductor switching element 2 may increase more than necessary. This may cause the slope of the current flowing through the semiconductor switching element 2 to become steep, which may cause an excessive surge voltage or the like to be generated, causing a large stress on the semiconductor switching element 2. In the worst case, the semiconductor switching element 2 may be damaged. As described above, by setting the specified time to a time longer than the time required for switching of the semiconductor switching element 2 when the first voltage or the second voltage is applied to the control terminal 2c of the semiconductor switching element 2 while the drive unit 12 has a high resistance value, it is possible to switch the semiconductor switching element 2 at an appropriate speed while suppressing unnecessary stress from being applied to the semiconductor switching element 2, even when a two-stage drive method is used.

[0026] The driving unit 12 switches to a low resistance state based on the processed control signal input from the timing adjustment circuit 14. For example, the driving unit 12 applies a second voltage to the control terminal 2c in response to the switching of the first control signal from the first state to the second state, thereby switching the semiconductor switching element 2 from an on state to an off state, and then applies a second voltage in a lower resistance state to the control terminal 2c in response to the switching of the second control signal from the first state to the second state. Then, the driving unit 12 applies a first voltage to the control terminal 2c in response to the switching of the first control signal from the second state to the first state, thereby switching the semiconductor switching element 2 from an off state to an on state, and then applies a first voltage in a lower resistance state to the control terminal 2c in response to the switching of the third control signal from the second state to the first state.

[0027] The voltage detection circuit 16 is connected to a pair of main terminals 2a, 2b of the semiconductor switching element 2. The drive circuit 10 is connected to a control terminal 2c of the semiconductor switching element 2, and is also connected to the pair of main terminals 2a, 2b of the semiconductor switching element 2. The voltage detection circuit 16 detects the voltage between the pair of main terminals 2a, 2b of the semiconductor switching element 2.

[0028] The current injection circuit 18 is connected to the voltage detection circuit 16 and also to the control terminal 2c of the semiconductor switching element 2. The current injection circuit 18 injects a current into the control terminal 2c of the semiconductor switching element 2 in accordance with the magnitude of the voltage between the pair of main terminals 2a, 2b of the semiconductor switching element 2 detected by the voltage detection circuit 16. For example, when the voltage between the pair of main terminals 2a, 2b becomes equal to or higher than a predetermined first set voltage, the current injection circuit 18 injects a current into the control terminal 2c in accordance with the magnitude of the voltage between the pair of main terminals 2a, 2b such that the magnitude of the current injected into the control terminal 2c increases as the voltage between the pair of main terminals 2a, 2b becomes greater than the first set voltage.

[0029] When the semiconductor switching element 2 is switched from the on state to the off state, the current injection circuit 18 injects a current into the control terminal 2c according to the magnitude of the voltage between the pair of main terminals 2a, 2b detected by the voltage detection circuit 16. When a current is injected from the current injection circuit 18 into the control terminal 2c, a drop in the voltage at the control terminal 2c is suppressed. This slows down the switching speed of the semiconductor switching element 2, and the slope of the drop in the current flowing between the pair of main terminals 2a, 2b becomes smaller. As a result, a rise in the voltage between the pair of main terminals 2a, 2b is suppressed. In other words, the surge voltage is suppressed from exceeding the withstand voltage of the semiconductor switching element 2.

[0030] In this way, when the semiconductor switching element 2 is switched from an on state to an off state, the current injection circuit 18 injects a current into the control terminal 2c according to the magnitude of the voltage between the pair of main terminals 2a, 2b detected by the voltage detection circuit 16, and by slowing down the rate of change of the semiconductor switching element 2 from an on state to an off state (reducing the slope of the decrease in the current flowing between the pair of main terminals 2a, 2b), it suppresses the voltage between the pair of main terminals 2a, 2b from rising above the first set voltage. In other words, the current injection circuit 18 suppresses the generation of a surge voltage above the withstand voltage of the semiconductor switching element 2 between the pair of main terminals 2a, 2b when the semiconductor switching element 2 is switched from an on state to an off state.

[0031] The drive circuit 10 further includes a negative bias detection circuit 20 (detection circuit), a comparator 22, and a latch circuit .

[0032] The negative bias detection circuit 20 is connected to the control terminal 2c of the semiconductor switching element 2. A predetermined negative bias detection voltage is set in the negative bias detection circuit 20. The negative bias detection circuit 20 detects whether the voltage of the control terminal 2c of the semiconductor switching element 2 is equal to or lower than the negative bias detection voltage. The negative bias detection voltage is set to, for example, a voltage (0V) that is the same potential as the main terminal 2b on the low potential side. However, the negative bias detection voltage is not limited to 0V, and can be set to any voltage between 0V and the second voltage. In other words, the negative bias detection circuit 20 detects whether the second voltage is applied to the control terminal 2c of the semiconductor switching element 2. In further other words, the negative bias detection circuit 20 detects whether the semiconductor switching element 2 is in an off state.

[0033] When the current injection circuit 18 injects a current into the control terminal 2c after the driver 12 switches the semiconductor switching element 2 from the on state to the off state, the voltage of the control terminal 2c becomes, for example, a voltage between the first voltage and the second voltage. In other words, when the current injection circuit 18 injects a current into the control terminal 2c, the semiconductor switching element 2 becomes a state between the on state and the off state.

[0034] The current injection circuit 18 injects a current into the control terminal 2c in accordance with the magnitude of the voltage between the pair of main terminals 2a, 2b, thereby reducing the slope of the change in the voltage at the control terminal 2c from the first voltage to the second voltage. In other words, the current injection circuit 18 slows down the rate at which the voltage at the control terminal 2c decreases from a positive bias voltage (first voltage) to a negative bias voltage (second voltage) in accordance with the magnitude of the voltage between the pair of main terminals 2a, 2b.

[0035] The negative bias detection circuit 20 detects the voltage of the control terminal 2c, thereby making it possible to detect that the semiconductor switching element 2 has switched to the OFF state when the current injection circuit 18 injects a current into the control terminal 2c.

[0036] The negative bias detection circuit 20 is connected to the main terminal 2b and the control terminal 2c of the semiconductor switching element 2, and is also connected to a latch circuit 24. The negative bias detection circuit 20 inputs to the latch circuit 24 a detection signal indicating a detection result as to whether or not a negative bias voltage is applied to the control terminal 2c of the semiconductor switching element 2.

[0037] The comparator 22 is connected to the output side of the voltage detection circuit 16, and receives an input of the magnitude of the voltage across the pair of main terminals 2a, 2b of the semiconductor switching element 2 detected by the voltage detection circuit 16. The comparator 22 compares whether the magnitude of the voltage across the pair of main terminals 2a, 2b of the semiconductor switching element 2 detected by the voltage detection circuit 16 is equal to or higher than a second set voltage. The comparator 22 inputs a signal indicating the result of the comparison to the latch circuit 24.

[0038] The second set voltage is set, for example, lower than the first set voltage at which the current injection circuit 18 starts injecting current into the control terminal 2c. The second set voltage is set, for example, slightly lower than the first set voltage. In other words, the comparator 22 detects the operation of the current injection circuit 18 based on the detection result of the voltage detection circuit 16. The comparator 22 inputs a signal representing the detection result of the operation of the current injection circuit 18 to the latch circuit 24. However, the second set voltage set in the comparator 22 may be set to any voltage that allows detection of whether the current injection circuit 18 is operating or not.

[0039] The latch circuit 24 performs processing to maintain the state of being equal to or higher than the second set voltage even after the comparison result of the comparator 22 changes from a state equal to or higher than the second set voltage to a state lower than the second set voltage until a negative bias voltage is detected by the negative bias detection circuit 20, and inputs the processed signal to the timing adjustment circuit 14. That is, when the current injection circuit 18 operates by switching the semiconductor switching element 2 from an on state to an off state, the latch circuit 24 outputs a signal indicating the period from when the current injection circuit 18 starts operating to when the semiconductor switching element 2 switches to the off state.

[0040] If the signal input from the latch circuit 24 becomes equal to or higher than the second set voltage before a predetermined time has elapsed from the timing of the first control signal switching from the first state to the second state, and the state of being equal to or higher than the second set voltage continues even after the predetermined time has elapsed, the timing adjustment circuit 14 delays the timing of the second control signal switching from the first state to the second state until the timing of the signal input from the latch circuit 24 switching from a state of being equal to or higher than the second set voltage to a state of being less than the second set voltage.

[0041] In other words, when the first control signal switches from the first state to the second state and the current injection circuit 18 operates as a result of the drive unit 12 applying the second voltage to the control terminal 2c, if it is assumed that the semiconductor switching element 2 will be in a state between the on state and the off state even after a predetermined time has elapsed, the timing adjustment circuit 14 delays the timing of the second control signal (processed control signal) switching from the first state to the second state until the semiconductor switching element 2 is in the off state.

[0042] FIG. 2 is a block diagram illustrating an example of a driving unit. 2, the drive unit 12 has switching elements 31 to 34 and a resistor element 35. The drive unit 12 receives power from a positive-side control power source P (first control power source) for applying a first voltage to the control terminal 2c of the semiconductor switching element 2 from a power source circuit (not shown) or the like, and a negative-side control power source N (second control power source) for applying a second voltage to the control terminal 2c of the semiconductor switching element 2. The drive unit 12 has a first input terminal 12p for receiving power from the positive-side control power source P and a second input terminal 12n for receiving power from the negative-side control power source N.

[0043] The switching elements 31, 32 are connected in series between the first input terminal 12p and the second input terminal 12n (between the positive side control power supply P and the negative side control power supply N). The connection point of the switching elements 31, 32 is connected to one end of a resistive element 35. The other end of the resistive element 35 is connected to the control terminal 2c of the semiconductor switching element 2. The switching elements 31, 32 are connected to the control terminal 2c of the semiconductor switching element 2 via the resistive element 35. The resistive element 35 is, for example, a gate resistor.

[0044] The switching elements 33, 34 are connected in series between the first input terminal 12p and the second input terminal 12n in parallel with the switching elements 31, 32. The connection point of the switching elements 33, 34 is connected between the other end of the resistance element 35 and the control terminal 2c of the semiconductor switching element 2. Therefore, the switching elements 33, 34 are connected to the control terminal 2c of the semiconductor switching element 2 without passing through the resistance element 35.

[0045] A first control signal input from a higher-level controller or the like is input to the control terminals of the switching elements 31 and 32. Meanwhile, control terminals of the switching elements 33 and 34 are connected to the timing adjustment circuit 14. A third control signal generated by the timing adjustment circuit 14 is input to the control terminal of the switching element 33. A second control signal generated by the timing adjustment circuit 14 is input to the control terminal of the switching element 34.

[0046] The switching elements 31 and 33 are, for example, NPN transistors. The switching elements 32 and 34 are, for example, PNP transistors. The switching elements 31 and 33 are turned on when the potential of the control terminal is made higher than the potential of the main terminal on the low potential side, and turned off when the potential of the control terminal is made equal to or lower than the potential of the main terminal on the low potential side. The switching elements 32 and 34 are turned on when the potential of the control terminal is made equal to or lower than the potential of the main terminal on the low potential side, and turned off when the potential of the control terminal is made higher than the potential of the main terminal on the low potential side.

[0047] In the drive unit 12, by turning the switching element 31 on and the switching elements 32 to 34 off, the control terminal 2c of the semiconductor switching element 2 is connected to the first input terminal 12p (positive side control power supply P) via the switching element 31 and the resistive element 35, resulting in a first application state in which a first voltage is applied to the control terminal 2c via the resistive element 35.

[0048] In the drive unit 12, by turning the switching element 33 on and the switching elements 32, 34 off, the control terminal 2c of the semiconductor switching element 2 is connected to the first input terminal 12p (positive side control power source P) via the switching element 33 without going through the resistive element 35, resulting in a second application state in which the first voltage is applied to the control terminal 2c with the resistance between the first input terminal 12p and the control terminal 2c lower than that in the first application state.

[0049] In the drive unit 12, by turning the switching element 32 on and turning the switching elements 31, 33, and 34 off, the control terminal 2c of the semiconductor switching element 2 is connected to the second input terminal 12n (negative side control power supply N) via the switching element 32 and the resistive element 35, resulting in a third application state in which the second voltage is applied to the control terminal 2c via the resistive element 35.

[0050] In the drive unit 12, by turning the switching element 34 on and the switching elements 31, 33 off, the control terminal 2c of the semiconductor switching element 2 is connected to the second input terminal 12n (negative side control power supply N) via the switching element 34 without going through the resistive element 35, resulting in a fourth application state in which the second voltage is applied to the control terminal 2c with the resistance between the second input terminal 12n and the control terminal 2c lower than that in the third application state.

[0051] In this way, the driving unit 12 can switch among a first application state in which the first voltage is applied to the control terminal 2c, a second application state in which the first voltage is applied to the control terminal 2c while the resistance between the first input terminal 12p and the control terminal 2c is lower than that in the first application state, a third application state in which the second voltage is applied to the control terminal 2c, and a fourth application state in which the second voltage is applied to the control terminal 2c while the resistance between the second input terminal 12n and the control terminal 2c is lower than that in the third application state. However, the configuration of the driving unit 12 is not limited to the above, and may be any configuration that can appropriately switch among the above four states.

[0052] Fig. 3 is a timing chart showing an example of the operation of the drive unit and the timing adjustment circuit. More specifically, Fig. 3 shows an example of the normal operation in which the current injection circuit 18 is not operating even when the semiconductor switching element 2 is switched from the on state to the off state.

[0053] As shown in FIG. 3, when the first control signal switches from the first state to the second state, the timing adjustment circuit 14 switches the third control signal from the first state to the second state in response to the switching of the first control signal from the first state to the second state (timing t1 in FIG. 3).

[0054] Furthermore, the timing adjustment circuit 14 starts measuring a predetermined time in response to the switching of the first control signal from the first state to the second state, and switches the second control signal from the first state to the second state after the predetermined time has elapsed from the timing of the switching of the first control signal from the first state to the second state (timing t1 to t2 in FIG. 3). In this way, the timing adjustment circuit 14 delays the timing of the switching of the second control signal from the first state to the second state by a predetermined time.

[0055] When the first control signal switches from the first state to the second state, the switching element 31 switches from the on state to the off state, and the switching element 32 switches from the off state to the on state. In response to the switching of the third control signal from the first state to the second state, the switching element 33 switches from the on state to the off state. Meanwhile, with a delay in the switching of the second control signal from the first state to the second state, the switching element 34 continues to be in the off state.

[0056] Therefore, when the first control signal switches from the first state to the second state, the switching element 32 is turned on and the switching elements 31, 33, and 34 are turned off, and the second voltage is applied to the control terminal 2c via the resistance element 35. In other words, when the first control signal switches from the first state to the second state, the drive unit 12 is turned to the third application state, and the semiconductor switching element 2 is switched from the on state to the off state.

[0057] When a predetermined time has elapsed since the timing of the first control signal switching from the first state to the second state and the second control signal switches from the first state to the second state, the switching element 34 switches from the off state to the on state. This causes the drive unit 12 to enter a fourth application state in which the second voltage is applied to the control terminal 2c in a lower resistance state. In this manner, in the fourth application state in which the second voltage is applied to the control terminal 2c in a lower resistance state, the fluctuation in the voltage of the control terminal 2c is suppressed compared to the third application state in which the second voltage is applied to the control terminal 2c via the resistive element 35, and the semiconductor switching element 2 can be maintained in the off state in a more stable state.

[0058] In this way, the drive unit 12 switches the semiconductor switching element 2 from the on state to the off state by switching to the third application state in response to the switching of the first control signal from the first state to the second state, and then switches from the third application state to the fourth application state in response to the switching of the second control signal (the control signal after processing by the timing adjustment circuit 14) from the first state to the second state.

[0059] When the first control signal switches from the second state to the first state, the timing adjustment circuit 14 switches the second control signal from the second state to the first state in response to the switching of the first control signal from the second state to the first state (timing t3 in FIG. 3).

[0060] Furthermore, the timing adjustment circuit 14 starts measuring a predetermined time in response to the switching of the first control signal from the second state to the first state, and switches the third control signal from the second state to the first state after the predetermined time has elapsed from the timing of the switching of the first control signal from the second state to the first state (timing t3 to t4 in FIG. 3). In this way, the timing adjustment circuit 14 delays the timing of the switching of the third control signal from the second state to the first state by a predetermined time.

[0061] The predetermined time for delaying the third control signal may be the same as or different from the predetermined time for delaying the second control signal. The predetermined time for delaying the second control signal and the predetermined time for delaying the third control signal may be set appropriately depending on the characteristics of the semiconductor switching element 2, etc.

[0062] When the first control signal switches from the second state to the first state, the switching element 31 switches from the off state to the on state, and the switching element 32 switches from the on state to the off state. In response to the switching of the second control signal from the second state to the first state, the switching element 34 switches from the on state to the off state. Meanwhile, with a delay in the switching of the third control signal from the second state to the first state, the switching element 33 continues in the off state.

[0063] Therefore, when the first control signal switches from the second state to the first state, the switching element 31 is turned on and the switching elements 32 to 34 are turned off, and the first voltage is applied to the control terminal 2c via the resistance element 35. In other words, when the first control signal switches from the second state to the first state, the drive unit 12 is turned to the first application state, and the semiconductor switching element 2 is switched from the off state to the on state.

[0064] When a predetermined time has elapsed since the timing of the first control signal switching from the second state to the first state and the third control signal switching from the second state to the first state, the switching element 33 switches from the off state to the on state. This causes the drive unit 12 to enter a second application state in which the first voltage is applied to the control terminal 2c in a lower resistance state. In this way, in the second application state in which the first voltage is applied to the control terminal 2c in a lower resistance state, the fluctuation in the voltage of the control terminal 2c is suppressed compared to the first application state in which the first voltage is applied to the control terminal 2c via the resistive element 35, and the semiconductor switching element 2 can be maintained in the on state in a more stable state.

[0065] In this way, the drive unit 12 switches the semiconductor switching element 2 from the off state to the on state by switching to the first application state in response to the switching of the first control signal from the second state to the first state, and then switches from the first application state to the second application state in response to the switching of the third control signal (the control signal after processing by the timing adjustment circuit 14) from the second state to the first state.

[0066] Thereafter, the driving unit 12 and the timing adjustment circuit 14 return to the operation at timing t1 in response to the switching of the first control signal from the first state to the second state, and repeat the same operation. This makes it possible to switch the semiconductor switching element 2 between the on state and the off state by a two-stage driving method.

[0067] Fig. 4 is a timing chart showing an example of the operation of the drive circuit according to the embodiment. More specifically, Fig. 4 shows an example of the operation of the drive circuit 10 when the current injection circuit 18 operates in response to the switching operation of the semiconductor switching element 2 from the on state to the off state. Fig. 4 shows an example of each of the voltage between the pair of main terminals 2a and 2b of the semiconductor switching element 2, the voltage of the control terminal 2c of the semiconductor switching element 2, the output signal of the negative bias detection circuit 20, the output signal of the comparator 22, the output signal of the latch circuit 24, the first control signal, and the second control signal when the semiconductor switching element 2 is switched from the on state to the off state.

[0068] When the first control signal switches from the first state to the second state, as described with reference to FIG. 3, the switching element 31 is turned off and the switching element 32 is turned on, resulting in a third application state in which the second voltage is applied to the control terminal 2c via the resistive element 35 (timing t11 in FIG. 4).

[0069] When the state where the first voltage is applied to the control terminal 2c is switched to the state where the second voltage is applied to the control terminal 2c, the voltage of the control terminal 2c gradually decreases from the first voltage to the second voltage according to the time constant associated with the resistive element 35, and the voltage between the pair of main terminals 2a, 2b gradually increases according to the voltage of the control terminal 2c. At this time, the voltage between the pair of main terminals 2a, 2b increases due to the occurrence of a surge, and there is a possibility that it may exceed the withstand voltage of the semiconductor switching element 2.

[0070] When the magnitude of the voltage between the pair of main terminals 2a, 2b becomes equal to or greater than a first set voltage set in the current injection circuit 18, the current injection circuit 18 starts injecting a current into the control terminal 2c (timing t13 in FIG. 4), thereby suppressing an increase in the voltage between the pair of main terminals 2a, 2b.

[0071] Furthermore, when the magnitude of the voltage between the pair of main terminals 2a, 2b becomes equal to or greater than the second set voltage set in the comparator 22, the comparator 22 detects an increase in the voltage between the pair of main terminals 2a, 2b equal to or greater than the second set voltage (timing t12 in FIG. 4). For example, when the magnitude of the voltage between the pair of main terminals 2a, 2b becomes equal to or greater than the second set voltage set in the comparator 22, the output signal of the comparator 22 switches from low to high. Then, when the output signal of the comparator 22 switches from low to high, for example, the output signal of the latch circuit 24 also switches from low to high.

[0072] When the voltage between the pair of main terminals 2a, 2b becomes less than the second set voltage as a result of current injection by the current injection circuit 18, the output signal of the comparator 22 switches from high to low (timing t14 in FIG. 4). On the other hand, the output signal of the latch circuit 24 remains high even after the voltage becomes less than the second set voltage. Furthermore, when the voltage between the pair of main terminals 2a, 2b becomes less than the first set voltage, the current injection circuit 18 stops injecting current into the control terminal 2c.

[0073] As described above, if the signal input from the latch circuit 24 becomes equal to or higher than the second set voltage (high state in Figure 4) before a predetermined time has elapsed from the timing of the first control signal switching from the first state to the second state, and this state of being equal to or higher than the second set voltage continues even after the predetermined time has elapsed, the timing adjustment circuit 14 delays the timing of the second control signal switching from the first state to the second state until the timing of the signal input from the latch circuit 24 switching from a state of being equal to or higher than the second set voltage to a state of being less than the second set voltage.

[0074] For example, assume that the timing of the passage of the predetermined time is between timing t12 and timing t14 in Fig. 4. If the output signal of the latch circuit 24 is in a state equal to or higher than the second set voltage (high state) at this timing, the timing adjustment circuit 14 maintains the second control signal in the first state without switching it from the first state to the second state.

[0075] Therefore, in this case, the off state of the switching element 34 is maintained, and switching to the fourth application state in which the second voltage is applied to the control terminal 2c in a lower resistance state is suppressed during operation of the current injection circuit 18. This makes it possible to suppress a decrease in the effect of the current injection circuit 18 in suppressing an increase in the voltage between the pair of main terminals 2a, 2b, caused by the current injection circuit 18 flowing to the switching element 34.

[0076] When the voltage of the control terminal 2c of the semiconductor switching element 2 drops below the negative bias detection level by the negative bias detection circuit 20 and the negative bias detection circuit 20 detects the application of a negative bias voltage to the control terminal 2c, the output signal of the latch circuit 24 switches from a state equal to or greater than the second set voltage (high state) to a state below the second set voltage (low state) (timing t15 in Figure 4).

[0077] The timing adjustment circuit 14 switches the second control signal from the first state to the second state in response to the output signal of the latch circuit 24 switching to a state below the second set voltage. This results in a fourth application state in which the second voltage is applied to the control terminal 2c in a lower resistance state, and the semiconductor switching element 2 can be maintained in the off state in a more stable state.

[0078] As described above, in the drive circuit 10 of this embodiment, when the first control signal switches from the first state to the second state and the drive unit 12 switches to the third application state, the timing adjustment circuit 14 delays the timing of switching the second control signal (processed control signal) from the first state to the second state until the semiconductor switching element 2 is in the off state if it is assumed that the semiconductor switching element 2 will be in a state between the on state and the off state even after a predetermined time has elapsed.

[0079] As a result, in the drive circuit 10 according to this embodiment, the current injection circuit 18 injects a current into the control terminal 2c, thereby suppressing an increase in voltage between the pair of main terminals 2a, 2b, and by applying a second voltage in a lower resistance state to the control terminal 2c after the semiconductor switching element 2 is switched to the off state, the semiconductor switching element 2 can be maintained in the off state in a more stable state. In this way, the drive circuit 10 according to this embodiment can simultaneously suppress a surge voltage that is equal to or greater than the withstand voltage between the pair of main terminals 2a, 2b and maintain a stable off state.

[0080] In the above embodiment, when the timing adjustment circuit 14 delays the timing of switching the second control signal from the first state to the second state, the OFF state of the semiconductor switching element 2 is detected based on the detection result of the negative bias detection circuit 20 (detection circuit), and the second control signal is switched from the first state to the second state. In other words, in the above embodiment, when the negative bias detection circuit 20 does not detect the application of a negative bias voltage to the control terminal 2c, the timing adjustment circuit 14 determines that the semiconductor switching element 2 is assumed to be in a state between the ON state and the OFF state even after a predetermined time has elapsed.

[0081] The method of detecting the off state of the semiconductor switching element 2 (the method of determining whether the semiconductor switching element 2 is expected to be in a state between the on state and the off state even after a predetermined time has elapsed) is not limited to the above.

[0082] FIG. 5 is a timing chart illustrating a modified example of the operation of the drive circuit according to the embodiment. As shown in FIG. 5, in this example, when the timing adjustment circuit 14 delays the timing of the second control signal switching from the first state to the second state, the second control signal is switched from the first state to the second state in response to a certain time having elapsed since the timing of the first control signal switching from the first state to the second state. The off state of the semiconductor switching element 2 can also be detected by the elapsed time from the timing of the first control signal switching from the first state to the second state. Therefore, as shown in FIG. 5, when the timing adjustment circuit 14 delays the timing of the second control signal switching from the first state to the second state, the second control signal may be switched from the first state to the second state in response to a certain time having elapsed since the timing of the first control signal switching from the first state to the second state.

[0083] FIG. 6 is a timing chart illustrating a modified example of the operation of the drive circuit according to the embodiment. As shown in FIG. 6, when the timing adjustment circuit 14 delays the timing of switching the second control signal from the first state to the second state, the timing adjustment circuit 14 may switch the second control signal from the first state to the second state after a certain time has elapsed since the timing at which the voltage between the pair of main terminals 2a, 2b becomes less than the second set voltage (for example, the timing at which the output signal of the comparator 22 switches from high to low).

[0084] FIG. 7 is a block diagram illustrating a modified example of the drive circuit according to the embodiment. As shown in FIG. 7, in the drive circuit 10a of this example, the negative bias detection circuit 20 is omitted, and a current detection circuit 26 is provided. The current detection circuit 26 detects the magnitude of the current flowing between the pair of main terminals 2a, 2b of the semiconductor switching element 2. The current detection circuit 26 detects, for example, whether the magnitude of the current flowing between the pair of main terminals 2a, 2b of the semiconductor switching element 2 has become equal to or less than a predetermined value. In other words, the current detection circuit 26 detects whether the semiconductor switching element 2 is in an OFF state. The predetermined value is, for example, 0 A. However, the predetermined value is not limited to 0 A, and may be any current value that can detect the OFF state of the semiconductor switching element 2.

[0085] The current detection circuit 26 inputs a detection signal representing the detection result of whether or not the magnitude of the current flowing between the pair of main terminals 2a, 2b of the semiconductor switching element 2 has become equal to or less than a predetermined value to the latch circuit 24. As in the case of the negative bias detection circuit 20, the latch circuit 24 performs processing to maintain the state of being equal to or greater than the second set voltage even after the comparison result of the comparator 22 has changed from a state of being equal to or greater than the second set voltage to a state of being less than the second set voltage until the current detection circuit 26 detects that the magnitude of the current flowing between the pair of main terminals 2a, 2b has become equal to or less than the predetermined value, and inputs the processed signal to the timing adjustment circuit 14.

[0086] As a result, in the drive circuit 10a, when the timing adjustment circuit 14 delays the timing of switching the second control signal from the first state to the second state, the drive circuit 10a switches the second control signal from the first state to the second state in response to the magnitude of the current flowing between the pair of main terminals 2a, 2b of the semiconductor switching element 2 becoming a predetermined value or less (e.g., 0 A) based on the detection result of the current detection circuit 26.

[0087] The off state of the semiconductor switching element 2 can also be detected by the magnitude of the current flowing between the pair of main terminals 2a, 2b of the semiconductor switching element 2. Therefore, as in the example shown in Fig. 7, a current detection circuit 26 that detects the magnitude of the current flowing between the pair of main terminals 2a, 2b of the semiconductor switching element 2 may be provided, and the timing adjustment circuit 14 may switch the second control signal from the first state to the second state in response to the magnitude of the current flowing through the semiconductor switching element 2 becoming equal to or less than a predetermined value based on the detection result of the current detection circuit 26 when the timing of switching the second control signal from the first state to the second state is delayed.

[0088] The method of detecting the OFF state of the semiconductor switching element 2 is not limited to the above, and any method capable of appropriately detecting the OFF state of the semiconductor switching element 2 may be used.

[0089] Furthermore, in the above embodiment, the timing adjustment circuit 14 detects the operation of the current injection circuit 18 when the drive unit 12 is in the third application state (when the second voltage is applied to the control terminal 2c via the resistive element 35) based on the detection result of the voltage detection circuit 16. More specifically, based on the detection result of the voltage detection circuit 16, it is detected that the current injection circuit 18 has operated when the output signal of the comparator 22 switches from low to high. However, the method of detecting the operation of the current injection circuit 18 is not limited to the above.

[0090] FIG. 8 is a block diagram illustrating a modified example of the drive circuit according to the embodiment. 8, the drive circuit 10b in this example further includes a current detection circuit 28. The current detection circuit 28 detects the magnitude of the current injected from the current injection circuit 18 to the control terminal 2c. The current detection circuit 28 inputs, for example, a detection result of the magnitude of the current injected from the current injection circuit 18 to the control terminal 2c to the comparator 22. In this example, the comparator 22 compares whether the magnitude of the current injected from the current injection circuit 18 to the control terminal 2c, detected by the current detection circuit 28, is equal to or greater than a predetermined threshold value.

[0091] In this example, the timing adjustment circuit 14 detects the operation of the current injection circuit 18 when the drive unit 12 is in the third application state based on the detection result of the current detection circuit 28. For example, based on the detection result of the current detection circuit 28, the timing adjustment circuit 14 detects that the current injection circuit 18 has operated when the output signal of the comparator 22 switches from low to high. In this case, too, it is possible to appropriately detect the operation of the current injection circuit 18, as in the above embodiment. In this way, the timing adjustment circuit 14 may detect the operation of the current injection circuit 18 when the drive unit 12 is in the third application state based on the detection result of the current detection circuit 28.

[0092] FIG. 9 is a block diagram illustrating a modified example of the drive circuit according to the embodiment. 9, in the driving circuit 10c of this example, the comparator 22 and the latch circuit 24 are omitted, and the output of the negative bias detection circuit 20 is input to the timing adjustment circuit 14. In this example, the timing adjustment circuit 14 detects the operation of the current injection circuit 18 when the driving unit 12 is in the third application state, based on the detection result of the negative bias detection circuit 20 that detects the magnitude of the voltage of the control terminal 2c.

[0093] The timing adjustment circuit 14 detects that the current injection circuit 18 has operated, for example, when the negative bias detection circuit 20 has not detected a negative bias voltage even after a predetermined time has elapsed since the timing of the first control signal switching from the first state to the second state. In this case, the timing adjustment circuit 14 delays the timing of the second control signal switching from the first state to the second state until the negative bias detection circuit 20 detects a negative bias voltage. In this case, as in the above embodiment, the operation of the current injection circuit 18 can be appropriately detected. In this way, the timing adjustment circuit 14 may detect the operation of the current injection circuit 18 when the drive unit 12 is in the third application state, based on the detection result of the negative bias detection circuit 20 (a detection circuit that detects the magnitude of the voltage at the control terminal 2c).

[0094] The method of detecting the operation of the current injection circuit 18 is not limited to the above, and any method capable of appropriately detecting the operation of the current injection circuit 18 may be used.

[0095] In the drive circuit 10, the negative bias detection circuit 20, the comparator 22, and the latch circuit 24 are provided as necessary and can be omitted. The configuration of the drive circuit 10 is not limited to the above, and may be any configuration that includes at least the drive unit 12, the timing adjustment circuit 14, the voltage detection circuit 16, and the current injection circuit 18 and allows the drive unit 12 and the timing adjustment circuit 14 to perform the above operations.

[0096] FIG. 10 is a block diagram showing a schematic diagram of a modified example of the drive unit. 10, in the driving section 12a of this example, the resistance element 35 is omitted, and resistance elements 41 to 44 are provided. The resistance element 41 is provided between the first input terminal 12p and the switching element 31. The resistance element 42 is provided between the switching element 32 and the second input terminal 12n. The resistance element 43 is provided between the connection point of the first input terminal 12p and the resistance element 41, and the switching element 33. The resistance element 44 is provided between the connection point of the second input terminal 12n and the resistance element 42, and the switching element 34.

[0097] The resistance value of the resistor element 43 is lower than the resistance value of the resistor element 41. The resistance value of the resistor element 44 is lower than the resistance value of the resistor element 42. As a result, in the drive unit 12a, the switching element 31 is turned on and the switching elements 32 to 34 are turned off to achieve a first application state in which the first voltage is applied to the control terminal 2c. The switching element 33 is turned on and the switching elements 31, 32, and 34 are turned off to achieve a second application state in which the first voltage is applied to the control terminal 2c with a resistance between the first input terminal 12p and the control terminal 2c lower than that in the first application state. The switching element 32 is turned on and the switching elements 31, 33, and 34 are turned off to achieve a third application state in which the second voltage is applied to the control terminal 2c. Then, by turning on the switching element 34 and turning off the switching elements 31 to 33, a fourth application state is established in which the second voltage is applied to the control terminal 2c with a lower resistance between the second input terminal 12n and the control terminal 2c than in the third application state. In this way, the drive unit 12a in this example can also appropriately switch between the first application state, the second application state, the third application state, and the fourth application state, as in the above embodiment.

[0098] FIG. 11 is a block diagram showing a schematic diagram of a modified example of the drive unit. 11, the driving unit 12b of this example further includes capacitors 46 and 48. The capacitor 46 is connected in parallel to the resistive element 42. The capacitor 48 is connected in parallel to the resistive element 44.

[0099] In this drive unit 12b, for example, when switching the switching element 32 from an OFF state to an ON state and switching the semiconductor switching element 2 from an ON state to an OFF state, the charge stored in the capacitance component between the control terminal 2c and the main terminal 2b of the semiconductor switching element 2 can be discharged to the capacitor 46, and the time required to switch the semiconductor switching element 2 from an ON state to an OFF state can be further shortened. Similarly, when switching the switching element 34 from an OFF state to an ON state and switching the semiconductor switching element 2 from an ON state to an OFF state, the charge stored in the capacitance component between the control terminal 2c and the main terminal 2b of the semiconductor switching element 2 can be discharged to the capacitor 48, and the time required to switch the semiconductor switching element 2 from an ON state to an OFF state can be further shortened.

[0100] The configuration of the drive unit is not limited to the above, and may be any configuration that can appropriately switch between the first application state, the second application state, the third application state, and the fourth application state.

[0101] The present embodiment includes the following aspects. (Appendix 1) A drive circuit for a semiconductor switching element, the drive circuit having a pair of main terminals and a control terminal, and an on state in which a current flows between the pair of main terminals, and an off state in which a current flow between the pair of main terminals is interrupted, the drive circuit switching the on state and the off state of the semiconductor switching element, a drive unit that receives an input of a control signal having a first state for setting the semiconductor switching element to the on state and a second state for setting the semiconductor switching element to the off state, the drive unit being connected to the control terminal of the semiconductor switching element, and switching the semiconductor switching element between the on state and the off state based on the control signal; a timing adjustment circuit that receives an input of the control signal, performs processing to delay, by a predetermined time, the timing of switching of the control signal from the first state to the second state and the timing of switching of the control signal from the second state to the first state, and inputs the processed control signal to the drive unit; a voltage detection circuit for detecting a voltage between the pair of main terminals of the semiconductor switching element; a current injection circuit connected to the voltage detection circuit and to the control terminal of the semiconductor switching element, which injects a current into the control terminal in accordance with a magnitude of a voltage between the pair of main terminals detected by the voltage detection circuit when the semiconductor switching element is switched from the on state to the off state, thereby slowing down a rate of change of the semiconductor switching element from the on state to the off state, thereby suppressing an increase in the voltage between the pair of main terminals above a first set voltage; Equipped with The drive unit is a first input terminal for receiving a supply of a first control power source for applying a first voltage to the control terminal, and a second input terminal for receiving a supply of a second control power source for applying a second voltage different from the first voltage to the control terminal, wherein the semiconductor switching element is set to the on state by applying the first voltage to the control terminal, and the semiconductor switching element is set to the off state by applying the second voltage to the control terminal; a first application state in which the first voltage is applied to the control terminal, a second application state in which the first voltage is applied to the control terminal in a state in which a resistance between the first input terminal and the control terminal is lower than that in the first application state, a third application state in which the second voltage is applied to the control terminal, and a fourth application state in which the second voltage is applied to the control terminal in a state in which a resistance between the second input terminal and the control terminal is lower than that in the third application state, by switching the semiconductor switching element from the on state to the off state by switching to the third application state in response to switching of the control signal from the first state to the second state, switching from the third application state to the fourth application state in response to switching of the processed control signal of the timing adjustment circuit from the first state to the second state; by switching the semiconductor switching element from the off state to the on state by switching to the first application state in response to switching of the control signal from the second state to the first state, switching from the first application state to the second application state in response to switching of the processed control signal of the timing adjustment circuit from the second state to the first state; the timing adjustment circuit is a semiconductor switching element drive circuit that delays the timing of switching the processed control signal from the first state to the second state until the semiconductor switching element reaches the off state when the semiconductor switching element is expected to be in a state between the on state and the off state even after the predetermined time has elapsed when the current injection circuit operates as a result of the control signal switching from the first state to the second state and the drive unit switching to the third application state.

[0102] (Appendix 2) a detection circuit for detecting a voltage of the control terminal of the semiconductor switching element, 2. The drive circuit for a semiconductor switching element as described in claim 1, wherein when the timing of switching of the processed control signal from the first state to the second state is delayed, the timing adjustment circuit detects the off state of the semiconductor switching element based on the detection result of the detection circuit, and switches the processed control signal from the first state to the second state.

[0103] (Appendix 3) 2. The drive circuit for a semiconductor switching element as described in claim 1, wherein, when the timing of switching of the processed control signal from the first state to the second state is delayed, the timing adjustment circuit switches the processed control signal from the first state to the second state in accordance with the elapse of a certain time from the timing of switching of the control signal from the first state to the second state.

[0104] (Appendix 4) 2. The drive circuit for a semiconductor switching element as described in claim 1, wherein the timing adjustment circuit switches the processed control signal from the first state to the second state in response to a lapse of a certain time from a time when the magnitude of the voltage between the pair of main terminals becomes less than a second set voltage that is lower than the first set voltage when the timing of switching of the processed control signal from the first state to the second state is delayed.

[0105] (Appendix 5) A current detection circuit is further provided to detect a magnitude of a current flowing between the pair of main terminals of the semiconductor switching element, 2. The drive circuit for a semiconductor switching element as described in claim 1, wherein the timing adjustment circuit switches the processed control signal from the first state to the second state in response to a magnitude of the current flowing between the pair of main terminals of the semiconductor switching element becoming equal to or less than a predetermined value based on the detection result of the current detection circuit when the timing of switching of the processed control signal from the first state to the second state is delayed.

[0106] (Appendix 6) The drive circuit for a semiconductor switching element described in any one of Appendices 1 to 5, wherein the timing adjustment circuit detects the operation of the current injection circuit when the drive unit is in the third application state based on the detection result of the voltage detection circuit.

[0107] (Appendix 7) a current detection circuit that detects the magnitude of a current injected from the current injection circuit to the control terminal; The drive circuit for a semiconductor switching element described in any one of Appendices 1 to 5, wherein the timing adjustment circuit detects the operation of the current injection circuit when the drive unit is in the third application state based on the detection result of the current detection circuit.

[0108] (Appendix 8) a detection circuit for detecting a voltage of the control terminal of the semiconductor switching element, The drive circuit for a semiconductor switching element according to any one of claims 1 to 5, wherein the timing adjustment circuit detects the operation of the current injection circuit when the drive unit is in the third application state based on the detection result of the detection circuit.

[0109] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, and are included in the scope of the invention and its equivalents described in the claims. [Explanation of symbols]

[0110] 2...semiconductor switching element, 4...rectifier element, 10, 10a to 10c...drive circuit, 12, 12a, 12b...drive unit, 14...timing adjustment circuit, 16...voltage detection circuit, 18...current injection circuit, 20...negative bias detection circuit, 22...comparator, 24...latch circuit, 26, 28...current detection circuit, 31 to 34...switching element, 35...resistance element, 41 to 44...resistance element, 46, 48...capacitor

Claims

1. A drive circuit for a semiconductor switching element, the drive circuit having a pair of main terminals and a control terminal, and an on state in which a current flows between the pair of main terminals, and an off state in which a current flow between the pair of main terminals is interrupted, the drive circuit switching the on state and the off state of the semiconductor switching element, a drive unit that receives an input of a control signal having a first state for setting the semiconductor switching element to the on state and a second state for setting the semiconductor switching element to the off state, the drive unit being connected to the control terminal of the semiconductor switching element, and switching the semiconductor switching element between the on state and the off state based on the control signal; a timing adjustment circuit that receives an input of the control signal, performs processing to delay, by a predetermined time, the timing of switching of the control signal from the first state to the second state and the timing of switching of the control signal from the second state to the first state, and inputs the processed control signal to the drive unit; a voltage detection circuit for detecting a voltage between the pair of main terminals of the semiconductor switching element; a current injection circuit connected to the voltage detection circuit and to the control terminal of the semiconductor switching element, which injects a current into the control terminal in accordance with a magnitude of a voltage between the pair of main terminals detected by the voltage detection circuit when the semiconductor switching element is switched from the on state to the off state, thereby slowing down a rate of change of the semiconductor switching element from the on state to the off state, thereby suppressing an increase in the voltage between the pair of main terminals above a first set voltage; Equipped with The drive unit is a first input terminal for receiving a supply of a first control power source for applying a first voltage to the control terminal, and a second input terminal for receiving a supply of a second control power source for applying a second voltage different from the first voltage to the control terminal, wherein the semiconductor switching element is set to the on state by applying the first voltage to the control terminal, and the semiconductor switching element is set to the off state by applying the second voltage to the control terminal; a first application state in which the first voltage is applied to the control terminal, a second application state in which the first voltage is applied to the control terminal in a state in which a resistance between the first input terminal and the control terminal is lower than that in the first application state, a third application state in which the second voltage is applied to the control terminal, and a fourth application state in which the second voltage is applied to the control terminal in a state in which a resistance between the second input terminal and the control terminal is lower than that in the third application state, by switching the semiconductor switching element from the on state to the off state by switching to the third application state in response to switching of the control signal from the first state to the second state, switching from the third application state to the fourth application state in response to switching of the processed control signal of the timing adjustment circuit from the first state to the second state; by switching the semiconductor switching element from the off state to the on state by switching to the first application state in response to switching of the control signal from the second state to the first state, switching from the first application state to the second application state in response to switching of the processed control signal of the timing adjustment circuit from the second state to the first state; The timing adjustment circuit is a semiconductor switching element drive circuit that delays the timing of switching the processed control signal from the first state to the second state until the semiconductor switching element reaches the off state when the semiconductor switching element is assumed to be in a state between the on state and the off state even after the specified time has elapsed when the current injection circuit operates as a result of the control signal switching from the first state to the second state and the drive unit switching to the third application state.

2. a detection circuit for detecting a voltage of the control terminal of the semiconductor switching element, 2. The semiconductor switching element drive circuit of claim 1, wherein when the timing of switching of the processed control signal from the first state to the second state is delayed, the timing adjustment circuit detects the off state of the semiconductor switching element based on the detection result of the detection circuit, and switches the processed control signal from the first state to the second state.

3. 2. The semiconductor switching element drive circuit of claim 1, wherein when the timing of the switching of the processed control signal from the first state to the second state is delayed, the timing adjustment circuit switches the processed control signal from the first state to the second state in response to a lapse of a certain time from the timing of the switching of the control signal from the first state to the second state.

4. 2. The drive circuit for a semiconductor switching element according to claim 1, wherein the timing adjustment circuit switches the processed control signal from the first state to the second state in response to a lapse of a certain time from a time when the magnitude of the voltage between the pair of main terminals becomes less than a second set voltage that is lower than the first set voltage, when the timing of switching of the processed control signal from the first state to the second state is delayed.

5. A current detection circuit is further provided to detect a magnitude of a current flowing between the pair of main terminals of the semiconductor switching element, 2. The drive circuit for a semiconductor switching element according to claim 1, wherein when the timing of switching of the processed control signal from the first state to the second state is delayed, the timing adjustment circuit switches the processed control signal from the first state to the second state in response to a magnitude of the current flowing between the pair of main terminals of the semiconductor switching element becoming equal to or less than a predetermined value based on the detection result of the current detection circuit.

6. 2. The semiconductor switching element drive circuit according to claim 1, wherein the timing adjustment circuit detects the operation of the current injection circuit when the drive unit is in the third application state based on the detection result of the voltage detection circuit.

7. a current detection circuit that detects the magnitude of a current injected from the current injection circuit to the control terminal; 2. The drive circuit for a semiconductor switching element according to claim 1, wherein the timing adjustment circuit detects an operation of the current injection circuit when the drive section is in the third application state based on a detection result of the current detection circuit.

8. a detection circuit for detecting a voltage of the control terminal of the semiconductor switching element, 2. The drive circuit for a semiconductor switching element according to claim 1, wherein the timing adjustment circuit detects the operation of the current injection circuit when the drive section is in the third application state based on the detection result of the detection circuit.

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