Semiconductor package and method of manufacturing the same

Abstract

To provide: a semiconductor package having simplified processes and improved reliability; and a method of manufacturing the same.SOLUTION: A semiconductor package includes: a first semiconductor chip that includes first pads; a second semiconductor chip arranged on a front surface facing the first semiconductor chip, and including second pads in contact with the first pads, and through-electrodes electrically connected to the second pads and extending to a rear surface opposite to the front surface; a dielectric layer 320 that covers at least portions of the respective first and second semiconductor chips, and includes an inner surface facing the first and second semiconductor chips and an outer surface that is opposite the inner surface; and bump structures arranged on a portion of the outer surface off the dielectric layer, and electrically coupled to the through-electrodes. The dielectric layer includes inorganic particles 321, and polymer chains 322 bonded to at least one sides of the respective inorganic particles, and coupled toward the inner surface and the outer surface via the inorganic particles as media.SELECTED DRAWING: Figure 2a

Description

[Technical field]

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same. [Background technology]

[0002] Semiconductor devices mounted in electronic devices are required to be compact, high performance, and large capacity. To achieve this, semiconductor packages that interconnect vertically stacked semiconductor chips using through electrodes (e.g., through silicon vias) are being developed. Summary of the Invention [Problem to be solved by the invention]

[0003] One of the problems to be solved by the present invention is to provide a semiconductor package and a manufacturing method thereof, which have simplified processes and improved reliability. [Means for solving the problem]

[0004] As a means for solving the above-mentioned problems, an exemplary embodiment of the present invention provides a semiconductor package including: a first semiconductor chip including a first pad; a second semiconductor chip arranged on a front surface facing the first semiconductor chip, a second pad in contact with the first pad, and a through electrode electrically connected to the second pad and extending to a back surface opposite the front surface; a dielectric layer covering at least a portion of each of the first and second semiconductor chips, and having an inner surface facing the first and second semiconductor chips and an outer surface opposite the inner surface; and a bump structure arranged on a portion of the outer surface of the dielectric layer and electrically connected to the through electrode, wherein the dielectric layer includes inorganic particles and polymer chains bonded to at least one side of each of the inorganic particles and connected toward the inner surface and the outer surface via the inorganic particles.

[0005] An exemplary embodiment of the present invention provides a semiconductor package including: a first semiconductor chip including a first pad; a second semiconductor chip disposed under the first semiconductor chip including a second pad in contact with the first pad and a through electrode electrically connected to the second pad; a dielectric layer covering at least a portion of each of the first semiconductor chip and the second semiconductor chip; and a bump structure disposed under the second semiconductor chip and electrically connected to the through electrode, wherein the dielectric layer is a nanocomposite in which inorganic particles and polymer chains are bonded.

[0006] An exemplary embodiment of the present invention provides a semiconductor package including: a first semiconductor chip including a first pad; a second semiconductor chip disposed below the first semiconductor chip including a second pad in contact with the first pad and a through electrode electrically connected to the second pad; a dielectric layer disposed below the first semiconductor chip and surrounding a side surface of the second semiconductor chip and a portion of the through electrode protruding to a back surface of the second semiconductor chip; and a bump structure disposed below the second semiconductor chip and electrically connected to the through electrode, wherein the dielectric layer includes polymer chains interconnected via inorganic particles.

[0007] An exemplary embodiment of the present invention provides a method for manufacturing a semiconductor package, the method including: preparing a semiconductor wafer including a first pad; attaching a spare semiconductor chip including a second pad disposed on a front side thereof and a plurality of spare through electrodes embedded in a spare substrate to the semiconductor wafer; etching the spare substrate so that at least a portion of each of the plurality of spare through electrodes is exposed on a back side of the spare semiconductor chip; forming a spare dielectric layer covering the back side of the spare semiconductor chip and at least a portion of each of the plurality of spare through electrodes exposed from the spare substrate - the spare dielectric layer is formed by a spin coating process - polishing the spare dielectric layer and the plurality of spare through electrodes - forming a flat surface consisting of a dielectric layer and a plurality of through electrodes - and forming a bump structure on the flat surface. Effect of the Invention

[0008] According to an embodiment of the present invention, by introducing a dielectric layer including a nanocomposite, a semiconductor package and a method for manufacturing the same can be provided with simplified processes and improved reliability.

[0009] The various and beneficial advantages and effects of the present invention are not limited to the above, but can be more easily understood in the course of describing specific embodiments of the present invention. [Brief description of the drawings]

[0010] [Figure 1a] 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. [Figure 1b] FIG. 1b is a plan view showing a cross section taken along line II' in FIG. [Figure 2a] FIG. 2 is a diagram illustrating a dielectric layer of an exemplary embodiment. [Figure 2b] FIG. 2 is a diagram illustrating a dielectric layer of an exemplary embodiment. [Figure 2c] 1 is a graph illustrating the thermal conduction properties of a nanocomposite. [Figure 3a] FIG. 1 illustrates the self-healing properties of a dielectric layer of an exemplary embodiment. [Figure 3b] FIG. 1 illustrates the self-healing properties of a dielectric layer of an exemplary embodiment. [Figure 3c] FIG. 1 illustrates the self-healing properties of a dielectric layer of an exemplary embodiment. [Figure 4a] 1B is a cross-sectional view showing a method for manufacturing the semiconductor package shown in FIG. 1A in the order of steps. [Figure 4b] 1B is a cross-sectional view showing a method for manufacturing the semiconductor package shown in FIG. 1A in the order of steps. [Figure 4c] 1B is a cross-sectional view showing a method for manufacturing the semiconductor package shown in FIG. 1A in the order of steps. [Figure 4d]1B is a cross-sectional view showing a method for manufacturing the semiconductor package shown in FIG. 1A in the order of steps. [Figure 4e] 1B is a cross-sectional view showing a method for manufacturing the semiconductor package shown in FIG. 1A in the order of steps. [Diagram 5] 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. [Figure 6] 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. [Figure 7] 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. [Figure 8] 1 is a cross-sectional view of a semiconductor package according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Unless otherwise specified, the terms "upper", "upper surface", "lower surface", "side surface", and the like in this specification are based on the drawings and may vary depending on the direction in which components are actually arranged.

[0012] Also, ordinal numbers such as "first," "second," "third," etc. may be used as labels of particular elements, stages, directions, etc. to distinguish various elements, stages, directions, etc. from one another. Terms not described herein with "first," "second," etc. may still be referred to as "first" or "second" in the claims. Furthermore, a term referred to by a particular ordinal number (e.g., "first" in a particular claim) may be described elsewhere as another ordinal number (e.g., "second" in the specification or other claims).

[0013] FIG. 1a is a cross-sectional view showing a semiconductor package 10A according to an exemplary embodiment of the present invention, and FIG. 1b is a plan view showing a cross section taken along line II' in FIG. 1a.

[0014] 1a and 1b, a semiconductor package 10A according to an embodiment may include a first semiconductor chip 100, a second semiconductor chip 200, and a dielectric layer 320. According to an embodiment, the semiconductor package 10A may further include a bump structure 412.

[0015] In the present invention, the active surface of the first semiconductor chip 100 and the active surface of the second semiconductor chip 200 are bonded to each other to minimize the signal transmission path between the first semiconductor chip 100 and the second semiconductor chip 200. The first semiconductor chip 100 and the second semiconductor chip 200 may be logic chips including a central processor (CPU), a graphic processor (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, or memory chips including a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM and flash memory), or the like. As an example, the first semiconductor chip 100 may include a logic circuit such as an application specific semiconductor (ASIC), and the second semiconductor chip 200 may include a cache memory circuit that provides cache information to the first semiconductor chip 100. The size of the second semiconductor chip 200 may be smaller than the size of the first semiconductor chip 100. For example, the width of the first semiconductor chip 100 may be larger than the width of the second semiconductor chip 200.

[0016] Furthermore, the first semiconductor chip 100 and the second semiconductor chip 200 may be directly bonded and joined without a separate connecting member (e.g., solder bumps, copper posts, etc.) Such a structure may be called hybrid bonding consisting of metal bonding through pads bonded to each other and dielectric bonding through insulating layers bonded to each other, or direct bonding.

[0017] Also, the dielectric layer 320 of the exemplary embodiment may be a nanocomposite including inorganic particles and polymer chains. According to the exemplary embodiment, the dielectric layer 320 is formed using a polymer solution to which inorganic particles for forming a nanocomposite are added, thereby reducing the process difficulty and the turn around time (TAT) (see FIG. 4c). The dielectric layer 320 includes inorganic particles connecting the polymer chains, and thus may have improved thermal conductivity characteristics compared to polymer resins that can be subjected to a spin coating process. Furthermore, the dielectric layer 320 made of a nanocomposite has self-healing properties against cracks, thereby improving the reliability of the semiconductor package 10A.

[0018] Each component of the semiconductor device 10A according to the exemplary embodiment will be described in detail below.

[0019] The first semiconductor chip 100 may include a first substrate 110, a first circuit layer 120, a first insulating layer 131, and a first pad 132 (or a "first bonding layer 130"). The first semiconductor chip 100 may have a flat underside provided by the first insulating layer 131 and the first pad 132.

[0020] The first substrate 110 may be a semiconductor wafer including a semiconductor element such as silicon or germanium, or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The first substrate 110 may have an active surface (e.g., a surface facing the first circuit layer 120) having an active region doped with impurities, and an opposite non-active surface.

[0021] The first circuit layer 120 may be disposed on the active surface of the first substrate 110. The first circuit layer 120 may include an integrated circuit including individual elements (not shown) formed on the active surface of the first substrate 110 and a wiring structure (not shown) electrically connecting the individual elements (not shown) to the first pads 132. The individual elements (not shown) may include various active and / or passive elements such as FETs such as planar FETs and FinFETs, memory elements such as flash memories, DRAMs, SRAMs, EEPROMs, PRAMs, MRAMs, FeRAMs, and RRAMs, logic elements such as ANDs, ORs, and NOTs, system LSIs, CISs, and MEMS. The wiring structure (not shown) may be formed in a multi-layer structure including wiring patterns and vias made of, for example, aluminum (Al), gold (Au), cobalt (Co), copper (Cu), nickel (Ni), lead (Pb), tantalum (Ta), tellurium (Te), titanium (Ti), tungsten (W), or a combination thereof.

[0022] The first insulating layer 131 may be disposed under the first circuit layer 120 and may be formed to surround the first pad 132. The first insulating layer 131 may include at least one of a material capable of being bonded to and bonded with the second insulating layer 231 of the second semiconductor chip 200, for example, silicon oxide (SiO), silicon nitride (SiN), and silicon carbonitride (SiCN). That is, at least a portion of the first insulating layer 131 may be bonded to the second insulating layer 231 to form a bonding surface between the first semiconductor chip 100 and the second semiconductor chip 200.

[0023] The first pad 132 may be a connection terminal electrically connected to the integrated circuit of the first circuit layer 120. The first pad 132 may be connected to the second pad 232 of the second semiconductor chip 200. The first pad 132 may include any one of copper (Cu), nickel (Ni), titanium (Ti), aluminum (Al), gold (Au), and silver (Ag), or an alloy thereof. The first pad 132 may form a bonding surface between the first semiconductor chip 100 and the second semiconductor chip 200 together with the first insulating layer 131. A barrier layer including at least one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) may be formed between the first insulating layer 131 and the first pad 132.

[0024] The second semiconductor chip 200 may include a second substrate 210, a second circuit layer 220, a second insulating layer 231, a second pad 232 (or a "second bonding layer 230"), and a through electrode 240. The second semiconductor chip 200 may have a flat upper surface provided by the second insulating layer 231 and the second pad 232 and in contact with the lower surface of the first semiconductor chip 100. According to an embodiment, the second semiconductor chip 200 may be provided in a smaller or larger number than those shown in the figure. For example, the second semiconductor chip 200 may be provided as two or more semiconductor chips horizontally arranged under the first semiconductor chip 100. According to an embodiment, the second semiconductor chip 200 may be provided as a plurality of semiconductor chips stacked vertically (Z-axis direction) under the first semiconductor chip 100.

[0025] The second semiconductor chip 200 may have a structure that is substantially the same as or similar to the first semiconductor chip 100, and therefore the same or similar components are denoted by the same or similar reference numerals, and the same components will not be described again. For example, the second substrate 210 and the second circuit layer 220 have the same or similar features as the first substrate 110 and the first circuit layer 120 described above, and therefore the corresponding components are denoted by similar reference numerals, and the same description will not be described again.

[0026] The second insulating layer 231 may be disposed on the second circuit layer 220 and may be formed to surround the second pad 232. The second insulating layer 231 may include at least one of a material capable of being bonded to the first insulating layer 131, such as silicon oxide (SiO), silicon nitride (SiN), and silicon carbonitride (SiCN).

[0027] The second pad 232 may be a connection terminal disposed on the front surface S1 facing the first semiconductor chip 100 and electrically connected to an integrated circuit of the second circuit layer 220. The second pad 232 may form a bonding surface between the first semiconductor chip 100 and the second semiconductor chip 200 together with the second insulating layer 231. The second pad 232 may include any one of copper (Cu), nickel (Ni), titanium (Ti), aluminum (Al), gold (Au), silver (Ag), or an alloy thereof. For example, the second pad 232 may be bonded and coupled to the first pad 132.

[0028] The through electrode 240 may be electrically connected to the second pad 232 and extend to a rear surface S2 opposite to the front surface S1. The through electrode 240 may protrude through the second substrate 210 to the rear surface S2 of the second substrate 210. The through electrode 240 may be electrically connected to the bump structure 412. The through electrode 240 may include a via plug and a side barrier film (not shown) surrounding a side of the via plug. The via plug may include, for example, tungsten (W), titanium (Ti), aluminum (Al), or copper (Cu), and may be formed by a plating process, a PVD process, or a CVD process. The side barrier film may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN), and may be formed by a plating process, a PVD process, or a CVD process. A side insulating film (not shown) including an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride (e.g., HARP (High Aspect Ratio Process) oxide) may be formed between the through electrode 240 and the second substrate 210.

[0029] The dielectric layer 320 may be formed to cover at least a portion of each of the first semiconductor chip 100 and the second semiconductor chip 200. The dielectric layer 320 may have an inner surface 320S1 facing the first semiconductor chip 100 and the second semiconductor chip 200 and an outer surface 320S2 opposite to the inner surface 320S1. In an exemplary embodiment, the dielectric layer 320 may be formed to surround a side surface of the second semiconductor chip 200 and a portion of the through electrode 240 protruding to the rear surface S2 of the second semiconductor chip 200. The dielectric layer 320 may include a nanocomposite having improved thermal properties and self-healing properties. This will be described in detail with reference to FIGS. 2a to 2c and 3a to 3c.

[0030] The bump structure 412 may be disposed under the second semiconductor chip 200 and electrically connected to the through-electrode 240. The bump structure 240 may be disposed on a portion of the outer surface 320S2 of the dielectric layer 320, for example, on the lower surface of the dielectric layer 320.

[0031] The semiconductor package 10A may be connected to an external device such as a module substrate or a main board through the bump structure 412. As an example, the bump structure 412 may include a pillar portion 412P and a solder portion 412S. The pillar portion 412P may include copper (Cu) or an alloy of copper (Cu), and the solder portion 412S may include a low melting point metal, for example, tin (Sn) or an alloy including tin (Sn) (Sn-Ag-Cu). According to an exemplary embodiment, the bump structure 412 may include only the pillar portion 412P or only the solder portion 412S. A protective layer 411 surrounding the bump structure 412 may be formed under the dielectric layer 320. The protective layer 411 may protect the bump structure 412 from external physical / chemical damage. The protective layer 411 may be formed using prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo-Imageable Dielectric (PID), photo solder resist, etc. According to the embodiment, the protective layer 411 may be formed in a form covering the lower surface of the pillar portion 412P or may be omitted.

[0032] An exemplary embodiment of the dielectric layer 320 will now be described with reference to Figures 2a-2c and 3a-3c in combination.

[0033] 2a-b are diagrams illustrating the dielectric layer 320 of an exemplary embodiment, and FIG. 2c is a graph illustrating the thermal conductivity properties of the nanocomposite.

[0034] 3a-3c are diagrams illustrating the self-healing properties of the dielectric layer 320 of the exemplary embodiment.

[0035] 2a and 2b, the dielectric layer 320 may be a nanocomposite in which inorganic particles 321 and polymer chains 322 are bonded together. For example, the nanocomposite may be manufactured by adding inorganic particles 321 to a polymer solution in which polymer chains 322 are dissolved. The "polymer solution" may include a polymer resin, a solvent, a reaction initiator, a dispersant for inorganic particles 321, and the like. The polymer resin may include, for example, polyimide, benzocyclobutene, polyhydroxystyrene, polybenzoxazoles, epoxy series, and the like. The solvent may include an organic solvent capable of dissolving the polymer resin. The reaction initiator may include a photoinitiator, a thermalinitiator, and the like. The content of inorganic particles 321 added to the "polymer solution" may be adjusted according to the physical properties of the nanocomposite. For example, the inorganic particles 321 may be added in a content ranging from about 0.1 wt % to about 50 wt %, but is not limited thereto.

[0036] The inorganic particles 321 and the polymer chains 322 can be physically and / or chemically bonded to each other. At least one side of each of the inorganic particles 321 has a negative polarity (δ - ), and the polymer chain 322 can be physically bonded to the at least one side of the inorganic particle 321. For example, the polymer chain 322 can have a negative polarity (δ - ) may be connected face-to-face. The polymer chains 322 may be aligned via the inorganic particles 321. The polymer chains 322 may be connected towards the inner surface 320S1 and the outer surface 320S2 of the dielectric layer 320 via the inorganic particles 321. The polymer chains 322 aligned via the inorganic particles 321 may provide a heat conduction path, thereby improving the heat dissipation characteristics of the dielectric layer 320.

[0037] The inorganic particles 321 are, for example, aluminum nitride (AlN), aluminum oxide (Al 2 O 3 ), silicon carbide (SiC), silicon nitride (Si 3 N 4 The silicate may include at least one of smectite-based materials selected from the group consisting of montmorillonite, nontronite, beidellite, volkonskoite, hectorite, saponite, laponite, sauconite, magadiite, and kenyaite; vermiculite-based materials; illite-based materials; and derivatives thereof.

[0038] The polymer chain 322 may include at least one of epoxy, polyimide (PI), benzocyclobutene (BCB), polyhydroxy styrene (PHS), polyhydroxyalkanoate (PHB), and polybenzoxazole, but is not limited thereto. The polymer chain 322 may include a functional group R that physically bonds with the inorganic particle 321. For example, the functional group R may be connected to the inorganic particle 321 by a hydrogen bond (HB). The functional group R may include at least one of nitrogen (N), oxygen (O), and fluorine (F). The functional group R may include, for example, an amine group, a hydroxyl group, a carboxylic group, an amide group, or the like.

[0039] The dielectric layer 320 of the exemplary embodiment may have improved thermal conductivity properties by including inorganic particles 321 that align the polymer chains 322 .

[0040] Figure 2c shows the thermal conductivity of nanocomposites composed of polymer resin and inorganic particles. "G1" shows the change in thermal conductivity depending on the content of silicon carbide (SiC) in nanocomposites composed of polystyrene and SiC. "G2" shows the change in thermal conductivity depending on the content of boron nitride (BN) in nanocomposites composed of epoxy and BN. "G3" shows the change in thermal conductivity depending on the content of polyethylene and aluminum oxide (Al). 2 O 3 Nanocomposite aluminum oxide (Al 2 O 3 "G4" shows the change in thermal conductivity of a nanocomposite made of polystyrene and aluminum nitride (AlN) depending on the content of AlN.

[0041] Referring to FIG. 2c, it can be seen that the thermal conductivity of the nanocomposite increases as the content of inorganic particles increases. Although the graph of FIG. 2c does not show an experimental example for the entire inorganic particles 321 described above, it can be predicted from this that the dielectric layer 320 (or "nanocomposite") of the exemplary embodiment has a thermal conductivity greater than that of a material containing only the polymer chains 322 described above. For example, the thermal conductivity of a material consisting of only the polymer chains 322 is about 0.2 W / mK or less, and the thermal conductivity of the dielectric layer 320 of the exemplary embodiment may be about 0.4 W / mK or more. For example, the thermal conductivity of the dielectric layer 320 may be in the range of about 0.4 W / mK to about 1.3 W / mK, about 0.4 W / mK to about 1.2 W / mK, about 0.4 W / mK to about 1.0 W / mK, etc., but is not limited thereto.

[0042] The dielectric layer 320 of the exemplary embodiment may have self-healing properties whereby broken polymer chains 322 rebond to adjacent inorganic particles 321 .

[0043] 3a to 3c show the process in which the cut polymer chains 322' are re-bonded to the inorganic particles 321a and 321b.

[0044] 3a, at least some of the polymer chains 322' constituting the dielectric layer 320 may be cut. The cut polymer chains 322' may have a first end T1 and a second end T2 spaced apart from each other.

[0045] 3b, the cut polymer chain 322' may diffuse toward the adjacent inorganic particles 321a, 321b. For example, the first end T1 of the cut polymer chain 322' may diffuse toward the adjacent first inorganic particle 321a. The second end T2 of the cut polymer chain 322' may diffuse toward the adjacent second inorganic particle 321b.

[0046] Referring to FIG. 3c, the cut polymer chain 322′ has a negative polarity (δ - ) to the adjacent inorganic particles 321a, 321b. For example, the first end T1 of the cut polymer chain 322' can be rebonded (HB') to the first inorganic particle 321a. The second end T2 of the cut polymer chain 322' can be rebonded (HB') to the second inorganic particle 321b. The cut polymer chain 322' and the adjacent inorganic particles 321a, 321b can be rebonded by hydrogen bonding.

[0047] 4a to 4e are cross-sectional views showing a method for manufacturing the semiconductor package 10A shown in FIG. 1a in the order of steps.

[0048] 4a, a semiconductor wafer 100W for a first semiconductor chip 100 may be prepared. The semiconductor wafer 100W may include a plurality of first semiconductor chips 100 separated by scribe lines SL. The semiconductor wafer 100W may include a first circuit layer 120 for the first semiconductor chip 100 and a first bonding layer 130 formed on a first substrate 110. The first bonding layer 130 may include a first insulating layer 131 and a first pad 132. The semiconductor wafer 100W may be disposed on a carrier CR such that a first active surface AS1 on which the first pads 132 are disposed faces the top.

[0049] Next, the spare semiconductor chip 200p may be attached to the semiconductor wafer 100W. The spare semiconductor chip 200p may include a spare substrate 210p before the thickness is adjusted by the backgrinding process, a second circuit layer 220 and a second bonding layer 230 disposed on the front surface of the spare substrate 210p, and a plurality of spare through electrodes 240p embedded in the spare substrate 210p. The spare semiconductor chip 200p may be disposed on the semiconductor wafer 100W such that the second active surface AS2 on which the second pads 232 are disposed faces downward. The spare semiconductor chip 200p may be disposed such that the second active surface AS2 contacts the first active surface AS1.

[0050] Then, a thermal compression process may be performed to bond the first semiconductor chip 100 and the spare semiconductor chip 200p. The thermal compression process may be performed in a thermal atmosphere ranging from about 100° C. to about 300° C. However, the temperature of the thermal atmosphere is not limited to the above range and may be various temperatures.

[0051] 4b, the preliminary substrate 210p may be etched so that at least a portion of each of the preliminary through electrodes 240p is exposed on the rear surface S2 of the preliminary semiconductor chip 200p. A back-grinding process and an etch-back process may be applied to the preliminary substrate 210p to form a substrate 210 having a desired thickness. For example, the preliminary substrate 210p may be reduced to a certain thickness by performing a back-grinding process, and the preliminary through electrodes 240p may be sufficiently exposed by applying an etch-back process under appropriate conditions.

[0052] Referring to FIG. 4c, a preliminary dielectric layer 320p may be formed to cover the preliminary semiconductor chip 200p. The preliminary dielectric layer 320p may cover the rear surface S2 of the preliminary semiconductor chip 200p and each of the preliminary through electrodes 240 exposed from the preliminary substrate 210p. The preliminary dielectric layer 320p may be formed by applying a polymer solution using a spin coating process and then curing the polymer solution. When the polymer solution is cured, a polymer chain may be bonded to the inorganic particles added to the polymer solution to form a nanocomposite. Thus, the preliminary dielectric layer 320p may include inorganic particles and polymer chains bonded to at least one side of each of the inorganic particles and aligned throughout the thickness of the preliminary dielectric layer 320p via the inorganic particles (see FIGS. 2a and 2b).

[0053] 4d, a polishing process may be applied to the preliminary dielectric layer 320p and the preliminary through electrodes 240p to form a flat surface of the dielectric layer 320 and the plurality of through electrodes 240. The polishing process may include a chemical mechanical polishing (CMP) process. The dielectric layer 320 may have an inner surface 320S1 that contacts the semiconductor wafer 100W and the preliminary semiconductor chip 200p and an outer surface 320S2 that is exposed at the top. The outer surface 320S2 of the dielectric layer 320 and the upper surfaces of the plurality of through electrodes 240 may be substantially coplanar.

[0054] 4e, a protective layer 411 and a bump structure 412 may be sequentially formed on the flat surface formed by the polishing process. The protective layer 411 may be formed using a photosensitive resin such as PID or PSR. The bump structure 412 may include a pillar portion 412P and a solder portion 412S. Then, a cutting process may be performed along a scribe line SL to separate the semiconductor packages.

[0055] FIG. 5 is a cross-sectional view showing a semiconductor package 10B according to an exemplary embodiment of the present invention.

[0056] Referring to FIG. 5, the exemplary embodiment semiconductor package 10B may have the same or similar features as those described with reference to FIGS. 1a to 4e, except that it further includes a through via structure 330 penetrating the dielectric layer 320.

[0057] The through via structure 330 may be disposed on the periphery of the second semiconductor chip 200 and electrically connected to the first semiconductor chip 100. For example, the second pad 232 of the second semiconductor chip 200 may be connected to the first inner pad 132a of the first semiconductor chip 100, and the through via structure 330 may be connected to the first outer pad 132b of the first semiconductor chip 100. The first inner pad 132a may include a signal pad, and the first outer pad 132b may include a power and / or ground pad, but is not limited thereto. According to an exemplary embodiment, the through via structure 330 may have a width greater than the width of the through electrode 240, but is not limited thereto.

[0058] The through via structure 330 may be electrically connected to at least a portion of the bump structure 240 located at a portion that does not vertically overlap the second semiconductor chip 200. The through via structure 330 may include any one of copper (Cu), nickel (Ni), titanium (Ti), aluminum (Al), gold (Au), and silver (Ag), or an alloy thereof.

[0059] FIG. 6 is a cross-sectional view showing a semiconductor package 10C according to an exemplary embodiment of the present invention.

[0060] 6, the semiconductor package 10C of the exemplary embodiment may have the same or similar features as those described with reference to FIGS. 1A to 5, except that the semiconductor package 10C further includes a redistribution structure 510 that redistributes the through electrodes 240. The redistribution structure 510 is disposed under the dielectric layer 320 and may include an insulating material layer 511, a redistribution pattern layer 512, and a redistribution via 513.

[0061] The redistribution pattern layer 512 of the present embodiment may be disposed directly on the lower surface of the dielectric layer 320. For example, the redistribution pattern layer 512 may include an upper pattern layer that is directly in contact with the dielectric layer 320 and embedded in the insulating material layer 511, and a lower pattern layer that is disposed under the insulating material layer 511. In this case, the redistribution via 513 may extend vertically in the insulating material layer 511 to connect the lower pattern layer and the upper pattern layer. In this manner, by introducing the redistribution structure 510, the layout of the bump structure 412 may be designed in various ways.

[0062] The insulating material layer 511 may be formed using a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or a photosensitive resin such as PID. The insulating material layer 511 may be formed in a plurality of layers depending on the number of layers of the redistribution pattern layer 512. Depending on the process, the boundaries between at least some of the layers of the insulating material layers 511 may not be clear. According to an exemplary embodiment, the pillar portion 412P of the bump structure 412 may be exposed from the insulating material layer 511, and a protection layer ("411" in FIG. 1a) for protecting the bump structure 412 may be formed under the redistribution structure 510.

[0063] The redistribution pattern layer 512 may electrically connect the bump structure 412 and the through electrode 240. The redistribution pattern layer 512 may include a metal material including, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The redistribution pattern layer 512 may include, for example, a ground pattern, a power pattern, and a signal pattern. The signal pattern may transmit data signals transmitted from the first semiconductor chip 100 and the second semiconductor chip 200 to the outside, or transmit data signals transmitted from the outside to the first semiconductor chip 100 and the second semiconductor chip 200. The redistribution pattern layer 512 may be formed with more or less layers than those shown in the figure (three layers).

[0064] The redistribution vias 513 may extend vertically within the insulating material layer 511 and be connected to the redistribution pattern layer 512. The redistribution vias 513 may have the form of a filled via in which a metal material is filled inside a via hole, or a conformal via in which a metal material is formed along the inner wall of a via hole. The redistribution vias 513 may be integrated with the redistribution pattern layer 512, but the embodiment of the present invention is not limited thereto. The redistribution vias 513 may be formed in more layers than those shown in the figure, corresponding to the redistribution pattern layer 512.

[0065] FIG. 7 is a cross-sectional view illustrating a semiconductor package 10D according to an exemplary embodiment of the invention.

[0066] 7, the semiconductor package 10D of the exemplary embodiment may have the same or similar features as those described with reference to FIG. 6, except that the uppermost redistribution pattern layer 512 is spaced apart from the dielectric layer 320. The redistribution structure 510 of the present embodiment may include an insulating material layer 511 disposed directly on the lower surface of the dielectric layer 320, a redistribution pattern layer 512 disposed under the insulating material layer 511, and a redistribution via 513 connected to the redistribution pattern layer 512 and the through electrode 240 in the insulating material layer 511. By spaced apart the dielectric layer 320 and the uppermost redistribution layer 512 in this manner, the adhesion of the redistribution pattern layer 512 can be ensured, and the redistribution pattern layer 512 can be realized with a fine pitch.

[0067] FIG. 8 is a cross-sectional view illustrating a semiconductor package 10E according to an exemplary embodiment of the invention.

[0068] 8, a semiconductor package 10E according to an embodiment may include a bonding structure (BS), a wiring substrate 600, and a heat dissipation structure 630. The bonding structure (BS) may include a first semiconductor chip 100, a second semiconductor chip 200, a dielectric layer 320, etc., and may have the same or similar features as those described with reference to FIGS.

[0069] The wiring board 600 is a support board on which a bonding structure (BS) is mounted, and may be a substrate for semiconductor packages, such as a printed circuit board (PCB), a ceramic board, or a tape wiring board. The wiring board 600 may include a lower pad 612, an upper pad 611, and a wiring circuit 613 that electrically connects the lower pad 612 and the upper pad 611. The main body of the wiring board 600 may include different materials depending on the type of board. For example, when the wiring board 600 is a printed circuit board, the main body may be a copper foil laminate or a wiring layer may be further laminated on a cross section or both sides of the copper foil laminate. The upper pad 611, the lower pad 612, and the rewiring circuit 613 may form an electrical path that connects the lower surface and the upper surface of the wiring board 600. An external connection bump 620 connected to the lower pad 612 may be disposed on the lower surface of the wiring board 600. The external connection bumps 620 may include tin (Sn), indium (In), bismuth (Bi), antimony (Sb), copper (Cu), silver (Ag), zinc (Zn), lead (Pb), and / or alloys thereof.

[0070] The heat dissipation structure 630 may be disposed to cover the upper part of the bonding structure (BS). The heat dissipation structure 630 may be attached to the wiring board 600 by an adhesive (not shown). The adhesive may be a thermally conductive adhesive tape, a thermally conductive grease, a thermally conductive adhesive, or the like. The heat dissipation structure 630 may be attached to the upper part of the bonding structure (BS) via a thermal transfer material layer 631. The thermal transfer material layer 631 may include, for example, a thermally conductive adhesive tape, a thermally conductive grease, a thermally conductive adhesive, or the like.

[0071] The heat dissipation structure 630 may include a conductive material having excellent thermal conductivity. For example, the heat dissipation structure 630 may include a metal or metal alloy including gold (Au), silver (Ag), copper (Cu), iron (Fe), etc., or a conductive material such as graphite, graphene, etc. The heat dissipation structure 630 may have a shape different from that shown in the figure. For example, it may have a shape that covers only the upper surface of the bonding structure (BS).

[0072] The present invention is not limited by the above-described embodiments and the accompanying drawings, but is limited by the scope of the accompanying claims. Therefore, within the scope of the technical idea of ​​the present invention described in the claims, various substitutions, modifications and changes are possible by a person having ordinary knowledge in the art, and these also belong to the scope of the present invention. [Explanation of symbols]

[0073] 10A, 10B, 10C, 10D, 10E: Semiconductor packages 100: First semiconductor chip 110: First substrate 120: 1st circuit layer 130: First bonding layer 131: First insulating layer 132: First pad 200: Second semiconductor chip 210: Second substrate 220: 2nd circuit layer 230: Second bonding layer 231: Second insulating layer 232: 2nd pad 240:Through electrode 320: Dielectric layer 321: Inorganic particles 322: Polymer chain 412: Bump structure

Claims

1. A semiconductor package comprising: a first semiconductor chip including a first pad; a second semiconductor chip disposed on a front surface facing the first semiconductor chip, the second semiconductor chip including a second pad in contact with the first pad, and a through electrode electrically connected to the second pad and extending to a back surface opposite the front surface; a dielectric layer covering at least a portion of each of the first and second semiconductor chips and having an inner surface facing the first and second semiconductor chips and an outer surface opposite the inner surface; a bump structure disposed on a portion of the outer surface of the dielectric layer and electrically connected to the through electrode; Including, The dielectric layer comprises inorganic particles and polymer chains bonded to at least one side of each of the inorganic particles and connected toward the inner surface and the outer surface via the inorganic particles.

2. the at least one side of each of the inorganic particles has a negative polarity; The semiconductor package of claim 1 , wherein the polymer chain includes a functional group that is physically bonded to the at least one side.

3. The semiconductor package of claim 2 , wherein the functional group is hydrogen bonded to the at least one side.

4. The semiconductor package of claim 2 , wherein the functional group includes at least one of nitrogen (N), oxygen (O), and fluorine (F).

5. The inorganic particles include aluminum nitride (AlN), aluminum oxide (Al ２ O ３ ), silicon carbide (SiC), silicon nitride (Si ３ N ４ 2. The semiconductor package of claim 1, comprising at least one of boron nitride (BN), and silicate.

6. 6. The semiconductor package of claim 5, wherein the silicate is at least one selected from the group consisting of smectite-based materials selected from the group consisting of Montmorillonite, Nontronite, Beidellite, Volkonskoite, Hectorite, Saponite, Laponite, Sauconite, Magadiite, and Kenyaite; vermiculite-based materials; illite-based materials; and derivatives thereof.

7. 2. The semiconductor package of claim 1, wherein the polymer chain comprises at least one of epoxy, polyimide (PI), benzocyclobutene (BCB), polyhydroxystyrene (PHS), polyhydroxyalkanoate (PHB), and polybenzoxazole (PBO).

8. The semiconductor package according to claim 1 , wherein the thermal conductivity of the dielectric layer is 0.4 W / mK or more.

9. the first semiconductor chip further includes a first insulating layer surrounding the first pad; The semiconductor package of claim 1 , wherein the second semiconductor chip further comprises a second insulating layer surrounding the second pad and in contact with the first insulating layer.

10. 10. The semiconductor package of claim 9, wherein the first insulating layer and the second insulating layer include at least one of silicon oxide (SiO), silicon nitride (SiN), and silicon carbonitride (SiCN).

11. The semiconductor package according to claim 1 , wherein a width of the first semiconductor chip is greater than a width of the second semiconductor chip.

12. The semiconductor package of claim 1 , further comprising: a redistribution pattern layer electrically connecting the bump structure and the through electrode; and an insulating material layer covering the redistribution pattern layer.

13. The semiconductor package of claim 12 , wherein the insulating material layer comprises a photosensitive resin.

14. The semiconductor package of claim 1 , wherein at least a portion of the bump structures does not overlap the second semiconductor chip.

15. The semiconductor package of claim 14 , further comprising a through via structure penetrating the dielectric layer and electrically connecting at least some of the bump structures to some of the first pads.

16. A semiconductor package comprising: a first semiconductor chip including a first pad; a second semiconductor chip disposed under the first semiconductor chip, the second semiconductor chip including a second pad in contact with the first pad and a through electrode electrically connected to the second pad; a dielectric layer covering at least a portion of each of the first semiconductor chip and the second semiconductor chip; a bump structure disposed under the second semiconductor chip and electrically connected to the through electrode; Including, The semiconductor package, wherein the dielectric layer is a nanocomposite in which inorganic particles and polymer chains are bonded together.

17. The semiconductor package of claim 16 , wherein the inorganic particles and the polymer chains are bonded by hydrogen bonds.

18. The semiconductor package of claim 16 , wherein the thermal conductivity of the nanocomposite is greater than the thermal conductivity of the polymer chains.

19. 20. The semiconductor package of claim 18, wherein the thermal conductivity of the nanocomposite is 0.4 W / mK or greater.

20. A semiconductor package comprising: a first semiconductor chip including a first pad; a second semiconductor chip disposed under the first semiconductor chip, the second semiconductor chip including a second pad in contact with the first pad and a through electrode electrically connected to the second pad; a dielectric layer that surrounds a side surface of the second semiconductor chip and a portion of the through electrode that protrudes to a back surface of the second semiconductor chip under the first semiconductor chip; a bump structure disposed under the second semiconductor chip and electrically connected to the through electrode; Including, The dielectric layer comprises polymer chains interconnected via inorganic particles.

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