Optical device and manufacturing method of the same

Abstract

To provide a manufacturing method of an optical device, in which deterioration of a light emitting efficiency is suppressed.SOLUTION: A manufacturing method of an optical device, using a III nitride semiconductor, includes: a step of forming an n-type layer, a first active layer, an intermediate layer, a second active layer, and a first p-type layer onto a substrate with an MOCVD method; a groove formation step of forming a groove with a depth reaching the intermediate layer from the first p-type layer side; an electron block layer formation step of forming an electron block layer formed of the III nitride semiconductor onto the intermediate layer exposed to a bottom surface of the groove by sputtering; a semiconductor layer formation step of forming a semiconductor layer formed of the III nitride semiconductor onto the electron block layer by sputtering; and a second p-type layer formation step of performing a p-type formation of the semiconductor layer by performing a thermal processing by performing an ion implantation of a p-type impurity to the semiconductor layer, and thereby forming a second p-type layer.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an optical device and a method for manufacturing the same. [Background technology]

[0002] In recent years, there has been a demand for higher resolution displays, and micro LED displays, in which each pixel is a tiny LED on the order of 1 to 100 μm, have been attracting attention. There are various methods for achieving full color, including a method in which three active layers that emit light in blue, green, and red, respectively, are stacked in sequence on the same substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent No. 5854419 Summary of the Invention [Problem to be solved by the invention]

[0004] In the method of stacking three active layers that emit blue, green, and red light in sequence on the same substrate, a process is required in which the crystal growth is once completed, the wafer is removed from the growth furnace, the grooves are formed, and then the wafer is returned to the growth furnace to re-grow the p-type layer.

[0005] However, the inventors' research revealed that the wafer is contaminated with impurities during this process, and the impurities act as donors, resulting in the formation of an unintended n-type layer at the regrowth interface. This results in the active layer being sandwiched between the n-type layers, reducing the light emission efficiency.

[0006] The present invention has been made in view of the above background, and aims to provide an optical device in which the decrease in light emission efficiency is suppressed, and a method for manufacturing the same. [Means for solving the problem]

[0007] One aspect of the present invention is A method for manufacturing an optical device using a Group III nitride semiconductor, comprising the steps of: an n-type layer formation step of forming an n-type layer made of an n-type Group III nitride semiconductor on a substrate by MOCVD; a first active layer formation step of forming a first active layer having a predetermined band gap energy on the n-type layer by an MOCVD method; an intermediate layer forming step of forming an intermediate layer made of an In-containing Group III nitride semiconductor on the first active layer by an MOCVD method; a second active layer forming step of forming a second active layer having a band gap energy different from that of the first active layer on the intermediate layer by an MOCVD method; a first p-type layer formation step of forming a first p-type layer made of a p-type Group III nitride semiconductor on the second active layer by an MOCVD method; a groove forming step of forming a groove having a depth reaching the intermediate layer from the first p-type layer side; an electron block layer forming step of forming an electron block layer made of a Group III nitride semiconductor by sputtering on the intermediate layer exposed at the bottom surface of the groove; a semiconductor layer forming step of forming a semiconductor layer made of a Group III nitride semiconductor on the electron block layer by sputtering; and forming a second p-type layer by ion-implanting a p-type impurity into the semiconductor layer and subjecting the semiconductor layer to a heat treatment to convert the semiconductor layer to a p-type state, thereby forming a second p-type layer.

[0008] Another aspect of the present invention is In optical devices using III-nitride semiconductors, an n-type layer formed on a substrate and made of an n-type Group III nitride semiconductor; a first active layer having a predetermined band gap energy and disposed on the n-type layer; an intermediate layer formed on the first active layer and made of a Group III nitride semiconductor containing In; a second active layer provided on the intermediate layer and having a band gap energy different from that of the first active layer; a first p-type layer provided on the second active layer and made of a p-type Group III nitride semiconductor; a groove having a depth reaching the intermediate layer from the first p-type layer side; an electron blocking layer made of a Group III nitride semiconductor and provided on the intermediate layer exposed at a bottom surface of the groove; a second p-type layer formed on the electron blocking layer and made of a p-type Group III nitride semiconductor; The concentration of O and Si at the interface between the intermediate layer and the electron blocking layer is 1×10 15 cm -3 The following are optical devices: Effect of the Invention

[0009] According to the above aspect, since the electron blocking layer and the second p-type layer are formed by sputtering, impurities at the interface between the intermediate layer and the electron blocking layer can be sufficiently reduced, thereby suppressing a decrease in luminous efficiency. [Brief description of the drawings]

[0010] [Figure 1] 1 is a cross-sectional view showing a configuration of a light-emitting device in an embodiment, taken along a direction perpendicular to a main surface of a substrate. [Diagram 2] 5A to 5C are diagrams illustrating a manufacturing process of the light emitting element according to the embodiment. [Diagram 3] 5A to 5C are diagrams illustrating a manufacturing process of the light emitting element according to the embodiment. [Figure 4] 5A to 5C are diagrams illustrating a manufacturing process of the light emitting element according to the embodiment. [Diagram 5] 5A to 5C are diagrams illustrating a manufacturing process of the light emitting element according to the embodiment. [Figure 6] FIG. 1 is a cross-sectional view showing the configuration of a light-emitting device in a first modified embodiment of the embodiment, taken along a direction perpendicular to a main surface of a substrate. [Figure 7] FIG. 11 is a cross-sectional view showing the configuration of a light-emitting device in a second modified embodiment of the embodiment, taken along a direction perpendicular to a main surface of a substrate. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] A method for manufacturing an optical device using a Group III nitride semiconductor includes an n-type layer formation step of forming an n-type layer made of an n-type Group III nitride semiconductor on a substrate by MOCVD, a first active layer formation step of forming a first active layer with a predetermined band gap energy on the n-type layer by MOCVD, an intermediate layer formation step of forming an intermediate layer made of a Group III nitride semiconductor containing In on the first active layer by MOCVD, a second active layer formation step of forming a second active layer with a band gap energy different from that of the first active layer on the intermediate layer by MOCVD, and The method includes a first p-type layer formation step of forming a first p-type layer made of a Group III nitride semiconductor by an MOCVD method, a groove formation step of forming a groove deep enough to reach the intermediate layer from the first p-type layer side, an electron block layer formation step of forming an electron block layer made of a Group III nitride semiconductor by sputtering on the intermediate layer exposed at the bottom surface of the groove, a semiconductor layer formation step of forming a semiconductor layer made of a Group III nitride semiconductor by sputtering on the electron block layer, and a second p-type layer formation step of ion-implanting p-type impurities into the semiconductor layer and subjecting it to heat treatment to convert the semiconductor layer to p-type, thereby forming a second p-type layer.

[0012] In the above-described method for manufacturing an optical device, the semiconductor layer forming step may also form a semiconductor layer on the first p-type layer.

[0013] In the above-mentioned method for manufacturing an optical device, after the semiconductor layer forming step, a high resistance region may be formed by implanting ions into a region of the semiconductor layer that contacts the second active layer and the intermediate layer, thereby making it possible to suppress current leakage.

[0014] In the above-described method for manufacturing an optical device, the electron blocking layer forming step may include the step of irradiating the wafer with a plasma gas to remove impurities on the wafer surface before forming the electron blocking layer.

[0015] In the above-mentioned method for manufacturing an optical device, the second p-type layer forming step may include a step of ion-implanting a p-type impurity into the electron blocking layer and heat-treating the layer to make the electron blocking layer p-type. By making the electron blocking layer p-type, holes can be efficiently injected into the first active layer. In addition, a larger barrier against electrons can be provided, improving the electron blocking function.

[0016] In the above-mentioned method for manufacturing an optical device, the optical device may be a light-emitting element, a light-receiving element, or a solar cell.

[0017] The optical device using a Group III nitride semiconductor comprises an n-type layer formed on a substrate and made of an n-type Group III nitride semiconductor, a first active layer formed on the n-type layer and having a predetermined band gap energy, an intermediate layer formed on the first active layer and made of a Group III nitride semiconductor containing In, a second active layer formed on the intermediate layer and having a band gap energy different from that of the first active layer, a first p-type layer formed on the second active layer and made of a p-type Group III nitride semiconductor, a groove having a depth reaching the intermediate layer from the first p-type layer side, an electron block layer formed on the intermediate layer exposed at a bottom surface of the groove and made of a Group III nitride semiconductor, and a second p-type layer formed on the electron block layer and made of a p-type Group III nitride semiconductor, 16 cm -3 The following is the result.

[0018] (Embodiment) FIG. 1 is a diagram showing the configuration of a light-emitting element in an embodiment. The light-emitting element in the embodiment can emit blue, green, and red light. The light-emitting element in the embodiment is a flip-chip type that extracts light from the back side of the substrate, and is mounted face-down on a mounting substrate (not shown). Although the embodiment has a one-chip structure for one pixel, a monolithic type may also be used. In other words, the element structure of the embodiment may be arranged in a matrix on the same substrate to form a micro LED display element.

[0019] 1. Structure of the light-emitting element As shown in FIG. 1, the light-emitting element in this embodiment has a substrate 10, an n-type layer 11, a first active layer 12, a first intermediate layer 13, a second active layer 14, a second intermediate layer 15, a third active layer 16, electron blocking layers 17, 19A, 19B, p-type layers 18, 20A, 20B, an n-side electrode 21, and p-side electrodes 22A to 22C.

[0020] The substrate 10 is a growth substrate for growing a group III nitride semiconductor, such as sapphire, Si, GaN, or ScAlMgO4 (SAM).

[0021] The n-type layer 11 is an n-type semiconductor provided on the substrate 10 via a low-temperature buffer layer or a high-temperature buffer layer (not shown). However, the buffer layer may be provided as necessary, and may not be provided when the substrate is GaN. The n-type layer 11 is, for example, n-GaN, n-AlGaN, or n-InGaN. The Si concentration is, for example, 1×10 18 ~100×10 18 cm -3 It is.

[0022] The first active layer 12 is a light emitting layer of SQW or MQW structure provided on the n-type layer 11. The emission wavelength is blue, 430 to 480 nm. The first active layer 12 has a structure in which 1 to 9 pairs of barrier layers made of AlGaN and well layers made of InGaN are alternately laminated, more preferably 1 to 7 pairs, and even more preferably 1 to 5 pairs.

[0023] An underlayer may be provided between the n-type layer 11 and the first active layer 12, if necessary. The underlayer is a semiconductor layer with a superlattice structure provided on the n-type layer 11, and serves to relieve lattice distortion of the semiconductor layer formed on the underlayer. The underlayer is formed by alternately laminating III-nitride semiconductor thin films with different compositions (e.g., two of GaN, InGaN, and AlGaN), and the number of pairs is, for example, 3 to 30. The underlayer may be undoped or may have 1×10 Si doped. 17 ~100×10 17 cm -3Also, as long as the strain can be relaxed, the superlattice structure is not necessary.

[0024] An ESD layer may be provided between the n-type layer 11 and the underlayer. The ESD layer is a layer provided to improve electrostatic breakdown voltage. The ESD layer is, for example, non-doped or lightly Si-doped GaN, InGaN, or AlGaN.

[0025] The first intermediate layer 13 is a semiconductor layer provided on the first active layer 12. The first intermediate layer 13 is a layer provided to enable individual control of light emission from the first active layer 12 and light emission from the second active layer 14. The first intermediate layer 13 also serves to protect the first active layer 12 from etching damage when forming second grooves 31 described below.

[0026] The first intermediate layer 13 has a structure in which a non-doped intermediate layer 13A and an n-type intermediate layer 13B are laminated in this order from the first active layer 12 side. The non-doped intermediate layer 12A and the n-type intermediate layer 12B may be made of the same material except for impurities. The reason for making the first intermediate layer 13 have such a two-layer structure will be described later.

[0027] The material of the first intermediate layer 13 is a group III nitride semiconductor containing In, for example, InGaN. The surfactant effect of In can suppress roughness of the surface of the first intermediate layer 13 and improve the surface flatness. Also, the lattice distortion can be alleviated.

[0028] The In composition of the first intermediate layer 13 (the molar ratio of In to the total Group III metals of the Group III nitride semiconductor) may be set so as to provide a band gap that does not absorb light emitted from the first active layer 12 and the second active layer 14. A preferred In composition is 10% or less, more preferably 5% or less, and even more preferably 2% or less. If the In composition is greater than 10%, it may cause the surface of the first intermediate layer 13 to become rough. The In content may be any value greater than 0%, and may be at a doping level (a level at which no mixed crystal is formed). For example, an In concentration of 1×10 14 cm -3 More than 1×10 22cm -3 The following is GaN.

[0029] The non-doped intermediate layer 13A is non-doped, and the n-type intermediate layer 13B is Si-doped. The Si concentration of the n-type intermediate layer 13B is 1×10 17 ~1000×10 17 cm -3 It is preferable to set the value to 10×10 17 ~100×10 17 cm -3 , and more preferably 20×10 17 ~80×10 17 cm -3 The n-type intermediate layer 13B may be modulation doped with Si, or a portion of the n-type intermediate layer 13B may be a non-doped region.

[0030] The thickness of the first intermediate layer 13 is preferably 20 to 150 nm. If it is thicker than 150 nm, the surface of the first intermediate layer 13 may become rough. If it is thinner than 20 nm, it may be difficult to control the depth of the second grooves 31 to be formed within the non-doped intermediate layer 13A when the second grooves 31 are formed, as described below. The thickness is more preferably 30 to 100 nm, and even more preferably 50 to 80 nm.

[0031] The thickness of the non-doped intermediate layer 13A is preferably 10 nm or more in order to control the etching depth and to avoid etching damage to the first active layer 12. The thickness of the n-type intermediate layer 13B is preferably 10 nm or more in order to independently control the light emission characteristics of each active layer.

[0032] The second active layer 14 is a layer provided on the first intermediate layer 13, and has a quantum well structure of SQW or MQW. The emission wavelength is green and is 510 to 570 nm. The quantum well structure is a structure in which 1 to 7 pairs of barrier layers made of GaN or AlGaN and well layers made of InGaN are alternately laminated.

[0033] A strain relaxation layer may be provided between the first intermediate layer 13 and the second active layer 14. By providing the strain relaxation layer, the strain of the second active layer 14 laminated thereon can be relaxed, and the crystal quality can be improved. The strain relaxation layer is an SQW structure or MQW structure in which a barrier layer and a well layer are laminated in order, and is a quantum well structure in which the thickness of the well layer is adjusted to be thin so as not to emit light. For example, the well layer can be made to be 1 nm or less in thickness so as not to emit light. The barrier layer is AlGaN, and the well layer is InGaN. The wavelength corresponding to the band edge energy of the well layer of the strain relaxation layer may be shorter than the emission wavelength of the second active layer 14, and is 400 to 460 nm if the emission wavelength is 500 to 560 nm, for example.

[0034] The second intermediate layer 15 is a semiconductor layer provided on the second active layer 14. The second intermediate layer 15 is provided for the same reason as the first intermediate layer 13, and is a layer provided to enable individual control of the light emission from the second active layer 14 and the light emission from the third active layer 16. In addition, the second intermediate layer 15 also serves to protect the second active layer 14 from etching damage when forming the first groove 30 described below.

[0035] The second intermediate layer 15 has a structure in which a non-doped intermediate layer 15A and an n-type intermediate layer 15B are laminated in this order from the second active layer 14 side. The non-doped intermediate layer 15A and the n-type intermediate layer 15B have the same structure as the non-doped intermediate layer 13A and the n-type intermediate layer 13B. In other words, the non-doped intermediate layer 15A and the n-type intermediate layer 15B are made of the same material as the non-doped intermediate layer 13A and the n-type intermediate layer 13B except for impurities, and the thickness range is also the same as the non-doped intermediate layer 13A and the n-type intermediate layer 13B. The non-doped intermediate layer 15A is non-doped, and the n-type intermediate layer 15B is Si-doped.

[0036] The third active layer 16 is a layer provided on the second intermediate layer 15, and has a quantum well structure of SQW or MQW. The emission wavelength is red, and is 590 to 700 nm. The quantum well structure is a structure in which 1 to 7 pairs of barrier layers made of InGaN and well layers made of InGaN are alternately laminated, more preferably 1 to 5 pairs, and even more preferably 1 to 3 pairs.

[0037] A strain relaxation layer may be provided between the second intermediate layer 15 and the third active layer 16. By providing the strain relaxation layer, it is possible to relax the strain in the third active layer 16 laminated thereon, and it is possible to improve the crystal quality. The strain relaxation layer has a structure in which, for example, a first strain relaxation layer and a second strain relaxation layer are laminated in this order from the second intermediate layer 15 side.

[0038] The first and second strain relaxation layers have the same structure as the strain relaxation layer between the first intermediate layer 13 and the second active layer 14. The wavelength corresponding to the band edge energy of the well layer of the first strain relaxation layer is, for example, 400 to 460 nm. The wavelength corresponding to the band edge energy of the well layer of the second strain relaxation layer is, for example, 510 to 570 nm.

[0039] The electron blocking layer 17 is a semiconductor layer provided on the third active layer 16. The electron blocking layer 17 is a layer that blocks electrons injected from the n-type layer 11 in order to confine them efficiently in the third active layer 16. The electron blocking layer 17 also functions as a protective layer that protects the active layer in addition to blocking electrons. The electron blocking layer 17 may be made of a material that has a wider band gap than the well layer of the third active layer 16, such as AlGaN, GaN, or InGaN. The thickness of the electron blocking layer 17 is preferably 2.5 to 50 nm, and more preferably 5 to 25 nm. The electron blocking layer 17 may be doped with an impurity, or may be doped with Mg. In this case, the Mg concentration is 1×10 18 ~1000×10 18 cm -3 It is better to say:

[0040] The p-type layer 18 is a semiconductor layer provided on the electron blocking layer 17, and is composed of a first layer and a second layer in that order from the electron blocking layer 17 side. The first layer is preferably p-GaN or p-InGaN. The thickness of the first layer is preferably 10 to 500 nm, more preferably 10 to 200 nm, and further preferably 10 to 100 nm. The Mg concentration of the first layer is 1×10 19 ~100×10 19 cm -3The second layer is preferably p-GaN or p-InGaN. The thickness of the second layer is preferably 2 to 50 nm, more preferably 4 to 20 nm, and further preferably 6 to 10 nm. The Mg concentration of the second layer is 1×10 20 ~100×10 20 cm -3 It is better to say:

[0041] A portion of the surface of the p-type layer 18 is etched to provide grooves, and a first groove 30 extending from the p-type layer 18 to the second intermediate layer 15, a second groove 31 extending to the first intermediate layer 13, and a third groove 32 extending to the n-type layer 11 are provided.

[0042] The first groove 30 has a depth that reaches the non-doped intermediate layer 15A of the second intermediate layer 15. In this way, by removing the n-type intermediate layer 15B of the second intermediate layer 15 under the p-side electrode 22B, an n-type layer is prevented from being positioned on the second active layer 14, so that the second active layer 14 emits light. In addition, the second groove 31 has a depth that reaches the non-doped intermediate layer 13A of the first intermediate layer 13. This is for the same reason, and by removing the n-type intermediate layer 13B of the first intermediate layer 13 under the p-side electrode 22C, an n-type layer is prevented from being positioned on the first active layer 12, so that the first active layer 12 emits light.

[0043] The electron blocking layers 19A and 19B are semiconductor layers provided on the non-doped intermediate layer 15A exposed at the bottom of the first groove 30 and on the non-doped intermediate layer 13A exposed at the bottom of the second groove 31, respectively, and are layers that block electrons injected from the n-type layer 11 in order to efficiently confine them in the first active layer 12 and the second active layer 14.

[0044] The electron blocking layers 19A and 19B are layers formed by sputtering, as described below. Therefore, impurities such as O and Si are not present at the interface between the non-doped intermediate layer 15A and the electron blocking layer 19A, and at the interface between the non-doped intermediate layer 13A and the electron blocking layer 19B, and no n-type layer is present. Here, the absence of impurities such as O and Si means that the impurity concentration is sufficiently small, for example, 1×10 16 cm -3More preferably, it is 1×10 15 cm -3 The following is the result.

[0045] The electron blocking layers 19A and 19B may be a single layer of GaN or AlGaN, or may be a structure in which two or more of AlGaN, GaN, and InGaN are stacked, or a structure in which layers are stacked with only different composition ratios. They may also be a superlattice structure. The superlattice structure can block electrons more efficiently. The superlattice structure is, for example, a structure in which p-AlGaN and p-InGaN are alternately stacked, or a structure in which p-AlGaN and p-GaN are alternately stacked. However, in consideration of the ease of formation by sputtering, the electron blocking layers 19A and 19B are preferably a single layer, or a layer in which the Al composition monotonically decreases or increases.

[0046] The thickness of the electron blocking layers 19A and 19B is preferably 5 to 50 nm, and more preferably 5 to 25 nm.

[0047] The electron blocking layers 19A and 19B are Mg-doped p-type. Mg is introduced by ion implantation as described below. By making them p-type, holes can be efficiently injected into the active layer. In addition, a larger barrier against electrons can be formed, enhancing the electron blocking function. The electron blocking layers 19A and 19B may be non-doped, but for the above reasons, they are preferably doped with Mg to make them p-type. The Mg concentration of the electron blocking layers 19A and 19B is 1×10 19 ~100×10 19 cm -3 It is better to say:

[0048] The p-type layers 20A and 20B are semiconductor layers provided on the electron blocking layers 19A and 19B, respectively, and are composed of a first layer and a second layer in that order from the electron blocking layer 19A, 19B side. The p-type layers 20A and 20B are layers formed by sputtering as described below, and Mg is introduced by ion implantation.

[0049] The first layer is preferably p-GaN or p-InGaN. The thickness of the first layer is preferably 10 to 500 nm, more preferably 10 to 200 nm, and further preferably 10 to 100 nm. The Mg concentration of the first layer is 1×10 19 ~100×10 19 cm -3 The second layer is preferably p-GaN or p-InGaN. The thickness of the second layer is preferably 2 to 50 nm, more preferably 4 to 20 nm, and further preferably 6 to 10 nm. The Mg concentration of the second layer is 1×10 20 ~100×10 20 cm -3 It is better to say:

[0050] In the first embodiment, the p-type layers 20A and 20B have a two-layer structure. However, in consideration of the ease of formation by sputtering, the p-type layers 20A and 20B are preferably a single layer, and more preferably a single Mg-doped GaN layer.

[0051] In the embodiment, the electron blocking layer 19A and the electron blocking layer 19B, and the p-type layer 20A and the p-type layer 20B are formed separately, but they may be formed as a continuous film. In that case, a layer of the same material as the electron blocking layers 19A and 19B is formed on the side surface of the second groove 31.

[0052] The n-side electrode 21 is an electrode provided on the n-type layer 11 exposed on the bottom surface of the third groove 32. When the substrate 10 is made of a conductive material, the n-side electrode 21 may be provided on the back surface of the substrate 10 without providing the third groove 32. The material of the n-side electrode 21 is, for example, Ti / Al or V / Al.

[0053] The p-side electrodes 22A to 22C are electrodes provided on the p-type layers 18, 20A, and 20B, respectively. The material of the p-side electrodes 22A to 22C is preferably a material that has a high reflectance of light of the emission wavelength and a low contact resistance with the p-type layers 18, 20A, and 20B. For example, Ag, Ni / Au, Co / Au, ITO / Ni / Al, Rh, Ru, etc. The red light emitted from the third active layer 16 toward the p-type layer 18 is reflected by the p-side electrode 22A and directed toward the substrate 10. Similarly, the green light emitted from the second active layer 14 toward the p-type layer 20A is reflected by the p-side electrode 22B and directed toward the substrate 10, and the blue light emitted from the first active layer 12 toward the p-type layer 20B is reflected by the p-side electrode 22C and directed toward the substrate 10.

[0054] As described above, in the light-emitting device of the embodiment, the electron blocking layers 19A, 19B and the p-type layers 20A, 20B are layers formed by sputtering, and therefore no n-type layer containing impurities such as O or Si exists between the non-doped intermediate layer 15A and the electron blocking layer 19A, and between the non-doped intermediate layer 13A and the electron blocking layer 19B. Therefore, the light-emitting device of the embodiment can suppress a decrease in luminous efficiency.

[0055] 2. Operation of the light-emitting element Next, the operation of the light emitting device in the embodiment will be described. In the light emitting device in the embodiment, red light can be emitted from the third active layer 16 by applying a voltage between the p-side electrode 22A and the n-side electrode 21, green light can be emitted from the second active layer 14 by applying a voltage between the p-side electrode 22B and the n-side electrode 21, and blue light can be emitted from the first active layer 12 by applying a voltage between the p-side electrode 22C and the n-side electrode 21. These lights can be controlled individually, and two or more of blue, green, and red can be emitted simultaneously.

[0056] In this way, in the light emitting element of the embodiment, light emission of blue, green, and red can be controlled by selecting the electrodes to which a voltage is applied, and the element can be used as one pixel of a display.

[0057] 3. Light-emitting device manufacturing process Next, a manufacturing process of the light emitting device in the embodiment will be described with reference to the drawings.

[0058] First, the substrate 10 is prepared, and hydrogen or nitrogen, and if necessary, ammonia, are added to the substrate, and the substrate is subjected to a heat treatment.

[0059] Next, a buffer layer is formed on the substrate 10, and an n-type layer 11, a first active layer 12, a first intermediate layer 13, a second active layer 14, a second intermediate layer 15, a third active layer 16, an electron blocking layer 17, and a p-type layer 18 are formed in this order on the buffer layer (see FIG. 2). Each layer is formed using the MOCVD method. The preferred growth temperatures for each layer are as follows:

[0060] The growth temperature of the first active layer 12 is preferably 700 to 950°C. This can improve the crystal quality and the light emission efficiency. The first active layer 12 is composed of a well layer and a barrier layer, and the well layer and the barrier layer may be formed at the same temperature or at different temperatures within the above temperature range. When they are formed at different temperatures, it is preferable that the growth temperature of the well layer is lower than the growth temperature of the barrier layer.

[0061] The growth temperature of the first intermediate layer 13 is preferably 700 to 1000°C. This is to suppress thermal damage to the first active layer 12. If the temperature is lower than 700°C, pits and point defects due to threading dislocations are likely to occur. The temperature is more preferably 800 to 950°C, and further preferably 850 to 950°C.

[0062] The growth temperature of the second active layer 14 is preferably 650 to 950°C. This can improve the crystal quality and the light emission efficiency. The second active layer 14 is composed of a well layer and a barrier layer, and the well layer and the barrier layer may be formed at the same temperature or at different temperatures within the above temperature range. When they are formed at different temperatures, it is preferable that the growth temperature of the well layer is lower than the growth temperature of the barrier layer. In addition, it is preferable that the growth temperature of the second active layer 14 is lower than the growth temperature of the first active layer 12.

[0063] The growth temperature of the second intermediate layer 15 is preferably in the same range as the growth temperature of the first intermediate layer 13. However, the growth temperature of the second intermediate layer 15 is preferably lower than the growth temperature of the first intermediate layer 13. This is because the green-emitting second active layer 14 is more susceptible to thermal damage than the blue-emitting first active layer 12, and is more susceptible to strain at the interface.

[0064] The growth temperature of the third active layer 16 is preferably 500 to 950°C. This can improve the crystal quality and the light emission efficiency. The third active layer 16 is composed of a well layer and a barrier layer, and the well layer and the barrier layer may be formed at the same temperature or at different temperatures within the above temperature range. When they are formed at different temperatures, it is preferable that the growth temperature of the well layer is lower than the growth temperature of the barrier layer. In addition, it is preferable that the growth temperature of the third active layer 16 is lower than the growth temperature of the second active layer 14.

[0065] The growth temperature of electron blocking layer 17 and p-type layer 18 is preferably 500 to 950°C in order to suppress thermal damage to first active layer 12, second active layer 14, and third active layer 16. To improve the crystallinity of electron blocking layer 17 and p-type layer 18, a higher growth temperature is preferable, more preferably 600 to 900°C, and even more preferably 700 to 900°C.

[0066] Next, a portion of the surface of the p-type layer 18 is dry etched until it reaches the non-doped intermediate layer 15A of the second intermediate layer 15 to form a first groove 30, and then dry etched until it reaches the non-doped intermediate layer 13A of the first intermediate layer 13 to form a second groove 31 (see Figure 3).

[0067] In the process of forming the first groove 30 and the second groove 31, the wafer is temporarily removed from the growth furnace and subjected to an etching process, which exposes the wafer to the atmosphere and contaminates the wafer surface with impurities such as O and Si.

[0068] Next, electron blocking layers 19A, 19B made of undoped AlGaN are formed by sputtering on undoped intermediate layer 15A of second intermediate layer 15 exposed by first groove 30, and on undoped intermediate layer 13A of first intermediate layer 13 exposed by second groove 31, and p-type layers 20A, 20B made of undoped GaN or InGaN are formed by sputtering on electron blocking layers 19A, 19B (see FIG. 4). Note that p-type layers 20A, 20B are not p-type at this stage, but are referred to as such because they will become p-type later.

[0069] As the sputtering target, an AlGaN sintered body is used to form the electron blocking layers 19A and 19B, and a GaN or InGaN sintered body is used to form the p-type layers 20A and 20B. Alternatively, a Ga target may be used and GaN may be grown by nitrogen plasma. The temperature during sputtering is 20°C to 700°C, and the pressure is 0.1 to 1 Pa. Ar or nitrogen is used as the gas. The sputtering method may be an RF method, a DC method, or the like.

[0070] In sputtering, plasma gas such as Ar or nitrogen is irradiated onto the wafer as a pretreatment. This plasma gas can remove impurities such as O and Si from the wafer surface. Therefore, no n-type layer due to impurities such as O and Si is formed at the interface between non-doped intermediate layer 15A and electron blocking layer 19A, and at the interface between non-doped intermediate layer 13A and electron blocking layer 19B. This can suppress the decrease in luminous efficiency.

[0071] Moreover, by irradiating the wafer with plasma gas, etching damage that occurs during the formation of the first groove 30 and the second groove 31 can be removed, improving the characteristics of the device. Also, particles adhering to the wafer can be removed, reducing the defect rate.

[0072] Furthermore, since the electron blocking layers 19A, 19B and the p-type layers 20A, 20B can be formed at low temperatures by sputtering, thermal damage to the first active layer 12, the second active layer 14, and the third active layer 16 can be suppressed.

[0073] Furthermore, since sputtering does not use hydrogen or ammonia as in the case of MOCVD, there is no possibility that hydrogen from these gases will inactivate the Mg in the electron blocking layer 17 or the p-type layer 18, causing the Mg to become highly resistive.

[0074] Next, Mg ions are implanted into the p-type layers 20A, 20B and the electron blocking layers 19A, 19B from the surface side of the p-type layers 20A, 20B. The implantation energy is controlled so that the implantation peak is in the p-type layers 20A, 20B. Ion implantation may be performed at room temperature, but is preferably performed at a temperature higher than room temperature. This can reduce the amount of implantation damage. For example, it is performed at a temperature of 400°C or higher. It is also preferable to perform it at 600°C or lower to suppress thermal damage.

[0075] In this manner, p-type layers 20A and 20B and electron blocking layers 19A and 19B are doped with Mg by ion implantation, because it is difficult to directly form an Mg-doped Group III nitride semiconductor by sputtering.

[0076] In the embodiment, Mg is ion-implanted into both the p-type layers 20A, 20B and the electron blocking layers 19A, 19B, but it may be ion-implanted only into the p-type layers 20A, 20B. However, since it is preferable to make the electron blocking layers 19A, 19B p-type, it is preferable to also implant ions into the electron blocking layers 19A, 19B as in the embodiment. Alternatively, it is possible to make the electron blocking layers 19A, 19B p-type by implanting ions only into the p-type layers 20A, 20B and diffusing Mg from the p-type layers 20A, 20B into the electron blocking layers 19A, 19B in a heat treatment in the next step.

[0077] Next, a heat treatment is performed to activate the ion-implanted Mg. The preferred heat treatment conditions are as follows: the heat treatment temperature is 800 to 1200°C, the pressure is 100 kPa to 1 GPa, and the atmosphere is nitrogen, an inert gas such as Ar, or ammonia. The heat treatment time is 1 second to 10 minutes. This heat treatment activates Mg, and the p-type layers 20A and 20B and the electron blocking layers 19A and 19B can be made p-type. The p-type layer 18 can also be made p-type. It is particularly preferable to perform the heat treatment in a nitrogen or ammonia atmosphere. This is to suppress the loss of nitrogen from the semiconductor layer. In order to reduce thermal damage to the active layer, it is preferable to perform the heat treatment at as low a temperature as possible. When the temperature is high, it is preferable to perform the heat treatment for a short time.

[0078] The mask used for sputtering and ion implantation can be photoresist, SiO2, etc. The mask used for sputtering may be left as it is and used as the mask for ion implantation.

[0079] The ion implantation may be performed multiple times by changing the acceleration voltage, allowing the distribution of Mg in the thickness direction to be adjusted.

[0080] Next, a partial area of ​​the surface of the p-type layer 20B is dry-etched until it reaches the n-type layer 11 to form a third groove 32 (see FIG. 5). Then, an n-side electrode 21 is formed on the n-type layer 11 exposed on the bottom surface of the third groove 32, and p-side electrodes 22A to 22C are formed on the p-type layers 18, 20A, and 20B. In this manner, the light-emitting device of the embodiment is manufactured.

[0081] As described above, in the method for manufacturing the light-emitting device according to the embodiment, the p-type layers 20A, 20B and the electron blocking layers 19A, 19B are formed by sputtering and ion implantation, so that no n-type layer containing impurities such as O or Si exists between the non-doped intermediate layer 15A and the electron blocking layer 19A, and between the non-doped intermediate layer 13A and the electron blocking layer 19B. This makes it possible to suppress a decrease in the light-emitting efficiency.

[0082] (First Variation of the Embodiment) As shown in Fig. 6, at the same time as forming the electron blocking layers 19A, 19B and the p-type layers 20A, 20B, the electron blocking layer 19C and the p-type layer 20C may be formed on the p-type layer 18 in this order from the p-type layer 18 side by sputtering. According to the first modified embodiment, it becomes easy to control the optical interference effect by controlling the thickness on each active layer. Also, since no mask is used, the manufacturing process can be simplified. Furthermore, since the p-type layer 20C is the surface on which the mask was not formed, the contact of the p-side electrode 22A can be improved.

[0083] (Modification 2 of the embodiment) As shown in FIG. 7, high resistance regions 23A and 23B may be formed by ion implantation in the regions of the electron blocking layer 19A and the p-type layer 20A that are in contact with the n-type intermediate layer 15B and the third active layer 16, and in the regions of the electron blocking layer 19B and the p-type layer 20B that are in contact with the n-type intermediate layer 13B and the second active layer 14. This prevents current leakage between the p-side electrode 22A and the p-side electrode 22B and between the p-side electrode 22B and the p-side electrode 22C, and makes it easier to control the emission of light from the first active layer 12, the second active layer 14, and the third active layer 16. Any element species may be implanted into the ions as long as it can increase the resistance. For example, B, Zn, Mg, etc. may be used. The high resistance may be achieved by co-doping a donor such as Si or Ge with an acceptor such as Mg.

[0084] (Other variations) In the embodiment, the light emitted is three colors, red, green, and blue, but the present invention is not limited to this, and any light emitted may be two or more colors having different emission wavelengths. For example, the light emitted may be four colors, red, yellow, green, and blue.

[0085] In the embodiment, the optical device of the present invention is used as a light emitting element, but the present invention can also be used as a light receiving element. When used as a light receiving element, for example, red, green, and blue light can be separately received.

[0086] Furthermore, the light-emitting element and the light-receiving element of the present invention can be used as a light source for generating an optical signal and a light-receiving element for receiving an optical signal in a wavelength division multiplexing optical communication device, thereby simplifying and reducing the cost of the optical communication device. For example, the red light, green light, and blue light emitted by the light-emitting element in the embodiment can be wavelength-multiplexed to generate and transmit a transmission signal. Furthermore, if the received signal is received by the light-receiving element in the embodiment, the red light, green light, and blue light can be separately received.

[0087] By arranging a large number of the light receiving elements according to the embodiment, the light receiving elements can also be used as a solar cell. [Explanation of symbols]

[0088] 10: Substrate 11:N-type layer 12: 1st active layer 13: First middle layer 14:Second active layer 15: Second middle tier 16: 3rd active layer 17, 19A, 19B: Electron blocking layer 18, 20A, 20B: p-type layer 21:n side electrode 22A~22C:p side electrode

Claims

1. A method for manufacturing an optical device using a Group III nitride semiconductor, comprising the steps of: an n-type layer formation step of forming an n-type layer made of an n-type Group III nitride semiconductor on a substrate by MOCVD; a first active layer formation step of forming a first active layer having a predetermined band gap energy on the n-type layer by MOCVD; an intermediate layer forming step of forming an intermediate layer made of an In-containing Group III nitride semiconductor on the first active layer by MOCVD; a second active layer forming step of forming a second active layer having a band gap energy different from that of the first active layer on the intermediate layer by MOCVD; a first p-type layer formation step of forming a first p-type layer made of a p-type Group III nitride semiconductor on the second active layer by MOCVD; a groove forming step of forming a groove having a depth reaching the intermediate layer from the first p-type layer side; an electron block layer forming step of forming an electron block layer made of a Group III nitride semiconductor by sputtering on the intermediate layer exposed at the bottom surface of the groove; a semiconductor layer forming step of forming a semiconductor layer made of a Group III nitride semiconductor on the electron blocking layer by sputtering; and forming a second p-type layer by ion-implanting a p-type impurity into the semiconductor layer and performing a heat treatment to convert the semiconductor layer to a p-type layer, thereby forming a second p-type layer.

2. The method for manufacturing an optical device according to claim 1 , wherein the semiconductor layer forming step also forms the semiconductor layer on the first p-type layer.

3. 3. The method for manufacturing an optical device according to claim 1, further comprising the step of: forming a high resistance region by implanting ions into a region of the semiconductor layer that is in contact with the second active layer and the intermediate layer after the semiconductor layer forming step.

4. The method for manufacturing an optical device according to claim 1 , wherein the electron blocking layer forming step includes the step of irradiating the wafer with a plasma gas to remove impurities on the wafer surface before forming the electron blocking layer.

5. The method for manufacturing an optical device according to claim 1 , wherein the second p-type layer forming step includes the step of ion-implanting a p-type impurity into the electron blocking layer and subjecting the layer to a heat treatment to make the electron blocking layer p-type.

6. The method for manufacturing an optical device according to claim 1 , wherein the optical device is a light-emitting element.

7. The method for manufacturing an optical device according to claim 1 , wherein the optical device is a light receiving element.

8. The method for manufacturing an optical device according to claim 1 , wherein the optical device is a solar cell.

9. In an optical device using a Group III nitride semiconductor, an n-type layer formed on a substrate and made of an n-type Group III nitride semiconductor; a first active layer having a predetermined band gap energy and disposed on the n-type layer; an intermediate layer provided on the first active layer and made of a Group III nitride semiconductor containing In; a second active layer provided on the intermediate layer and having a band gap energy different from that of the first active layer; a first p-type layer provided on the second active layer and made of a p-type Group III nitride semiconductor; a groove having a depth reaching the intermediate layer from the first p-type layer side; an electron blocking layer made of a Group III nitride semiconductor and provided on the intermediate layer exposed at a bottom surface of the groove; a second p-type layer formed on the electron blocking layer and made of a p-type Group III nitride semiconductor; The concentration of O and Si at the interface between the intermediate layer and the electron blocking layer is 1×10 １６ cm －３ An optical device as follows:

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