Phase synchronization device, signal transmitting circuit, and phase synchronization method

Abstract

To reduce a circuit scale of a phase synchronization device that keeps a phase of a signal passing through a transmission path in the same phase at a transmission destination and a transmission source.SOLUTION: A phase synchronization device 100 includes: a standard signal generating circuit 1 that outputs a standard signal; a signal transmitting circuit 10 that transmits a reference signal obtained by changing a phase of the standard signal based on an error signal; a signal receiving circuit 20 that receives the reference signal, outputs the reference signal to the signal transmitting circuit 10 as a return signal, and also outputs the reference signal as a synchronization signal; and a transmission path 4 that transmits the reference signal and the return signal. The signal transmitting circuit 10 has a phase comparator 6 to which each of the standard signal, the reference signal, and the return signal is input, and which generates and outputs an error signal corresponding to a phase difference between a center value of the phase of the reference signal and the phase of the return signal, and the phase of the reference signal.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a phase synchronization device, a signal transmission circuit, and a phase synchronization method. [Background technology]

[0002] There are cases where it is required to keep the phase of a signal transmitted through a transmission line in the same phase at the source and destination. For example, in a distributed radar, the antennas are placed at distant locations, and there is a problem that the cable expands and contracts due to heat, vibration, etc., causing fluctuations in the signal phase, so it is necessary to align the signal phase.

[0003] For example, the optical transmission device and optical transmission system described in Patent Document 1 include a feedback loop circuit that uses a phase comparator to compare the phase of a signal generated by a voltage-controlled oscillator, which has traveled back and forth through an optical transmission line and returned to the phase of a reference signal source, and controls the voltage-controlled oscillator so that the two are synchronized. The convergence of the feedback loop circuit has the effect of keeping the phase of the signal at the transmission destination and the phase of the signal at the transmission source in phase. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2020 / 026347 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the optical transmission device and optical transmission system described in Patent Document 1, the one-way phase shift to be corrected is extracted from the round-trip phase shift using a frequency divider, so not only the phase difference but also the frequency is halved. Since the two signals input to the phase comparator must have the same frequency, a mixer circuit is required to frequency convert the reflected signal that has returned after traveling back and forth along the transmission line, which creates a problem of large circuit size.

[0006] The present disclosure has been made to solve the problems described above, and aims to reduce the circuit size of a phase synchronization device that keeps the phase of a signal passing through a transmission path in phase at the destination and source. [Means for solving the problem]

[0007] In order to achieve the above object, a phase synchronization device according to the present disclosure includes a reference signal generating section, a signal transmitting section, a signal receiving section, and a transmission path. The reference signal generating circuit outputs a reference signal. The signal transmitting section transmits a reference signal obtained by changing the phase of the reference signal based on an error signal. The signal receiving section receives the reference signal, outputs the reference signal to the signal transmitting section as a return signal, and outputs the reference signal as a synchronization signal. The transmission path transmits the reference signal and the return signal to the signal transmitting section. The signal transmitting section has a phase comparator to which the reference signal, the reference signal, and the return signal are respectively input, and which generates and outputs an error signal corresponding to the phase difference between the phase of the reference signal and the central value of the phase of the return signal and the phase of the reference signal. Effect of the Invention

[0008] According to the present disclosure, a phase comparator is provided that halves only the phase difference without halving the frequency of the return signal that has traveled back and forth along the transmission path, thereby eliminating the need for a mixer circuit and allowing the circuit size of a phase synchronization device that keeps the phase of the signal passing through the transmission path in phase at the destination and source to be reduced. [Brief description of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a phase synchronization device according to a first embodiment; [Diagram 2] FIG. 1 is a diagram showing a configuration example of a signal folding circuit according to a first embodiment; [Diagram 3] FIG. 1 is a diagram showing an example of the configuration of a phase comparator according to a first embodiment; [Figure 4] FIG. 1 is a diagram showing a configuration example of an integrating circuit according to a first embodiment; [Diagram 5] FIG. 1 is a diagram showing an example of a circuit configuration of a phase comparator and an integrating circuit according to a first embodiment; [Figure 6] FIG. 1 shows waveforms of a reference signal and a folding signal input to a combining circuit in a steady state according to the first embodiment, and a combined signal output from the combining circuit; [Figure 7] FIG. 1 shows waveforms of a reference signal and a composite signal input to a phase comparator in a steady state according to the first embodiment, a lead signal and a lag signal output from the phase comparator, and an output voltage of an integrating circuit. [Figure 8] FIG. 1 shows waveforms of a reference signal and a composite signal input to a phase comparator, a lead signal and a lag signal output from the phase comparator, and an output voltage of an integrating circuit when a phase delay is large according to the first embodiment. [Figure 9] FIG. 1 shows waveforms of a reference signal and a composite signal input to a phase comparator, a lead signal and a lag signal output from the phase comparator, and an output voltage of an integrating circuit when the phase delay is small according to the first embodiment; [Figure 10] FIG. 13 is a diagram showing a configuration example of a phase synchronization device according to a second embodiment; [Figure 11] FIG. 1 is a diagram showing a first application example of a phase synchronization device according to a first embodiment; [Figure 12] FIG. 13 is a diagram showing a second application example of the phase synchronization device according to the first embodiment. [Figure 13] FIG. 13 is a diagram showing a third application example of the phase synchronization device according to the first embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] A phase synchronization device, a signal transmission circuit, and a phase synchronization method according to the present embodiment will be described in detail below with reference to the drawings. Note that the same or corresponding parts in the drawings are given the same reference characters, and their description will not be repeated in principle.

[0011] (Embodiment 1) 1 shows a configuration example of a phase synchronization device 100 according to a first embodiment. The phase synchronization device 100 includes a reference signal generating circuit 1 that outputs a reference signal, a signal transmitting circuit 10 that transmits a synchronization signal, and a signal receiving circuit 20 that receives the synchronization signal. The reference signal generating circuit 1 is, for example, a crystal oscillator, and generates a high-frequency signal and outputs it to the signal transmitting circuit 10 as a reference signal. Note that the reference signal is not limited to a high-frequency signal. The reference signal generating circuit 1, the signal transmitting circuit 10, and the signal receiving circuit 20 are examples of a reference signal generating unit, a signal transmitting unit, and a signal receiving unit, respectively.

[0012] The signal transmission circuit 10 includes a phase shifter 2 that changes the phase of an input signal and outputs it, a signal separation circuit 3 that separates the input signal and outputs it as a transmission signal, a phase comparator 6 that compares the phases of the input signals and outputs an error signal corresponding to the phase difference, and an integration circuit 7 that integrates the error signal and outputs a phase control signal that controls the amount of phase shift of the phase shifter 2. The error signals include a lead signal that indicates a phase lead and a lag signal that indicates a phase lag.

[0013] The phase shifter 2 outputs a reference signal, which is obtained by changing the phase of the reference signal output from the reference signal generating circuit 1 in response to a phase control signal output from the integrating circuit 7, to the signal separating circuit 3 and the phase comparator 6. For example, a discrete phase shifter IC (Integrated Circuit) is used as the phase shifter 2. The signal separating circuit 3 outputs the reference signal to the signal receiving circuit 20 via the transmission path 4. For example, a coaxial cable, an optical fiber cable, or the like is used as the transmission path 4.

[0014] The signal receiving circuit 20 includes a signal folding back circuit 5 that sends back a part of the input reference signal to the signal transmitting circuit 10 as a folding back signal and outputs the remainder as a synchronization signal.

[0015] The configuration of the signal folding circuit 5 will be described with reference to FIG. 2. As shown in FIG. 2, the signal folding circuit 5 includes a signal separation circuit 51 that separates and outputs an input signal, and a distribution circuit 52 that distributes and outputs the input signal. The signal separation circuit 51 separates a reference signal that is input via the transmission line 4 and output to the distribution circuit 52, and a folded signal that is input from the distribution circuit 52 and output to the signal transmission circuit 10 via the transmission line 4. For example, a high-frequency circulator or an optical circulator is used for the signal separation circuit 51. The distribution circuit 52 distributes the reference signal input from the signal separation circuit 51, outputs a part of the reference signal to the signal separation circuit 51, and outputs the remaining reference signal as a synchronization signal. For example, a Wilkinson divider or an optical distributor is used for the distribution circuit 52.

[0016] As shown in Fig. 1, the signal separation circuit 3 separates and outputs a reference signal output from the phase shifter 2 and a return signal output from the signal receiving circuit 20 via a transmission line 4. The signal separation circuit 3 outputs the reference signal input from the phase shifter 2 to the transmission line 4, but does not output it to the phase comparator 6. Also, the signal separation circuit 3 outputs the return signal input via the transmission line 4 to the phase comparator 6, but does not output it to the phase shifter 2. For example, a high-frequency circulator or an optical circulator is used as the signal separation circuit 3. The signal separation circuit 3 is an example of a signal input / output circuit.

[0017] The phase comparator 6 generates an error signal corresponding to the phase difference between the center value of the phase of the reference signal input from the phase shifter 2 and the folding signal input from the signal separation circuit 3, and the reference signal input from the reference signal generating circuit 1, and outputs the error signal to the integration circuit 7.

[0018] The configuration of phase comparator 6 will be described with reference to Fig. 3. As shown in Fig. 3, phase comparator 6 includes a combining circuit 61 that combines input signals and outputs a combined signal, a phase lead detection circuit 62 that detects a phase lead of the combined signal and outputs a lead signal, and a phase lag detection circuit 63 that detects a phase lag of the combined signal and outputs a lag signal.

[0019] The combining circuit 61 combines the reference signal input from the phase shifter 2 and the folded signal input from the signal separation circuit 3 to output a combined signal. The combining circuit 61 is, for example, a logic circuit wired to an FPGA (Field Programmable Gate Array). The phase lead detection circuit 62 outputs the time difference between the rising time of the reference signal input from the reference signal generation circuit 1 and the rising time of the combined signal input from the combining circuit 61 as a lead signal. The phase lead detection circuit 62 is, for example, a logic circuit and a flip-flop circuit wired to an FPGA. The phase lag detection circuit 63 outputs the time difference between the falling time of the reference signal input from the reference signal generation circuit 1 and the falling time of the combined signal input from the combining circuit 61 as a lag signal. The phase lag detection circuit 63 is, for example, a logic circuit and a flip-flop circuit wired to an FPGA.

[0020] As shown in FIG. 1, the integration circuit 7 integrates the error signal input from the phase comparator 6 and outputs a phase control signal to the phase shifter 2 .

[0021] The configuration of the integrating circuit 7 will be described with reference to FIG. 4. As shown in FIG. 4, the integrating circuit 7 includes a charge pump circuit 71 that combines and outputs input signals, and a loop filter 72 that integrates the output from the charge pump circuit 71. The charge pump circuit 71 combines and outputs the lead signal input from the phase lead detection circuit 62 as positive and the lag signal input from the phase lag detection circuit 63 as negative. The charge pump circuit 71 may combine and output the lead signal input from the phase lead detection circuit 62 as negative and the lag signal input from the phase lag detection circuit 63 as positive. For example, a current type charge pump IC is used for the charge pump circuit 71. The loop filter 72 integrates the output from the charge pump circuit 71 and outputs a phase control signal to the phase shifter 2. For example, a lag-lead type low-pass filter is used for the loop filter 72.

[0022] The signal transmitting circuit 10 and the signal receiving circuit 20 configured as described above become a feedback loop circuit, and in a steady state, the difference between the center value of the phase of the reference signal input from the phase shifter 2 and the phase of the return signal input from the signal separation circuit 3, and the phase of the reference signal input from the reference signal generating circuit 1 converges to zero.

[0023] Here, the phase of the signals in each circuit will be explained. If the phase of the reference signal output from the reference signal generating circuit 1 is θ0 and the phase shift amount of the phase shifter 2 is Φ, then the phase of the reference signal output from the phase shifter 2 is θ0+Φ. For simplicity, the phase shift amount of the signal separation circuit 3 will be ignored. If the phase shift amount of the transmission line 4 is ψ, then the phase of the reference signal output from the transmission line 4 and input to the signal folding circuit 5 will be θ0+Φ+ψ. For simplicity, the phase shift amount of the signal folding circuit 5 will be ignored. The phase of the synchronization signal output from the signal folding circuit 5 is θ0+Φ+ψ.

[0024] The phase of the return signal output from the transmission line 4 and input to the signal separation circuit 3 is θ0+Φ+2ψ. As described above, the phase comparator 6 compares the center value of the phase of the reference signal input from the phase shifter 2 and the phase of the return signal input from the signal separation circuit 3 with the phase of the reference signal input from the reference signal generation circuit 1. The center value of the phase of the reference signal and the phase of the return signal is {(θ0+Φ)+(θ0+Φ+2ψ)} / 2, and the phase of the reference signal is θ0. When the feedback loop is converged, the difference between the two is zero, so {(θ0+Φ)+(θ0+Φ+2ψ)} / 2-θ0=0, and solving this equation for Φ gives Φ=-ψ. The phase of the synchronization signal output from the signal return circuit 5 is θ0+Φ+ψ, but when the feedback loop is converged, Φ=-ψ holds, so it becomes θ0, and is in phase with the reference signal output from the reference signal generation circuit 1.

[0025] Next, an example of the circuit configuration of the combiner circuit 61, phase lead detector circuit 62, and phase lag detector circuit 63 of the phase comparator 6, and the charge pump circuit 71 and loop filter 72 of the integrator circuit 7 will be described with reference to Fig. 5. In the example of Fig. 5, the combiner circuit 61 of the phase comparator 6 includes an OR circuit 611. The OR circuit 611 is a circuit that calculates the OR of the reference signal input from the phase shifter 2 and the folded signal input from the signal separation circuit 3, and may be, for example, an OR circuit wired to an FPGA.

[0026] Here, the operation of the combiner circuit 61 in the steady state will be described with reference to FIG. 6. FIG. 6 is a timing diagram showing the waveforms of the reference signal and the folded signal input to the combiner circuit 61 in the steady state and the combined signal output from the combiner circuit 61. As shown in FIG. 6, at time t0, the reference signal and the folded signal input to the OR circuit 611 are both at low level, and the combined signal output from the OR circuit 611 is at low level. At time t1, the reference signal input to the OR circuit 611 is at high level, and the folded signal is at low level, so the combined signal output from the OR circuit 611 is at high level. At time t2, the reference signal and the folded signal input to the OR circuit 611 are both at high level, and the combined signal output from the OR circuit 611 is at high level. At time t3, the reference signal input to the OR circuit 611 is at low level, and the folded signal is at high level, so the combined signal output from the OR circuit 611 is at high level. At time t4, the reference signal and the folded back signal input to the OR circuit 611 are both at a low level, so that the combined signal output from the OR circuit 611 is at a low level.

[0027] As shown in Fig. 5, the phase lead detection circuit 62 includes a NOT circuit 621, a logical AND circuit 622, and a flip-flop circuit 623. The NOT circuit 621 is a circuit that inverts the logic of the reference signal input from the reference signal generation circuit 1, and is, for example, a NOT circuit wired to an FPGA. The logical AND circuit 622 is a circuit that calculates the logical AND of the reference signal input from the reference signal generation circuit 1 and the composite signal input from the composite circuit 61, and is, for example, a logical AND circuit wired to an FPGA. The flip-flop circuit 623 is a circuit that latches the signal input from the NOT circuit 621 with the composite signal input from the composite circuit 61, outputs a lead signal, and resets the state with the signal input from the logical AND circuit 622, and is, for example, a D flip-flop circuit wired to an FPGA.

[0028] The phase delay detection circuit 63 includes a NOT circuit 631, a NOR circuit 632, and a flip-flop circuit 633. The NOT circuit 631 is a circuit that inverts the logic of the reference signal input from the reference signal generation circuit 1, and is, for example, a NOT circuit wired to an FPGA. The NOR circuit 632 is a circuit that calculates the NOR of the reference signal input from the reference signal generation circuit 1 and the composite signal input from the composite circuit 61, and is, for example, a NOR circuit wired to an FPGA. The flip-flop circuit 633 is a circuit that latches the composite signal input from the composite circuit 61 with the signal input from the NOT circuit 631, outputs a delay signal, and resets the state with the signal input from the NOR circuit 632, and is, for example, a D flip-flop circuit wired to an FPGA.

[0029] The charge pump circuit 71 includes a current source circuit 711, a current source circuit 712, a switch 713, and a switch 714. The switch 713 is a circuit that is turned on when the lead signal input from the phase lead detection circuit 62 is at a high level and turned off when the lead signal is at a low level, and for example, a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) is used. The switch 714 is a circuit that is turned on when the delay signal input from the phase lag detection circuit 63 is at a high level and turned off when the delay signal is at a low level, and for example, a MOSFET is used. The current source circuit 711 is a circuit that generates a constant current and flows the current from a power supply to the switch 713, and for example, a constant current circuit configured with a MOSFET is used. The current source circuit 712 is a circuit that generates a constant current and flows the current from the switch 714 to the ground, and for example, a constant current circuit configured with a MOSFET is used.

[0030] The loop filter 72 charges when a switch 713 of the charge pump circuit 71 is ON, and discharges when a switch 714 is ON, thereby increasing or decreasing the output voltage and integrating the output from the charge pump circuit 71.

[0031] The OR circuit 611 outputs a composite signal of the reference signal and the return signal to the NOT circuit 621, the AND circuit 622, and the flip-flop circuit 623 of the phase lead detection circuit 62, and to the NOT circuit 631, the NOR circuit 632, and the flip-flop circuit 633 of the phase lag detection circuit 63.

[0032] Here, the operation of the phase lead detection circuit 62, the phase lag detection circuit 63, the charge pump circuit 71, and the loop filter 72 in the steady state will be described with reference to FIG. 7. FIG. 7 is a timing diagram showing the waveforms of the reference signal and the composite signal input to the phase lead detection circuit 62 and the phase lag detection circuit 63 in the steady state, the lead signal output from the phase lead detection circuit 62, the lag signal output from the phase lag detection circuit 63, and the output voltage of the integration circuit 7. At time t0 shown in FIG. 7, the reference signal input to the NOT circuit 621 is at a low level, so the D terminal input signal of the flip-flop circuit 623 is at a high level. In addition, the composite signal input to the CLK terminal of the flip-flop circuit 623 rises, so the lead signal output from the Q terminal is latched to a high level. Furthermore, the reference signal input to the AND circuit 622 is at a low level, and the composite signal is at a high level, so the CLR terminal input signal of the flip-flop circuit 623 is at a low level, and the lead signal is not cleared and is maintained at a high level.

[0033] At time t1, the reference signal input to the AND circuit 622 is at a high level, and the composite signal is at a high level, so that the CLR terminal input signal of the flip-flop circuit 623 is at a high level, and the advance signal is cleared to a low level. At time t2, the composite signal is at a high level, so that the composite signal input to the D terminal of the flip-flop circuit 633 is at a high level. Also, the reference signal input to the NOT circuit 631 falls, so that the CLK terminal input signal of the flip-flop circuit 633 rises, and the delay signal output from the Q terminal is latched to a high level. Furthermore, the reference signal input to the NOR circuit 632 is at a low level, and the composite signal is at a high level, so that the CLR terminal input signal of the flip-flop circuit 633 is at a low level, and the delay signal is not cleared and is maintained at a high level. At time t3, the reference signal input to the NOR circuit 632 is at a low level, and the composite signal is at a low level, so that the CLR terminal input signal of the flip-flop circuit 623 is at a high level, and the delay signal is cleared to a low level.

[0034] From time t0 to t1, the lead signal is at a high level and the lag signal is at a low level, so the switch 713 of the charge pump circuit 71 is ON and the switch 714 is OFF, so that the current source circuit 711 charges the loop filter 72, and the output voltage of the integrator circuit 7 rises. From time t1 to t2, both the lead signal and the lag signal are at a low level, so that both the switch 713 and the switch 714 of the charge pump circuit 71 are OFF, so that the charge is held in the loop filter 72, and the output voltage of the integrator circuit 7 does not change. From time t2 to t3, the lead signal is at a low level and the lag signal is at a high level, so that the switch 713 of the charge pump circuit 71 is OFF and the switch 714 is ON, so that the charge of the loop filter 72 is discharged to the current source circuit 712, and the output voltage of the integrator circuit 7 drops. The output voltage of the integrator circuit 7 is a phase control signal. When the cutoff frequency of the loop filter 72 is set sufficiently lower than the frequency of the reference signal, the output voltage of the integrator circuit 7 becomes a DC voltage, and the phase control signal input to the phase shifter 2 becomes constant.

[0035] Next, the operation of the phase lead detection circuit 62, the phase lag detection circuit 63, the charge pump circuit 71, and the loop filter 72 in a transient state will be described with reference to Fig. 8 and Fig. 9. Fig. 8 is a timing diagram showing the waveforms of the reference signal and the composite signal input to the phase lead detection circuit 62 and the phase lag detection circuit 63, the lead signal output from the phase lead detection circuit 62, the lag signal output from the phase lag detection circuit 63, and the output voltage of the integrating circuit 7 when the phase lag is large. When the composite signal is significantly delayed with respect to the reference signal, the time during which the lag signal is at a high level is longer than the time during which the lead signal is at a high level, so that the output voltage of the integrating circuit 7 decreases. When the phase lag is large, the average value of the output voltage of the integrating circuit 7 decreases, and the phase shift amount of the phase shifter 2 is adjusted by the phase control signal in a direction to eliminate the phase lag.

[0036] 9 is a timing diagram showing the waveforms of the reference signal and the composite signal input to the phase lead detection circuit 62 and the phase lag detection circuit 63, the lead signal output from the phase lead detection circuit 62, the lag signal output from the phase lag detection circuit 63, and the output voltage of the integrating circuit 7 when the phase lag is small. When the lag of the composite signal relative to the reference signal becomes small, the difference between the time when the lead signal is at a high level and the time when the lag signal is at a high level becomes small, so the output voltage of the integrating circuit 7 decreases, but the decrease is more gradual than when the phase lag is large. When the phase of the reference signal and the phase of the return signal become in phase in a steady state, the time when the lead signal is at a high level and the time when the lag signal is at a high level become equal, so the average value of the output voltage of the integrating circuit 7 becomes constant, and the phase shift amount of the phase shifter 2 converges to a fixed value. In other words, the value obtained by subtracting the pulse width of the lag signal from the pulse width of the lead signal corresponds to the phase difference between the reference signal and the return signal. As described above, if the amount of phase shift in the transmission line 4 is ψ, the fixed value of the amount of phase shift in the phase shifter 2 in the steady state is −ψ.

[0037] In the examples of FIGS. 7, 8 and 9, the case where the rising time of the composite signal is earlier than the rising time of the reference signal is shown, but there are also cases where the rising time of the reference signal is earlier than the rising time of the composite signal.

[0038] As described above, according to the first embodiment, since a phase comparator that halves only the phase difference without halving the frequency of the return signal that has returned after traveling back and forth through the transmission line 4 is provided, a mixer circuit is not required, and the circuit scale of the phase synchronization device 100 that keeps the phase of the signal passing through the transmission line 4 in phase at the transmission source and destination can be reduced. Also, the phase of the synchronization signal output from the signal return circuit 5 can be aligned with the phase of the reference signal output from the reference signal generating circuit 1, and the in-phase states can be maintained even if the phase shift amount of the transmission line 4 varies.

[0039] (Embodiment 2) In the phase synchronization device 100 of embodiment 1, the signal separation circuit 3 of the signal transmission circuit 10 and the signal separation circuit 51 of the signal receiving circuit 20 separate the signal to be transmitted and the signal to be received, whereas the signal transmission circuit 10 and the signal receiving circuit 20 of the phase synchronization device 200 of embodiment 2 each include a transmission circuit that transmits a signal and a receiving circuit that receives a signal.

[0040] 10 shows a configuration example of a phase synchronization device 200 according to the second embodiment. The components described in the first embodiment will not be described. The transmission circuit 8a of the signal transmission circuit 10 is a circuit that transmits the reference signal input from the phase shifter 2, and uses, for example, a signal amplifier, an E / O converter, and an SFP (Small Form-factor Pluggable) module. The transmission path 4a transmits the reference signal input from the transmission circuit 8a to the reception circuit 9a of the signal reception circuit 20. For the transmission path 4a, for example, a coaxial cable, a multi-core optical fiber cable, etc. are used.

[0041] The receiving circuit 9a of the signal receiving circuit 20 is a circuit that receives a reference signal input from the transmission line 4a, and for example, uses a low noise amplifier, an O / E converter, an SFP module, etc. The transmitting circuit 8b is a circuit that transmits a return signal input from the distribution circuit 52, and for example, uses a signal amplifier, an E / O converter, an SFP module, etc. The transmission line 4b transmits the return signal input from the signal return circuit 5 to the receiving circuit 9b. The transmission line 4b is a transmission line of the same length as the transmission line 4a, and for example, a coaxial cable, a multi-core optical fiber cable, etc. are used for the transmission line 4b. In other words, the electrical lengths of the transmission lines 4a and 4b are the same. The receiving circuit 9b of the signal transmitting circuit 10 is a circuit that outputs a return signal input from the transmission line 4b to the phase comparator 6, and for example, uses a low noise amplifier, an O / E converter, an SFP module, etc. The transmitting circuit 8a and the receiving circuit 9b are examples of signal input / output circuits.

[0042] Here, the operation of the phase synchronization device 200 will be described. The operation described in the first embodiment will not be described. The transmission circuit 8a shown in FIG. 10 outputs the reference signal input from the phase shifter 2 to the transmission line 4a. At this time, the electrical signal may be converted into an optical signal before being output. The transmission line 4a transmits the reference signal input from the transmission circuit 8a and outputs it to the reception circuit 9a. The reception circuit 9a outputs the reference signal input from the transmission line 4a to the distribution circuit 52. At this time, if the reference signal input from the transmission line 4a is an optical signal, it is converted into an electrical signal before being output. The transmission circuit 8b outputs the return signal input from the distribution circuit 52 to the transmission line 4b. At this time, the electrical signal may be converted into an optical signal before being output. The transmission line 4b transmits the return signal input from the signal return circuit 5 and outputs it to the reception circuit 9b. The reception circuit 9b outputs the return signal input from the transmission line 4b to the phase comparator 6. At this time, if the return signal input from the transmission line 4b is an optical signal, it is converted into an electrical signal before being output.

[0043] Next, the phase of the signal in each circuit will be described. For simplicity, the phase shifts of the transmitting circuits 8a and 8b and the receiving circuits 9a and 9b will be ignored. The phase shift of the transmission line 4a is ψ a , the phase shift of the transmission line 4b is ψ b Then, similarly to the first embodiment, the phase of the return signal output from the receiving circuit 9b and input to the phase comparator 6 is θ0+Φ+ψ a +ψ b The center value of the phase of the reference signal and the phase of the folded signal is {(θ0+Φ)+(θ0+Φ+ψ a +ψ b )} / 2 and the phase of the reference signal is θ0. When the feedback loop is in a converged state, the difference between the two is zero, so {(θ0+Φ)+(θ0+Φ+ψ a +ψ b )} / 2-θ0=0. Since the transmission lines 4a and 4b have the same length, ψ a =ψ b Using this fact, we solve this equation for Φ, and get Φ=-ψ a The phase of the sync signal output from the signal folding circuit 5 is θ0+Φ+ψa However, when the feedback loop has converged, Φ=―ψ a Since the above equation holds, the phase becomes θ0, and the phase becomes the same as the reference signal output from the reference signal generating circuit 1.

[0044] As described above, according to the second embodiment, it is possible to obtain the same effect as that of the first embodiment without using the signal separation circuit 3 and the signal separation circuit 51. For example, an existing SFP module can be used as the transmission circuit 8a and the reception circuit 9b, and the reception circuit 9a and the transmission circuit 8b.

[0045] The phase synchronization device 100 according to the first embodiment and the phase synchronization device 200 according to the second embodiment can be applied to various devices and systems. For example, the phase synchronization device 100 or the phase synchronization device 200 may be applied to a radar device. A radar device 300 to which the phase synchronization device 100 is applied will be described with reference to FIG. 11. Descriptions of the components described in the first and second embodiments will be omitted.

[0046] The radar signal generating circuits 30a to 30c shown in FIG. 11 generate radar signals based on signals input from the signal receiving circuits 20a to 20c. The radar signal generating circuits 30a to 30c use, for example, a PLL (Phase Locked Loop) circuit that multiplies the input signal, and a DA converter that adjusts the frequency, amplitude, and phase of the output signal of the PLL circuit. The phase shifters 40a to 40c shift the phase of the radar signals input from the radar signal generating circuits 30a to 30c, respectively. The phase shifters 40a to 40c use, for example, a phase shifter IC. The antennas 50a to 50c radiate the radar signals input from the phase shifters 40a to 40c, respectively, into space. The antennas 50a to 50c use, for example, a copper foil antenna printed on a board.

[0047] Next, the operation of the radar device 300 will be described. The operation described in the first and second embodiments will not be described. The reference signal generating circuit 1 shown in FIG. 11 generates a reference signal and outputs it to the signal transmitting circuits 10a to 10c in phase. The signal transmitting circuits 10a to 10c correct the phase of the reference signal input from the reference signal generating circuit 1 by the convergence operation of a feedback loop, and output the reference signal to the signal receiving circuits 20a to 20c via the transmission paths 4a to 4c. The signal receiving circuits 20a to 20c output a part of the reference signal input via the transmission paths 4a to 4c, which has been phase-corrected to be in phase with the reference signal output by the reference signal generating circuit 1, as a synchronization signal to the radar signal generating circuits 30a to 30c. The radar signal generating circuits 30a to 30c generate radar signals from the synchronization signals input from the signal receiving circuits 20a to 20c, and output the radar signals to the phase shifters 40a to 40c. The phase shifters 40a to 40c adjust the phases of the radar signals input from the radar signal generation circuits 30a to 30c, respectively, to set array factors of composite antenna patterns formed by the antennas 50a to 50c. The antennas 50a to 50c radiate the radar signals input from the phase shifters 40a to 40c into space.

[0048] As a result, even if the radar signal generation circuits 30a to 30c are arranged in a distributed manner, they can be operated as an active phased array antenna. Even if the phase shift amount of the transmission lines 4a to 4c varies, the phase can be corrected so that the array factor of the active phased array antenna does not change. In the example of Fig. 11, there are three antenna systems, but this is not limiting and two or more systems may be used.

[0049] For example, the phase synchronization device 100 or the phase synchronization device 200 may be applied to an aircraft monitoring device. An aircraft monitoring device 400 to which the phase synchronization device 100 is applied will be described with reference to Fig. 12. Descriptions of the components described in the first and second embodiments will be omitted.

[0050] The receiving devices 60a to 60c shown in FIG. 12 receive signals transmitted from aircraft. For the receiving devices 60a to 60c, for example, a receiving station of a secondary surveillance radar described in a reference (Hiroki Miyazaki et al., "Basic Experimental Results of Wide-Area Multilateration," published at the 10th Electronic Navigation Research Institute Research Presentation (June 2010)) is used. The signal detection time measuring units 70a to 70c detect the arrival time of a signal received from an aircraft based on the rising time of a synchronization signal input from the signal receiving circuits 20a to 20c, respectively, and output detection time information indicating the detection time. For the signal detection time measuring units 70a to 70c, for example, a detector IC that detects the amplitude of a received signal and an FPGA wired to measure the rising time of an output signal from the detector IC are used. The aircraft position calculation unit 80 calculates the position of the aircraft using the detection time information input from the signal detection time measuring units 70a to 70c. The aircraft position calculation unit 80 is, for example, a computer that executes a program stored in a memory using a CPU.

[0051] Next, the operation of the aircraft monitoring device 400 will be described. The operation described in the first and second embodiments will not be described. The receiving devices 60a to 60c each measure the arrival time of a signal received from an aircraft and output it to the aircraft position calculation unit 80. The signal receiving circuits 20a to 20c each output a part of a reference signal, which is input via the transmission paths 4a to 4c and is phase-corrected to be in phase with the reference signal output by the reference signal generating circuit 1, as a synchronization signal to the signal detection time measurement units 70a to 70c. The signal detection time measurement units 70a to 70c each detect the arrival time of a signal received from an aircraft based on the synchronization signal input from the signal receiving circuits 20a to 20c, and output the detection time information to the aircraft position calculation unit 80. The aircraft position calculation unit 80 calculates the position of the aircraft based on the detection time information input from the signal detection time measurement units 70a to 70c.

[0052] In the receiving device described in the reference document, the arrival time of the signal received from the aircraft is detected based on a timing signal generated by a GPS (Global Positioning System) receiver, but in the aircraft monitoring device 400, the synchronization signal output by the signal receiving circuits 20a to 20c is used as the reference, so the position of the aircraft can be estimated even in an environment where GPS radio waves cannot reach. Also, in the receiving device described in the reference document, disturbances such as multipath fading superimposed on the GPS signal cause errors in the accuracy of aircraft position calculation, but since the aircraft monitoring device 400 does not use GPS, it is not affected by this.

[0053] For example, the phase synchronization device 100 or the phase synchronization device 200 may be applied to a time synchronization system. A time synchronization system 500 to which the phase synchronization device 100 is applied will be described with reference to Fig. 13. Descriptions of the components described in the first and second embodiments will be omitted.

[0054] The signal transmission circuit 10 shown in Fig. 13 outputs a reference signal in which the phase of the reference signal input from the reference signal generation circuit 1 is corrected by the convergence operation of a feedback loop. The time synchronization device 90a generates a synchronization signal in phase with the reference signal output from the reference signal generation circuit 1 based on the reference signal, and corrects the time information output from the time synchronization device 903a based on the synchronization signal to obtain accurate time information. The time synchronization device 90a includes a signal receiving circuit 20a, a signal transmission circuit 10a, a time coarse synchronization device 903a, a rising edge comparison circuit 901a, and a time correction circuit 902a.

[0055] The signal receiving circuit 20a outputs a part of the reference signal input via the transmission line 4a as a synchronization signal. The signal transmitting circuit 10a outputs a reference signal obtained by correcting the phase of the synchronization signal input from the signal receiving circuit 20a by the convergence operation of a feedback loop.

[0056] The time coarse synchronizer 903a generates time information and a 1PPS signal. For example, a GPS receiver, an NTP (Network Time Protocol) client, or the like is used for the time coarse synchronizer 903a. The rising edge comparator circuit 901a detects the rising edge times of the synchronization signal input from the signal receiving circuit 20a and the 1PPS (Pulse Per Second) signal input from the time coarse synchronizer 903a, measures the time difference between them, and outputs it. For example, a counter circuit wired in an FPGA is used for the rising edge comparator circuit 901a. The time correction circuit 902a corrects the time information input from the time coarse synchronizer 903a based on the time difference output from the rising edge comparator circuit 901a, and outputs accurate time information. For example, a computer that executes a program stored in a memory with a CPU is used. The configuration of the time synchronization device 90b is omitted because it is similar to that of the time synchronization device 90a.

[0057] Next, the operation of the rough time synchronizer 903a will be described. The operation described in the first and second embodiments will not be described. The signal receiving circuit 20a generates a synchronization signal in phase with the reference signal output by the reference signal generating circuit 1 from the reference signal input via the transmission line 4a, and outputs it to the signal transmitting circuit 10a and the rising edge comparison circuit 901a. The signal transmitting circuit 10a outputs a reference signal in which the phase of the synchronization signal input from the signal receiving circuit 20a is corrected to the time synchronizer 90b via the transmission line 4b. The rough time synchronizer 903a generates a 1PPS signal and outputs it to the rising edge comparison circuit 901a. It also generates time information and outputs it to the time correction circuit 902a. The rising edge comparison circuit 901a detects the rising edge of the synchronization signal input from the signal receiving circuit 20a and the 1PPS signal input from the rough time synchronizer 903a, thereby measuring the time difference between them. It also outputs time difference information indicating the measured time difference to the time correction circuit 902a. The time correction circuit 902a corrects the time information input from the time coarse synchronizer 903a based on the time difference information input from the rising edge comparator 901a, and outputs accurate time information. The operation of the time synchronizer 90b is similar to that of the time synchronizer 90a, so a description thereof will be omitted.

[0058] The synchronization signal output from the signal receiving circuit 20a is phase-corrected by the signal transmitting circuit 10 so that it is in phase with the reference signal output from the reference signal generating circuit 1, and is output to the signal receiving circuit 20b via the transmission line 4b. Similarly, the synchronization signal output from the signal receiving circuit 20b is phase-corrected by the signal transmitting circuit 10a so that it is in phase with the synchronization signal output from the signal receiving circuit 20a, and is output via the transmission line 4c. As a result, in a steady state, the reference signal output from the reference signal generating circuit 1, the synchronization signal output from the signal receiving circuit 20a, and the synchronization signal output from the signal receiving circuit 20b are all in phase.

[0059] The 1PPS signal and time information output from the coarse time synchronizer 903a contain an error in the time direction, the magnitude of which is, for example, about 10 nsec in a GPS receiver. On the other hand, in the time synchronization system 500, for example, if the rising edge comparison circuit 901a is a counter circuit that operates with a 1 GHz clock, the time difference between the rising edge timing of the synchronization signal output from the signal receiving circuit 20a and the 1PPS signal output from the coarse time synchronizer 903a can be measured with a resolution of 1 nsec, and accurate time information can be generated by the time correction circuit 902a. Also, in the time synchronization system 500, the time synchronization devices can be connected in a daisy chain.

[0060] Although the preferred embodiments have been described in detail above, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the claims.

[0061] In the above embodiment, the phase lead detection circuit 62 outputs the time difference between the rising time of the reference signal and the rising time of the composite signal as a lead signal, and the phase lag detection circuit 63 outputs the time difference between the falling time of the reference signal and the falling time of the composite signal as a lag signal, but the present disclosure is not limited to this. For example, the phase lag detection circuit 63 may output the time difference between the rising time of the reference signal and the rising time of the composite signal as a lag signal, and the phase lead detection circuit 63 may output the time difference between the falling time of the reference signal and the falling time of the composite signal as a lead signal.

[0062] Various aspects of the present disclosure are summarized below as appendices.

[0063] (Appendix 1) a reference signal generating unit that outputs a reference signal; a signal transmitting unit that transmits a reference signal obtained by changing the phase of the reference signal based on an error signal; a signal receiving unit that receives the reference signal, outputs the reference signal to the signal transmitting unit as a return signal, and outputs the reference signal as a synchronization signal; a transmission path for transmitting the reference signal and the return signal; Equipped with The signal transmission unit is a phase comparator which receives the reference signal, the reference signal, and the folded signal, generates and outputs the error signal corresponding to a phase difference between the phase of the reference signal and a central value of the phase of the folded signal, and the phase of the reference signal; having Phase synchronizer. (Appendix 2) the signal transmitting unit and the signal receiving unit are a feedback loop circuit in which a phase of the reference signal output by the reference signal generating unit and a phase of the synchronization signal output by the signal receiving unit converge to the same phase. 2. A phase synchronizer as claimed in claim 1. (Appendix 3) The phase comparator includes: a combining circuit for combining the reference signal and the folded signal to output a combined signal; a phase lead detection circuit that outputs a time difference between a rising edge of the reference signal and a rising edge of the composite signal input from the composite circuit as a lead signal; a phase delay detection circuit that outputs a time difference between a falling edge time of the reference signal and a falling edge time of the composite signal input from the composite circuit as a delay signal; Equipped with 3. A phase synchronisation device as claimed in claim 1 or 2. (Appendix 4) The lead signal and the lag signal are the error signals, and a value obtained by subtracting a pulse width of the lag signal from a pulse width of the lead signal corresponds to a phase difference between the reference signal and the return signal. 4. A phase synchronizer as claimed in claim 3. (Appendix 5) The signal transmission unit is an integration circuit that integrates the error signal output from the phase comparator and outputs an integrated value as a phase control signal; a phase shifter that changes the phase of the reference signal based on the phase control signal to generate and output the reference signal; Equipped with 5. A phase synchronization device according to any one of claims 1 to 4. (Appendix 6) The signal transmission unit is an integration circuit that integrates the error signal output from the phase comparator and outputs an integrated value as a phase control signal; a phase shifter that changes the phase of the reference signal based on the phase control signal to generate and output the reference signal; Equipped with The integrating circuit includes: a charge pump circuit which combines the lead signal input from the phase lead detection circuit as a positive signal and the lag signal input from the phase lag detection circuit as a negative signal and outputs the combined signal; a loop filter that integrates an output from the charge pump circuit and outputs the phase control signal to the phase shifter; Equipped with 5. A phase synchronisation device according to claim 3 or 4. (Appendix 7) The signal transmission unit is a signal input / output circuit that outputs the reference signal output from the phase shifter to the signal receiving unit via the transmission path, and outputs the folded signal input from the signal receiving unit via the transmission path to the phase comparator, 7. A phase synchronisation device as claimed in claim 5 or 6. (Appendix 8) The signal receiving unit is a signal separation circuit that separates the reference signal, which is input via the transmission line and output to a distribution circuit, from the folded signal, which is input from the distribution circuit and output to the transmission line; a distribution circuit that distributes the reference signal input from the signal separation circuit, outputs a part of the reference signal to the signal separation circuit, and outputs the remaining part of the reference signal as the synchronization signal; Equipped with 8. A phase synchronization device according to any one of claims 1 to 7. (Appendix 9) the transmission line includes a first transmission line and a second transmission line having the same electrical length as the first transmission line; the reference signal is transmitted through the first transmission path, and the return signal is transmitted through the second transmission path. 9. A phase synchronization device according to any one of claims 1 to 8. (Appendix 10) the signal transmitting unit, the signal receiving unit, and the transmission path are each provided in a plurality of units, The plurality of signal transmitting units and the plurality of signal receiving units are connected in a daisy chain via the plurality of transmission paths, 10. A phase synchronization device according to any one of claims 1 to 9. (Appendix 11) a signal transmitting circuit that transmits a transmission signal inputted through a transmission line to a signal receiving circuit that transmits the transmission signal as a return signal through the transmission line and outputs the transmission signal as a synchronization signal, and receives the return signal from the signal receiving circuit through the transmission line, a phase shifter that outputs a reference signal obtained by changing the phase of a reference signal output from a reference signal generating circuit; a signal input / output circuit that outputs the reference signal output from the phase shifter to the signal receiving circuit via the transmission path as the transmission signal, and outputs the folded signal input from the signal receiving circuit via the transmission path; a phase comparator that generates and outputs an error signal corresponding to a phase difference between a center value of the phase of the reference signal and the phase of the return signal and the phase of the reference signal; an integration circuit that integrates the error signal output from the phase comparator and outputs a phase control signal that controls a phase shift amount of the phase shifter; Equipped with The phase shifter generates the reference signal by changing a phase of the reference signal based on the phase control signal input from the integrating circuit. Signal transmission circuit. (Appendix 12) A reference signal is output from the reference signal generating unit, a reference signal obtained by changing the phase of the reference signal based on the error signal is transmitted from a signal transmitting unit; receiving the reference signal, and outputting the reference signal as a return signal and a synchronization signal from a signal receiving unit; Transmitting the reference signal and the return signal via a transmission path; In the signal transmission unit, the reference signal, the reference signal, and the folded signal are input, and the error signal corresponding to a phase difference between the phase of the reference signal and a central value of the phase of the folded signal, and the phase of the reference signal is generated and output; A phase synchronization method for a phase synchronization device. [Explanation of symbols]

[0064] 1 Reference signal generating circuit, 2 Phase shifter, 3 Signal separation circuit, 4, 4a to 4c Transmission path, 5 Signal folding circuit, 6 Phase comparator, 7 Integration circuit, 8a, 8b Transmission circuit, 9a, 9b Receiving circuit, 10, 10a to 10c Signal transmission circuit, 20, 20a to 20c Signal receiving circuit, 30a to 30c Radar signal generating circuit, 40a to 40c Phase shifter, 50a to 50c Antenna, 51 Signal separation circuit, 52 Distribution circuit, 60a to 60c Receiving device, 61 Synthesis circuit, 62 Phase lead detection circuit, 63 Phase lag detection circuit, 70a to 70c Signal detection time measurement unit, 71 Charge pump circuit, 72 Loop filter, 80 Aircraft position calculation unit, 90a, 90b Time synchronization device, 100, 200 Phase synchronization device, 300 Radar device, 400 aircraft monitoring device, 500 time synchronization system, 611 logical OR circuit, 621 NOT circuit, 622 logical AND circuit, 623 flip-flop circuit, 631 NOT circuit, 632 NOR circuit, 633 flip-flop circuit, 711 current source circuit, 712 current source circuit, 713 switch, 714 switch, 901a, 901b rise comparison circuit, 902a, 902b time correction circuit, 903a, 903b time coarse synchronization device.

Claims

1. a reference signal generating unit that outputs a reference signal; a signal transmitting unit that transmits a reference signal obtained by changing the phase of the reference signal based on an error signal; a signal receiving unit that receives the reference signal, outputs the reference signal to the signal transmitting unit as a return signal, and outputs the reference signal as a synchronization signal; a transmission path for transmitting the reference signal and the return signal; Equipped with The signal transmission unit is a phase comparator which receives the reference signal, the reference signal, and the folded signal, generates and outputs the error signal corresponding to a phase difference between the phase of the reference signal and a center value of the phase of the folded signal, and the phase of the reference signal; having Phase synchronizer.

2. the signal transmitting unit and the signal receiving unit are a feedback loop circuit in which a phase of the reference signal output by the reference signal generating unit and a phase of the synchronization signal output by the signal receiving unit converge to the same phase.

2. The phase synchronizer according to claim 1.

3. The phase comparator includes: a combining circuit for combining the reference signal and the folded signal to output a combined signal; a phase lead detection circuit that outputs a time difference between a rising edge of the reference signal and a rising edge of the composite signal input from the composite circuit as a lead signal; a phase delay detection circuit that outputs a time difference between a falling edge time of the reference signal and a falling edge time of the composite signal input from the composite circuit as a delay signal; Equipped with 3. A phase synchronization device according to claim 1 or 2.

4. The lead signal and the lag signal are the error signals, and a value obtained by subtracting a pulse width of the lag signal from a pulse width of the lead signal corresponds to a phase difference between the reference signal and the return signal.

4. The phase synchronizer according to claim 3.

5. The signal transmission unit is an integration circuit that integrates the error signal output from the phase comparator and outputs an integrated value as a phase control signal; a phase shifter that changes the phase of the reference signal based on the phase control signal to generate and output the reference signal; Equipped with 3. A phase synchronization device according to claim 1 or 2.

6. The signal transmission unit is an integration circuit that integrates the error signal output from the phase comparator and outputs an integrated value as a phase control signal; a phase shifter that changes the phase of the reference signal based on the phase control signal to generate and output the reference signal; Equipped with The integrating circuit includes: a charge pump circuit which combines the lead signal input from the phase lead detection circuit as a positive signal and the lag signal input from the phase lag detection circuit as a negative signal and outputs the combined signal; a loop filter that integrates an output from the charge pump circuit and outputs the phase control signal to the phase shifter; Equipped with 4. The phase synchronizer according to claim 3.

7. The signal transmission unit is a signal input / output circuit that outputs the reference signal output from the phase shifter to the signal receiving unit via the transmission path, and outputs the folded signal input from the signal receiving unit via the transmission path to the phase comparator, 6. The phase synchronizer according to claim 5.

8. The signal receiving unit is a signal separation circuit that separates the reference signal, which is input via the transmission line and output to a distribution circuit, from the folded signal, which is input from the distribution circuit and output to the transmission line; a distribution circuit that distributes the reference signal input from the signal separation circuit, outputs a part of the reference signal to the signal separation circuit, and outputs the remaining reference signal as the synchronization signal; Equipped with 3. A phase synchronization device according to claim 1 or 2.

9. the transmission line includes a first transmission line and a second transmission line having the same electrical length as the first transmission line; the reference signal is transmitted through the first transmission path, and the return signal is transmitted through the second transmission path.

3. A phase synchronization device according to claim 1 or 2.

10. the signal transmitting unit, the signal receiving unit, and the transmission path are each provided in a plurality of units, The plurality of signal transmitting units and the plurality of signal receiving units are connected in a daisy chain via the plurality of transmission paths, 3. A phase synchronization device according to claim 1 or 2.

11. a signal transmitting circuit that transmits a transmission signal inputted through a transmission line to a signal receiving circuit that transmits the transmission signal as a return signal through the transmission line and outputs the transmission signal as a synchronization signal, and receives the return signal from the signal receiving circuit through the transmission line, a phase shifter that outputs a reference signal obtained by changing the phase of a reference signal output from a reference signal generating circuit; a signal input / output circuit that outputs the reference signal output from the phase shifter to the signal receiving circuit via the transmission path as the transmission signal, and outputs the folded signal input from the signal receiving circuit via the transmission path; a phase comparator that generates and outputs an error signal corresponding to a phase difference between a center value of the phase of the reference signal and the phase of the return signal and the phase of the reference signal; an integration circuit that integrates the error signal output from the phase comparator and outputs a phase control signal that controls a phase shift amount of the phase shifter; Equipped with The phase shifter generates the reference signal by changing a phase of the reference signal based on the phase control signal input from the integrating circuit. Signal transmission circuit.

12. A reference signal is output from the reference signal generating unit, a reference signal obtained by changing the phase of the reference signal based on the error signal is transmitted from a signal transmitting unit; receiving the reference signal, and outputting the reference signal as a return signal and a synchronization signal from a signal receiving unit; Transmitting the reference signal and the return signal via a transmission path; In the signal transmission unit, the reference signal, the reference signal, and the folded signal are input, and the error signal corresponding to a phase difference between the phase of the reference signal and a central value of the phase of the folded signal, and the phase of the reference signal is generated and output; A phase synchronization method for a phase synchronization device.

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