Signal transmission circuit and power conversion device

Abstract

To allow signals to be transmitted properly.SOLUTION: A signal transmission circuit includes a first circuit, a transformer, and a second circuit. The first circuit allows a first signal to be input, generates a transmission signal according to a change in a logical value of the first signal, and uses a first potential as a reference for operation. The transformer includes a first coil to which the transmission signal is input from the first circuit, and a second coil that is inductively coupled with the first coil to output a pair of reception signals. The second circuit allows a pair of reception signals to be input from the second coil, performs a comparison with hysteresis on the potential difference between the pair of reception signals to generate a second signal, and uses a second potential as a reference for operation. The second circuit includes a detection circuit that performs a comparison to detect whether the potential difference exceeds a prescribed range and outputs its result as the second signal, and a reset circuit that resets the operation of the detection circuit when a logical value of the second signal is maintained for a preset period.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a signal transmission circuit and a power conversion device. [Background technology]

[0002] The signal transmission circuit disclosed in Patent Document 1 includes a transformer having a first coil and a second coil, a first circuit connected to the first coil, and a second circuit connected to the second coil. A first signal is input to the first circuit. A second signal is output from the second circuit.

[0003] The second circuit includes a detection circuit, two rectifier circuits, a control circuit, and two output resistors. The detection circuit detects a voltage signal generated at each end of the second coil, and generates and outputs a second signal based on the voltage signal. The control circuit controls the control voltage provided to the two rectifier circuits, and controls the bias voltage sent to each of them via the output resistor.

[0004] The power conversion device disclosed in Patent Document 1 includes two of the above-mentioned signal transmission circuits, two switching elements, and two driver units. The second circuit of each signal transmission circuit is connected to the input terminal of the corresponding driver unit. The output terminal of each driver unit is connected to the input terminal of the corresponding switching element. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2018 / 066165 Summary of the Invention [Problem to be solved by the invention]

[0006] The voltage across the second coil fluctuates due to, for example, the opening and closing of a switching element. Suppressing the fluctuation in the voltage across the second coil contributes to suppressing malfunction of a detection circuit connected to the second coil, and ultimately to suppressing malfunction of the opening and closing of the switching element.

[0007] In order to suppress the fluctuation of the voltage across the second coil and thus to suppress the malfunction of the second circuit, control of the control voltage and bias voltage applied to the two rectifier circuits is adopted. When the time change in potential due to the opening and closing of the switching element is significant, it is expected that the opening and closing of the switching element will not be able to prevent the malfunction of the second circuit. Suppressing the occurrence of such an event is desirable from the viewpoint of the second signal reflecting the first signal in the signal transmission circuit and thus suppressing the malfunction of the opening and closing of the switching element in the power conversion device.

[0008] The signal transmission circuit according to the present disclosure aims to transmit a signal appropriately, and the power conversion device according to the present disclosure aims to suppress malfunction of a switching element thereof. [Means for solving the problem]

[0009] A signal transmission circuit according to the present disclosure comprises: a first circuit which receives a first signal, generates a transmission signal corresponding to a change in the logical value of the first signal, and uses a first potential as a reference for operation; a transformer having a first coil to which the transmission signal is input from the first circuit, and a second coil which is inductively coupled with the first coil to output a pair of reception signals; and a second circuit which receives the pair of reception signals from the second coil, generates a second signal by performing a comparison with hysteresis on the potential difference between the pair of reception signals, and uses a second potential as a reference for operation.

[0010] In a first aspect of the signal transmission circuit, the second circuit has: a detection circuit that performs the comparison to detect whether the potential difference exceeds a predetermined range or not, and outputs the result as the second signal; and a reset circuit that resets the operation of the detection circuit when the logical value of the second signal is maintained for a predetermined period.

[0011] A second aspect of the signal transmission circuit according to the present disclosure is the first aspect, wherein the second circuit further includes an offset circuit that generates a pair of third signals by applying a DC voltage based on the second potential as an offset voltage to the pair of received signals, and the detection circuit generates the second signal by performing the comparison with respect to the potential difference between the pair of third signals generated by the offset circuit.

[0012] A third aspect of the signal transmission circuit according to the present disclosure is the second aspect, wherein the offset circuit has: a first input terminal to which one of the pair of received signals is input; a second input terminal to which the other of the pair of received signals is input; a first output terminal to which one of the pair of third signals is input; a second output terminal to which the other of the pair of third signals is input; a first resistor having one end connected to the first output terminal and the other end to which the DC voltage is applied; a second resistor having one end connected to the second output terminal and the other end to which the DC voltage is applied; a first capacitor connected between the first input terminal and the first output terminal; and a second capacitor connected between the second input terminal and the second output terminal.

[0013] A fourth aspect of the signal transmission circuit according to the present disclosure is the third aspect, wherein the second circuit further includes a first clamp circuit and a second clamp circuit connected in series between the first input terminal and the second input terminal. The first clamp circuit includes: a first diode; a second diode connected in parallel with the first diode and having a forward direction opposite to that of the first diode; and a first current limiting resistor connected in series with each of the first diode and the second diode. The second clamp circuit includes: a third diode; a fourth diode connected in parallel with the third diode and having a forward direction opposite to that of the third diode; and a second current limiting resistor connected in series with each of the third diode and the fourth diode.

[0014] A fifth aspect of the signal transmission circuit according to the present disclosure is any of the first to fourth aspects, in which the first circuit includes: a pulse generation circuit that generates a fourth signal generated by a first pulse train having a plurality of pulses in a portion of a period in which the first signal has a first logical value, and a second pulse train having a plurality of pulses following the first pulse train in that portion; and an output circuit that generates the transmission signal in response to a change in the logical value of the fourth signal. One period of the pulses in the second pulse train is longer than one period of the pulses in the first pulse train.

[0015] A sixth aspect of the signal transmission circuit according to the present disclosure is the fifth aspect, in which the output circuit includes a transistor having a first electrode to which a fixed potential is applied, a second electrode that outputs the transmission signal, and a third electrode to which the fourth signal is applied and that controls conduction between the first electrode and the second electrode, and the first circuit further includes a third resistor having one end connected to one end of the first coil and the other end to which the fixed potential is applied.

[0016] A seventh aspect of the signal transmission circuit according to the present disclosure is the fifth aspect, in which the output circuit includes: a first transistor having a first electrode to which a fixed potential is applied, a second electrode that outputs the transmission signal, and a third electrode to which the fourth signal is applied and that controls conduction between the first electrode and the second electrode. The first circuit further includes: a second transistor in an on state having a first electrode connected to one end of the first coil and a second electrode to which the fixed potential is applied.

[0017] A first aspect of the power conversion device according to the present disclosure includes: an output line; a first switching element having one end to which a fixed potential is applied and the other end connected to the output line; a second switching element having one end connected to the output line and the other end to which a third potential is applied, and turned on exclusively with the first switching element; a first signal transmission circuit adopting any of the first to fifth aspects of the signal transmission circuit according to the present disclosure; a second signal transmission circuit adopting any of the first to fifth aspects of the signal transmission circuit according to the present disclosure; and a first latch circuit that outputs a signal for controlling whether or not the first switching element is conductive, is set by the second signal output by the first signal transmission circuit, and is reset by the second signal output by the second signal transmission circuit. Both the second potential in the first signal transmission circuit and the second potential in the second signal transmission circuit are the potential of the output line.

[0018] A second aspect of the power conversion device according to the present disclosure is the first aspect thereof, further comprising: a third signal transmission circuit adopting any one of the first to fifth aspects of the signal transmission circuit according to the present disclosure; a fourth signal transmission circuit adopting any one of the first to fifth aspects of the signal transmission circuit according to the present disclosure; and a second latch circuit outputting a signal for controlling whether or not the second switching element is conductive, the second latch circuit being set by the second signal output by the third signal transmission circuit and being reset by the second signal output by the fourth signal transmission circuit. Both the second potential in the third signal transmission circuit and the second potential in the fourth signal transmission circuit are the third potential. Effect of the Invention

[0019] According to the first aspect of the signal transmission circuit of the present disclosure, a signal is transmitted appropriately.

[0020] According to the second aspect of the signal transmission circuit of the present disclosure, the influence of fluctuations in the second potential is reduced compared to when comparison is performed based on a pair of received signals.

[0021] According to a third aspect of the signal transmission circuit of the present disclosure, the input impedance of the second circuit can be adjusted by setting the impedance of each of the first resistor, the second resistor, the first capacitor, and the second capacitor. Such adjustment increases the potential difference between a pair of received signals. Such adjustment suppresses fluctuations in the DC voltage.

[0022] According to the fourth aspect of the signal transmission circuit of the present disclosure, increases and decreases in a pair of received signals are limited.

[0023] According to the fifth aspect of the signal transmission circuit of the present disclosure, the first pulse train appropriately reflects the first signal in the second signal, and the second pulse train increases the reliability of signal transmission while reducing current consumption.

[0024] According to the sixth aspect of the signal transmission circuit of the present disclosure, the difference between the displacement current flowing in one end of the first coil and the displacement current flowing in the other end of the first coil is reduced, thereby suppressing malfunctions caused by the difference.

[0025] According to the seventh aspect of the signal transmission circuit of the present disclosure, the difference between the displacement current flowing in one end of the first coil and the displacement current flowing in the other end of the first coil is reduced, and malfunctions caused by this difference are suppressed over a wide temperature range.

[0026] The advantages of the signal transmission circuit according to the present disclosure can be obtained by either the first or second aspect of the power conversion device according to the present disclosure. [Brief description of the drawings]

[0027] [Figure 1] 1 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000 according to a first embodiment. [Diagram 2] 3 is a waveform diagram illustrating the temporal changes of various signals according to the first embodiment. FIG. [Diagram 3] 11 is a waveform diagram illustrating the advantage of providing a self-reset circuit 241. FIG. [Figure 4]FIG. 11 is a circuit diagram illustrating a configuration of a power conversion device 2000 according to a second embodiment. [Diagram 5] 1 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000a. [Figure 6] 1 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000b. [Figure 7] 1 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000x. [Figure 8] 1 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000y. [Figure 9] 3 is a waveform diagram illustrating the temporal changes of various signals in the signal transmission circuits 1000a and 1000b. [Figure 10] 10A to 10C are waveform diagrams illustrating examples of changes over time in various signals in signal transmission circuits 1000x and 1000y. [Figure 11] 1 is a graph illustrating the rectification characteristics of a diode. [Figure 12] 13 is a waveform diagram illustrating various signals in the third embodiment. FIG. [Figure 13] 11 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000 to which a first circuit 100 according to a fourth embodiment is applied. FIG. [Figure 14] FIG. 11 is a circuit diagram showing a path through which a displacement current Idev2 flows. [Figure 15] 1 is a circuit diagram showing a path through which a displacement current Idev1 flows. [Figure 16] 11 is a waveform diagram illustrating the temporal changes of various signals in the first circuit 100 according to the fourth embodiment. FIG. [Figure 17] 11 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000 to which a first circuit 100 according to a fifth embodiment is applied. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] <1. Signal transmission circuit> A first embodiment of the present disclosure relates to a signal transmission circuit. Fig. 1 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000 according to a first embodiment.

[0029] The signal transmission circuit 1000 includes an input terminal 50, a first circuit 100, a transformer 10, a second circuit 200, and an output terminal 51. The input terminal 50 may be considered to be included in the first circuit 100. The output terminal 51 may be considered to be included in the second circuit 200.

[0030] <1-1. 1st circuit 100> The first circuit 100 has a pulse generating circuit 101 and an output circuit 102. A first signal S1 is input to the first circuit 100 via an input terminal 50. The first signal S1 indicates two logical values. Ideally, the first signal S1 is a square wave, but may be a waveform with a gentle curve that allows the pulse generating circuit 101 to discriminate between the two logical values.

[0031] <1-2. Pulse generating circuit 101> The pulse generating circuit 101 outputs a signal J1 according to a change in the value of the first signal S1. Specifically, the pulse generating circuit 101 distinguishes the value of the first signal S1 into two logical values, "H" and "L". When the first signal S1 transitions from "L" to "H", the pulse generating circuit 101 outputs a train of multiple pulses (hereinafter, simply referred to as a "pulse train") or a single pulse in the signal J1. The following mainly describes the case where a pulse train is generated in the signal J1.

[0032] When the first signal S1 transitions from "H" to "L", the pulse generating circuit 101 stops outputting the pulse train in the signal J1. The pulse generating circuit 101 is realized by, for example, a multivibrator.

[0033] The so-called pulse width of the pulse in the signal J1, here the length of the period during which the pulse is at "H", has a specified value. The specified value is shorter than the expected period between adjacent transitions of two logic values ​​in the first signal S1 in the opposite directions. The pulse train continues to be generated when the first signal S1 transitions from "L" to "H", and the generation of the pulse train stops when the first signal S1 transitions from "H" to "L".

[0034] <1-3. Output circuit 102> The output circuit 102 receives the signal J1 and outputs a transmission signal VT2 that reflects the signal J1. Since the output circuit 102 is a component of the first circuit 100 together with the pulse generating circuit 101, the transmission signal VT2 can be said to be a signal that corresponds to the waveform of the first signal S1 that is generated by the first circuit 100 and input to the first circuit 100, specifically, a signal that corresponds to a change in its logical value.

[0035] For example, the output circuit 102 is realized by an inverter having field effect transistors (hereinafter also simply referred to as "transistors") 103 and 104. For example, a P-channel type transistor is used as the transistor 103, and for example, an N-channel type transistor is used as the transistor 103.

[0036] The transistor 103 has a gate, a source, and a drain. The source and drain can be considered as a first electrode and a second electrode that are mutually conductive by a signal applied to the gate. The gate can be considered as a third electrode that controls the conduction between the first electrode and the second electrode. Similarly, the transistor 104 has a source as a first electrode, a drain as a second electrode, and a gate as a third electrode.

[0037] A signal J1 is applied to both the gate of transistor 103 and the gate of transistor 104. The drain of transistor 103 and the drain of transistor 104 are connected to each other, and the potentials of these drains are output from output circuit 102 and therefore from first circuit 100 as transmission signal VT2. The potentials of these drains are based on potential G1. Specifically, potential G1 of first circuit 100 is applied to the source of transistor 104, and a fixed potential VCC higher than potential G1 is applied to the source of transistor 103. In this way, the operation of first circuit 100 is based on potential G1. Potential VT1 of the source of transistor 103 is output from output circuit 102 and therefore from first circuit 100.

[0038] The transformer 10 has a first coil 11 and a second coil 12. The first coil 11 and the second coil 12 are inductively coupled. The transformer 10 has a first end P1, a second end P2, a third end P3, and a fourth end P4. One end of the first coil 11 is connected to the first end P1, and the other end is connected to the second end P2. One end of the second coil 12 is connected to the third end P3, and the other end is connected to the fourth end P4. A parasitic capacitance Cp exists between the first end P1 side of the first coil 11 and the third end P3 side of the second coil 12, and between the second end P2 side of the first coil 11 and the fourth end P4 side of the second coil 12.

[0039] The first terminal P1 is connected to the source of the transistor 103, and receives a potential VT1 from the first circuit 100. The second terminal P2 is connected to the drain of the transistor 103 and the drain of the transistor 104, and receives a transmission signal VT2 from the first circuit 100.

[0040] When the pulse rises in the signal J1, the transistor 103 transitions from an on state to an off state, and the transistor 104 transitions from an off state to an on state. A potential VT1 is output from the first circuit 100, and a potential G1 is output as a transmission signal VT2. A current flows through the first coil 11 from the first terminal P1 to the second terminal P2. When the current starts to flow, an increase in the current causes the potential of the third terminal P3 to rise so as to prevent the increase, and the potential of the fourth terminal P4 to fall.

[0041] When the pulse of the signal J1 falls, the transistor 103 transitions from an off state to an on state, and the transistor 104 transitions from an on state to an off state. Both ends of the first coil 11 are shorted via the transistor 103 in the first circuit 100, and the current flowing through the first coil 11 is reduced. Due to this reduction, the potential of the third terminal P3 decreases and the potential of the fourth terminal P4 increases so as to prevent this reduction.

[0042] The potential of the third terminal P3 is input to the second circuit 200 as a receiving signal VR1. The potential of the fourth terminal P4 is input to the second circuit 200 as a receiving signal VR2. The second coil 12 outputs a pair of receiving signals VR1, VR2. The reference potential of the receiving signals VR1, VR2 is a potential G2 that is the reference for the operation of the second circuit 200. The potential difference between the potentials G1, G2 may vary.

[0043] <1-4.Second circuit 200> The second circuit 200 includes a detection circuit 240, an offset circuit 220, and clamp circuits 205 and 206. The potential that serves as a reference for the operation of the second circuit 200 is potential G2.

[0044] The offset circuit 220 has input terminals P5 and P6 and output terminals P7 and P8. A received signal VR1 is provided to the input terminal P5, and a received signal VR2 is provided to the input terminal P6. A signal VRO1 is output from the output terminal P7, and a signal VRO2 is output from the output terminal P8. The offset circuit 220 provides an offset voltage to the received signals VR1 and VR2 to generate signals VRO1 and VRO2, respectively.

[0045] <1-5.Detection circuit 240> The detection circuit 240 has input terminals P9 and P10 and an output terminal P11. A signal VRO1 is applied to the input terminal P9, and a signal VRO2 is applied to the input terminal P10. A second signal S2 is output from the output terminal P11. The second signal S2 is output from an output terminal 51. The detection circuit 240 operates with a potential G2 as a reference.

[0046] The second signal S2 takes potentials corresponding to two logical values ​​"H" and "L" depending on the potential difference between the signals VRO1 and VRO2, specifically, the value obtained by subtracting the potential of the signal VRO2 from the potential of the signal VRO1 (hereinafter tentatively referred to as the "subtraction voltage value") ΔV. Specifically, the detection circuit 240: (i) raises the logical value of the second signal S2 from "L" to "H" when the subtraction voltage value ΔV changes from a state less than a positive first threshold to a state equal to or greater than the first threshold; (ii) lowers the logical value of the second signal S2 from "H" to "L" when the subtraction voltage value ΔV changes from a state greater than a negative second threshold to a state equal to or less than the second threshold; (iii) maintains the logical value of the second signal S2 even if there is a change in the subtraction voltage value ΔV other than the above (i) and (ii); and (iv) sets the logical value of the second signal S2 to "L" by resetting, taking precedence over the above operations (i) to (iii).

[0047] In view of this operation, the signals VRO1 and VRO2 can be considered as a pair of detection signals. The detection circuit 240 performs a comparison with a hysteresis between the pair of reception signals VR1 and VR2 using a first threshold value and a second threshold value to detect whether the potential difference between the pair of reception signals VR1 and VR2 exceeds a predetermined range, and generates the result of the detection as a second signal S2.

[0048] For example, the detection circuit 240 is realized by a hysteresis comparator or a Schmitt trigger circuit. Potentials G2 and VCC are applied to the detection circuit 240, and the potential difference between the two is the operating voltage of the detection circuit 240. The potential VCC applied to the detection circuit 240 is higher than the potential G2. The potential VCC applied to the detection circuit 240 and the potential VCC applied to the output circuit 102 may be different.

[0049] <1-6. Offset circuit 220> The offset circuit 220 has voltage dividing resistors 223 and 224 and capacitors 221 and 222. The voltage dividing resistor 223 and the capacitor 221 constitute an RC high-pass filter, and have the effect of removing low-frequency noise and DC components from the received signal VR1. The voltage dividing resistor 224 and the capacitor 222 constitute an RC high-pass filter, and have the effect of removing low-frequency noise and DC components from the received signal VR2.

[0050] Specifically, capacitor 221 is connected between input terminal P5 and output terminal P7, and capacitor 222 is connected between input terminal P6 and output terminal P8. One end of voltage-dividing resistor 223 is connected to output terminal P7. One end of voltage-dividing resistor 224 is connected to output terminal P8. The other end of voltage-dividing resistor 223 and the other end of voltage-dividing resistor 224 are, for example, connected together, and a DC voltage D1 based on potential G2 is applied to both of them as an offset voltage (which can also be seen as a bias voltage).

[0051] Since the DC voltage D1 is applied as an offset voltage to both of the reception signals VR1 and VR2 to generate the signals VRO1 and VRO2, the subtraction voltage value ΔV can be considered to be the potential difference between the reception signals VR1 and VR2, specifically, the value obtained by subtracting the potential of the reception signal VR2 from the potential of the reception signal VR1. From this perspective, the second circuit 200 can be considered to perform a comparison having hysteresis on the potential difference between the pair of reception signals VR1 and VR2, and generate the second signal S2 as a result of the comparison.

[0052] The detection circuit 240 performing the above comparison based on a pair of signals VRO1, VRO2 contributes to reducing the influence of fluctuations in potential G2, and ultimately the influence of voltage fluctuations Vdif, which will be described later, more than when the comparison is performed based on a pair of received signals VR1, VR2.

[0053] For example, the offset circuit 220 has a DC offset voltage circuit 225. The DC offset voltage circuit 225 outputs a DC voltage D1 with respect to the potential G2. The DC offset voltage circuit 225 is realized by, for example, a known DC voltage source. The DC offset voltage circuit 225 may be provided outside the offset circuit 220.

[0054] The DC voltage D1 is set to, for example, the median value of the voltage range (hereinafter tentatively referred to as the "appropriate voltage range") of the input terminals P9 and P10 in which the detection circuit 240 can appropriately perform the above-mentioned operation. The DC voltage D1 may alternatively be set according to the characteristics of the received signals VR1 and VR2 and the performance of the detection circuit 240.

[0055] For example, when the appropriate voltage range is 0 to 5 V with respect to the potential G2, the maximum value of the receiving signal VR1 is 1 V, and the minimum value of the receiving signal VR2 is -1 V, 2.5 V is adopted for the DC voltage D1. With this adoption, the maximum value of the signal VRO1 becomes 3.5 V, and a margin of 1.5 (= 5 - 3.5) V is obtained for the upper limit of the appropriate voltage range. With this adoption, the minimum value of the signal VRO2 becomes 1.5 V, and a margin of 1.5 (= 1.5 - 0) V is obtained for the lower limit of the appropriate voltage range.

[0056] For example, when the appropriate voltage range is 0 to 5 V with respect to the potential G2, the maximum value of the receiving signal VR1 is 1.2 V, and the minimum value of the receiving signal VR2 is −0.8 V, 2.3 V is adopted for the DC voltage D1. By adopting this, a margin of 1.5 V is obtained at both the upper and lower limits of the appropriate voltage range.

[0057] For example, when the appropriate voltage range is 1 to 5 V with respect to the potential G2, the maximum value of the receiving signal VR1 is 1 V, and the minimum value of the receiving signal VR2 is −1 V, 3 V is adopted for the DC voltage D1. By adopting this, a margin of 1 V is obtained at both the upper and lower limits of the appropriate voltage range.

[0058] The voltage dividing resistors 223, 224 and the transformer 10, more specifically, the voltage dividing resistors 223, 224 and the second coil 12 are connected via the capacitors 221, 222. Due to the presence of the capacitors 221, 222, even if the impedance of the voltage dividing resistors 223, 224 is small, the fluctuation of the received signals VR1, VR2 is unlikely to become small, and even if the impedance of the voltage dividing resistors 223, 224 is large, the fluctuation of the DC voltage D1 is suppressed. Therefore, there is a design advantage in that the voltage dividing resistors 223, 224 are easily designed.

[0059] The input impedance of the second circuit 200 can be adjusted by setting the offset circuit 220, specifically, by setting the impedance of each of the voltage dividing resistors 223 and 224 and the capacitors 221 and 222. Such adjustment contributes to increasing the potential difference between the received signals VR1 and VR2.

[0060] For example, the values ​​of the capacitors 221 and 222 can be adjusted to match the impedance between the second circuit 200 and the transformer 10, and the potential difference between the received signals VR1 and VR2 can be adjusted. Impedance matching contributes to improving the S / N ratio. Even in this case, the fluctuation of the DC voltage D1 described above can be suppressed, and design advantages can be obtained.

[0061] Fig. 2 is a waveform diagram illustrating the time-dependent changes of various signals. Specifically, Fig. 2 illustrates the waveforms of the logical value of the first signal S1, the logical value of the signal J1, the received signals VR1 and VR2, the signals VRO1 and VRO2, and the logical value of the second signal S2. Fig. 2 also illustrates the waveform of the voltage fluctuation Vdif, which will be described later.

[0062] The logical value of the first signal S1 transitions (rises) from "L" to "H" at time t_on, and transitions (falls) from "H" to "L" at time t_off.

[0063] The signal J1 outputs a pulse train during a period in which the logical value of the first signal S1 is "H". Fig. 2 illustrates an example in which the signal J1 outputs four pulses during a period in which the logical value of the first signal S1 is "H". Due to the function of the output circuit 102, the logical value of the transmission signal VT2 is inverted from the logical value of the signal J1, and the logical value of the signal J1 is the inversion of the logical value of the transmission signal VT2. In Fig. 2, the inversion of the logical value of the transmission signal VT2 is indicated together with the signal J1 by adding an overline to the symbol "VT2".

[0064] Both of the received signals VR1 and VR2 fluctuate with respect to the potential G2. At the time when the pulse in the signal J1 rises, a current flows from the first terminal P1 to the second terminal P2 in the first coil 11, so that at that time, the received signal VR1 rises once and the received signal VR2 falls once, and then each shows an attenuating waveform. At this time, introducing the current i flowing in the first coil 11 and the mutual inductance L between the first coil 11 and the second coil 12, the value of the received signal VR1 is expressed as L (di / dt) and the value of the received signal VR2 is expressed as -L (di / dt).

[0065] At the point when the pulse of signal J1 falls, received signal VR1 falls once and received signal VR2 rises once, then each exhibits an attenuating waveform. At this time, the value of received signal VR1 is expressed as -L (di / dt), and the value of received signal VR2 is expressed as L (di / dt).

[0066] In this way, the current i functions similarly to the transmission signal VT2 in that it responds to changes in the logical value of the first signal S1, since the value of its time derivative (di / dt) determines the reception signals VR1 and VR2. It can be said that the first circuit 100 generates the current i in response to changes in the logical value of the first signal S1, and the current i is input from the first circuit 100 to the first coil 11. For example, it can be said that the transmission signal VT2 is output from the drain of the transistor 104 as the drain potential of the transistor 104, and the current i is a transmission signal that is output from the drain of the transistor 104 as a current flowing through the drain of the transistor 104.

[0067] In the period when the voltage fluctuation Vdif is rising (hereinafter referred to as the "rising period"), the received signal VR2 rises at the time when the pulse in the signal J1 rises, and then attenuates. The voltage fluctuation Vdif indicates the voltage of the potential G1 based on the potential G2. Specifically, when a voltage fluctuation amount per unit time (hereinafter also simply described as "time differential") dv / dt occurs in the potential G2 based on the potential G1, a voltage determined by the product of a certain time constant and the time differential dv / dt corresponds to the voltage fluctuation Vdif. The time constant is the product of the capacitance value of the parasitic capacitance Cp and the resistance value of the equivalent resistance R^ of the second circuit 200. The equivalent resistance R^ includes the resistance components of the clamp circuits 205 and 206 and the wiring resistance of the second circuit 200.

[0068] The voltage fluctuation Vdif is based on the potential G2, and during the rise period, the relationship is Vdif = -(dv / dt) · Cp · R^ (the symbol Cp indicates the electrostatic capacitance value of the parasitic capacitance Cp, and the symbol R^ indicates the resistance value of the equivalent resistance R^).

[0069] When the rate at which the potential G2 drops from the potential G1 increases, the voltage variation Vdif rises. At this time, the parasitic capacitance Cp is charged by the displacement current caused by the voltage variation Vdif. FIG. 2 illustrates a state in which the voltage variation Vdif starts to rise at time t_dvdt, and the fourth pulse of the signal J1 rises during the rising period. When the pulse rises in the signal J1 during the rising period, the amount by which the receiving signal VR1 rises from the potential G2 increases, reflecting the drop in the potential G2. The receiving signal VR2 does not fall from the potential G2, but rises from the potential G2 by an amount smaller than the amount by which the receiving signal VR1 rises. Alternatively, the receiving signal VR2 falls from the potential G2 by an amount smaller than the amount in which the voltage variation Vdif does not rise. After the pulse rises in the signal J1, the current flowing from the first terminal P1 to the second terminal P2 decreases, and the receiving signals VR1 and VR2 attenuate and return to the potential G2.

[0070] When the time derivative dv / dt of the voltage at potential G2 no longer occurs, the voltage fluctuation Vdif reaches a steady state. Therefore, at the falling edge of the fourth pulse in signal J1 after the voltage fluctuation Vdif reaches a steady state, the received signals VR1 and VR2 behave in the same manner as at the falling edges of the other pulses.

[0071] FIG. 2 illustrates an example in which, even during the rising period, the subtraction voltage value ΔV changes from a state below the first threshold value to a state equal to or greater than the first threshold value, and illustrates an example in which the logical value of the second signal S2 rises from “L” to “H” in accordance with the above operation (i).

[0072] The case where the pulse of the signal J1 falls during the rising period will be explained later in "<1-7. Self-resetting circuit 241>".

[0073] The signals VRO1 and VRO2 have waveforms similar to those of the received signals VR1 and VR2, respectively. Due to the high-pass filter obtained by the capacitor 221 and the voltage dividing resistor 223, and the DC offset voltage circuit 225, the signal VRO1 shows the same rising edge and subsequent attenuation as the received signal VR1, and the falling edge and subsequent attenuation, with respect to the DC voltage D1. Due to the high-pass filter obtained by the capacitor 222 and the voltage dividing resistor 224, and the DC offset voltage circuit 225, the signal VRO2 shows the same rising edge and attenuation as the received signal VR2, with respect to the DC voltage D1.

[0074] Because the detection circuit 240 operates as described above, a pulse train appears in the second signal S2 corresponding to the pulse train generated in the signal J1 based on the first signal S1. The interval between adjacent transitions in the pulse train appearing in the signal J1 is equal to the interval between adjacent transitions in the pulse train appearing in the second signal S2 corresponding to the pulse train.

[0075] <1-7. Self-resetting circuit 241> The second circuit 200 includes a self-resetting circuit 241. The second signal S2 is input to the self-resetting circuit 241, which outputs a reset signal R1. The reset signal R1 is input to the detection circuit 240, causing the detection circuit 240 to reset its operation.

[0076] The self-reset circuit 241 prevents the second signal S2 from becoming "H" for a period exceeding a preset period (hereinafter also tentatively referred to as an "allowable period"). Specifically, the self-reset circuit 241 activates a reset signal R1 when the allowable period has elapsed since the logical value of the second signal S2 rose. The detection circuit 240 is reset by the activation of the reset signal R1. This reset causes the logical value of the second signal S2 to become "L" (see (iv) above). The self-reset circuit 241 functions as a reset circuit that resets the operation of the detection circuit 240 in the signal transmission circuit 1000 itself when the logical value of the second signal S2, here "H", is maintained for the allowable period.

[0077] The self-reset circuit 241 is realized by, for example, a timer that starts at the rising edge of the logical value of the second signal S2 and outputs a one-pulse reset signal R1 when an allowable period has elapsed.

[0078] For example, the self-reset circuit 241 has a capacitor that is charged with a constant current while the logical value of the second signal S2 is "H," and is configured to output a one-pulse reset signal R1 when the voltage to which the capacitor is charged exceeds a threshold.

[0079] Fig. 3 is a waveform diagram for explaining the advantage of providing the self-reset circuit 241. Fig. 3 shows the waveforms of the logical value of the first signal S1, the logical value of the signal J1, the receiving signals VR1 and VR2, and the logical value of the second signal S2. In Fig. 3, the inversion of the logical value of the transmitting signal VT2 is also shown together with the signal J1 by adding an overline to the symbol "VT2". In Fig. 3, the logical value of the first signal S1 rises at time t_on and falls at time t_off.

[0080] The final pulse of the pulse train appearing in signal J1 rises at time t_s. In Fig. 3, the trailing pulse of the pulse train appearing in signal J1 also falls at time t_off, but the trailing pulse may also fall before time t_off.

[0081] A case is illustrated in which the voltage fluctuation Vdif is 0 V from time t_on to time t_dvdt (that is, the potential G1 is equal to the potential G2) and starts to rise from time t_dvdt.

[0082] In FIG. 3, the symbols "..." in the logical values ​​of the signal J1, the received signals VR1 and VR2, and the second signal S2 respectively indicate that similar waveforms are repeated.

[0083] Unlike FIG. 2, the voltage fluctuation Vdif rises from time t_dvdt before the last pulse of the pulse train of the signal J1 falls. As described above, during the rising period, the potential of the potential G2 falls below the potential G1. Therefore, in response to the fall, the reception signal VR1 rises instead of falling. As a result, the potential difference between the reception signals VR1 and VR2 is smaller than the potential difference when the pulse in the signal J1 falls when the voltage fluctuation Vdif is stationary. As a result, the potential difference between the signals VRO1 and VRO2 is also small (not shown in FIG. 3), and the above-mentioned operation of the detection circuit 240 "(ii) lowering the logical value of the second signal S2 from "H" to "L" when the subtraction voltage value ΔV changes from a state larger than the negative second threshold to a state equal to or smaller than the second threshold" may not be performed. Due to such a malfunction, the logical value of the second signal S2 rises to "H" at time t_s and then maintains "H" even after time t_off (see the dashed line). Such a malfunction in which the logical value of the second signal S2 remains "H" longer than the logical value of the signal J1 is "H" is hereinafter referred to as "high latch" for convenience.

[0084] The self-resetting circuit 241 realizes the above-mentioned operation of the detection circuit 240, "(iv) taking precedence over the above operations (i) to (iii), the logical value of the second signal S2 is set to "L" by resetting," and contributes to reducing high latch. FIG. 3 illustrates an example in which the logical value of the second signal S2 becomes "L" at time t_d by resetting. In this case, the time from time t_s to time t_d corresponds to the allowable period. Such reduction in high latch contributes to the second signal S2 appropriately reflecting the signal J1, and thus to the appropriate transmission of the first signal S1 to the second signal S2.

[0085] The tolerance period is preferably longer than the pulse width used for the pulse generated by the signal J1. Even if there is no operational malfunction, a pulse reflecting the pulse is generated in the second signal S2, and if the tolerance period is equal to or shorter than the pulse width, normal operation will not be performed. For example, the tolerance period is equal to or shorter than one period of a pulse in the pulse train generated by the signal J1.

[0086] <1-8.Clamp circuits 205, 206> The clamp circuits 205 and 206 are connected in series between the input terminals P5 and P6. A potential G2 is applied to the connection point between the clamp circuits 205 and 206. The clamp circuit 205 is disposed closer to the input terminal P5 than the clamp circuit 206.

[0087] Specifically, clamp circuit 205 includes, for example, diodes 201 and 202 and resistor 207. In clamp circuit 205, diode 201 and resistor 207 are connected in series. In clamp circuit 205, diode 202 and resistor 207 are connected in series. Diodes 201 and 202 are connected in parallel with their forward directions reversed. Diode 202 is connected in parallel with diode 201, and its forward direction is reverse to that of diode 201.

[0088] 1, the forward direction of diode 201 is the direction from clamp circuit 206 to input terminal P5, and the forward direction of diode 202 is the direction from input terminal P5 to clamp circuit 206. For example, the cathode of diode 201 and the anode of diode 202 are both connected to input terminal P5 via resistor 207, and a potential G2 is applied to both the anode of diode 201 and the cathode of diode 202.

[0089] A current flows through the parasitic capacitance Cp between the first end P1 of the first coil 11 and the third end P3 of the second coil 12 through the clamp circuit 205. The clamp circuit 205 contributes to suppressing the charging and discharging of the parasitic capacitance Cp. This suppression limits the rise and fall of the potential of the third end P3 (which can also be said to be the potential of the received signal VR1).

[0090] Specifically, clamp circuit 206 includes, for example, diodes 203 and 204 and resistor 208. In clamp circuit 206, diode 203 and resistor 208 are connected in series. In clamp circuit 206, diode 204 and resistor 208 are connected in series. Diodes 203 and 204 are connected in parallel with their forward directions reversed. Diode 204 is connected in parallel with diode 203, and its forward direction is reverse to that of diode 203.

[0091] 1, the forward direction of diode 203 is the direction from clamp circuit 205 to input terminal P6, and the forward direction of diode 204 is the direction from input terminal P6 to clamp circuit 205. For example, the cathode of diode 203 and the anode of diode 204 are both connected to input terminal P6 via resistor 208, and a potential G2 is applied to both the anode of diode 203 and the cathode of diode 204.

[0092] A current flows through the parasitic capacitance Cp between the second end P2 of the first coil 11 and the fourth end P4 of the second coil 12 through the clamp circuit 206. The clamp circuit 206 contributes to suppressing the charging and discharging of the parasitic capacitance Cp. This suppression limits the rise and fall of the potential at the fourth end P4 (which can also be said to be the potential of the received signal VR2).

[0093] Both clamp circuits 205 and 206 contribute to reducing malfunction of the detection circuit 240 due to fluctuations in the potential difference between potentials G1 and G2 (which can be expressed, for example, by the time derivative dv / dt described above).

[0094] The settings of the resistors 207 and 208 will be explained later in <2-6. Setting of current limiting resistor>.

[0095] <2. Power conversion device> A second embodiment of the present disclosure relates to a power conversion device. Fig. 4 is a circuit diagram illustrating a configuration of a power conversion device 2000 according to the second embodiment.

[0096] First signals S1a, S1b, S1x, and S1y having two logical values ​​are input to the power conversion device 2000. The power conversion device 2000 outputs an output potential OUT to the external load 1 via an output line 7. The output potential OUT is the potential of the output line 7. The external load 1 is driven by the output potential OUT. The external load 1 is, for example, a motor.

[0097] The control circuit 4 receives an input signal IN at its input terminal 8, outputs a first signal S1a from its output terminal 8a, and outputs a first signal S1x from its output terminal 8b. For example, the logical value of the first signal S1a is inverted by an inverter to obtain the first signal S1b. For example, the logical value of the first signal S1x is inverted by an inverter to obtain the first signal S1y.

[0098] The power conversion device 2000 includes an upper arm circuit 2000a and a lower arm circuit 2000b. The upper arm circuit 2000a and the lower arm circuit 2000b are connected via an output line 7. It can also be seen that the output line 7 is included in the power conversion device 2000.

[0099] <2-1. Upper arm circuit 2000a> The upper arm circuit 2000a includes signal transmission circuits 1000a and 1000b, a latch circuit 6a, a logic circuit 5a, a driver 3a, and a switching element 2a. The switching element 2a may be, for example, a power semiconductor switching element. The switching element 2a may be, for example, a reverse conducting IGBT (IGBT stands for insulated gate bipolar transistor: the same applies below) 130.

[0100] The signal transmission circuit 1000a includes an input terminal 50a, a first circuit 100a, a transformer 10a, a second circuit 200a, and an output terminal 51a. The input terminal 50a may be considered to be included in the first circuit 100a. The output terminal 51a may be considered to be included in the second circuit 200a.

[0101] The signal transmission circuit 1000b includes an input terminal 50b, a first circuit 100b, a transformer 10b, a second circuit 200b, and an output terminal 51b. The input terminal 50b may be considered to be included in the first circuit 100b. The output terminal 51b may be considered to be included in the second circuit 200b.

[0102] A first signal S1a is input to the input terminal 50a. A first signal S1b is input to the input terminal 50b. A second signal S2a is output from the output terminal 51a. A second signal S2b is output from the output terminal 51b.

[0103] The latch circuit 6a has a set terminal P100a, a reset terminal P101a, and an output terminal P102a. When the logical value of the signal input to the set terminal P100a is "H", the latch circuit 6a is set, and the signal Qa output from the output terminal P102a has the logical value "H". When the logical value of the signal input to the reset terminal P101a is "H", the latch circuit 6a is reset, and the signal Qa has the logical value "L".

[0104] The set terminal P100a is connected to the output terminal 51a, which receives the second signal S2a, and the reset terminal P101a is connected to the output terminal 51b, which receives the second signal S2b.

[0105] The logic circuit 5a has an input terminal P110a and an output terminal P111a. The input terminal P110a is connected to the output terminal P102a.

[0106] The driver 3a has an input terminal P120 and an output terminal P121. The input terminal P120 is connected to the output terminal P111a.

[0107] The gate of the reverse conducting IGBT 130 is connected to the output terminal P121. A fixed potential HV is applied to the collector of the reverse conducting IGBT 130, which is one terminal of the switching element 2a. The emitter of the reverse conducting IGBT 130, which is the other terminal of the switching element 2a, is connected to the output line 7. The gate of the reverse conducting IGBT 130 functions as an input terminal for driving the switching element 2a. The potential HV is based on a potential G3. The potential G3 is, for example, a ground potential.

[0108] <2-2. Lower arm circuit 2000b> The lower arm circuit 2000b includes signal transmission circuits 1000x and 1000y, a latch circuit 6b, a logic circuit 5b, a driver 3b, and a switching element 2b. For example, a power semiconductor switching element is used for the switching element 2b. For example, a reverse conducting IGBT 131 is used for the switching element 2b. A field effect transistor may be used for either or both of the switching elements 2a and 2b.

[0109] The signal transmission circuit 1000x includes an input terminal 50x, a first circuit 100x, a transformer 10x, a second circuit 200x, and an output terminal 51x. The input terminal 50x may be considered to be included in the first circuit 100x. The output terminal 51x may be considered to be included in the second circuit 200x.

[0110] The signal transmission circuit 1000y includes an input terminal 50y, a first circuit 100y, a transformer 10y, a second circuit 200y, and an output terminal 51y. The input terminal 50y may be considered to be included in the first circuit 100y. The output terminal 51y may be considered to be included in the second circuit 200y.

[0111] A first signal S1x is input to the input terminal 50x. A first signal S1y is input to the input terminal 50y. A second signal S2x is output from the output terminal 51x. A second signal S2y is output from the output terminal 51y.

[0112] The latch circuit 6b has a set terminal P100b, a reset terminal P101b, and an output terminal P102b. When the logical value of the signal input to the set terminal P100b is "H", the latch circuit 6b is set, and the signal Qb output from the output terminal P102b has the logical value "H". When the logical value of the signal input to the reset terminal P101b is "H", the latch circuit 6b is reset, and the signal Qb has the logical value "L".

[0113] The set terminal P100b is connected to the output terminal 51x, which receives the second signal S2x, and the reset terminal P101b is connected to the output terminal 51y, which receives the second signal S2y.

[0114] The logic circuit 5b has an input terminal P110b and an output terminal P111b. The input terminal P110b is connected to the output terminal P102b.

[0115] The driver 3b has an input terminal P123 and an output terminal P124. The input terminal P123 is connected to the output terminal P111b.

[0116] The gate of the reverse conducting IGBT 131 is connected to the output terminal P124. The collector of the reverse conducting IGBT 131, which is one terminal of the switching element 2b, is connected to the output line 7. A potential G3 is applied to the emitter of the reverse conducting IGBT 131, which is the other terminal of the switching element 2b. The gate of the reverse conducting IGBT 131 functions as an input terminal for driving the switching element 2b.

[0117] <2-3. Signal transmission circuits 1000a, 1000b, 1000x, 1000y> For example, each of the signal transmission circuits 1000a, 1000b, 1000x, and 1000y in the second embodiment employs the configuration of the signal transmission circuit 1000 in the first embodiment. The advantages of the signal transmission circuit 1000 can be obtained in the power conversion device 2000 in the second embodiment.

[0118] Fig. 5 is a circuit diagram illustrating the configuration of a signal transmission circuit 1000a. Fig. 6 is a circuit diagram illustrating the configuration of a signal transmission circuit 1000b. Fig. 7 is a circuit diagram illustrating the configuration of a signal transmission circuit 1000x. Fig. 8 is a circuit diagram illustrating the configuration of a signal transmission circuit 1000y.

[0119] The configuration of the signal transmission circuit 1000a (see FIG. 5) is the same as that of the signal transmission circuit 1000 (see FIG. 1) described in the first embodiment, except for the connection relationship with the output line 7. Specifically, the first circuit 100, the pulse generating circuit 101, the output circuit 102, the transistors 103 and 104, the transformer 10, the first coil 11, the second coil 12, the input terminal 50, the output terminal 51, the second circuit 200, the diodes 201, 202, 203, and 204, the clamp circuits 205 and 206, the resistors 207 and 208, the offset circuit 220, the capacitors 221 and 222, the voltage dividing resistors 223 and 224, the DC offset voltage circuit 225, and the like described in the first embodiment. , the detection circuit 240, the self-reset circuit 241, the first terminal P1, the second terminal P2, the third terminal P3, the fourth terminal P4, the input terminals P5 and P6, the output terminals P7 and P8, the input terminals P9 and P10, the output terminal P11, the parasitic capacitance Cp, the first signal S1, the second signal S2, the signals J1, VRO1 and VRO2, the potential VT1, the transmission signal VT2, the reception signals VR1 and VR2, the DC voltage D1, the reset signal R1, and the subtraction voltage value ΔV are respectively the first circuit 100a, the pulse generating circuit 101a, and the output circuit 102a. , transistors 103a, 104a, transformer 10a, first coil 11a, second coil 12a, input terminal 50a, output terminal 51a, second circuit 200a, diodes 201a, 202a, 203a, 204a, clamp circuits 205a, 206a, resistors 207a, 208a, offset circuit 220a, capacitors 221a, 222a, voltage dividing resistors 223a, 224a, DC offset voltage circuit 225a, detection circuit 240a, self-reset circuit 241a, first The configuration and operation of the signal transmission circuit 1000a will be explained by replacing the terminal P1a, the second terminal P2a, the third terminal P3a, the fourth terminal P4a, input terminals P5a, P6a, output terminals P7a, P8a, input terminals P9a, P10a, output terminal P11a, parasitic capacitance Cpa, first signal S1a, second signal S2a, signals J1a, VRO1a, VRO2a, potential VT1a, transmission signal VT2a, reception signals VR1a, VR2a, DC voltage D1a, reset signal R1a, and subtraction voltage value ΔVa.

[0120] However, in the configuration of the signal transmission circuit 1000a, the output line 7 is connected to both the anodes of the diodes 201a and 203a and the cathodes of the diodes 202a and 204a, and an output potential OUT is provided. The DC offset voltage circuit 225a outputs a DC voltage D1a based on the output potential OUT. The operating voltage of the detection circuit 240a is the potential difference between the potential VCC and the output potential OUT. The output potential OUT corresponds to the potential G2 in the first embodiment.

[0121] The configuration of the signal transmission circuit 1000b (see FIG. 6) is the same as the configuration of the signal transmission circuit 1000a (see FIG. 5). Specifically, the signal transmission circuit 1000a includes a first circuit 100a, a pulse generating circuit 101a, an output circuit 102a, transistors 103a and 104a, a transformer 10a, a first coil 11a, a second coil 12a, an input terminal 50a, an output terminal 51a, a second circuit 200a, diodes 201a, 202a, 203a, and 204a, clamp circuits 205a and 206a, resistors 207a and 208a, an offset circuit 220a, capacitors 221a and 222a, voltage dividing resistors 223a and 224a, a DC input terminal 51a, and a The offset voltage circuit 225a, the detection circuit 240a, the self-reset circuit 241a, the first terminal P1a, the second terminal P2a, the third terminal P3a, the fourth terminal P4a, the input terminals P5a and P6a, the output terminals P7a and P8a, the input terminals P9a and P10a, the output terminal P11a, the parasitic capacitance Cpa, the first signal S1a, the second signal S2a, the signals J1a, VRO1a, and VRO2a, the potential VT1a, the transmission signal VT2a, the reception signals VR1a and VR2a, the DC voltage D1a, the reset signal R1a, and the subtraction voltage value ΔVa. 100b, a pulse generating circuit 101b, an output circuit 102b, transistors 103b, 104b, a transformer 10b, a first coil 11b, a second coil 12b, an input terminal 50b, an output terminal 51b, a second circuit 200b, diodes 201b, 202b, 203b, 204b, clamp circuits 205b, 206b, resistors 207b, 208b, an offset circuit 220b, capacitors 221b, 222b, voltage dividing resistors 223b, 224b, a DC offset voltage circuit 225b, a detection circuit 240b, a self-reset The configuration and operation of the signal transmission circuit 1000b will be explained by replacing these with the set circuit 241b, the first terminal P1b, the second terminal P2b, the third terminal P3b, the fourth terminal P4b, the input terminals P5b, P6b, the output terminals P7b, P8b, the input terminals P9b, P10b, the output terminal P11b, the parasitic capacitance Cpb, the first signal S1b, the second signal S2b, the signals J1b, VRO1b, VRO2b, the potential VT1b, the transmission signal VT2b, the reception signals VR1b, VR2b, the DC voltage D1b, the reset signal R1b, and the subtraction voltage value ΔVb.

[0122] The configuration of the signal transmission circuit 1000x (see FIG. 7) is the same as that of the signal transmission circuit 1000 (see FIG. 1) described in the first embodiment, except for the difference in potentials G2 and G3. Specifically, the first circuit 100, the pulse generating circuit 101, the output circuit 102, the transistors 103 and 104, the transformer 10, the first coil 11, the second coil 12, the input terminal 50, the output terminal 51, the second circuit 200, the diodes 201, 202, 203, and 204, the clamp circuits 205 and 206, the resistors 207 and 208, the offset circuit 220, the capacitors 221 and 222, the voltage dividing resistors 223 and 224, the DC offset voltage circuit 225, the detection The output circuit 240, the self-reset circuit 241, the first terminal P1, the second terminal P2, the third terminal P3, the fourth terminal P4, the input terminals P5 and P6, the output terminals P7 and P8, the input terminals P9 and P10, the output terminal P11, the parasitic capacitance Cp, the first signal S1, the second signal S2, the signals J1, VRO1 and VRO2, the potential VT1, the transmission signal VT2, the reception signals VR1 and VR2, the DC voltage D1, the reset signal R1, the subtraction voltage value ΔV, and the potential G2 are respectively connected to the first circuit 100x, the pulse generating circuit 101x, and the output circuit 102. x, transistors 103x, 104x, transformer 10x, first coil 11x, second coil 12x, input terminal 50x, output terminal 51x, second circuit 200x, diodes 201x, 202x, 203x, 204x, clamp circuits 205x, 206x, resistors 207x, 208x, offset circuit 220x, capacitors 221x, 222x, voltage dividing resistors 223x, 224x, DC offset voltage circuit 225x, detection circuit 240x, self-reset circuit 241x, first terminal The configuration and operation of the signal transmission circuit 1000x will be explained by replacing P1x, the second terminal P2x, the third terminal P3x, the fourth terminal P4x, input terminals P5x, P6x, output terminals P7x, P8x, input terminals P9x, P10x, output terminal P11x, parasitic capacitance Cpx, first signal S1x, second signal S2x, signals J1x, VRO1x, VRO2x, potential VT1x, transmission signal VT2x, reception signals VR1x, VR2x, DC voltage D1x, reset signal R1x, subtraction voltage value ΔVx, and potential G3.

[0123] The configuration of the signal transmission circuit 1000y (see FIG. 8) is the same as the configuration of the signal transmission circuit 1000x (see FIG. 7). Specifically, in the signal transmission circuit 1000x, the first circuit 100x, the pulse generating circuit 101x, the output circuit 102x, the transistors 103x and 104x, the transformer 10x, the first coil 11x, the second coil 12x, the input terminal 50x, the output terminal 51x, the second circuit 200x, the diodes 201x, 202x, 203x, and 204x, the clamp circuits 205x and 206x, the resistors 207x and 208x, the offset circuit 220x, the capacitors 221x and 222x, the voltage dividing resistors 223x and 224x, the DC The offset voltage circuit 225x, the detection circuit 240x, the self-reset circuit 241x, the first terminal P1x, the second terminal P2x, the third terminal P3x, the fourth terminal P4x, the input terminals P5x and P6x, the output terminals P7x and P8x, the input terminals P9x and P10x, the output terminal P11x, the parasitic capacitance Cpx, the first signal S1x, the second signal S2x, the signals J1x, VRO1x and VRO2x, the potential VT1x, the transmission signal VT2x, the reception signals VR1x and VR2x, the DC voltage D1x, the reset signal R1x, and the subtraction voltage value ΔVx are respectively circuit 100y, a pulse generating circuit 101y, an output circuit 102y, transistors 103y, 104y, a transformer 10y, a first coil 11y, a second coil 12y, an input terminal 50y, an output terminal 51y, a second circuit 200y, diodes 201y, 202y, 203y, 204y, clamp circuits 205y, 206y, resistors 207y, 208y, an offset circuit 220y, capacitors 221y, 222y, voltage dividing resistors 223y, 224y, a DC offset voltage circuit 225y, a detection circuit 240y, The configuration and operation of the signal transmission circuit 1000y will be explained by replacing the self-reset circuit 241y, the first terminal P1y, the second terminal P2y, the third terminal P3y, the fourth terminal P4y, the input terminals P5y, P6y, the output terminals P7y, P8y, the input terminals P9y, P10y, the output terminal P11y, the parasitic capacitance Cpy, the first signal S1y, the second signal S2y, the signals J1y, VRO1y, VRO2y, the potential VT1y, the transmission signal VT2y, the reception signals VR1y, VR2y, the DC voltage D1y, the reset signal R1y, and the subtraction voltage value ΔVy.

[0124] Each of the signal transmission circuits 1000a, 1000b, 1000x, and 1000y in the second embodiment operates in the same manner as the signal transmission circuit 1000 in the first embodiment. However, the output potential OUT in the signal transmission circuits 1000a and 1000b corresponds to the potential G2 in the signal transmission circuit 1000, and the potential G3 in the signal transmission circuits 1000x and 1000y corresponds to the potential G2 in the signal transmission circuit 1000.

[0125] When the signal transmission circuit 1000 is used in the signal transmission circuit 1000a, the potential G2 is the output potential OUT. When the signal transmission circuit 1000 is used in the signal transmission circuit 1000b, the potential G2 is the output potential OUT. When the signal transmission circuit 1000 is used in the signal transmission circuit 1000x, the potential G2 is the potential G3. When the signal transmission circuit 1000 is used in the signal transmission circuit 1000y, the potential G2 is the potential G3.

[0126] For example, the input signal IN has information for driving the external load 1. The control circuit 4 generates the first signals S1a and S1x based on the input signal IN. For example, the first signals S1a and S1x are activated by exclusively taking on the logical value "H". The logical values ​​of the first signals S1b and S1y are inversely related to the logical values ​​of the first signals S1b and S1x, respectively. The following illustrates an example in which the potential corresponding to the logical value "H" is higher than the potential corresponding to the logical value "L".

[0127] The signal transmission circuit 1000a performs signal transmission via the transformer 10a and outputs a second signal S2a. The signal transmission circuit 1000b performs signal transmission via the transformer 10b and outputs a second signal S2b. The signal transmission circuit 1000x performs signal transmission via the transformer 10x and outputs a second signal S2x. The signal transmission circuit 1000y performs signal transmission via the transformer 10y and outputs a second signal S2y.

[0128] The second signal S2a is input to the set terminal P100a. When the second signal S2a takes on a logical value of "H", the signal Qa output from the output terminal P102a takes on a logical value of "H". The second signal S2b is input to the reset terminal P101a. When the second signal S2b takes on a logical value of "H", the signal Qa takes on a logical value of "L".

[0129] As described above, similar to the relationship between the signal J1 and the second signal S2 described in the first embodiment (see FIG. 2), the waveform of the logical value of the second signal S2a shows a pulse train reflecting the pulse train of the logical value of the signal J1a. Therefore, the waveform of the logical value of the second signal S2a does not necessarily reflect the waveform of the logical value of the first signal S1a. However, due to the function of the latch circuit 6a, once the second signal S2a takes on a logical value of "H", the signal Qa continues to take on a logical value of "H" until the second signal S2b takes on a logical value of "H". Similarly, once the second signal S2b takes on a logical value of "H", the signal Qa continues to take on a logical value of "L" until the second signal S2a takes on a logical value of "H". Since the logical values ​​of the second signal S2b and the second signal S2a are in an inverted relationship, the signal Qa takes on a logical value reflecting the logical value of the first signal S1a.

[0130] The signal Qa functions as a drive-on signal that permits the switching element 2a to be turned on, similar to the first signal S1a. Similarly, the signal Qa functions as a drive-off signal that prohibits the switching element 2a from being turned on, similar to the first signal S1b. The signal Qa controls whether the switching element 2a is allowed to be conductive.

[0131] The second signal S2x is input to the set terminal P100b. When the second signal S2x takes on a logical value of "H", the signal Qb output from the output terminal P102b takes on a logical value of "H". The second signal S2y is input to the reset terminal P101b. When the second signal S2y takes on a logical value of "H", the signal Qb takes on a logical value of "L".

[0132] Due to the function of the latch circuit 6b, the signal Qb takes on a logical value that reflects the logical value of the first signal S1x. Like the first signal S1x, the signal Qb functions as a drive-on signal that permits the switching element 2b to be turned on. Similarly, like the first signal S1y, the signal Qb also functions as a drive-off signal that prohibits the switching element 2b from being turned off. The signal Qb controls whether or not the switching element 2b is allowed to be conductive.

[0133] A signal Qa is input to an input terminal P110a. A logic circuit 5a generates a signal Ka from the signal Qa and outputs it from an output terminal P111a. A signal Qb is input to an input terminal P110b. A logic circuit 5b generates a signal Kb from the signal Qb and outputs it from an output terminal P111b. The signal Kb is provided to an input terminal P123. The signal Ka is provided to an input terminal P120.

[0134] The driver 3a amplifies the signal Ka by a predetermined gain and drives the switching element 2a. The driver 3b amplifies the signal Kb by a predetermined gain and drives the switching element 2b.

[0135] The signal Qa functions as both a drive-on signal and a drive-off signal for the switching element 2a. The logic circuit 5a modulates the signal Qa, for example, when the signal Qa has a logical value of "H", to generate a signal Ka. Similarly, the logic circuit 5b modulates the signal Qb, for example, when the signal Qb has a logical value of "H", to generate a signal Kb. The signal Ka is intermittently activated, for example, when the signal Qa has a logical value of "H", and is not activated, when the signal Qa has a logical value of "L". The signal Kb is intermittently activated, for example, when the signal Qb has a logical value of "H", and is not activated, when the signal Qb has a logical value of "L".

[0136] Since the logical values ​​of the first signals S1a, S1x are exclusively "H" and the logical values ​​of the signals Qa, Qb are also exclusively "H", the signals Ka, Kb generated as described above do not simultaneously turn on the switching elements 2a, 2b when the second signals S2a, S2b, S2x, S2y are normally obtained. The switching elements 2a, 2b are exclusively turned on, but are not necessarily turned on complementarily.

[0137] If the on-resistance of the switching element 2a is ignored, when the switching element 2a is turned on while the switching element 2b is off, the output potential OUT rises toward the potential HV. If the on-resistance of the switching element 2b is ignored, when the switching element 2b is turned on while the switching element 2a is off, the output potential OUT falls toward the potential G3.

[0138] The second circuit 200a of the signal transmission circuit 1000a, the second circuit 200b of the signal transmission circuit 1000b, and the driver 3a are all connected to the output line 7 and operate with the output potential OUT as a reference potential. The output potential OUT fluctuates between potential G3 and potential HV depending on the on-state time of the switching elements 2a and 2b. The potential difference between potentials G3 and HV is, for example, several hundred to several thousand volts.

[0139] The control circuit 4 and the first circuits 100a, 100b, 100x, and 100y are not directly connected to the output line 7. The control circuit 4 is DC-isolated from the drivers 3a and 3b and the switching elements 2a and 2b.

[0140] For example, even if the drivers 3a and 3b and the switching elements 2a and 2b are arranged in a high-voltage area taking into consideration the potential HV, the control circuit 4 can be arranged in a low-voltage area that is DC-separated from the high-voltage area. Such an arrangement contributes to preventing malfunction of the control circuit 4 and electric shock.

[0141] <2-4. Output potential OUT as the reference for the potential of the second circuit> It is assumed that an event similar to the high latch of the second signal S2 due to the malfunction of the detection circuit 240 in the second circuit 200 described in the first embodiment with reference to Fig. 3 may occur in either or both of the second signals S2a and S2b. In such a case, both of the second signals S2a and S2b become "H", and the signal Qa may not function normally as a drive-on signal like the first signal S1a or as a drive-off signal like the first signal S1b. The same applies to the signal Qb.

[0142] In this way, if the signals Qa and Qb do not function normally as drive-on signals or drive-off signals, it is possible that an event will occur in which the switching elements 2a and 2b are simultaneously turned on. To avoid such an event, it is desirable that an event similar to the high latch of the second signal S2 does not occur in the second signals S2a, S2b, S2x, and S2y.

[0143] Signal transmission circuits 1000a, 1000b, 1000x, and 1000y are adopted in the power conversion device 2000, and in the second circuits 200a, 200b, 200x, and 200y that each have, the operation of the self-reset circuits 241a, 241b, 241x, and 241y can be used to obtain operation similar to that of the second circuit 200 in the signal transmission circuit 1000, which contributes to preventing high latch from occurring in the second signals S2a, S2b, S2x, and S2y.

[0144] Therefore, in the power conversion device 2000 according to the second embodiment, malfunction of the switching elements 2a and 2b is suppressed.

[0145] <2-5. Fluctuations in potential G2> The output potential OUT fluctuates between potentials G3 and HV as the switching elements 2a and 2b open and close. The fluctuation in potential G2 explained using the signal transmission circuit 1000 occurs due to the fluctuation in the output potential OUT when the signal transmission circuit 1000 is employed as the signal transmission circuits 1000a and 1000b, for example. The fluctuation in the output potential OUT also induces a time differential dv / dt of the voltage, similar to the fluctuation in potential G2.

[0146] In the following, for simplicity of explanation, a case is exemplified in which, when the switching element 2a is in an off state, the switching element 2b is turned off and the output potential OUT drops toward potential G3 (dv / dt<0). When, when the switching element 2a is in an off state, the switching element 2b is turned on and the output potential OUT rises toward potential HV, the positive and negative signs of the time derivative dv / dt are different. Since the following deals with an event caused by the time derivative dv / dt, the following effects can be obtained in either case by changing the direction of the displacement current flow depending on whether the time derivative dv / dt is positive or negative.

[0147] In addition, the following description is based on the assumption that the potentials G1 and G3 are equal. The following description deals with events caused by the time differential dv / dt, and the assumption is that the difference is in the DC voltage, and does not affect the time differential dv / dt itself, so the following effects can be obtained even when the potentials G1 and G3 are different.

[0148] For example, the rise in the voltage fluctuation Vdif in the signal transmission circuit 1000 illustrated in Figures 2 and 3 occurs before and after the falling edge of the first signal S1 illustrated in these figures. The voltage fluctuation Vdif is caused, for example, by the turning off of the switching element 2b in response to the falling edge of the first signal S1a when the signal transmission circuit 1000 is used as the signal transmission circuit 1000a.

[0149] However, the voltage fluctuation Vdif illustrated in Figures 2 and 3 corresponds to a voltage rise caused by the turn-off of the switching element 2b in response to one falling edge of the logic value of the first signal S1a provided to the signal transmission circuit 1000a; and the transition of the logic value of the first signal S1 illustrated in Figures 2 and 3 corresponds to a transition of the logic value of the first signal S1a that occurs after the first signal S1a having the falling edge to which the turn-off responds.

[0150] The turning off of the switching element 2b in response to the falling edge of the logical value of a certain first signal S1a occurs with a delay from the falling edge due to the operation of the signal transmission circuit 1000a. Since a similar delay also occurs in the signal transmission circuit 1000, the above correspondence relationship may occur.

[0151] Similar to the voltage fluctuation Vdif in the signal transmission circuit 1000, in the signal transmission circuit 1000a, the potential at the third terminal P3a rises by -(dv / dt)·Cpa·Ra^, where Cpa represents the capacitance value of the parasitic capacitance Cpa, and Ra^ represents the resistance value of the equivalent resistance of the second circuit 200a. Similarly, in the signal transmission circuit 1000b, the potential at the third terminal P3b rises by -(dv / dt)·Cpb·Rb^, where Cpb represents the capacitance value of the parasitic capacitance Cpb, and Rb^ represents the resistance value of the equivalent resistance of the second circuit 200b.

[0152] It is desirable to suppress these increases, since they may cause the high latch described in Fig. 3. For example, the parasitic capacitance Cpa is charged and discharged with a current represented by the product of the time differential dv / dt and the capacitance value of the parasitic capacitance Cpa, and the parasitic capacitance Cpb is charged and discharged with a current represented by the product of the time differential dv / dt and the capacitance value of the parasitic capacitance Cpb.

[0153] When clamp circuits 205 and 206 in signal transmission circuit 1000 charge and discharge parasitic capacitance Cp, a current expressed by the product of time differential dv / dt and the capacitance value of parasitic capacitance Cp flows, similar to the charging and discharging of parasitic capacitances Cpa and Cpb.

[0154] The parasitic capacitance Cpa is charged and discharged via either or both of the clamp circuits 205a and 206a. The parasitic capacitance Cpb is charged and discharged by either or both of the clamp circuits 205b and 206b. Similar to the clamp circuits 205 and 206 in the signal transmission circuit 1000, the clamp circuits 205a and 206a contribute to suppressing the charging and discharging of the parasitic capacitance Cpa, and the clamp circuits 205b and 206b contribute to suppressing the charging and discharging of the parasitic capacitance Cpb.

[0155] FIG. 9 is a waveform diagram illustrating the time-dependent changes of various signals in the signal transmission circuits 1000a and 1000b. Specifically, FIG. 9 illustrates the waveforms of the logical value of the input signal IN, the logical values ​​of the first signals S1a and S1b, the logical values ​​of the signals J1a and J1b, the received signals VR1a, VR2a, VR1b, and VR2b, the signals VRO1a, VRO2a, VRO1b, and VRO2b, the second signals S2a and S2b, and the logical value of the output potential OUT. FIG. 9 also illustrates the waveform of the voltage fluctuation Vdif. In FIG. 9, the inversion of the logical value of the transmission signal VT2a is shown together with the signal J1a by adding an overline to the symbol "VT2a."

[0156] The logical value of the input signal IN rises from "L" to "H" at time t_on. In response to this, the logical value of the first signal S1a also rises at time t_on, and the logical value of the first signal S1b falls from "H" to "L" at time t_on.

[0157] The logical value of the input signal IN falls from "H" to "L" at time t_off. In response to this, the logical value of the first signal S1a also falls at time t_off, and the logical value of the first signal S1b rises from "L" to "H" at time t_off.

[0158] The signal J1a outputs a pulse train during a period in which the logical value of the first signal S1a is "H". In Fig. 9, the signal J1a outputs four pulses during a period in which the logical value of the first signal S1a is "H". The signal J1b outputs a pulse train during a period in which the logical value of the first signal S1b is "H".

[0159] The receiving signals VR1a, VR2a, VR1b, and VR2b all fluctuate with respect to the output potential OUT. At the time when the pulse in the signal J1a rises, the receiving signal VR1a rises once, and the receiving signal VR2a falls once, and then each shows an attenuating waveform. Introducing the current ia flowing through the first coil 11a and the mutual inductance La between the first coil 11a and the second coil 12a, the value of the receiving signal VR1a is expressed as La (dia / dt), and the value of the receiving signal VR2a is expressed as -La (dia / dt).

[0160] At the time when the pulse of signal J1a falls, the received signal VR1a falls once and the received signal VR2a rises once, and then each shows an attenuating waveform. At this time, the value of the received signal VR1a is expressed as -La (dia / dt), and the value of the received signal VR2a is expressed as La (dia / dt).

[0161] At the time when the pulse in signal J1b rises, the received signal VR1b rises once and the received signal VR2b falls once, and then each shows a waveform that attenuates. Introducing the current ib flowing through the first coil 11b and the mutual inductance Lb between the first coil 11b and the second coil 12b, the value of the received signal VR1b is expressed as Lb (dib / dt) and the value of the received signal VR2b is expressed as -Lb (dib / dt).

[0162] At the time when the pulse of signal J1b falls, the received signal VR1b falls once and the received signal VR2b rises once, then each shows an attenuating waveform. At this time, the value of the received signal VR1b is expressed as -Lb (dib / dt), and the value of the received signal VR2b is expressed as Lb (dib / dt).

[0163] As in Fig. 2, the voltage fluctuation Vdif starts to rise from time t_dvdt. In the rising period, when the pulse in the signal J1a rises, the received signal VR2a also rises together with the received signal VR1a, and then decays. Since no pulse train is generated in the signal J1b during the rising period, no such exceptional waveform is generated in the received signal VR2b.

[0164] The signals VRO1a, VRO2a, VRO1b, and VRO2b have waveforms similar to those of the received signals VR1a, VR2a, VR1b, and VR2b, respectively. Due to the high-pass filter obtained by the capacitor 221a and the voltage dividing resistor 223a and the DC offset voltage circuit 225a, the signal VRO1a shows the same rise and subsequent attenuation as the received signal VR1a, and the same fall and subsequent attenuation as the received signal VR1a, with the DC voltage D1a as the reference. Due to the high-pass filter obtained by the capacitor 222a and the voltage dividing resistor 224a and the DC offset voltage circuit 225a, the signal VRO2a shows the same rise and attenuation as the received signal VR2a, with the DC voltage D1a as the reference. Due to the high-pass filter obtained by the capacitor 221b and the voltage dividing resistor 223b and the DC offset voltage circuit 225b, the signal VRO1b shows the same rise and subsequent attenuation as the received signal VR1b, and the same fall and subsequent attenuation as the received signal VR1b, with the DC voltage D1b as the reference. Due to the high-pass filter obtained by the capacitor 222b and the voltage dividing resistor 224b and the DC offset voltage circuit 225b, the signal VRO2b shows the same rise and attenuation as the received signal VR2b, with the DC voltage D1b as the reference.

[0165] 9 illustrates a case where even during the rising period, the effect of the voltage fluctuation Vdif on the subtraction voltage value ΔVa (the potential difference between the signals VRO1a and VRO2a, specifically, the value obtained by subtracting the potential of the signal VRO2a from the potential of the signal VRO1a) is small, and the subtraction voltage value changes from a state below the first threshold to a state equal to or greater than the first threshold. In accordance with the above operation (i), the logical value of the second signal S2a rises from "L" to "H".

[0166] Fig. 10 is a waveform diagram illustrating the time-dependent changes of various signals in the signal transmission circuits 1000x and 1000y. Specifically, Fig. 10 illustrates the waveforms of the logical value of the input signal IN, the logical values ​​of the first signals S1x and S1y, the logical values ​​of the signals J1x and J1y, the received signals VR1x, VR2x, VR1y, and VR2y, the signals VRO1x, VRO2x, VRO1y, and VRO2y, the second signals S2x and S2y, and the logical values ​​of the output potential OUT. Also in Fig. 10, the inversion of the logical value of the transmission signal VT2x is indicated together with the signal J1x by adding an overline to the symbol "VT2x."

[0167] For example, since the first signals S1a and S1x are exclusively activated to take on the logical value “H”, the waveforms of the logical values ​​of the first signals S1x and S1y in FIG. 10 transition in the same manner as the waveforms of the logical values ​​of the first signals S1b and S1a in FIG. 9, respectively.

[0168] Therefore, the waveforms of the logical values ​​of signals J1x, J1y, the received signals VR1x, VR2x, VR1y, VR2y, the signals VRO1x, VRO2x, VRO1y, VRO2y, and the second signals S2x, S2y in Figure 10 appear similar to the waveforms of the logical values ​​of signals J1b, J1a, the received signals VR1b, VR2b, VR1a, VR2a, the signals VRO1b, VRO2b, VRO1a, VRO2a, and the second signals S2b, S2a in Figure 10, respectively.

[0169] 10 illustrates a case where even during the rising period, the effect of the voltage fluctuation Vdif on the subtraction voltage value ΔVy (the potential difference between the signals VRO1y and VRO2y, specifically, the value obtained by subtracting the potential of the signal VRO2y from the potential of the signal VRO1y) is small, and the subtraction voltage value changes from a state below the first threshold to a state equal to or greater than the first threshold. In accordance with the above operation (i), the logical value of the second signal S2y rises from "L" to "H".

[0170] However, since the signal transmission circuits 1000x and 1000y use the potential G3 as a reference potential, the reception signals VR1x, VR2x, VR1y, and VR2y fluctuate with respect to the potential G3. The DC offset voltage circuit 225x outputs a DC voltage D1x with respect to the potential G3, so the signals VRO1x and VRO2x fluctuate with respect to the DC voltage D1x. The DC offset voltage circuit 225y outputs a DC voltage D1y with respect to the potential G3, so the signals VRO1y and VRO2y fluctuate with respect to the DC voltage D1y.

[0171] At time t_on: the logical value of the second signal S2b is "L" (see Figure 9), and the logical value of the second signal S2a rises, causing the logical value of the signal Qa (not shown) to become "H"; the logical value of the second signal S2x is "L" (see Figure 10), and the logical value of the second signal S2y rises, causing the logical value of the signal Qb (not shown) to become "L"; and the logical value of the output potential OUT becomes "H".

[0172] At time t_off: the logical value of the second signal S2a is "L" (see Figure 9), and the rising logical value of the second signal S2b causes the signal Qa (not shown) to become "L"; the logical value of the second signal S2y is "L" (see Figure 10), and the rising logical value of the second signal S2x causes the signal Qb (not shown) to become "H"; and the logical value of the output potential OUT becomes "L".

[0173] When the subtraction voltage value is little affected by the voltage fluctuation Vdif in this way, the logical value of the input signal IN is reflected in the logical value of the output potential OUT.

[0174] <2-6. Setting the current limiting resistor> The resistor 207a in the clamp circuit 205a in the signal transmission circuit 1000a can be said to be a current limiting resistor that limits the magnitude of the current that flows through the diodes 201a and 202a and contributes to the charging and discharging of the parasitic capacitance Cpa. Similarly, the resistor 208a in the clamp circuit 206a can be said to be a current limiting resistor that limits the magnitude of the current that flows through the diodes 203a and 204a and contributes to the charging and discharging of the parasitic capacitance Cpa. Similarly, the resistors 207b and 208b in the signal transmission circuit 1000b, the resistors 207x and 208x in the signal transmission circuit 1000x, the resistors 207y and 208y in the signal transmission circuit 1000y, and the resistors 207 and 208 in the signal transmission circuit 1000 can all be said to be current limiting resistors.

[0175] FIG. 11 is a graph illustrating the rectification characteristics of a diode. The horizontal axis represents forward voltage, and the vertical axis represents forward current. The diode may be any of the diodes 201a, 202a, 203a, 204a, 201b, 202b, 203b, 204b, 201x, 202x, 203x, 204x, 201y, 202y, 203y, and 204y. Curve F1 shows the current flowing through the diode when no current limiting resistor is provided, and curve F2 shows the current flowing through the diode when a current limiting resistor is provided.

[0176] When a current limiting resistor is provided, a forward current iD flows when a forward voltage VD is applied to the diode. As can be seen from a comparison of the curves F1 and F2, the forward current decreases when a current limiting resistor is provided. The current flowing through the clamp circuit 206a corresponds to both the forward current iD flowing through the diode 201a and the forward current iD flowing through the diode 202a. The current flowing during charging and discharging of the parasitic capacitance Cpa is the product of the capacitance value of the parasitic capacitance Cpa and its time differential (dv / dt). Therefore, setting the resistor 207a according to the assumed value of the time differential (dv / dt) limits the displacement current that charges and discharges the parasitic capacitance Cpa, thereby reducing the effect of the voltage fluctuation Vdif on the received signals VR1a and VR2a, and contributing to suppressing malfunction of the detection circuit 240a. Setting the resistor 208a in the same manner contributes to suppressing malfunction of the detection circuit 240b.

[0177] For example, when the output potential OUT drops due to the turning on of the switching element 2b, the displacement current flowing through the diode 202a of the clamp circuit 205a and the diode 204a of the clamp circuit 206a to discharge the parasitic capacitance Cpa is limited, reducing the effect of the voltage fluctuation Vdif on the received signals VR1a and VR2a, thereby contributing to suppression of malfunction of the detection circuit 240a. The displacement current flowing through the diode 202b of the clamp circuit 205b and the diode 204b of the clamp circuit 206b to discharge the parasitic capacitance Cpb is limited, reducing the effect of the voltage fluctuation Vdif on the received signals VR1b and VR2b, thereby contributing to suppression of malfunction of the detection circuit 240b.

[0178] Similarly, when the output potential OUT rises due to the turning on of the switching element 2a, the displacement current flowing through the diode 201a of the clamp circuit 205a and the diode 203a of the clamp circuit 206a to charge the parasitic capacitance Cpa is limited, reducing the effect of the voltage fluctuation Vdif on the received signals VR1a and VR2a, thereby contributing to suppression of malfunction of the detection circuit 240a. The displacement current flowing through the diode 201b of the clamp circuit 205b and the diode 203b of the clamp circuit 206b to charge the parasitic capacitance Cpb is limited, reducing the effect of the voltage fluctuation Vdif on the received signals VR1b and VR2b, thereby contributing to suppression of malfunction of the detection circuit 240b.

[0179] Similarly, the displacement current flowing through the diode 201x of the clamp circuit 205x and the diode 203x of the clamp circuit 206x to charge the parasitic capacitance Cpx is limited, reducing the effect of the voltage fluctuation Vdif on the received signals VR1x and VR2x, thereby contributing to suppression of malfunction of the detection circuit 240x. The displacement current flowing through the diode 202x of the clamp circuit 205x and the diode 204x of the clamp circuit 206x to discharge the parasitic capacitance Cpx is limited, reducing the effect of the voltage fluctuation Vdif on the received signals VR1x and VR2x, thereby contributing to suppression of malfunction of the detection circuit 240x.

[0180] Similarly, the displacement current flowing through the diode 201y of the clamp circuit 205y and the diode 203y of the clamp circuit 206y to charge the parasitic capacitance Cpy is limited, reducing the effect of the voltage fluctuation Vdif on the received signals VR1y and VR2y, thereby contributing to suppression of malfunction of the detection circuit 240y. The displacement current flowing through the diode 202y of the clamp circuit 205y and the diode 204y of the clamp circuit 206y to discharge the parasitic capacitance Cpy is limited, reducing the effect of the voltage fluctuation Vdif on the received signals VR1y and VR2y, thereby contributing to suppression of malfunction of the detection circuit 240y.

[0181] The settings of the resistors 207a, 208a, 207b, 208b, 207x, 208x, 207y, and 208y contribute to suppressing malfunctions of the detection circuits 240a, 240b, 240x, and 240y, and thereby contribute to the output potential OUT appropriately reflecting the input signal IN.

[0182] Similarly, in the signal transmission circuit 1000, setting the resistors 207 and 208 according to the assumed value of the time differential (dv / dt) limits the displacement current that charges and discharges the parasitic capacitance Cp. Such a limit contributes to reducing the effect of the voltage fluctuation Vdif on the reception signals VR1 and VR2, and thus to suppressing malfunction of the detection circuit 240. Such a contribution contributes to the second signal S2 appropriately reflecting the signal J1, and thus to the appropriate transmission of the first signal S1 to the second signal S2.

[0183] However, if the time differential (dv / dt) exceeds an expected value, the displacement current caused by the time differential (dv / dt) may become larger than the charge / discharge current flowing as the forward current iD set by the current limiting resistor. In this case, the high latch described in FIG. 3 may also occur in the signal transmission circuits 1000a, 1000b, 1000x, and 1000y.

[0184] Just as the self-reset circuit 241 in the signal transmission circuit 1000 contributes to avoiding high latch, the self-reset circuits 241a, 241b, 241x, and 241y contribute to avoiding high latch in the signal transmission circuits 1000a, 1000b, 1000x, and 1000y, respectively, thereby contributing to the output potential OUT properly reflecting the input signal IN.

[0185] The self-reset circuits 241a, 241b, 241x, and 241y contribute to avoiding high latch in the detection circuits 240a, 240b, 240x, and 240y, respectively, but do not directly affect the waveform of the output potential OUT. This is because the second signals S2a and SS2b are input to the latch circuit 6a, and the second signals S2x and S2y are input to the latch circuit 6b, and the logical value of the output potential OUT is based on the logical value of the signal Qa output by the latch circuit 6a and the logical value of the signal Qb output by the latch circuit 6b.

[0186] For example, in the upper arm circuit 2000a, assume that a high latch occurs in the detection circuit 240a, in which the logical value of the second signal S2a remains at "H" even after the logical value of the first signal S1a transitions from "H" to "L" and the logical value of the first signal S1b transitions from "L" to "H." In this case, both of the second signals S2a and S2b take on the logical value "H," making the logical value of the signal Qa uncertain, and the logical value of the output potential OUT may be maintained at "H."

[0187] However, when the logical value of the first signal S1a subsequently transitions from "L" to "H" and the logical value of the first signal S1b transitions from "H" to "L", the signal J1a generates a new pulse train while the logical value of the second signal S2b is in the "L" state. The falling edge of the pulse in this pulse train causes the logical value of the second signal S2a to become "L" and the logical value of the output potential OUT to become "L". This reduces the effect of causing the external load 1 to malfunction.

[0188] <3. Transformation of pulse train> The third embodiment of the present disclosure relates to modification of pulse trains in the signals J1, J1a, J1b, J1x, and J1y. In the following, the pulse train in the signal J1a will be described first.

[0189] Fig. 12 is a waveform diagram illustrating various signals in the third embodiment. Fig. 12 illustrates the waveforms of the logical value of the input signal IN, the logical value of the signal J1a, the received signals VR1a and VR2a, the logical value of the second signal S2a, and the logical value of the output potential OUT. Fig. 12 also illustrates the waveform of the voltage fluctuation Vdif. The logical value of the input signal IN is the same as the logical value of the first signal S1a (see Fig. 9), and both are shown together in Fig. 12.

[0190] The logical value of the input signal IN rises from "L" to "H" at time t_on, and falls from "H" to "L" at time t_off. The voltage variation Vdif begins to rise at time t_dvdt, which is before time t_on, and is still rising at time t_on. In this way, the voltage variation Vdif may start to rise before time t_on due to the falling edge of the logical value of the input signal IN that occurs before time t_on.

[0191] In the logical value of the signal J1a, a pulse train is generated during a period in which the logical value of the first signal S1a is "H." In Fig. 12, the first pulse of the logical value of the signal J1a rises at time t_on. At this rising edge, if there is no influence of the voltage fluctuation Vdif, the receiving signal VR1a rises and the receiving signal VR2a falls. However, Fig. 12 illustrates a case in which the receiving signal VR2a also rises due to the influence of the rising voltage fluctuation Vdif at time t_on, and the subtraction voltage value does not exceed the first threshold value.

[0192] Due to the influence of such voltage fluctuation Vdif, the second signal S2a does not reflect the first pulse of the signal J1a and remains at "L." In Fig. 12, the pulse that would occur in the logical value of the second signal S2a if there was no influence of the voltage fluctuation Vdif is indicated by a dotted line.

[0193] The second pulse of the logical value of the signal J1a rises at time t_r. At time t_r, the voltage fluctuation Vdif is in a steady state, and neither of the receiving signals VR1a nor VR2a is affected by the voltage fluctuation Vdif. At time t_r, the receiving signal VR1a rises, the receiving signal VR2a falls, and the logical value of the second signal S2a rises. After that, a pulse reflecting the pulse train of the logical value of the signal J1a is generated in the logical value of the second signal S2a.

[0194] The logical value of the output potential OUT rises in response to the rising of the logical value of the second signal S2a. If the logical value of the second signal S2a reflects the first pulse of the logical value of the signal J1a (see the pulse shown by the dashed line), the logical value of the output potential OUT rises at time t_on (see the dashed line). Due to the effect of the voltage fluctuation Vdif, the logical value of the output potential OUT rises at time t_r.

[0195] The logical value of the output potential OUT falls in response to the rising edge of the logical value of the second signal S2b (not shown). For example, in the second signal S2b, a pulse train is generated in response to the falling edge of the input signal IN (see FIG. 9), so that the logical value of the output potential OUT falls at time t_off in FIG. 12.

[0196] Since it is desirable for the rising edge of the logical value of the output potential OUT to properly reflect the rising edge of the logical value of the input signal IN, when the first pulse of the pulse train of the logical value of the signal J1a is not reflected in the logical value of the second signal S2a, it is desirable for the subsequently occurring pulses to be reflected in the logical value of the second signal S2a. From this perspective, the occurrence of a pulse train including multiple pulses in the logical value of the signal J1a contributes to the logical value of the second signal S2a properly reflecting the logical value of the signal J1a, and therefore the output potential OUT properly reflecting the input signal IN, particularly at the rising edge.

[0197] If the voltage fluctuation Vdif is still increasing at the time when the second pulse rises (i.e., time t_r in accordance with FIG. 12), then this pulse may not be reflected in the logic value of the second signal S2a either. When the rising period is long, among the pulse trains generated in the logic value of the signal J1a, the number of pulses whose rising edges occur during the rising period is large. From this perspective, a pulse train may continue to be generated in the logic value of the signal J1a during the period when the logic value of the input signal IN is “H” and, consequently, the logic value of the first signal S1a remains “H”.

[0198] However, the malfunction where the waveform of the received signal VR2a is distorted by the voltage fluctuation Vdif and the subtracted voltage value does not exceed the first threshold does not necessarily occur corresponding to all the pulses whose rising edges occur during the rising period. The displacement current resulting from the voltage fluctuation Vdif tends to be smaller as the rising period is longer. This is because when the parasitic capacitance Cpa is small, the total amount of the displacement current is small, and the voltage fluctuation Vdif is smaller as the rising period is longer.

[0199] Therefore, just because a long rising period is assumed, it is not necessary to generate a pulse train throughout the entire rising period. On the other hand, a voltage fluctuation Vdif with a short rising period generates a large displacement current. Thus, the pulse generation circuit 101a generates a pulse train C1 in the signal J1a from the time t_on when the first signal S1a rises until the assumed value Ta elapses. The assumed value Ta is set to be the length assumed as the rising period for the voltage fluctuation Vdif caused by the displacement current having the minimum value that causes a malfunction, or a length longer than that length.

[0200] Introducing the number N of pulses in the pulse train C1, there is a relationship of (N - 1)·T1+Th<Ta<N·T1 between the assumed value Ta, one period T1 of the pulse, and the period length Th during which the pulse is “H” (in FIG. 12, N = 4).

[0201] The assumed value Ta is set to 12 ns, for example, when it is assumed that the potential difference of the potential HV,G3 is 1200 V and the time derivative (dv / dt) is 100 kV / μs, so 1200 V / (100 kV / μs)=12 ns.

[0202] After the assumed value Ta has elapsed from time t_on, the pulse generation circuit 101a may generate a pulse train C2 (hereinafter referred to as the "second pulse train" for the sake of convenience, and the pulse train from time t_on until the assumed value Ta has elapsed is also referred to as the "first pulse train") in the signal J1a. The generation of the second pulse train C2 is desirable from the viewpoint of enhancing the reliability of signal transmission from the input signal IN to the output potential OUT.

[0203] It can be said that the first pulse train C1 has a plurality of pulses generated during a part of the period in which the logical value of the signal J1a takes "H", and the second pulse train C2 has a plurality of pulses generated following the first pulse train C1 during the part. The assumed value Ta is adopted for the length of the part.

[0204] It is desirable that the second pulse train C2 is not generated from the viewpoint of reducing the power consumption. Also, even when the second pulse train C2 is generated according to the logical value of the signal J1a, reducing its generation frequency lower than that of the first pulse train C1 contributes to reducing the power consumption. For example, one cycle T2 of the pulses in the second pulse train C2 is longer than one cycle T1 of the pulses in the first pulse train C1. In FIG. 12, it is also exemplified that the pulses of the second pulse train C2 become "H" with the length of the period Th.

[0205] Regarding the logical value of the signal J1b, the pulse generation circuit 101b generates a pulse train from the time t_off (see FIG. 9) when the logical value of the first signal S1b rises until the assumed value Tb has elapsed. The assumed value Tb is set to be the length assumed as the rising period for the voltage fluctuation Vdif caused by the displacement current having the minimum value that causes malfunction, or longer than the length.

[0206] By introducing the number M of pulses in the pulse train, there is a relationship of (M - 1)·T1 + Th < Tb < M·T1 among the assumed value Tb, one cycle T1 of the pulses, and the period length Th during which the pulses are "H".

[0207] It is desirable from the viewpoint of improving the reliability of the signal transmission from the input signal IN to the output potential OUT that the pulse generating circuit 101b generates a pulse train in the signal J1b after the expected value Tb has elapsed from the time t_off, similarly to the second pulse train C2. The period of this pulse train is longer than the period of the pulse train generated from the time t_off until the expected value Tb has elapsed, which contributes to a reduction in current consumption.

[0208] The pulse trains of the signals J1x and J1y can be modified in the same manner as the pulse trains of the signals J1b and J1a, respectively. Similarly, the pulse train of the signal J1 can be modified in the same manner as the pulse train of the signal J1a.

[0209] <4. First modification of the first circuit> The fourth embodiment of the present disclosure relates to a first modification of the first circuits 100, 100a, 100b, 100x, and 100y. First, the first modification of the first circuit 100 will be described below.

[0210] FIG. 13 is a circuit diagram illustrating the configuration of a signal transmission circuit 1000 to which a first modification of the first circuit 100 is applied.

[0211] In the first modification, the first circuit 100 further includes a resistor 105. The resistor 105 includes one end connected to the first end P1 and the other end to which a potential VCC is applied. In the first circuit 100 illustrated in FIG. 1, the source of the transistor 103 is connected to the first end P1, but in the first modification, the one end of the resistor 105 is connected to the first end P1. The potential VT1 is the potential of the other end of the resistor 105, and is output from the first circuit 100 to the first end P1.

[0212] The resistance value of resistor 105 is a value approximate to the resistance value of the on-resistance of transistor 103 (hereinafter tentatively referred to as "on-resistance value"), specifically, for example, a value of 90 to 110% of the on-resistance value, desirably a value of 95 to 105% of the on-resistance value. When the voltage fluctuation Vdif causes the potential G2 serving as the reference of the second circuit 200 to be higher than the potential G1 serving as the reference of the first circuit 100, a displacement current flows in the first circuit 100.

[0213] The resistance value of resistor 105 being close to the on-resistance value of transistor 103 reduces the difference between the displacement current flowing through one end and first end P1 of first coil 11 and the displacement current flowing through the other end and second end P2 of first coil 11, contributing to preventing malfunctions, described below, caused by the difference. From this perspective, it is desirable that the wiring resistance from a power source (not shown) that applies a potential VCC to the other end of resistor 105 to the first end P1 be equal to the wiring resistance from the second end P2 to a power source (not shown) that applies a potential G1 to the source of transistor 104.

[0214] Even if the resistance value of resistor 105 differs from the on-resistance value of transistor 103, the effect of reducing the difference between these two types of displacement currents can be obtained, although the effect varies depending on the degree of the difference.

[0215] 14 and 15 are circuit diagrams showing elements through which displacement currents Idev1 and Idev2 flow when potential G2 rises relative to potential G1 under the influence of voltage fluctuation Vdif. Fig. 14 shows the path through which displacement current Idev2 flows via transistor 103. Fig. 15 shows the path through which displacement current Idev1 flows via resistor 105.

[0216] In the path shown in FIG. 14, a displacement current Idev2 flows from the diode 203 and resistor 208 of the clamp circuit 206 to the transistor 103 via the parasitic capacitance Cp that is parasitic on the transformer 10 between the second terminal P2 and the fourth terminal P4.

[0217] In the path shown in FIG. 15, a displacement current Idev1 flows from the diode 201 and resistor 207 of the clamp circuit 205 to the resistor 105 via the parasitic capacitance Cp that is parasitic on the transformer 10 between the first terminal P1 and the third terminal P3.

[0218] Here, the displacement currents Idev1 and Idev2 are generated during a transitional period when the time derivative dv / dt occurs. The displacement currents Idev1 and Idev2 do not flow between the first terminal P1 and the second terminal P2 to which the first coil 11 is connected, or between the third terminal P3 and the fourth terminal P4 to which the second coil 12 is connected. This is because the frequency of the displacement currents Idev1 and Idev2 generated during the transitional period is high, and the impedance of both the first coil 11 and the second coil 12 is high.

[0219] 1 is employed, a potential difference occurs between the first terminal P1 and the second terminal P2 due to the on-resistance of the transistor 103 and the displacement current Idev2. This potential difference reduces the amplitude of the pulse of the signal J1 generated by the pulse generating circuit 101, and thus affects the amplitude of the signals VRO1 and VRO2 input to the detection circuit 240, which may result in incorrect detection and lead to malfunction. The resistor 105 employed in the first modification contributes to suppressing the potential difference, and thus also contributes to suppressing the malfunction.

[0220] Fig. 16 is a waveform diagram illustrating the temporal changes of various signals in the first modification of the first circuit 100. Specifically, Fig. 16 illustrates the waveforms of the first signal S1, the signal J1, the potential difference ΔG, the currents I1 and I2, and the transmission signal VT2.

[0221] A current I1 flows through the first terminal P1, and a current I2 flows through the second terminal P2. With reference to FIG. 1, the direction of both currents I1 and I2 from the first circuit 100 to the first coil 11 is considered positive. A value H1 of the first signal S1 corresponds to a logical value "H" of the first signal S1. A value L1 of the first signal S1 corresponds to a logical value "L" of the first signal S1. A value H2 of the transmission signal VT2 is based on a potential G1 and corresponds to a logical value "H" of the transmission signal VT2. A potential difference ΔG is the voltage (G1-G2) of the potential G1 based on the potential G2.

[0222] The dashed waveform shows the case where the first circuit 100 illustrated in FIG. 1 without the resistor 105 is employed, and the solid waveform shows the case where the first variant is employed.

[0223] 16 also illustrates the waveform of the voltage fluctuation Vdif. A case is illustrated in which both events occur in which the time derivative dv / dt of the first coil 11 increases and decreases with respect to the second coil 12.

[0224] As shown by the dashed line, the waveforms of the currents I1 and I2 are significantly different when there is no resistor 105. This is because: the first terminal P1 is connected to the source of the transistor 103, and the second terminal P2 is connected to the drain of the transistor 103; the on-resistance of the transistor 103 exists between the first terminal P1 and the second terminal P2; and the resistance value from the first terminal P1 to the power supply that applies the potential VCC is different from the resistance value from the second terminal P2 to the power supply.

[0225] Due to the difference between the currents I1 and I2, the potential of the transmission signal VT2 temporarily drops. If the period in which the voltage fluctuation Vdif rises due to the drop in the time differential dv / dt overlaps with the period in which a pulse occurs in the logical value of the signal J1, the pulse is canceled out and disappears, which may lead to a malfunction in which the first circuit 100 cannot correctly transmit the transmission signal VT2.

[0226] When the resistor 105 is provided, the impedance of the path through which the displacement current Idev1 flows (see FIG. 15) and the impedance of the path through which the displacement current Idev2 flows (see FIG. 14) can be made closer to each other by adjusting the resistance value of the resistor 105. This makes the waveforms of the currents I1 and I2 closer to each other, the potential of the transmission signal VT2 is less likely to fluctuate, and the loss of the pulse is less likely to occur. In this way, the resistor 105 contributes to preventing the first circuit 100 from malfunctioning, and thus contributes to the appropriate output of the second signal S2.

[0227] The first modification can be applied to any of the first circuits 100a, 100b, 100x, and 100y. By applying this, the second signals S2a, S2b, S2x, and S2y are obtained by appropriately reflecting the first signals S1a, S1b, S1x, and S1y, specifically, by reflecting the pulse trains generated in the signals J1a, J1b, J1x, and J1y. Applying the first modification contributes to the output potential OUT output by the power conversion device 2000 appropriately reflecting the input signal IN.

[0228] <5. Second modification of the first circuit> The fifth embodiment of the present disclosure relates to a second modification of the first circuits 100, 100a, 100b, 100x, and 100y. First, the second modification of the first circuit 100 will be described below.

[0229] 17 is a circuit diagram illustrating a configuration of a signal transmission circuit 1000 to which the second modification of the first circuit 100 is applied. The second modification of the first circuit 100 has a configuration in which the resistor 105 of the first modification of the first circuit 100 is replaced with a transistor 106 in an on state.

[0230] Specifically, in the second modification, the first circuit 100 further includes a P-channel transistor 106. The transistor 106 includes a drain connected to the first terminal P1 and a source to which a fixed potential VCC is applied. In the first circuit 100 illustrated in FIG. 1, a potential VT1 is output from the source of the transistor 103 to the first terminal P1, but in the second modification, a potential VT1 is output from the drain of the transistor 106 to the first terminal P1.

[0231] For example, a potential G1 is applied to the gate of the transistor 106. The potential G1 is lower than the potential VCC applied to the source, and the transistor 106 is maintained in the on state.

[0232] The transistor 106 is a P-channel transistor having an on-resistance value that is slightly different from the on-resistance value of the transistor 103 .

[0233] Since transistors 106 and 103 are both P-channel transistors, the temperature characteristics of the on-resistance values ​​of the two are similar. This similarity in temperature characteristics brings about an advantage that, compared to the fourth embodiment, the function of preventing malfunction of first circuit 100 is less dependent on the temperature environment in which first circuit 100 is used and can be easily obtained over a wide temperature range.

[0234] Even if the on-resistance values ​​of the transistors 103 and 106 are different, the effect of reducing the difference between the two types of displacement currents can be obtained, although the effect differs depending on the degree of the difference.

[0235] An IGBT may be used for the transistor 103. For example, if an IGBT is used for the transistor 103, an IGBT is also used for the transistor 106. The collector and emitter of the IGBT can be considered as a first electrode and a second electrode that are mutually conductive by a signal applied to the gate. The gate can be considered as a third electrode that controls the conductivity between the first electrode and the second electrode.

[0236] In the first circuit 100, the first terminal P1 and the source of the transistor 104 can also be connected via an N-channel transistor in an on-state. In this case, a transistor having an on-resistance value that is slightly different from the on-resistance value of the transistor 104 is used as the N-channel transistor.

[0237] Even if the on-resistance value of the N-channel transistor differs from the on-resistance value of the transistor 103, the effect of reducing the difference between the two types of displacement currents can be obtained, although the effect varies depending on the degree of the difference.

[0238] An IGBT may be used as the transistor 104. For example, when an IGBT is used as the transistor 104, an IGBT in an on state is used instead of the above-mentioned N-channel transistor.

[0239] The second modification can be applied to any of the first circuits 100a, 100b, 100x, and 100y. By applying this, the second signals S2a, S2b, S2x, and S2y are obtained by appropriately reflecting the first signals S1a, S1b, S1x, and S1y, specifically, by reflecting the pulse trains generated in the signals J1a, J1b, J1x, and J1y. Applying the second modification contributes to the output potential OUT output by the power conversion device 2000 appropriately reflecting the input signal IN.

[0240] <6. Variations on the Limitation of Displacement Current> 1 and 11, for example, the higher the resistance value of resistor 207 in clamp circuit 205, the larger the voltage drop in resistor 207 becomes and the higher the voltage supported by diodes 201 and 202 becomes, so that the effect of voltage fluctuation Vdif is more easily suppressed.

[0241] The magnitude of the current limiting resistor can also be set from the following viewpoint: For example, if the rectification characteristics of the diodes 201 and 202 in the clamp circuit 205 are improved, the displacement current can be limited even if the resistance value of the resistor 207 is reduced, and typically the resistor 207 may be omitted.

[0242] However, if resistor 207 is omitted, the received signals VR1 and VR2 are also suppressed even though the displacement current is suppressed, which is undesirable from the viewpoint of transmitting signals. On the other hand, lowering the rectification characteristics of diodes 201 and 202 and increasing the resistance value of resistor 207 is undesirable from the viewpoint of loosening the restriction on the displacement current. It is desirable to set resistor 207 taking such a trade-off into consideration. The same applies to resistors 208, 207a, 208a, 207b, 208b, 207x, 208x, 207y, and 208y.

[0243] For example, the displacement current can be limited as follows, taking into consideration the appropriate voltage range of the detection circuit 240, the DC voltage D1, and the expected time differential dv / dt.

[0244] The upper limit of the appropriate voltage range is substantially lowered by clamp circuit 205. The lower limit of the appropriate voltage range is substantially raised by clamp circuit 206. Both the substantial lowering and increasing will be described assuming that their absolute values ​​are 1V.

[0245] For example, even if the appropriate voltage range is 0 to 5V, the substantial upper limit is lowered to 4V by clamp circuit 205, and the substantial upper limit is raised to 1V by clamp circuit 206. When the appropriate voltage range is 0 to 5V, its median value of 2.5V is adopted for DC voltage D1. And even when the appropriate voltage range has a substantial upper limit of 4V and a substantial lower limit of 0V by clamp circuits 205 and 206, 2.5V can be adopted for DC voltage D1. This is because the median value between these upper and lower limits is also 2.5V.

[0246] When the displacement current is limited by clamp circuit 205 but not limited by clamp circuit 206, the appropriate voltage range is substantially narrowed from 0 to 5 V to 0 to 4 V. In this case, it is desirable to adopt 2 V, the median value of 0 to 4 V, for DC voltage D1.

[0247] Alternatively, when the appropriate voltage range is 0 to 5V, but operation is unstable in the region near the boundary, the region where operation is unstable may be substantially eliminated using clamp circuits 205 and 206. For example, when operation of detection circuit 240 is unstable between 0 and 0.5V, clamp circuit 206 sets the substantial lower limit of the appropriate voltage range to 0.5V. For example, when operation of detection circuit 240 is unstable between 4.5 and 5V, clamp circuit 205 sets the substantial upper limit of the appropriate voltage range to 4.5V. Setting clamp circuits 205 and 206 in this manner to substantially narrow the appropriate voltage range contributes to avoiding unstable operation of detection circuit 240.

[0248] Assume that the appropriate voltage range is 0 to 5V, the median value of DC voltage D1 is 2.5V, and the substantial appropriate voltage range is narrowed to 2 to 3V by clamp circuits 205, 206. In such a case, the fluctuation of received signal VR1 increases due to voltage fluctuation Vdif (see FIG. 2), and assuming a fluctuation of, for example, 1V occurs, signal VRO1 rises to 3.5 (=2.5+1)V with respect to potential G2. At this time, the potential of signal VRO1 exceeds 3V, which is the upper limit of the appropriate voltage range of detection circuit 240, and detection circuit 240 may malfunction.

[0249] When the occurrence of voltage fluctuations Vdif that cause such fluctuations in received signal VR1 is anticipated, it is desirable to design clamp circuit 205 so that the upper limit of the substantial appropriate voltage range is higher than 3.5 V, for example, 4 V. If clamp circuit 205 is designed so that the upper limit of the substantial appropriate voltage range is 4 V and DC voltage D1 is maintained at 2.5 V, it is desirable to design clamp circuit 206 so that the lower limit of the substantial appropriate voltage range is 1 V.

[0250] The clamp circuits 205a, 206a, 205b, 206b, 205x, 206x, 205y, and 206y can be designed in a similar manner.

[0251] <7. Modifications of the lower arm circuit 2000b> The output potential OUT is the reference potential for the signal transmission circuits 1000a and 1000b of the upper arm circuit 2000a. Therefore, like the potential G2 that is the reference potential for the signal transmission circuit 1000, it is desirable to reduce the influence of the voltage fluctuation Vdif caused by the fluctuation of the output potential OUT. In contrast, the potential G3 that is the reference potential for the signal transmission circuits 1000x and 1000y of the lower arm circuit 2000b does not necessarily cause the voltage fluctuation Vdif. From this perspective, the signal transmission circuits 1000x and 1000y do not necessarily have to have the same configuration as the signal transmission circuit 1000.

[0252] Specifically, for example, the self-reset circuits 241x and 241y may be omitted in the signal transmission circuits 1000x and 1000y.

[0253] It should be noted that the embodiments can be freely combined, and each embodiment can be modified or omitted as appropriate.

[0254] Various aspects of the present disclosure are summarized below as appendices.

[0255] (Appendix 1) a first circuit that receives a first signal, generates a transmission signal according to a change in a logical value of the first signal, and operates based on a first potential; a transformer having a first coil to which the transmission signal is input from the first circuit, and a second coil inductively coupled with the first coil to output a pair of reception signals; a second circuit that receives the pair of reception signals from the second coil, performs a comparison having hysteresis with respect to a potential difference of the pair of reception signals to generate a second signal, and uses the second potential as a reference for operation; Equipped with The second circuit is a detection circuit that performs the comparison to detect whether the potential difference exceeds a predetermined range and outputs the result as the second signal; a reset circuit that resets the operation of the detection circuit when the logical value of the second signal is maintained for a preset period; A signal transmission circuit having the following features.

[0256] (Appendix 2) The second circuit is an offset circuit that generates a pair of third signals by applying a DC voltage based on the second potential as an offset voltage to the pair of received signals; and 2. The signal transmission circuit according to claim 1, wherein the detection circuit generates the second signal by performing the comparison on a potential difference between the pair of third signals generated by the offset circuit.

[0257] (Appendix 3) The offset circuit includes: a first input terminal to which one of the pair of received signals is input; a second input terminal to which the other of the pair of received signals is input; a first output terminal to which one of the pair of third signals is input; a second output terminal to which the other of the pair of third signals is input; a first resistor having one end connected to the first output terminal and the other end to which the DC voltage is applied; a second resistor having one end connected to the second output terminal and the other end to which the DC voltage is applied; a first capacitor connected between the first input terminal and the first output terminal; 3. The signal transmission circuit according to claim 2, further comprising a second capacitor connected between the second input terminal and the second output terminal.

[0258] (Appendix 4) The second circuit is a first clamp circuit and a second clamp circuit connected in series between the first input terminal and the second input terminal; and The first clamp circuit is A first diode; a second diode connected in parallel with the first diode and having a forward direction opposite to that of the first diode; a first current limiting resistor connected in series with each of the first diode and the second diode; Including, The second clamp circuit is A third diode; a fourth diode connected in parallel with the third diode and having a forward direction opposite to that of the third diode; a second current limiting resistor connected in series with each of the third diode and the fourth diode; 4. The signal transmission circuit of claim 3,

[0259] (Appendix 5) The first circuit is a pulse generating circuit that generates a fourth signal generated by a first pulse train having a plurality of pulses during a portion of a period during which the first signal has a first logical value, and a second pulse train having a plurality of pulses following the first pulse train during the portion; an output circuit that generates the transmission signal in response to a change in the logical value of the fourth signal; Including, 5. The signal transmission circuit according to claim 1, wherein one period of pulses in the second pulse train is longer than one period of pulses in the first pulse train.

[0260] (Appendix 6) The output circuit includes: a transistor having a first electrode to which a fixed potential is applied, a second electrode that outputs the transmission signal, and a third electrode to which the fourth signal is applied and that controls conduction between the first electrode and the second electrode; Including, The first circuit is a third resistor having one end connected to one end of the first coil and the other end to which the fixed potential is applied; 6. The signal transmission circuit of claim 5, further comprising:

[0261] (Appendix 7) The output circuit includes: a first transistor having a first electrode to which a fixed potential is applied, a second electrode that outputs the transmission signal, and a third electrode to which the fourth signal is applied and that controls conduction between the first electrode and the second electrode; Including, The first circuit is a second transistor in an on-state, the second transistor having a first electrode connected to one end of the first coil and a second electrode to which the fixed potential is applied; 6. The signal transmission circuit of claim 5, further comprising:

[0262] (Appendix 8) An output line; a first switching element having one end to which a fixed potential is applied and the other end connected to the output line; a second switching element having one end connected to the output line and another end to which a third potential is applied, the second switching element being turned on exclusively with the first switching element; A first signal transmission circuit employing the signal transmission circuit according to any one of Supplementary Note 1 to Supplementary Note 5; A second signal transmission circuit in which the signal transmission circuit according to any one of Supplementary Note 1 to Supplementary Note 5 is adopted; a first latch circuit that outputs a signal for controlling whether or not the first switching element is conductive, that is set by the second signal output by the first signal transmission circuit, and that is reset by the second signal output by the second signal transmission circuit; Equipped with a power conversion device, wherein both the second potential in the first signal transmission circuit and the second potential in the second signal transmission circuit are the potential of the output line.

[0263] (Appendix 9) A third signal transmission circuit in which the signal transmission circuit according to any one of Supplementary Note 1 to Supplementary Note 5 is adopted; A fourth signal transmission circuit in which the signal transmission circuit according to any one of Supplementary Note 1 to Supplementary Note 5 is adopted; a second latch circuit that outputs a signal for controlling whether or not the second switching element is conductive, that is set by the second signal output by the third signal transmission circuit, and that is reset by the second signal output by the fourth signal transmission circuit; Further comprising: The power conversion device according to claim 8, wherein the second potential in the third signal transmission circuit and the second potential in the fourth signal transmission circuit are both the third potential. [Explanation of symbols]

[0264] 2a, 2b switching elements, 6a, 6b latch circuit, 7 output line, 10, 10a, 10b, 10x, 10y transformer, 11 first coil, 12, 12a, 12b, 12x, 12y second coil, 100, 100a, 100b, 100x, 100y first circuit, 101, 101a, 101b, 101x, 101y pulse generating circuit, 102, 102a, 102b, 102x, 102y output circuit, 103, 103a, 103b, 103x, 103y, 106 transistor, 105, 207, 207a, 207b, 207x, 207y, 208, 208a, 208b, 208x, 208y Resistors, 200, 200a, 200b, 200x, 200y Second circuit, 201 to 204, 201a to 204a, 201b to 204b, 201x to 204x, 201y to 204y Diodes, 205, 205a, 205b, 205x, 205y, 206, 206a, 206b, 206x, 206y Clamp circuits, 220, 220a, 220b, 220x, 220y Offset circuits, 221, 221a, 221b, 221x, 221y, 222, 222a, 222b, 222x, 222y Capacitor, 223, 223a, 223b, 223x, 223y, 224, 224a, 224b, 224x, 224y Voltage dividing resistor, 240, 240a, 240b, 240x, 240y Detection circuit, 241, 241a, 241b, 241x, 241y Self-reset circuit, 1000, 1000a, 1000b, 1000x, 1000y Signal transmission circuit, 2000 Power conversion device, C1 First pulse train, C2 Second pulse train, D1, D1a, D1b, D1x, D1y DC voltage, G1, G2, G3, HV, VCC Potential, i, ia, ib Current, J1,J1a,J1b,J1x,J1y,Qa,Qb,VRO1,VRO1a,VRO1b,VRO1x,VRO1y,VRO2,VRO2a,VRO2b,VRO2x,VRO2y Signal, P1,P1a,P1b,P1x,P1y 1st end, OUT Output potential, P5,P5a,P5b,P5x,P5y,P6,P6a,P6b,P6x,P6y Input terminal, P7,P7a,P7b,P7x,P7y,P8,P8a,P8b,P8x,P8y Output terminal, S1,S1a,S1x,S1y 1st signal, S2, S2a, S2b, S2x, S2y 2nd signal, T1, T2 one cycle, Ta expected value, VR1,VR1a,VR1b,VR1x,VR1y,VR2,VR2a,VR2b,VR2x,VR2y are received signals, VT2,VT2a,VT2b,VT2x,VT2y are transmitted signals, ΔV,ΔVa,ΔVb,ΔVx,ΔVy are subtracted voltage values.

Claims

1. a first circuit that receives a first signal, generates a transmission signal according to a change in a logical value of the first signal, and operates based on a first potential; a transformer including a first coil to which the transmission signal is input from the first circuit, and a second coil inductively coupled with the first coil to output a pair of reception signals; a second circuit that receives the pair of reception signals from the second coil, performs a comparison having hysteresis with respect to a potential difference of the pair of reception signals to generate a second signal, and uses the second potential as a reference for operation; Equipped with The second circuit is a detection circuit that performs the comparison to detect whether the potential difference exceeds a predetermined range and outputs the result as the second signal; a reset circuit that resets the operation of the detection circuit when the logical value of the second signal is maintained for a preset period; A signal transmission circuit having the following features.

2. The second circuit is an offset circuit for generating a pair of third signals obtained by applying a DC voltage based on the second potential as an offset voltage to the pair of received signals; Further comprising:

2. The signal transmission circuit according to claim 1, wherein the detection circuit generates the second signal by performing the comparison on a potential difference between the pair of third signals generated by the offset circuit.

3. The offset circuit includes: a first input terminal to which one of the pair of received signals is input; a second input terminal to which the other of the pair of received signals is input; a first output terminal to which one of the pair of third signals is input; a second output terminal to which the other of the pair of third signals is input; a first resistor having one end connected to the first output terminal and the other end to which the DC voltage is applied; a second resistor having one end connected to the second output terminal and the other end to which the DC voltage is applied; a first capacitor connected between the first input terminal and the first output terminal; 3. The signal transmission circuit according to claim 2, further comprising a second capacitor connected between the second input terminal and the second output terminal.

4. The second circuit is a first clamp circuit and a second clamp circuit connected in series between the first input terminal and the second input terminal; Further comprising: The first clamp circuit includes: A first diode; a second diode connected in parallel with the first diode and having a forward direction opposite to that of the first diode; a first current limiting resistor connected in series with each of the first diode and the second diode; Including, The second clamp circuit includes: A third diode; a fourth diode connected in parallel with the third diode and having a forward direction opposite to that of the third diode; a second current limiting resistor connected in series with each of the third diode and the fourth diode; The signal transmission circuit according to claim 3 .

5. The first circuit is a pulse generating circuit that generates a fourth signal generated by a first pulse train having a plurality of pulses during a portion of a period during which the first signal has a first logical value, and a second pulse train having a plurality of pulses following the first pulse train during the portion; an output circuit that generates the transmission signal in response to a change in the logical value of the fourth signal; Including, 5. The signal transmission circuit according to claim 1, wherein one period of the pulses in the second pulse train is longer than one period of the pulses in the first pulse train.

6. The output circuit includes: a transistor having a first electrode to which a fixed potential is applied, a second electrode that outputs the transmission signal, and a third electrode to which the fourth signal is applied and that controls conduction between the first electrode and the second electrode; Including, The first circuit is a third resistor having one end connected to one end of the first coil and the other end to which the fixed potential is applied; The signal transmission circuit according to claim 5 , further comprising:

7. The output circuit includes: a first transistor having a first electrode to which a fixed potential is applied, a second electrode that outputs the transmission signal, and a third electrode to which the fourth signal is applied and that controls conduction between the first electrode and the second electrode; Including, The first circuit is a second transistor in an on-state, the second transistor having a first electrode connected to one end of the first coil and a second electrode to which the fixed potential is applied; The signal transmission circuit according to claim 5 , further comprising:

8. An output line; a first switching element having one end to which a fixed potential is applied and the other end connected to the output line; a second switching element having one end connected to the output line and the other end to which a third potential is applied, the second switching element being turned on exclusively with the first switching element; A first signal transmission circuit in which the signal transmission circuit according to claim 1 is adopted; A second signal transmission circuit in which the signal transmission circuit according to claim 1 is adopted; a first latch circuit that outputs a signal for controlling whether or not the first switching element is conductive, that is set by the second signal output from the first signal transmission circuit, and that is reset by the second signal output from the second signal transmission circuit; Equipped with a second potential in the first signal transmission circuit and a second potential in the second signal transmission circuit, the second potential being equal to a potential of the output line;

9. a third signal transmission circuit in which the signal transmission circuit according to claim 1 is adopted; a fourth signal transmission circuit in which the signal transmission circuit according to claim 1 is adopted; a second latch circuit that outputs a signal for controlling whether or not the second switching element is conductive, that is set by the second signal output by the third signal transmission circuit, and that is reset by the second signal output by the fourth signal transmission circuit; Further comprising: The power conversion device according to claim 8 , wherein both the second potential in the third signal transmission circuit and the second potential in the fourth signal transmission circuit are the third potential.

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