Semiconductor device, motor system, in-vehicle device, and vehicle

Abstract

To provide a semiconductor device capable of identifying which detection among at least two detections by a plurality of protection circuits triggered the other detection when a state requiring protection is detected.SOLUTION: A semiconductor device (1) includes a plurality of protection circuits (21-25) and a memory circuit (27) configured to store identification information for identifying the protection circuit that has detected a state requiring protection. The identification information includes order information. The order information includes information regarding at least the first protection circuit in the order of detection among the plurality of protection circuits.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The invention disclosed in this specification relates to a semiconductor device, a motor system, an in-vehicle device, and a vehicle. [Background technology]

[0002] Conventionally, various semiconductor integrated circuit devices equipped with a plurality of protection circuits have been developed (see, for example, Patent Document 1).

[0003] Each of the multiple protection circuits outputs a protection signal that is at a low level when it does not detect a state requiring protection (when no abnormality is detected) and is at a high level when it detects a state requiring protection (when an abnormality is detected). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent Publication No. 2021-65040

[0005] [overview] The protection signals output from the protection circuits are stored in, for example, a register. The data stored in the register is used to identify the cause of a malfunction when a malfunction occurs in, for example, the semiconductor integrated circuit device.

[0006] However, when at least two of a plurality of protection circuits detect a state requiring protection, there is a problem in that it is not clear which detection triggered the other detection.

[0007] The semiconductor device disclosed in the present specification includes a plurality of protection circuits and a memory circuit configured to store identification information for identifying the protection circuit that has detected a state requiring protection. The identification information includes order information. The order information includes information regarding at least the first protection circuit in the order of detection of the plurality of protection circuits.

[0008] A motor system disclosed in this specification includes the semiconductor device configured as described above, an inverter, and a motor. The semiconductor device is a motor drive device configured to drive the motor via the inverter.

[0009] The in-vehicle device disclosed in this specification includes a motor system having the above-described configuration.

[0010] The vehicle disclosed in this specification includes the on-board device having the above-described configuration. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a diagram showing a schematic configuration of a motor system according to an embodiment. [Diagram 2] FIG. 2 is a perspective view of the appearance of the semiconductor integrated circuit device. [Diagram 3] FIG. 3 is a timing chart of the protection signal. [Figure 4] FIG. 4 is a diagram illustrating a first example of the contents stored in a register. [Diagram 5] FIG. 5 is a diagram showing a reference example of the contents stored in a register. [Figure 6] FIG. 6 is a diagram illustrating a second example of the contents stored in the register. [Figure 7] FIG. 7 is a diagram illustrating a third example of the contents stored in the register. [Figure 8] FIG. 8 is a diagram illustrating a fourth example of the contents stored in the register. [Figure 9] FIG. 9 is a diagram illustrating a relationship between bit data and a protection circuit. [Figure 10] FIG. 10 is a diagram illustrating a fifth example of the contents stored in the register. [Figure 11] FIG. 11 is a diagram illustrating a relationship between bit data and a protection circuit. [Figure 12] FIG. 12 is a diagram illustrating a relationship between bit data and a protection circuit. [Figure 13] FIG. 13 is a diagram illustrating a relationship between bit data and a protection circuit. [Figure 14] FIG. 14 is an external perspective view of the vehicle.

[0012] [Detailed Description] <Motor system> 1 is a diagram showing a schematic configuration of a motor system SYS1 according to an embodiment. The motor system SYS1 includes a semiconductor device 1, high-side switches 2H-4H, low-side switches 2L-4L, a motor 5, Hall sensors 6-8, a host device 9, and a capacitor C1.

[0013] The semiconductor device 1 is a motor driving device.

[0014] In this embodiment, the high-side switches 2H to 4H and the low-side switches 2L to 4L are each an N-channel MOS (Metal Oxide Semiconductor) field effect transistor. The high-side switches 2H to 4H and the low-side switches 2L to 4L may each be configured with a switch element other than an N-channel MOS field effect transistor. The high-side switches 2H to 4H and the low-side switches 2L to 4L form an inverter. The motor 5 is a three-phase brushless DC motor. The hall sensor 6 is a U-phase hall sensor, the hall sensor 7 is a V-phase hall sensor, and the hall sensor 8 is a W-phase hall sensor. The host device 9 is, for example, an MCU (Micro Controller Unit).

[0015] The semiconductor device 1 drives the motor 5 via an inverter based on the differential Hall signals output from the Hall sensors 6 to 8 and a control signal output from a host device 9.

[0016] A connection node between the high-side switch 2H and the low-side switch 2L is connected to the U-phase of the motor 5. A connection node between the high-side switch 3H and the low-side switch 3L is connected to the V-phase of the motor 5. A connection node between the high-side switch 4H and the low-side switch 4L is connected to the W-phase of the motor 5.

[0017] The semiconductor device 1 is a semiconductor integrated circuit device 1A shown in Fig. 2. The semiconductor integrated circuit device 1A is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a case (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the case to the outside of the semiconductor integrated circuit device 1A. The semiconductor integrated circuit device 1A is formed by encapsulating the semiconductor chip in a case (package) made of resin. Note that the number of external terminals of the semiconductor integrated circuit device 1A and the type of case for the semiconductor integrated circuit device 1A shown in Fig. 2 are merely examples, and can be designed arbitrarily.

[0018] 1, the semiconductor device 1 includes comparators 10 to 12, a logic circuit 13, pre-drivers 14 to 19, a charge pump circuit 20, protection circuits 21 to 25, and a communication circuit 26. The logic circuit 13 includes a register 27.

[0019] The semiconductor device 1 also has terminals B, HU+, HU-, HV+, HV-, HW+, HW-, C, C_P, C_M, DUH, VS_U, DUL, DVH, VS_V, DVL, DWH, VS_W, DWL, and PGND as external terminals for establishing electrical connection with the outside.

[0020] The comparator 10 supplies the logic circuit 13 with a result of comparison between the differential Hall signals output from the Hall sensor 6. The comparator 11 supplies the logic circuit 13 with a result of comparison between the differential Hall signals output from the Hall sensor 7. The comparator 12 supplies the logic circuit 13 with a result of comparison between the differential Hall signals output from the Hall sensor 8.

[0021] The logic circuit 13 controls the pre-drivers 14 to 19 based on the output signals of the comparators 10 to 12 and a control signal output from the host device 9, thereby controlling the energization of the motor 5.

[0022] The pre-drivers 14, 16, and 18 drive the high-side switches 2H to 4H, respectively. The pre-drivers 15, 17, and 19 drive the low-side switches 2L to 4L, respectively.

[0023] The charge pump circuit 20 uses a capacitor C1 to boost the power supply voltage VCC to a voltage VG. The voltage VG is supplied to the positive power supply terminals of the pre-drivers 14, 16, and 18.

[0024] The protection circuits 21 to 25 detect an abnormality in the semiconductor device 1. As described later, the actual protection operation is performed by the logic circuit 13, and therefore the protection circuits 21 to 25 may be called abnormality detection circuits.

[0025] The protection circuit 21 outputs a protection signal S1 to the logic circuit 13. The protection signal S1 goes to high level when it detects a state where an undervoltage abnormality occurs in the power supply voltage VCC, that is, a state where the semiconductor device 1 needs to be protected, and goes to low level when it detects a state where an undervoltage abnormality does not occur in the power supply voltage VCC. When the protection signal S1 is at high level, the logic circuit 13 performs a protection operation for the semiconductor device 1 (for example, an operation of setting all output signals of the pre-drivers 14 to 19 to low level).

[0026] The protection circuit 22 outputs a protection signal S2 to the logic circuit 13. The protection signal S2 goes to high level when it detects a state in which an overvoltage abnormality occurs in the power supply voltage VCC, that is, a state in which protection of the semiconductor device 1 is necessary, and goes to low level when it detects a state in which an overvoltage abnormality does not occur in the power supply voltage VCC. When the protection signal S2 is at high level, the logic circuit 13 performs a protection operation for the semiconductor device 1 (for example, an operation to stop the boost operation of the charge pump circuit 20).

[0027] The protection circuit 23 outputs a protection signal S3 to the logic circuit 13. The protection signal S3 becomes high level when it detects a state in which a low voltage abnormality occurs in the voltage VG output from the charge pump circuit 20, that is, a state in which protection of the semiconductor device 1 is necessary, and becomes low level when it detects a state in which a low voltage abnormality does not occur in the voltage VG output from the charge pump circuit 20. When the protection signal S3 is at a high level, the logic circuit 13 performs a protection operation for the semiconductor device 1 (for example, an operation of setting all output signals of the pre-drivers 14, 16, and 18 to a low level and setting all output signals of the pre-drivers 15, 17, and 19 to a high level).

[0028] The protection circuit 24 outputs a protection signal S4 to the logic circuit 13. The protection signal S4 becomes high level when it detects a state in which a low voltage abnormality occurs in the gate-source voltage of one of the high-side switches 2H to 4H and the low-side switches 2L to 4L that should be turned on by the control of the logic circuit 13, that is, a state in which protection of the semiconductor device 1 is required, and becomes low level when it detects a state in which a low voltage abnormality does not occur in the gate-source voltage of one of the high-side switches 2H to 4H and the low-side switches 2L to 4L that should be turned on by the control of the logic circuit 13. When the protection signal S4 is at high level, the logic circuit 13 performs a protection operation for the semiconductor device 1 (for example, an operation of setting all output signals of the pre-drivers 14 to 19 to low level).

[0029] The protection circuit 25 outputs a protection signal S5 to the logic circuit 13. The protection signal S5 becomes high level when detecting a state in which an overvoltage abnormality occurs in the drain-source voltage of one of the high-side switches 2H to 4H and the low-side switches 2L to 4L that should be turned on by the control of the logic circuit 13, that is, a state in which protection of the semiconductor device 1 is required, and becomes low level when detecting a state in which an overvoltage abnormality does not occur in the drain-source voltage of one of the high-side switches 2H to 4H and the low-side switches 2L to 4L that should be turned on by the control of the logic circuit 13. When the protection signal S5 is at high level, the logic circuit 13 performs a protection operation for the semiconductor device 1 (for example, an operation of setting all output signals of the pre-drivers 14 to 19 to low level).

[0030] The communication circuit 26 performs communication with the host device 9 .

[0031] The register 27 stores identification information for identifying a protection circuit that has detected a state requiring protection of the semiconductor device 1. When there are multiple protection circuits that have detected a state requiring protection of the semiconductor device 1, the identification information may be information for identifying all of the protection circuits that have detected the state requiring protection of the semiconductor device 1, or information for identifying some of the protection circuits that have detected the state requiring protection of the semiconductor device 1.

[0032] <Register contents> Here, the contents stored in the register 27 after time t1 shown in FIG. 3 when the protection signals S1 to S5 change as shown in the timing chart of FIG. 3 will be described.

[0033] The transitions of the protection signals S1 to S5 shown in FIG. 3 occur when an overvoltage occurs in the power supply voltage VCC, for example, when the protection operation by the protection signal S2 is an operation to stop the boost operation of the charge pump circuit 20, when the protection operation by the protection signal S3 is an operation to set all output signals of the pre-drivers 14, 16, and 18 to a low level and all output signals of the pre-drivers 15, 17, and 19 to a high level, and when the protection operation by the protection signal S4 is an operation to set all output signals of the pre-drivers 14 to 19 to a low level.

[0034] In this case, if the power supply voltage VCC becomes an overvoltage, the protection signal S2 goes to high level and the boost operation of the charge pump circuit 20 stops. As a result of the boost operation of the charge pump circuit 20 stopping, the voltage VG output from the charge pump circuit 20 becomes a low voltage, so that the protection signal S3 goes to high level and the U, V, and W phases of the motor 5 go to low level (ground potential), and as the U, V, and W phases of the motor 5 go to low level (ground potential), the protection signal S4 goes to high level.

[0035] FIG. 4 is a diagram showing a first example of the contents stored in the register 27. In the first example shown in FIG. 4, the register 27 stores in the address A1 that the protection circuit that first detected the state in which the semiconductor device 1 needs protection is the protection circuit 22. In FIG. 4 and FIGS. 5 to 7, 8, 9, and 11 to 13 described later, "VCC UVLO" means the protection circuit 21, "VCC OVP" means the protection circuit 22, "VG UVLO" means the protection circuit 23, "VGS UVLO" means the protection circuit 24, and "VDS UVLO" means the protection circuit 25. In FIG. 4, "1" means that the protection circuit is the first to detect the state in which the semiconductor device 1 needs protection, and "0" means that the protection circuit is other than the protection circuit that first detected the state in which the semiconductor device 1 needs protection.

[0036] 4, the specific information stored by register 27 includes sequence information, which is information about the first detection order of the multiple protection circuits. Therefore, when at least two of the multiple protection circuits detect a state requiring protection, it is possible to know which detection triggered the other detections, based on the stored contents of register 27. In addition, because the sequence information does not include information about the second or subsequent detections, the data capacity of register 27 can be reduced.

[0037] 5 is a diagram showing a reference example of the contents stored in the register 27. In FIG. 5, "1" means that the protection circuit has detected a state in which the semiconductor device 1 needs protection, and "0" means that the protection circuit has not detected a state in which the semiconductor device 1 needs protection. In the reference example shown in FIG. 5, the specific information stored in the register 27 does not include order information. Therefore, although it is possible to know from the contents stored in the register 27 that the protection circuits that have detected a state in which the semiconductor device 1 needs protection are the protection circuits 22, 23, and 24, when at least two of the multiple protection circuits have detected a state in which protection is needed, it is not possible to know which detection triggered the detection of the others.

[0038] FIG. 6 is a diagram showing a second example of the contents stored in the register 27. In the second example shown in FIG. 6, the register 27 stores in the address A1 that the protection circuit that first detected the state in which the semiconductor device 1 needs protection is the protection circuit 22, the protection circuit that second detected the state in which the semiconductor device 1 needs protection is the protection circuit 23, and the protection circuit that third detected the state in which the semiconductor device 1 needs protection is the protection circuit 24. In FIG. 6, in the area of ​​"1st DET", "1" means that the protection circuit is the first to detect the state in which the semiconductor device 1 needs protection, and "0" means that the protection circuit is other than the protection circuit that first detected the state in which the semiconductor device 1 needs protection. Similarly, in FIG. 6, in the area of ​​"2nd DET", "1" means that the protection circuit is the second to detect the state in which the semiconductor device 1 needs protection, and "0" means that the protection circuit is other than the protection circuit that second detected the state in which the semiconductor device 1 needs protection. Similarly, in FIG. 6 , in the “3rd DET” area, “1” means that this is the protection circuit that was the third to detect a state in which protection of the semiconductor device 1 is required, and “0” means that this is a protection circuit other than the third to detect a state in which protection of the semiconductor device 1 is required.

[0039] 6, the specific information stored by register 27 includes order information, and the order information includes information regarding all orders of detection by the multiple protection circuits. Therefore, when at least two of the multiple protection circuits detect a state requiring protection, it is possible to know which detection triggered the other detections, based on the stored contents of register 27. In addition, since the order information includes information regarding all orders of detection by the multiple protection circuits, the entire transition of detection by the multiple protection circuits can also be understood based on the stored contents of register 27.

[0040] Fig. 7 is a diagram showing a third example of the storage contents of register 27. In the second example of the storage contents of register 27 shown in Fig. 6, all pieces of information relating to the orders are stored at the same address A1, whereas in the third example of the storage contents of register 27 shown in Fig. 7, all pieces of information relating to the orders are stored at different addresses for each order. Specifically, in the third example of the storage contents of register 27 shown in Fig. 7, information relating to the first order is stored at address A1, information relating to the second order is stored at address A2, and information relating to the third order is stored at address A1.

[0041] Except for the points described above, the third example of the storage contents of register 27 shown in Fig. 7 is the same as the second example of the storage contents of register 27 shown in Fig. 6. The third example of the storage contents of register 27 shown in Fig. 7 allows access to only necessary information, thereby reducing the amount of data to be read.

[0042] Fig. 8 is a diagram illustrating a fourth example of the stored contents of register 27. In the fourth example illustrated in Fig. 8, register 27 stores in address A1 that protection circuit 22 is the protection circuit that first detected a state in which protection of semiconductor device 1 is required.

[0043] The protection circuit that first detects a state in which protection of the semiconductor device 1 is required is represented by the bit data D2, D1, and D0. Since the relationship between the bit data D2, D1, and D0 and the protection circuits is as shown in Fig. 9, in the fourth example shown in Fig. 8, the protection circuit that first detects a state in which protection of the semiconductor device 1 is required is the protection circuit 22.

[0044] 8, the order information stored in the register 27 is information about a protection circuit that has detected a state requiring protection of the semiconductor device 1. In other words, the order information stored in the register 27 does not include information about a protection circuit that has not detected a state requiring protection of the semiconductor device 1. Therefore, the data capacity of the register 27 can be reduced.

[0045] Fig. 10 is a diagram showing a schematic diagram of a fifth example of the stored contents of the register 27. In the fifth example shown in Fig. 10, the register 27 stores in an address A1 that the protection circuit that first detected a state in which the semiconductor device 1 needs protection is the protection circuit 22, the protection circuit that second detected a state in which the semiconductor device 1 needs protection is the protection circuit 23, and the protection circuit that third detected a state in which the semiconductor device 1 needs protection is the protection circuit 24.

[0046] The protection circuit that first detects a state in which protection of the semiconductor device 1 is required is represented by the bit data D8, D7, and D6. Since the relationship between the bit data D8, D7, and D6 and the protection circuits is as shown in Fig. 10, in the fifth example shown in Fig. 10, the protection circuit that first detects a state in which protection of the semiconductor device 1 is required is the protection circuit 22.

[0047] The protection circuit that is second to detect a state requiring protection of the semiconductor device 1 is represented by the bit data D5, D4, and D3. Since the relationship between the bit data D5, D4, and D3 and the protection circuits is as shown in Fig. 12, in the fifth example shown in Fig. 10, the protection circuit that is second to detect a state requiring protection of the semiconductor device 1 is the protection circuit 23.

[0048] The protection circuit that is the third to detect a state requiring protection of the semiconductor device 1 is represented by the bit data D2, D1, and D0. Since the relationship between the bit data D2, D1, and D0 and the protection circuits is as shown in Fig. 13, in the fifth example shown in Fig. 10, the protection circuit that is the third to detect a state requiring protection of the semiconductor device 1 is the protection circuit 24.

[0049] 10, the register 27 does not include information regarding protection circuits that do not detect a state requiring protection of the semiconductor device 1. Therefore, the data capacity of the register 27 can be reduced.

[0050] The communication circuit 26 may transmit specific information to the host device 9 and receive a command based on the specific information from the host device 9. This makes it possible to partially reset the semiconductor device 1 in accordance with the specific information, rather than resetting the entire semiconductor device 1 based on the specific information. Also, for example, when protection of the U phase is detected first, it is possible to protect only the U phase and continue driving the motor 5 using only the remaining V phase and W phase.

[0051] <Motor system application examples> Fig. 14 is an external view of a vehicle X. The vehicle X shown in Fig. 14 is equipped with various electronic devices X11 to X18 that operate by receiving a supply of voltage output from a battery (not shown). Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual positions for convenience of illustration.

[0052] The electronic device X11 is an engine control unit that performs engine-related controls (such as injection control, electronic throttle control, idling control, oxygen sensor heater control, and auto-cruise control).

[0053] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamps) and DRL (daytime running lamps).

[0054] The electronic device X13 is a transmission control unit that performs control related to the transmission.

[0055] The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, electronic suspension control, etc.).

[0056] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and the like.

[0057] The electronic device X16 is an electronic device that is installed in the vehicle X at the factory as a standard equipment or a manufacturer's option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0058] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0059] The X18 electronic equipment is an electronic device equipped with a high-voltage motor, such as an EPS [Electric Power Steering], an in-vehicle blower, an oil pump, a water pump, or a battery cooling fan.

[0060] The motor system described above can be incorporated into any of the electronic devices X11 to X18 that require a motor.

[0061] <Other> The above-described embodiments should be considered in all respects as illustrative and not restrictive, and the technical scope of the invention disclosed in this specification is indicated by the claims, not by the description of the above-described embodiments, and should be understood to include all modifications that fall within the meaning and scope of the claims.

[0062] For example, the semiconductor device is not limited to a motor drive device as long as it includes a plurality of protection circuits and a memory circuit, and may be, for example, a gate driver, a DC / DC converter, or the like.

[0063] The types of abnormalities detected by the protection circuit are not limited to those described in the embodiment, and may be, for example, overcurrent, overheating, and the like.

[0064] <Additional Notes> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0065] The semiconductor device (1) of the present disclosure comprises a plurality of protection circuits (21-25) and a memory circuit (27) configured to store specific information for identifying the protection circuit that has detected a state requiring protection, the specific information including sequence information, and the sequence information includes information regarding at least the first protection circuit in terms of the detection sequence of the plurality of protection circuits (first configuration).

[0066] According to the semiconductor device of the first configuration described above, when at least two of the multiple protection circuits detect a state requiring protection, it is possible to determine which detection triggered the other detections.

[0067] In the semiconductor device of the first configuration, the sequence information may be information relating to the first order (second configuration).

[0068] In the semiconductor device of the first configuration, the sequence information may include information relating to all orders (third configuration).

[0069] In the semiconductor device of the third configuration, the storage circuit may be configured to store all of the information relating to the orders at different addresses for each order (fourth configuration).

[0070] In the semiconductor device of any one of the first to fourth configurations, the order information may be information about the protection circuit that detected a state requiring protection (fifth configuration).

[0071] The semiconductor device of any of the first to fifth configurations may be configured (sixth configuration) to include a communication circuit (26) configured to transmit the specific information to an external device (9) disposed outside the semiconductor device and to receive a command based on the specific information from the external device.

[0072] The semiconductor device according to any one of the first to sixth configurations may be configured as a motor drive device (seventh configuration) configured to drive the motor (5) via inverters (2H to 4H, 2L to 4L).

[0073] A motor system (SYS1) according to the present disclosure includes the semiconductor device of the seventh configuration, the inverter, The motor is also provided (eighth configuration).

[0074] The in-vehicle devices (X11 to X18) of the present disclosure have a configuration (ninth configuration) including the motor system of the eighth configuration.

[0075] A vehicle (X) of the present disclosure has a configuration (tenth configuration) including the on-vehicle device of the ninth configuration described above. [Explanation of symbols]

[0076] 1 Semiconductor device 1A Semiconductor integrated circuit device 2H, 3H, 4H High Side Switch 2L, 3L, 4L Low Side Switch 5 Motor 6~8 Hall sensors 9 Host Device 10~11 Comparator 13 Logic Circuits 14~19 Pre-driver 20 Charge pump circuit 21~25 Protection circuit 26 Communication Circuits 27 Registers C1 Capacitor SYS1 Motor system X11~X18 Electronic equipment X Vehicle

Claims

1. A plurality of protection circuits; a memory circuit configured to store identification information identifying the protection circuit that detected a condition requiring protection; Equipped with The specific information includes order information, The sequence information includes information regarding at least a first detection sequence of the protection circuits.

2. The semiconductor device according to claim 1 , wherein the sequence information is information regarding the first order.

3. The semiconductor device according to claim 1 , wherein said sequence information includes information regarding all sequences.

4. 4. The semiconductor device according to claim 3, wherein said memory circuit is configured to store all of said information relating to said orders at different addresses for each order.

5. 5. The semiconductor device according to claim 1, wherein the order information is information regarding the protection circuit that has detected a state requiring protection.

6. The semiconductor device according to claim 1 , further comprising a communication circuit configured to transmit the specific information to an external device disposed outside the semiconductor device, and to receive a command based on the specific information from the external device.

7. 10. The semiconductor device according to claim 1, which is a motor drive device configured to drive a motor via an inverter.

8. The semiconductor device of claim 7; The inverter; The motor; A motor system comprising:

9. An in-vehicle device comprising the motor system according to claim 8.

10. A vehicle comprising the on-board device according to claim 9.

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