Power vector analyzer and method for measuring one or more power signals

Abstract

To analyze power signals of a motor from a new perspective.SOLUTION: A power vector analyzer 130 for analyzing power from a DUT motor 120 comprises: one or more channels for measuring a reference voltage signal from a power line connected to the DUT 120; one or more channels for measuring a reference current signal from the power line; a user interface having a display and one or more operating units; and a quadrature synchronous detector (QSD) 46 for each phase of apparent power to be measured. The QSD 46 is configured to use the reference voltage signal and the reference current signal to determine the apparent power for each phase of the power to be measured by the DUT 120 and display the apparent power for each phase on the display 144.SELECTED DRAWING: Figure 14

Description

[Technical field]

[0001] The present disclosure relates to power vector analyzers, and more specifically, to power vector analyzers that use a synchronous composite detector that uses a composite nulling vector to calibrate to a reference operating point of a motor. [Background technology]

[0002] According to Precedence Research, the global electric vehicle (EV) motor market was worth US$8.5 billion in 2022 and is projected to be worth approximately US$65.95 billion by 2032, expanding at a compound annual growth rate of 21% from 2023 to 2032. Hence, there is a need to fuel this growth through technological improvements.

[0003] The electric vehicle (EV) market is growing rapidly, with governments working to phase out gasoline-powered cars and replace them with electric vehicles. Each EV typically has one or two three-phase electric motors totaling around 500 HP (horsepower, 1 HP = 0.7457 kW). For example, a single Tesla motor operates at 200 kW using variable three-phase pulse-width modulated sine wave power provided by a DC to AC inverter. The inverter frequency can vary from 20 Hz to 300 Hz, and the motor drive voltage is 750 V. pp and the current fluctuates on the order of 27A. pp It varies on the order of .

[0004] The ability to analyze a power signal, such as an electric motor, to determine the phase and magnitude of the power signal relative to a reference signal is useful. U.S. Patent No. 6,525,522 describes one example of a system having this capability, and is incorporated herein by reference in its entirety.

[0005] There are examples of motor analysis tools on the market. An example of a prior art motor analysis is the Fluke Model 438-II Power Quality Analyzer & Motor Analyzer. Examples of three-phase power analyzers that can display power in a vector plot are the Fluke 437 Series II 400Hz Power Quality Monitor and Energy Analyzer, the Hioki PW6001 Power Analyzer, and the Yokogawa WT3000E Precision Power Analyzer. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] U.S. Patent No. 6,525,522 [Non-patent literature]

[0007] [Non-Patent Document 1] "Fluke 438-II Power Quality Analyzer & Motor Analyzer" product information site, Fluke Corporation, USA, [online], [searched October 16, 2024], Internet<https: / / www.fluke.com / en-us / product / electrical-testing / power-quality / 438-ii> [Non-Patent Document 2] "Fluke 438-II Power Quality Analyzer & Motor Analyzer" product information site, Fluke Corporation, USA, [online], [searched October 16, 2024], Internet < [Non-Patent Document 3] "Fluke 437 Series II 400 Hz Power Quality Monitor and Energy Analyzer" product information site, Fluke Corporation, USA, [online], [searched October 16, 2024], Internet<https: / / www.fluke.com / en-us / product / electrical-testing / power-quality / 437-series-ii> [Non-Patent Document 4] "Power Analyzer PW6001 Product Information" product information site, HIOKI EE Corporation, [online], [searched October 16, 2024], Internet<https: / / www.hioki.co.jp / jp / products / detail / ?product_key=649> [Non-Patent Document 5] "Precision Power Analyzer WT3000E" product information site, Yokogawa Measurement Corporation, [online], [searched October 16, 2024], Internet<https: / / tmi.yokogawa.com / jp / solutions / discontinued / wt3000e-precision-power-analyzer / > [Non-Patent Document 6] "Reactive power", Motor glossary, NIDEK Co., Ltd., [online], [Retrieved October 16, 2024], Internet<https: / / www.nidec.com / jp / technology / motor / glossary / item / reactive_power / > [Non-Patent Document 7] "Differential probe | High voltage" product information site, Tektronix, [online], [searched October 16, 2024], Internet<https: / / www.tek.com / ja / products / oscilloscopes / oscilloscope-probes / high-voltage-differential-probes> [Non-Patent Document 8] "Current Probe" product information site, Tektronix, [online], [searched October 16, 2024], Internet<https: / / www.tek.com / ja / products / oscilloscopes / oscilloscope-probes / current-probes> [Non-Patent Document 9] "Oscilloscope" product information site, Tektronix, [online], [searched October 19, 2024], Internet<https: / / www.tek.com / ja / products / oscilloscopes> [Non-Patent Document 10] "Introduction to the Programming Interface Command Translator on Oscilloscopes", especially "PI (programming, or programmatic, interface) Command", Tektronix, [online], [Retrieved October 19, 2024], Internet<https: / / www.tek.com / en / documents / technical-brief / pi-command-translator-on-oscilloscopes-tech-brief> Summary of the Invention [Problem to be solved by the invention]

[0008] As mentioned above, various devices for analyzing electric power signals are commercially available. However, there remains a need for methods and devices that can analyze electric power signals from new perspectives. [Means for solving the problem]

[0009] An embodiment of the present application is a power vector analyzer (PVA) for analyzing power signals under load, such as power signals in an electric motor or from a power grid. The embodiment of the PVA can also provide additional capabilities to existing motor or power analyzers. The embodiment of the present application provides an improved user interface and easy-to-understand nulling vector calculation. The nulling vector measurement used in the embodiment provides a composite power measurement, which the PVA can display as a trace of the real-time variation of the composite load impedance of a motor or other power consuming system, which is represented as a power vector. For example, the ability to analyze the start-up characteristics of a power signal and the behavior of power consumers such as motors and large equipment is valuable. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 shows an embodiment of a user interface on a power vector analyzer (PVA) displaying three-phase quiescent power. [Diagram 2] Figure 2 shows an embodiment of the user interface on the PVA during the static power nulling process. [Diagram 3] Figure 3 shows an embodiment of a user interface on a power vector analyzer displaying the nulled quiescent power. [Figure 4] FIG. 4 shows an embodiment of a user interface on a power vector analyzer displaying measured power transients (transient signals) versus nulled quiescent power. [Diagram 5] FIG. 5 shows an embodiment of a display showing measured power transients (transient signals) including limit circles for nulled quiescent power. [Figure 6] Figure 6 shows an embodiment of a user interface on a power vector analyzer and illustrates various possible probe configurations. [Figure 7] FIG. 7 shows an embodiment of a power vector analyzer with a quadrature synchronous detector (QSD) for single-phase power and a single-phase motor with load. [Figure 8] Figure 8 shows the power vector relationships. [Figure 9] Figure 9 is an example block diagram using three QSDs for three-phase power. [Figure 10] FIG. 10 shows an example of QSD generating a nulling vector. [Figure 11] Figure 11 shows a more focused flow chart of QSD. [Figure 12] FIG. 12 shows a block diagram of the rotation block. [Figure 13] Figure 13 shows an example of a scale block diagram. [Figure 14] FIG. 14 shows an embodiment of the power vector analyzer architecture. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] The PVA of this embodiment can display the quiescent power signal prior to any operation of a device under test such as a motor or other power plant. FIG. 1 shows a user interface 10 with controls 12 on the left and a display 14 on the right. Dots such as 16 represent the "reference" apparent power signal for each of the three phases on a polar coordinate grid, each phase being 120 degrees out of phase with the other two. Controls 12 allow the user to select to set the probe configuration, start and stop the nulling process, clear and plot previously determined nulled quiescent powers. The term "reference apparent power" applies to the apparent power displayed before removing the quiescent power, to distinguish it from the apparent power measured after the nulling process.

[0012] FIG. 2 shows an embodiment of a user interface during the null calculation process, which is described in detail below. The nulling process essentially removes the quiescent power from the apparent power measurements, allowing for a more accurate display and measurement of transient power fluctuations. The lines (e.g., 18) between each of the dots (e.g., 16) and the center 20 of the chart represent the process of determining a Null Vector, which the system adds to the reference apparent power to remove the quiescent power from future measurements. FIG. 3 shows the resulting display, which indicates that all three dots have been moved to the center 20, and that the quiescent power has been nulled, causing the apparent power to appear as zero on all three phases.

[0013] FIG. 4 shows the temporal apparent power variation relative to the center of the null, with transients (e.g., 22) shown for each phase of power. In one aspect of the embodiment, the user can set a limit mask, represented by circle 24 in FIGS. 4 and 5. The limit mask sets limits on the apparent power measurement as to how "far" or large the transients can be from the center of the null before the PVA reacts to the transients. In one embodiment, when the power line is connected to a powered device (e.g., a motor under load), if the apparent power transients exceed the limit mask (e.g., 28), this may cause the device under test (DUT) to fail the test. In another embodiment, the limit mask may indicate a condition on the power line that requires closer monitoring or some action to be taken. A message such as "Transients Detected" (e.g., 26) is displayed on the user interface.

[0014] As mentioned above, the PVA can operate with a three-phase source or with a single-phase source. Figure 6 shows four different variations on the configuration of the user interface controls 30 for controlling the probes used to send power signal measurements to the PVA. The leftmost one shows a probe configuration 32 for a single-phase source, using one probe for voltage (1V) and one for current (1I), so the configuration is 1V1I. Each probe is connected to one channel of the PVA. The second from the left 34 shows a two voltage probe (2V) and two current probe (2I) configuration for a single-phase source, but with two conductors like the 220V source. The second from the right 36 shows a three-phase source (3P), using two voltage probes (2V) and two current probes (2I). The final panel shows the probe controls set to a three-phase source at 38, in a "delta" configuration using three voltage probes and three current probes. The final configuration, not selected in Figure 6, consists of a three-phase power setup in a "wye" configuration using three voltage probes and three current probes.

[0015] FIG. 7 shows a diagram of an electric motor 40 connected to a load 42 and to a power source 44. In this embodiment, the PVA has a "nulled" quadrature synchronous detector (QSD) at 46. How the QSD in this embodiment determines the nulling vector that nulls the quiescent power is described in detail below. The QSD outputs active power P and reactive power Q. FIG. 8 shows the relationship between P, Q and apparent power S shown in the user interfaces of FIGS. 1-5.

[0016] In this configuration, one method of testing the motor may be to follow this process: A user connects one or more voltage probes (such as 48) and one or more current probes (such as 49) to the power lines. The user then selects the Nulling button shown above in Figures 1-3 to begin the nulling process.

[0017] The nulling process may be done using one of two options. In one embodiment, the user connects a "golden" reference device (such as a motor), i.e., a device that meets all specifications and has documented responses, to the PVA. The user then presses the nulling button for each of the phases to be measured. The user interface may also have a master nulling function to do all three simultaneously. This nulling will very briefly move the phase traces mentioned above to the center of the graphical display as shown in Figures 2 and 3. All further displays of composite power are relative to this reference.

[0018] Because the PVA of this embodiment can operate with both single-phase and three-phase power sources, in this description these options will be referred to as the "measured phase" or "measured phase," where the measured phase includes one phase of a single-phase power source or each of the three phases of a three-phase power source.

[0019] In another embodiment, the user sets a DUT device, such as a motor, to a reference load value, frequency and voltage. The PVA uses these to generate a nulling vector to null out the quiescent power. All further displays of composite power are made with respect to this reference. In another embodiment, a combination such as a DUT and golden motor combination may be used.

[0020] In this description, the voltage and current signals that the QSD uses to null the quiescent power are referred to as the "reference voltage" and "reference current." Once the nulling process is complete and the PVA is monitoring the power signal, for simplicity, the monitored voltage and current will continue to be referred to as the reference voltage and reference current.

[0021] Once the nulling process is complete, the PVA may test different loads on the DUT, and therefore different voltage and frequency settings to test with different loads. For an optimal implementation, the PVA channels connected to the voltage and current signals would use analog-to-digital converters (ADCs). For an ideal implementation, all A / D samples would be streamed to the display. However, some test and measurement equipment in which the PVA may be implemented may not have a sufficient sample rate to support streaming. The test and measurement equipment would operate with a long enough record length so that only small gaps in the processing stream would not make it to the display.

[0022] One aspect of this embodiment is the ability to allow the user to set limit masks as described above in FIG. 5. As described above, the user can define limits at which the PVA will flag transient apparent power variations that exceed the limit mask. Using the limit mask, the user can set thresholds such as the number of times a transient signal exceeds the limit mask on a phase and the length of time the transient signal exceeds the limit mask as a pass / fail trigger or for a level of notification. Returning to FIG. 5, the display will provide a notification 26 that a transient signal has been detected. To aid in setting and monitoring the limit masks, the PVA may have a rotary knob that allows the user to rotate the grid, view the data in a 3-phase view, or manually adjust to optimize the data layout for each phase of the motor. This makes it easier to draw and display the masks. It also allows the data for all three phases to be displayed in the correct global phase relative to each other.

[0023] During test and analysis mode operation, the PVA may perform composite apparent power measurements and display the measurements. Glitches and transient signal variations are captured on the display and provided for limit mask testing. This has the advantage of allowing continuous monitoring and debugging of problems with the DUT.

[0024] We now describe a QSD with nulling for a loaded single-phase powered device (e.g., a motor using a single-phase power supply 44) as shown in Figure 7. The QSD with nulling 46 receives an input from a high voltage probe 48 as a reference signal and an input from a current probe 49 as an input signal. The QSD outputs active power P and reactive power Q which are used to determine apparent power. Figure 8 shows the relationship between active power in watts, reactive power in VAR (Volt Ampere reactive), and apparent power S in VA (Volt Ampere).

[0025] Figure 9 shows the configuration of a three-phase powered device under load. Each of the power phases 44A-44C has a corresponding QSD 46A-46C. These QSDs measure composite power. Each QSD has high voltage probes 48A-C and current probes 49A-C.

[0026] FIG. 10 shows a detailed depiction of one QSD 46. It is replicated for each of the phases measured by the PVA as described above. FIG. 10 shows the layout and the description in this application focuses on the nulling process. The QSD receives a voltage signal (also called reference voltage) at the top and a current signal (also called reference current) at the bottom. The voltage signal is demodulated and downsampled at 50 and the current signal is demodulated and downsampled at 52. The application of the filters creates transients at the beginning and end of the acquired waveform, so the demodulated and downsampled voltage signal is trimmed at 54 and the current signal is trimmed at 56 to remove the transients. The reference voltage signal is represented by the cosine of the reference voltage signal. The Hilbert filter 58 uses the cosine of the voltage signal and rotates or shifts the phase by 90 degrees. This changes the phase of the voltage signal, shifting each frequency component by 90 degrees at "V90" (referred to herein as the shifted voltage signal). The cosine of the voltage signal, Vr, is sent to mixer 60 where it is mixed with the cosine of the nulling angle θ from amplifier 62. The initial value of the nulling angle θ is between -π and π. The nulling angle and nulling gain come from a scaler sweep module 64. A sine of the nulling angle 66 is mixed with the shifted voltage signal in mixer 68.

[0027] The outputs of mixers 60 and 68 are summed at 70 to produce Vq. Vq then goes to mixer 72 where it is mixed with the inverse of the nulling gain from inverter 74 to produce the nulling vector 97. The nulling vector is added to the demodulated and down sampled current signal at summing node 76. The result of that summation is then mixed with the shifted voltage signal at mixer 78 and the cosine of the voltage signal at mixer 80. The outputs of mixers 78 and 80 are low pass filtered at 82 and 84, respectively. These low pass filters are based on frequency f and are scaled by a factor of two at 86 and 88 to produce the reactive power Q and the active power P. The average of Q at 90 and the average of P at 92 are fed back to the nulling scaler sweep block 64 and the process is repeated until the values ​​of P and Q are equal to zero. This centers the display of apparent power as shown in FIG. 3. The gain and phase values ​​that drive the gain and phase values ​​to zero are the final nulling vector. Adding the nulling vector to the input voltage and current signals cancels these signals and removes the quiescent power. The nulling flags at 94 determine when the nulling process occurs. The nulling process begins when the user presses the nulling button on the user interface. Once the nulling process reaches zero values ​​for Q and P, the nulling flags are reset to 0.

[0028] The process shown in Figure 10 is replicated for other power phases as necessary so that all three power phases are nulled simultaneously. The above process occurs because the user selected the Nulling button in the user interface and set the Nulling flag to 1 or on. Once the process is complete, the Nulling flag is reset to 0. The QSD continues to run the nulling process unless the nulling process is turned off. Apparent power measurements after the nulling process is complete do not include the quiescent power that was removed by the nulling process.

[0029] A menu option allows the user to turn off the nulling process at any time to observe the actual total power. A switch 96 may allow control of whether the nulling process is performed or not. FIG. 11 shows a more focused version of the QSD for making these measurements when the nulling process is off, i.e., switch 96 is open. It should be noted that the process is performed as in FIG. 10, but simplified to make it easier to understand the composite apparent power measurement without the nulling process. Like FIG. 10, FIG. 11 shows the input power signal, which has a reference voltage signal component in voltage in volts RMS (root mean square) across the load and a reference current in amperes RMS. The figure shows the phase angle as φ. The term ω is the rate of change of the phase of the waveform and is equal to 2πf, where f is frequency and t is time. The ω term ranges between 20 and 2000.

[0030] In this process, at 77, a reference voltage signal is represented comprising the cosine of (ωt) of the reference voltage signal V, before applying the Hilbert filter at 58. In the present description, this representation is referred to as the cosine voltage function. Similarly, the cosine of (ωt+φ) is used as a representation of the reference current signal A at 79, here referred to as the cosine current function, where the cosine current function is phase shifted with respect to the reference voltage. The cosine current function and the cosine voltage function are multiplied by 80 to generate PP, the active power, as described below. The cosine voltage signal is shifted 90 degrees by the Hilbert filter to obtain the sine voltage function Vsin(ωt). The sine voltage function is multiplied by the cosine current function at 78 to generate a signal QQ, which also generates the reactive power, as described below. These two signals are low pass filtered and then scaled by a factor of two, as described with respect to FIG. 10. As explained below, a scale factor of 2 produces reactive power as VAsin(φ) and active power as VAcos(φ), which are then used to determine the apparent power on the power line, which is used for display.

[0031] The signals PP and QQ are obtained as follows. [Number 1] QQ = A·cos(ωt + φ)·V·sin(ωt) [Number 2] PP = A·cos(ωt + φ)·V·cos(ωt) Rearranging the terms and applying the trigonometric formula cos(a+b) = cos(a)cos(b) - sin(a)sin(b) to both QQ and PP, we get: [Number 3] QQ = VA·cos(ωt)cos(φ)sin(ωt) - VA·sin(ωt)sin(φ)sin(ωt) [Number 4] PP = VA·cos(ωt)cos(φ)cos(ωt) - VA·sin(ωt)sin(φ)cos(ωt) Applying the trigonometric formulas cos(a)sin(a) = sin(2a) / 2, sin(a)sin(a) = cos(2a) / 2 - 1 / 2 and cos(a)cos(a) = cos(2a) / 2 + 1 / 2, and rearranging, we get: [Number 5] QQ = VA / 2 ·sin(2ωt)cos(φ) + VA / 2 · sin(φ) - VA / 2 ·cos(2 ωt)sin(φ) [Number 6] PP = VA / 2 ·cos(2ωt)cos(φ) + VA / 2 · cos(φ) - VA / 2 ·sin(2 ωt)sin(φ)

[0032] A low-pass filter is then applied to QQ and PP to remove the higher frequency terms, leaving QQ = VA / 2· sin(φ) and PP = VA / 2· cos(φ). Applying the scale factor of 2 shown gives Q = VA sin(φ) and P = VA cos(φ). These power measurements are then used to find the apparent power S on the line at that point.

[0033] FIG. 12 shows an embodiment of the rotation block 98. The rotation block is independent of the rotation of the composite output signal of the QSD in a normalized XY plane (P is defined as the X-axis location and Q is defined as the Y-axis location). The normal P and Q output signals of the QSD on each of the three phases of a three-phase motor are displayed on a polar grid map. Each individual phase has a normal rotation of 0 on the polar grid display. This causes the overall phase difference of each phase of the motor to be lost. In FIG. 12, the cosine of the phase of the power signals P and Q is multiplied with the P signal at 100 and then summed with the sine of the phase angle 102 at summing node 104. Similarly, the cosine of the phase angle is multiplied with the Q signal at 106 and then summed with the sine of the phase angle 108 at summing node 110.

[0034] In one embodiment, the first phase of the motor may be displayed on the display with a rotation angle of zero. The second phase may be displayed with a rotation of 120 degrees, and the third phase may be displayed with a rotation of 240 degrees. For example, referring to the image on the right side of FIG. 1, each dot is offset from each other by 120 degrees. In another embodiment, an additional global phase measurement between the three voltages may be made and used to set the phase angle of the rotation block. Another useful display embodiment may be to display all three phases with a rotation angle of zero in an overlay. The power of all three phases of the motor can be directly visually compared in the overlay display. Furthermore, this allows only one limit mask to be created for all three phases (legs). When creating the limit mask, it may be useful to rotate the polar grid to an angle that is convenient for drawing the limit mask. Once the limit mask is drawn, it may be best to rotate it on the display.

[0035] 13 is an embodiment of the apparent power block 114 which calculates the apparent power and the power factor angle φ. The purpose of the apparent power block 114 is to output P in watts, Q in VAr, S in VA, and φ in degrees.

[0036] A possible advantage of doing this from the output of the QSD, rather than measuring the voltage and current waveforms directly, is that the averaging effect of the QSD reduces noise and improves the resolution of the measurement. A second advantage is that the measurements track their location in time within the acquired data stream, which changes based on load, frequency, and voltage. Measurements can be time tagged, and these markers on the XY display with its polar grid can be tracked along with cursors on the YT display of the three input voltage waveforms and the three input current waveforms.

[0037] FIG. 14 shows an embodiment of a block diagram of a PVA configured with a DUT motor 120 after the system has been nulled with a golden reference motor. Alternatively, the DUT motor can be used to null the system at a reference frequency, voltage and load setting. In this embodiment, the only hardware required for this architecture is a test and measurement device such as three voltage probes, three current probes and an oscilloscope or digitizer 130. The user also provides a variable load 122 and the DUT motor 120. A further aspect of the invention is a software application 124 that may be executed on the test and measurement device 130, such as an oscilloscope or digitizer system. One or more processors on the device 130 may be configured to run the software application 124. The QSD described above can be implemented in a processor or logic circuit.

[0038] The architecture consists of three main QSD processing paths, one for each leg of the three-phase powered device. Note that a single-phase motor can be analyzed by enabling only one phase (leg) of the signal processing path. In this description, the first QSD path is used with the understanding that the description applies to each phase (leg). The current probe 128 is connected to one channel of the test and measurement device 130, and the high voltage probe 126 is connected to another channel of the test and measurement device 130. Each channel has one or more analog-to-digital converters (ADCs), such as 132 and 134.

[0039] As mentioned above, depending on the capabilities of the device, the samples from the ADC may be streamed continuously or used to form long records (LR) such as 136 or 138. Although these are named LR here, they may also be streamed continuously. These represent a continuous stream of samples going into the signal processing path, with all output samples going to an infinite persistence display. The persistence may also be configured to decay. This continuous stream is sometimes called the roll mode block and is optional if the device 130 does not have a high enough streaming sample rate to support the highest frequency sampled by the motor. This includes distortion harmonics. If the roll mode sample rate is not high enough, this roll mode block is not used and a relatively long record length waveform is used to ensure that there is a relatively short dead time between multiple acquisitions and a large proportion of all samples are displayed on the display.

[0040] The QSD 46 described above operates on sampled voltage and current signals. Depending on the setting of the nulling flag, the QSD may detect nulled quiescent power or perform a composite power measurement. Rotation block 98 and apparent power block 114 are applied to the signal. The user may then turn limit testing on or off at 140 and draw a limit mask if selected at 142. All results are then displayed as a single display 144 or as a multi-layer display showing data from all three phases (legs) at 146.

[0041] In operation, the user connects the probe to the test and measurement instrument and to a power driving device such as a motor. The user then configures the test and measurement instrument acquisition to capture all six channels with the appropriate gain settings. The PVA software application is then launched and these signals are assigned to the channels of the test and measurement instrument. First, the test and measurement instrument must perform a nulling process. The user sets the desired frequency, reference load and voltage. If a golden reference motor is used in the nulling process, once nulling is achieved the user must switch the probe to the power driving device of the DUT. The nulling feature can also be used to monitor three-phase power in a power grid, for example. The nulling feature can be used to null the nominal quiescent power so that only deviations from the nominal power are displayed on the PVA polar grid display. This is useful for capturing power transients such as lightning strikes, load switching variations or other types of transients that may occur. In this regard, the user continuously observes the composite power data as the motor changes state, the measured power vectors P, Q and S, and the transient behavior due to real-time load changes, allowing the user to set masks for pass / fail tests and other triggered events.

[0042] The user interface includes play / pause / stop playback controls with fast forward for quick visual analysis of the entire time record, and the ability to see all samples across the entire interval in a single view on the display provides insight not previously available in power analyzers.

[0043] It should be noted that this embodiment includes the sum of several elements. The combination of these elements creates a new and very useful PVA. As part of these architectural elements for an embodiment of the present invention, it may include an inverter 131 as shown in FIG. 14. This drives a power drive device as part of a DUT or lab setup for testing. It is configured to provide three-phase pulse width modulated sinusoidal voltages and currents. Its frequency may be varied over a range and its voltage may be varied to achieve optimal operation of the electric motor in terms of torque and power.

[0044] As part of testing the powered device, the user will use a variable load. The customer test automation software 124 controls the load setting. The powered device is coupled to the shaft of the variable load. The customer provides the customer test automation software for testing the powered device and controlling the PVA setting in the required sequence.

[0045] Thus, embodiments provide a PVA for the analysis of high power electrical devices such as single-phase and three-phase motors. The PVA provides a real-time continuous composite power plot of all three phases of the motor. It can provide plots representing the apparent, reactive and real power of each phase of the motor. The PVA also has a unique nulling feature similar to the calibration of a one-port VNA, calibrating against a reference power setting. The reference power setting may be taken from a reference motor or the DUT may be set to a reference voltage, load and frequency and then a nulling calibration is performed. Once nulled, the PVA can continuously monitor and capture all samples over time in an infinite persistence display. It can create power maps over the entire range of loads, frequencies and voltages. It also captures glitches and other buggy behavior. For limit testing, it can flag glitches and transients. Using a test and measurement equipment platform for the PVA also allows other measurement waveform analysis tools of the test and measurement equipment to be used in the motor testing process, providing additional benefits to the user.

[0046] Aspects of the disclosed technology can operate on specially created hardware, firmware, digital signal processors, or specially programmed general-purpose computers, including processors that operate according to programmed instructions. The term "controller" or "processor" in this application contemplates microprocessors, microcomputers, ASICs, and dedicated hardware controllers, among others. Aspects of the disclosed technology can be implemented in computer-available data and computer-executable instructions, such as one or more program modules, executed by one or more computers (including a monitoring module) or other devices. Generally, program modules include routines, programs, objects, components, data structures, and the like, which, when executed by a processor in a computer or other device, perform particular tasks or implement particular abstract data types. The computer-executable instructions may be stored in computer-readable storage media, such as hard disks, optical disks, removable storage media, solid-state memory, RAM, and the like. As will be appreciated by those skilled in the art, the functionality of the program modules may be combined or distributed as desired in various embodiments. Furthermore, such functionality may be embodied in whole or in part in firmware or hardware equivalents, such as integrated circuits, field programmable gate arrays (FPGAs), etc. Certain data structures may be used to more effectively implement one or more aspects of the disclosed techniques, and such data structures are considered to be within the scope of the computer-executable instructions and computer-usable data described herein.

[0047] The disclosed aspects may, in some cases, be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more computer-readable media that may be read and executed by one or more processors. Such instructions may be referred to as computer program products. A computer-readable medium as described herein means any medium that can be accessed by a computing device. By way of example, and not limitation, computer-readable media may include computer storage media and communication media.

[0048] Computer storage media means any medium that can be used to store computer-readable information. By way of example and not limitation, computer storage media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital video disc (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile removable or non-removable media implemented in any technology. Computer storage media excludes signals themselves and transitory forms of signal transmission.

[0049] A communication medium refers to any medium capable of communicating computer readable information. By way of example, and not limitation, communication media may include coaxial cables, fiber optic cables, air, or any other medium suitable for communicating electrical, optical, radio frequency (RF), infrared, acoustic, or other types of signals. Working Example

[0050] In the following, examples useful for understanding the technology disclosed in the present application are presented. The embodiment of the technology may include one or more of the examples described below and any combination thereof.

[0051] Example 1 is a power vector analyzer for analyzing power from a device under test (DUT), comprising one or more channels for measuring a reference voltage signal from a power line connected to the DUT, one or more channels for measuring a reference current signal from the power line, a user interface including a display and one or more operation units, and a quadrature synchronous detector (QSD) for each phase of the apparent power being measured, the QSD being configured to use the reference voltage signals from the one or more channels and the reference current signals from the one or more channels to determine the apparent power of each phase of the apparent power being measured of the DUT, and to display the apparent power of each of the phases on the display.

[0052] Example 2 is the power vector analyzer of example 1, further comprising one or more processors, the one or more processors: receiving a signal from the user via the one or more controls on the user interface indicating that the user wishes to initiate a nulling process; sending a signal to the QSD to generate a nulling vector; applying the nulling vector to the reference voltage and the reference current to eliminate quiescent power; displaying apparent power signals related to the test voltage and test current for the nulled quiescent power of each of the phases of the apparent power to be measured; The one or more processors are configured to execute a program that causes the one or more processors to perform the steps of:

[0053] Example 3 is the power vector analyzer of Example 2, wherein the one or more processors are further configured to display the reference apparent power signal of each of the phases being measured when the QSD of each of the phases generates a nulling vector such that the reference apparent power signal is zero.

[0054] Example 4 is a power vector analyzer of Example 3, wherein the program that causes the one or more processors to perform a process of displaying the reference apparent power signal includes a program that causes each of the reference power signals to be overlaid on a single display and displayed.

[0055] Example 5 is the power vector analyzer of any of Examples 2 to 4, wherein the reference voltage signal and the reference current signal of the nulling process are generated by a DUT operating at a reference load value, a reference frequency and a reference voltage.

[0056] Example 6 is the power vector analyzer of any of Examples 2 to 5, wherein the reference voltage signal and the reference current signal of the nulling process are generated by a reference motor used to generate the nulled quiescent power.

[0057] Example 7 is a power vector analyzer according to any of Examples 1 to 6, in which three phases of power are measured, there are three QSDs for each of the power phases, and the apparent power display displays the apparent power for each of the three power phases.

[0058] Example 8 is a power vector analyzer of any of Examples 1 to 7, wherein the reference voltage signal from the one or more channels and the reference current signal from the one or more channels are quiescent operating powers of the power line of the DUT.

[0059] Example 9 is a power vector analyzer of any of Examples 1 to 8, wherein the one or more operating units include an operating unit that enables a user to move the apparent power signals of each of the phases to be measured on the display unit according to the user's desire.

[0060] Example 10 is a power vector analyzer of any of Examples 1 to 9, wherein the one or more controls include an control that enables a user to define a limit mask on the display, the limit mask indicating an area of ​​the apparent power signal that is within an acceptable range.

[0061] Example 11 is a power vector analyzer of Example 10, wherein the one or more processors are further configured to execute a program that causes the one or more processors to perform a process of passing the DUT if the measured value of the apparent power does not exceed the limit mask, and a process of failing the DUT if the measured value of the apparent power exceeds the limit mask.

[0062] Example 12 is the power vector analyzer of any one of Examples 1 to 11, wherein the process of generating the apparent power by the QSD of each of the power phases using the reference voltage signal and the reference current signal includes: a process of multiplying the reference voltage signal, which is expressed as a cosine voltage function, by the reference current signal, which is expressed as a cosine current function whose phase is shifted with respect to the reference voltage signal, and filtering the result to obtain an active power signal; shifting the cosine voltage function by 90 degrees to generate the shifted voltage function as a sine voltage function; filtering the multiplication of the sine voltage function and the cosine current function to generate a reactive power signal; generating the apparent power using the reactive power signal and the real power signal; This is carried out by.

[0063] Example 13 is a method for measuring one or more power signals, comprising: measuring a reference voltage signal from a power line connected to a device under test (DUT); measuring a reference current signal from the power line; obtaining the reference voltage signal and the reference current signal using a quadrature synchronous detector (QSD) for each of the phases of the power being measured, and generating an apparent power for each of the phases of the power being measured by the DUT; A process for displaying the apparent power relative to the nulled quiescent power of each of the phases of the apparent power to be measured; Equipped with.

[0064] Example 14 is the method of example 13, receiving a signal from a user, via one or more controls on a user interface, indicating that the user wishes to initiate a nulling process; sending a signal to the QSD to generate a nulling vector; applying the nulling vector to a reference voltage signal and a reference current signal to generate a nulled quiescent power; Processing to display the apparent power signal for each nulled quiescent power of the power phases; It further comprises:

[0065] Example 15 is the method of example 14, further comprising: the QSD generating a nulling vector to indicate a reference apparent power in each of the phases being measured when the reference voltage signal and the reference current signal become zero.

[0066] Example 16 is the method of example 14, wherein the reference voltage signal and the reference current signal are generated by the DUT operating at a reference load value, a reference frequency and a reference voltage.

[0067] Example 17 is the method of example 14, in which the reference voltage signal and the reference current signal are generated by a reference DUT and are used to generate a nulled quiescent power.

[0068] Example 18 is the method of any of examples 13 to 17, wherein either three phases of power or one phase of power or both are measured.

[0069] Example 19 is the method of example 17, wherein three phases of apparent power are measured and the process of displaying the apparent power signals includes displaying the apparent power signals for each of the three phases superimposed on one display.

[0070] Example 20 is the method of any of examples 13 to 19, further comprising a process for allowing a user to move the apparent power signals of each of the phases to be measured on the display according to the user's desire.

[0071] Example 21 is the method of any of examples 13 to 20, further comprising allowing a user to define a limit mask on the display, the limit mask indicating a region of apparent power that is within an acceptable range.

[0072] Example 22 is the method of any of Examples 13 to 21, wherein the process of generating the apparent power by the QSD of each of the power phases using the reference voltage signal and the reference current signal includes: a process of multiplying the reference voltage signal, which is expressed as a cosine voltage function, by the reference current signal, which is expressed as a cosine current function whose phase is shifted with respect to the reference voltage signal, and filtering the result to obtain an active power signal; shifting the cosine voltage function by 90 degrees to generate the shifted voltage function as a sine voltage function; filtering the multiplication of the sine voltage function and the cosine current function to generate a reactive power signal; generating the apparent power using the reactive power signal and the real power signal; This is carried out by.

[0073] In addition, the present description refers to specific features. It should be understood that the disclosure herein includes all possible combinations of those specific features. When a specific feature is disclosed in connection with a particular aspect or embodiment, that feature can also be used in connection with other aspects and embodiments, to the extent possible.

[0074] Furthermore, when the application refers to a method having two or more defined steps or processes, those defined steps or processes may be performed in any order or simultaneously, unless the context precludes such a possibility.

[0075] All features disclosed in the specification, claims, abstract and drawings, and all steps in any disclosed method or process, may be combined in any combination, except where at least some of such features or steps are mutually exclusive combinations. Each feature disclosed in the specification, abstract, claims and drawings may be replaced by an alternative feature serving the same, equivalent or similar purpose, unless expressly stated otherwise.

[0076] For purposes of illustration, specific embodiments of the invention have been illustrated and described, but it will be understood that various modifications can be made without departing from the spirit and scope of the invention. Accordingly, the invention should not be limited, except as by the appended claims. [Explanation of symbols]

[0077] 10 User Interface 12 Control section 14 Display section 16 Reference apparent power signal 20 Center of the Chart 22 Transient signal 24 Limit Mask 40 Electric Motor 42 Load 44 Power supply 46 Quadrature Synchronous Detector (QSD) 48 Voltage Probes 49 Current Probe 50 Demodulation and Downsampling Blocks 52 Demodulation and Downsampling Block 54 Trimming Block 56 Trimming Block 58 Hilbert Filter 60 Mixer 62 Amplifier 64 Scalar Sweep Module 68 Mixer 70 Summing Nodes 72 Mixer 76 Summing Nodes 78 Mixer 80 Mixer 82 Low-pass filter 84 Low Pass Filter 86 Multiplier 88 Multiplier 90 average blocks 92 average blocks 96 Switch 97 Null Vector 98 Rotating Block 104 Summing Node 110 Summing Node 114 Apparent Power Block 120 DUT motor 122 Variable Load 124 Software Applications 130 Test and measurement equipment 131 Inverter 132 Analog-to-Digital Converter 134 Analog-to-Digital Converter 136 Long Record Block 138 Long Record Block 144 Single Display 146 Multi-layer display

Claims

1. 1. A power vector analyzer for analyzing power from a device under test (DUT), comprising: one or more channels for measuring a reference voltage signal from a power line connected to the DUT; one or more channels for measuring a reference current signal from the power line; a user interface including a display and one or more operation units; A quadrature synchronous detector (QSD) for each phase of the apparent power to be measured; Equipped with A power vector analyzer, wherein the QSD is configured to determine apparent power for each phase of the measured apparent power of the DUT using a reference voltage signal from the one or more channels and a reference current signal from the one or more channels, and to display the apparent power for each of the phases on the display.

2. one or more processors; the one or more processors receiving a signal from the user via the one or more controls on the user interface indicating that the user wishes to initiate a nulling process; sending a signal to the QSD to generate a nulling vector; applying the nulling vector to the reference voltage and the reference current to eliminate quiescent power; displaying apparent power signals related to the test voltage and test current for the nulled quiescent power of each of the phases of the apparent power to be measured; 2. A power vector analyzer as claimed in claim 1, configured to execute a program which causes said one or more processors to:

3. 3. The power vector analyzer of claim 2, wherein the one or more processors are further configured to execute a program that causes the one or more processors to perform processing to display a reference apparent power signal of each of the phases being measured when the QSD of each of the phases generates a nulling vector such that the reference apparent power signal is zero.

4. 3. The power vector analyzer of claim 2, wherein the reference voltage signal and the reference current signal of the nulling process are generated by the DUT operating at a reference load value, a reference frequency and a reference voltage.

5. 3. The power vector analyzer of claim 2, wherein the reference voltage signal and the reference current signal of the nulling process are generated by a reference motor used to generate nulled quiescent power.

6. 2. The power vector analyzer of claim 1, wherein said reference voltage signal from said one or more channels and said reference current signal from said one or more channels are quiescent operating powers of said power supply lines of said DUT.

7. 2. The power vector analyzer of claim 1, wherein the one or more controls include a control that allows a user to define a limit mask on the display, the limit mask indicating an area of ​​the apparent power signal that is within an acceptable range.

8. generating the apparent power by the QSD of each of the power phases using the reference voltage signal and the reference current signal; a process of multiplying the reference voltage signal, which is expressed as a cosine voltage function, by the reference current signal, which is expressed as a cosine current function whose phase is shifted with respect to the reference voltage signal, and filtering the result to obtain an active power signal; shifting the cosine voltage function by 90 degrees to generate the shifted voltage function as a sine voltage function; filtering the multiplication of the sine voltage function and the cosine current function to generate a reactive power signal; generating the apparent power using the reactive power signal and the real power signal; 2. The power vector analyzer of claim 1, wherein the power vector analyzer is performed by:

9. 1. A method for measuring one or more power signals, comprising: measuring a reference voltage signal from a power line connected to a device under test (DUT); measuring a reference current signal from the power line; obtaining the reference voltage signal and the reference current signal using a quadrature synchronous detector (QSD) for each of the phases of power to be measured, and generating an apparent power for each of the phases of power to be measured of the DUT; A process for displaying the apparent power relative to the nulled quiescent power of each of the phases of the apparent power to be measured; 13. A method for measuring one or more power signals comprising:

10. receiving a signal from a user, via one or more controls on a user interface, indicating that the user wishes to initiate a nulling process; sending a signal to the QSD to generate a nulling vector; applying the nulling vector to the reference voltage signal and the reference current signal to generate a nulled quiescent power; Processing to display the apparent power signal for each nulled quiescent power of the power phases; The method of claim 9 further comprising:

11. generating the apparent power using the reference voltage signal and the reference current signal by the QSD of each of the power phases, a process of multiplying the reference voltage signal, which is expressed as a cosine voltage function, by the reference current signal, which is expressed as a cosine current function whose phase is shifted with respect to the reference voltage signal, and filtering the result to obtain an active power signal; shifting the cosine voltage function by 90 degrees to generate the shifted voltage function as a sine voltage function; filtering the multiplication of the sine voltage function and the cosine current function to generate a reactive power signal; generating the apparent power using the reactive power signal and the real power signal; The method of measuring one or more power signals according to claim 9 , which is performed by:

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