Semiconductor device

Abstract

To provide a semiconductor device with little variation in characteristics.SOLUTION: A semiconductor device includes a first insulator, a second insulator having an opening on the first insulator, a third insulator provided inside the opening and having a first recess, a first oxide provided inside the first recess and having a second recess, a second oxide provided inside the second recess, a first conductor and a second conductor electrically connected to the second oxide and spaced apart from each other, a fourth insulator on the second oxide, and a third insulator sandwiched between the fourth insulators and having a region overlapping with the second oxide, and the second oxide has, in a top view, a first region, a second region, and a third region sandwiched between the first region and the second region, the first conductor has the first region and a region overlapping with the second insulator, the second conductor has the second region and a region overlapping with the second insulator, and the third conductor has a region overlapping with the third region.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] In this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. Semiconductor elements such as transistors, semiconductor circuits, arithmetic devices, and memory devices are all embodiments of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be considered to include semiconductor devices.

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in the present specification etc. relates to an object, a method, or a manufacturing method. Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. [Background technology]

[0004] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, and memories are mainly used. A CPU is a collection of semiconductor elements having semiconductor integrated circuits (at least transistors and memories) separated from a semiconductor wafer and on which electrodes serving as connection terminals are formed.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and used as one of the components of various electronic devices.

[0006] In addition, a technology for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has been attracting attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors have also been attracting attention as other materials.

[0007] It is also known that a transistor using an oxide semiconductor has an extremely low leakage current in a non-conducting state. For example, a low-power consumption CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Patent Document 1). In addition, a memory device that can retain stored data for a long period of time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor has been disclosed (see Patent Document 2).

[0008] Furthermore, in recent years, with the trend toward smaller and lighter electronic devices, there is an increasing demand for higher density integrated circuits, and there is also a demand for improved productivity in the manufacture of semiconductor devices including integrated circuits. [Prior art documents] [Patent documents]

[0009] [Patent Document 1] JP 2012-257187 A [Patent Document 2] JP 2011-151383 A Summary of the Invention [Problem to be solved by the invention]

[0010] An object of one embodiment of the present invention is to provide a semiconductor device with little variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract problems other than these from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming a first insulator; forming a first opening in the first insulator; forming a second insulator over the first insulator and inside the first opening; forming a first oxide on the second insulator; forming a second oxide on the first oxide; removing the second insulator, the first oxide, and the second oxide located above the first insulator; forming a first conductor over the first insulator, the second insulator, the first oxide, and the second oxide; forming a third insulator on the first conductor; forming a second opening in the third insulator and the first conductor so that at least a part of the second oxide is exposed; forming a fourth insulator over the third insulator and inside the second opening; forming a second conductor on the fourth insulator; and removing the fourth insulator and the second conductor located above the third insulator.

[0013] In the above, the second insulator, the first oxide, and the second oxide located above the first insulator are preferably removed by a CMP method.

[0014] In the above, the first oxide is preferably formed by an ALD method.

[0015] In the above, the second oxide is preferably formed by an ALD method.

[0016] Another embodiment of the present invention includes a first insulator, a second insulator having an opening on the first insulator, a third insulator provided inside the opening and having a first recess, a first oxide provided inside the first recess and having a second recess, a second oxide provided inside the second recess, a first conductor electrically connected to the second oxide and spaced apart from each other, and a second conductor, a fourth insulator on the second oxide, and a fourth insulator between the fourth insulator. and a third conductor sandwiched between the first oxide and the second oxide in a top view, the second oxide having a first region, a second region, and a third region sandwiched between the first region and the second region, the first conductor having a first region and a region overlapping with the second insulator, the second conductor having a second region and a region overlapping with the second insulator, and the third conductor having a region overlapping with the third region.

[0017] In the above, the first oxide preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0018] In the above, the second oxide preferably contains indium, an element M (the element M is one or more selected from aluminum, gallium, yttrium, tin, and titanium), and zinc.

[0019] In the above, it is preferable that the third insulator be in contact with a side surface of the opening and the first insulator.

[0020] In the above, the second oxide is preferably in contact with the bottom and side surfaces of the second recess.

[0021] In the above, it is preferable that the upper surfaces of the second insulator, the third insulator, the first oxide, and the second oxide are at approximately the same height in a cross-sectional view. Effect of the Invention

[0022] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0023] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. Note that effects other than these will become apparent from the description in the specification, drawings, claims, etc., and it is possible to extract effects other than these from the description in the specification, drawings, claims, etc. [Brief description of the drawings]

[0024] [Figure 1] Fig. 1A is a top view of a semiconductor device according to one embodiment of the present invention, and Fig. 1B and Fig. 1C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Diagram 2] Fig. 2A is a top view of a semiconductor device according to one embodiment of the present invention, and Fig. 2B and Fig. 2C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Diagram 3]Fig. 3A is a top view of a semiconductor device according to one embodiment of the present invention, and Fig. 3B and Fig. 3C are cross-sectional views of the semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 4 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 5] Figure 5A is a diagram for explaining the classification of IGZO crystal structures, Figure 5B is a diagram for explaining the XRD spectrum of a CAAC-IGZO film, and Figure 5C is a diagram for explaining the ultrafine electron beam diffraction pattern of a CAAC-IGZO film. [Figure 6] Fig. 6A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 6B and Fig. 6C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 7] Fig. 7A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 7B and Fig. 7C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 8] 8A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIGS. 8B and 8C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 9] 9A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG. 9B and FIG. 9C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 10] 10A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 10B and FIG 10C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 11] Fig. 11A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 11B and Fig. 11C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 12] Fig. 12A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 12B and Fig. 12C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 13]Fig. 13A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 13B and Fig. 13C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 14] 14A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 14B and FIG 14C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] Fig. 15A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 15B and Fig. 15C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 16A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 16B and FIG 16C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 17A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 17B and FIG 17C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 18A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 18B and FIG 18C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19] Fig. 19A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 19B and Fig. 19C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 20A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 20B and FIG 20C are cross-sectional views illustrating the method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] Fig. 21A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and Fig. 21B and Fig. 21C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22]22A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 22B and FIG 22C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 23A is a top view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention, and FIG 23B and FIG 23C are cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] FIG. 24 is a top view illustrating a microwave processing device according to one embodiment of the present invention. [Diagram 25] FIG. 25 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 26] FIG. 26 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 27] FIG. 27 is a cross-sectional view illustrating a microwave processing apparatus according to one embodiment of the present invention. [Figure 28] 28A and 28B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Figure 29] FIG. 29 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 30] FIG. 30 is a cross-sectional view illustrating a configuration of a memory device according to one embodiment of the present invention. [Diagram 31] 31A and 31B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Diagram 32] 32A and 32B are cross-sectional views of a semiconductor device according to one embodiment of the present invention. [Diagram 33] FIG. 33 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 34] FIG. 34 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [Diagram 35] 35A and 35B are block diagrams illustrating a configuration example of a storage device according to one embodiment of the present invention, and a perspective view illustrating a configuration example of a storage device according to one embodiment of the present invention. [Diagram 36]36A to 36H are circuit diagrams illustrating configuration examples of a memory device according to one embodiment of the present invention. [Figure 37] 37A and 37B are schematic diagrams of a semiconductor device according to one embodiment of the present invention. [Figure 38] 38A and 38B are diagrams illustrating an example of an electronic component. [Figure 39] 39A to 39E are schematic diagrams of a memory device according to one embodiment of the present invention. [Diagram 40] 40A to 40H are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] Hereinafter, the embodiments will be described with reference to the drawings. However, it will be easily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that the modes and details can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the following embodiments.

[0026] In addition, in the drawings, the size, thickness of layers, or areas may be exaggerated for clarity. Therefore, the scale is not necessarily limited. The drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, in an actual manufacturing process, layers or resist masks may be unintentionally thinned by etching or other processes, but this may not be reflected in the drawings to facilitate understanding. In addition, in the drawings, the same reference numerals are used in common between different drawings for the same parts or parts having similar functions, and repeated explanations may be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be attached.

[0027] In order to facilitate understanding of the invention, particularly in top views (also called "plan views") or perspective views, some components may be omitted from the drawings. Also, some hidden lines may be omitted from the drawings.

[0028] In addition, in this specification, ordinal numbers such as first, second, etc. are used for convenience and do not indicate the order of steps or stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" for explanation. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

[0029] In addition, in this specification, the terms "above" and "below" indicating the arrangement are used for convenience in order to explain the positional relationship between the components with reference to the drawings. In addition, the positional relationship between the components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation.

[0030] For example, when it is explicitly stated in this specification that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are considered to be disclosed in this specification. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and a connection relationship other than that shown in a figure or text is also considered to be disclosed in the figure or text. Here, X and Y are objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0031] In this specification, a transistor is an element having at least three terminals including a gate, a drain, and a source. A region where a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) (hereinafter, also referred to as a channel formation region) is provided, and a current can flow between the source and the drain through the channel formation region. In this specification, a channel formation region refers to a region through which a current mainly flows.

[0032] In addition, the functions of the source and drain may be interchanged when transistors of different polarities are used, or when the direction of current changes during circuit operation, etc. For this reason, in this specification and the like, the terms source and drain may be used interchangeably.

[0033] The channel length refers to, for example, a region where the semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap in a top view of a transistor, or a distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in a channel formation region. Note that the channel length of one transistor does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0034] The channel width refers to, for example, the length of a channel formation region in a vertical direction based on the channel length direction in a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate electrode overlap in a top view of a transistor, or in a channel formation region. Note that the channel width does not necessarily have the same value in all regions in one transistor. In other words, the channel width of one transistor may not be determined to a single value. Therefore, in this specification, the channel width is defined as any one value, maximum value, minimum value, or average value in the channel formation region.

[0035] In this specification and the like, depending on the structure of a transistor, the channel width in a region where a channel is actually formed (hereinafter also referred to as an "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter also referred to as an "apparent channel width"). For example, when a gate electrode covers a side surface of a semiconductor, the effective channel width may be larger than the apparent channel width, and the influence of this may not be negligible. For example, in a fine transistor in which a gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

[0036] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not precisely known, it is difficult to accurately measure the effective channel width.

[0037] In this specification, when simply described as a channel width, it may refer to an apparent channel width. Alternatively, when simply described as a channel width, it may refer to an effective channel width. Note that the values ​​of the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image, etc.

[0038] Note that impurities in a semiconductor refer to, for example, anything other than the main components constituting the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. The inclusion of impurities can, for example, increase the density of defect states in the semiconductor or reduce the crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor, such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also function as an impurity. For example, the inclusion of impurities can cause oxygen deficiencies (V O :oxygen vacancy) may be formed.

[0039] In this specification and the like, an oxynitride is a material whose composition contains more oxygen than nitrogen. For example, a silicon oxynitride is a material whose composition contains more oxygen than nitrogen. A nitride oxide is a material whose composition contains more nitrogen than oxygen. For example, a silicon nitride oxide is a material whose composition contains more nitrogen than oxygen.

[0040] In this specification and the like, the term "insulator" can be replaced with an insulating film or an insulating layer, the term "conductor" can be replaced with a conductive film or a conductive layer, and the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer.

[0041] In addition, in this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less. "Approximately parallel" refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. "Perpendicular" refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0042] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0043] In this specification and the like, normally-off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the drain current flowing through the transistor per 1 μm of channel width is 1×10 -20 A or less, 1×10 at 85℃ -18 A or less, or 1×10 at 125°C -16 This means that it is A or lower.

[0044] (Embodiment 1) In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention and a manufacturing method thereof will be described with reference to FIGS. 1A to 23C.

[0045] <Example of semiconductor device configuration> A configuration of a semiconductor device having a transistor 200 will be described with reference to FIGS. 1A to 1C. FIG. 1A is a top view of the semiconductor device. FIGS. 1B and 1C are cross-sectional views of the semiconductor device. FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some elements are omitted in the top view of FIG. 1A for clarity.

[0046] A semiconductor device of one embodiment of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on the insulator 212, a transistor 200 on the insulator 214, an insulator 280 on the transistor 200, an insulator 282 (insulator 282a and insulator 282b) on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, an insulator 284 on the insulator 283 and on the insulator 274, and an insulator 286 on the insulator 284. The insulators 212, 214, 280, 282, 283, 284, and 274 function as interlayer films. The transistor 200 also includes a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the conductor 242 (conductor 242a and conductor 242b) of the transistor 200 and functions as a plug. An insulator 241 (insulator 241a and insulator 241b) is provided in contact with a side surface of the conductor 240 that functions as a plug. A conductor 246 (conductor 246a and conductor 246b) that is electrically connected to the conductor 240 and functions as a wiring is provided on the insulator 284 and the conductor 240. An insulator 286 is provided on the conductor 246 and the insulator 284. Also, as shown in Figures 1A and 1B, conductor 240a does not overlap oxide 230 and is electrically connected to conductor 242a in a region outside the end of oxide 230, and conductor 240b does not overlap oxide 230 and is electrically connected to conductor 242b in a region outside the end of oxide 230.

[0047] Insulator 283 contacts a portion of the top surface of insulator 214 , the side of insulator 216 , the side of insulator 222 , the side of insulator 219 , the side of insulator 272 , the side of insulator 280 , and the side of insulator 282 .

[0048] Insulator 241a is provided in contact with the inner wall of the opening of insulator 272, insulator 280, insulator 282, insulator 283, and insulator 284, a first conductor of conductor 240a is provided in contact with the side surface of insulator 241a, and a second conductor of conductor 240a is provided further inward. Insulator 241b is provided in contact with the inner wall of the opening of insulator 272, insulator 280, insulator 282, insulator 283, and insulator 284, a first conductor of conductor 240b is provided in contact with the side surface of insulator 241b, and a second conductor of conductor 240b is provided further inward. Here, the height of the upper surface of conductor 240 and the height of the upper surface of insulator 284 in the region overlapping with conductor 246 can be made to be approximately the same. Note that, although the transistor 200 shows a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, the structures may be distinguished by giving ordinal numbers in the order of formation.

[0049] [Transistor 200] As shown in FIGS. 1A to 1C , the transistor 200 includes an insulator 216 on an insulator 214, conductors 205 (conductors 205a, 205b, and 205c) disposed so as to be embedded in the insulator 214 or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 219 on the insulator 222, an insulator 224 disposed so as to be embedded in the insulator 219, and an oxide 230 (oxide 230a and oxide 230b). 30b), conductor 242a and conductor 242b on insulator 219, insulator 224, and oxide 230, insulator 252 and insulator 250a on oxide 230, insulator 250b on insulator 250a, conductor 260 (conductor 260a and conductor 260b) located on insulator 250b and overlapping with part of oxide 230, and insulator 272 arranged on insulator 219 and conductor 242 (conductor 242a and conductor 242b).

[0050] Here, as shown in FIG. 1B, the insulator 224 is provided inside the opening of the insulator 219 and has a first recess. The oxide 230a is provided inside the insulator 224, i.e., in the first recess, and has a second recess. The oxide 230b is provided inside the oxide 230a, i.e., in the second recess. The insulator 224 contacts the side of the opening of the insulator 219 and the insulator 222. The oxide 230b contacts the bottom surface and side of the second recess of the oxide 230a. The upper surface of the insulator 219, the upper surface of the insulator 224, the oxide 230a, and the upper surfaces of the oxide 230b are arranged so as to be approximately aligned. The conductor 242 has an area that contacts a part of the upper surface of the oxide 230b. The insulator 252 contacts at least the side of the conductor 242. 1B and 1C, the upper surface of conductor 260 is disposed so as to substantially coincide with the upper surfaces of insulators 250 and 280. Insulator 282 contacts the upper surfaces of conductor 260, insulator 250, and insulator 280.

[0051] In the following, the oxide 230a and the oxide 230b may be collectively referred to as the oxide 230. Furthermore, the insulator 250a and the insulator 250b may be collectively referred to as the insulator 250.

[0052] The insulator 280 and the insulator 272 have openings that reach the oxide 230b. The insulator 250, the insulator 252, and the conductor 260 are disposed in the openings. In addition, the conductor 260, the insulator 252, and the insulator 250 are disposed between the conductor 242a and the conductor 242b in the channel length direction of the transistor 200. The insulator 250 has a region in contact with a side surface of the conductor 260 and a region in contact with a bottom surface of the conductor 260.

[0053] The oxide 230 preferably has an oxide 230a arranged on the insulator 224 and an oxide 230b arranged on the oxide 230a. By arranging the oxide 230a so as to encase the oxide 230b, it is possible to suppress the diffusion of impurities from the lateral direction of the oxide 230a and from structures formed below the oxide 230a to the oxide 230b. It is also preferable that the insulator 252 contacts at least the side surface of the conductor 242. By arranging the insulator 252 in this manner, it is possible to suppress oxidation of the side surface of the conductor 242 and suppress a decrease in the on-current of the transistor 200.

[0054] Note that, in the transistor 200, the oxide 230 has a structure in which two layers of the oxide 230a and the oxide 230b are stacked, but the present invention is not limited to this. For example, the oxide 230b may have a single layer or a stacked structure of three or more layers, or each of the oxide 230a and the oxide 230b may have a stacked structure.

[0055] The conductor 260 functions as a first gate (also referred to as a top gate) electrode, and the conductor 205 functions as a second gate (also referred to as a back gate) electrode. The insulator 250 functions as a first gate insulator, and the insulators 222 and 224 function as second gate insulators. The conductor 242a functions as one of a source or a drain, and the conductor 242b functions as the other of the source or the drain. At least a part of a region of the oxide 230 that overlaps with the conductor 260 functions as a channel formation region.

[0056] Here, FIG. 4 shows an enlarged view of the vicinity of the channel formation region in FIG. 1B. As shown in FIG. 4, the oxide 230b has a region 230bc that functions as a channel formation region of the transistor 200, and regions 230ba and 230bb that are provided on either side of the region 230bc and function as a source region or a drain region. At least a portion of the region 230bc overlaps with the conductor 260. In other words, the region 230bc is provided in a region between the conductor 242a and the conductor 242b. The region 230ba is provided so as to overlap with a portion of the conductor 242a, and the region 230bb is provided so as to overlap with a portion of the conductor 242b.

[0057] The region 230bc functioning as a channel formation region has fewer oxygen vacancies or a lower impurity concentration than the region 230ba and the region 230bb, and therefore has a lower carrier concentration and a higher resistance. The region 230ba and the region 230bb functioning as a source region or a drain region have many oxygen vacancies or a higher impurity concentration such as hydrogen, nitrogen, or a metal element, and therefore have an increased carrier concentration and a lower resistance. That is, the region 230ba and the region 230bb have a higher carrier concentration and a lower resistance than the region 230bc.

[0058] Here, the carrier concentration of the region 230bc functioning as a channel forming region is 1×10 18 cm -3 It is preferable that the value is less than 1×10 17 cm-3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 230bc that functions as a channel formation region is not particularly limited, but is, for example, 1×10 -9 cm -3 It can be said that:

[0059] A region may be formed between the region 230bc and the region 230ba or the region 230bb, the carrier concentration of which is equal to or lower than that of the region 230ba and the region 230bb, and equal to or higher than that of the region 230bc. That is, the region functions as a junction region between the region 230bc and the region 230ba or the region 230bb. The junction region may have a hydrogen concentration equal to or lower than that of the region 230ba and the region 230bb, and equal to or higher than that of the region 230bc. The junction region may have an oxygen vacancy equal to or less than that of the region 230ba and the region 230bb, and equal to or more than that of the region 230bc.

[0060] 4 shows an example in which the regions 230ba, 230bb, and 230bc are formed in the oxide 230b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 230b but also in the oxide 230a.

[0061] In addition, it may be difficult to clearly detect the boundaries between the regions in the oxide 230. The concentrations of metal elements, hydrogen, nitrogen, and other impurity elements detected in each region may not only vary stepwise from region to region, but may also vary continuously within each region. In other words, it is sufficient that the concentrations of metal elements, hydrogen, nitrogen, and other impurity elements decrease in the region closer to the channel formation region.

[0062] In the transistor 200, it is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the oxide 230 (the oxide 230a and the oxide 230b) including a channel formation region.

[0063] In addition, the metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide having a wide band gap in this way, the off-state current of a transistor can be reduced.

[0064] As the oxide 230, for example, a metal oxide such as an In-M-Zn oxide having indium, an element M, and zinc (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used. Alternatively, as the oxide 230, an In-Ga oxide, an In-Zn oxide, or an indium oxide may be used.

[0065] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 230b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a.

[0066] In this manner, by arranging oxide 230a so as to encase oxide 230b, it is possible to suppress the diffusion of impurities and oxygen into oxide 230b from structures formed laterally and below oxide 230a.

[0067] In addition, since the oxide 230a and the oxide 230b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced. Since the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, the effect of interface scattering on carrier conduction is small, and a high on-current can be obtained.

[0068] It is preferable that the oxide 230b has crystallinity, and it is particularly preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 230b.

[0069] CAAC-OS has a highly crystalline and dense structure and is free of impurities or defects (e.g., oxygen vacancies (V O In particular, by subjecting the metal oxide to heat treatment at a temperature at which the metal oxide does not polycrystallize (for example, 400° C. or higher and 600° C. or lower) after formation of the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0070] On the other hand, it is difficult to identify clear grain boundaries in CAAC-OS, so it is unlikely that the electron mobility will decrease due to grain boundaries. Therefore, metal oxides with CAAC-OS have stable physical properties. Therefore, metal oxides with CAAC-OS are resistant to heat and highly reliable.

[0071] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region in which a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies is called a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and generate electrons that serve as carriers. For this reason, if oxygen vacancies are present in a region in an oxide semiconductor in which a channel is formed, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region in an oxide semiconductor in which a channel is formed, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that a region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0072] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor and heat treatment is performed. In this way, oxygen is supplied from the insulator to the oxide semiconductor, and oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or drain region, this may cause a decrease in the on-current or a decrease in the field effect mobility of the transistor 200. Furthermore, if the oxygen supplied to the source region or drain region varies within the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0073] Therefore, in the oxide semiconductor, the region 230bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 230ba and 230bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 230ba and 230bb.

[0074] Therefore, in this embodiment, in a state where the conductor 242a and the conductor 242b are provided on the oxide 230, a microwave treatment is performed in an atmosphere containing oxygen, and the oxygen vacancies in the region 230bc and the V O The microwave treatment herein refers to a treatment using an apparatus having a power source that generates high-density plasma using microwaves, for example.

[0075] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be made to work. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 230bc. The V O H is split off, hydrogen H is removed from the region 230bc, and oxygen vacancy V O can be compensated for with oxygen. That is, in the region 230bc, "V O H→H+V O " occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, the oxygen vacancies in the region 230bc and the V O H can be reduced, lowering the carrier concentration.

[0076] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like are shielded by the conductors 242a and 242b and do not reach the regions 230ba and 230bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 272 and 280 that are provided to cover the oxide 230 and the conductor 242. As a result, during microwave processing, the V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0077] In particular, the above-mentioned effect is large when the microwave treatment is performed in an atmosphere containing oxygen after the insulating film that becomes the insulator 250b is formed. In addition, it is preferable to perform the microwave treatment in an atmosphere containing oxygen after the insulating film that becomes the insulator 250a is formed, and further perform the microwave treatment in an atmosphere containing oxygen after the insulating film that becomes the insulator 250b is formed. By performing the microwave treatment in an atmosphere containing oxygen through the insulator 250a or the insulator 250b in this way, oxygen can be efficiently injected into the region 230bc. In addition, the oxygen injected into the region 230bc can be in various forms such as oxygen atoms, oxygen molecules, and oxygen radicals (atoms or molecules having unpaired electrons, or ions). Note that the oxygen injected into the region 230bc may be in one or more of the above forms, and is particularly preferably in the form of oxygen radicals. In addition, the film quality of the insulator 250a and the insulator 250b can be improved, so that the reliability of the transistor 200 is improved.

[0078] In this manner, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. O By removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb, which function as source and drain regions, can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 200, and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0079] By adopting the above-mentioned configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device having good electrical characteristics.

[0080] In FIG. 1 and other figures, the side of the opening in which the conductor 260 and the like are embedded is approximately perpendicular to the surface on which the oxide 230b is formed, including the groove of the oxide 230b, but this embodiment is not limited to this. For example, the bottom of the opening may be U-shaped with a gentle curve. Also, for example, the side of the opening may be inclined with respect to the surface on which the oxide 230b is formed.

[0081] 1C, in a cross-sectional view of the transistor 200 in the channel width direction, a curved surface may be formed between the side surface of the oxide 230 and the top surface of the oxide 230. In other words, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0082] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 230b in the region overlapping with the conductor 242, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By forming the curved surface in this manner, the coverage of the oxide 230 by the insulator 250 and the conductor 260 can be improved.

[0083] The oxide 230 preferably has a laminated structure of a plurality of oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of element M to the metal element that is the main component is preferably greater than the atomic ratio of element M to the metal element that is the main component in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230a, the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide 230b. In addition, in the metal oxide used for the oxide 230b, the atomic ratio of In to element M is preferably greater than the atomic ratio of In to element M in the metal oxide used for the oxide 230a.

[0084] Moreover, the oxide 230b is preferably a crystalline oxide such as CAAC-OS. A crystalline oxide such as CAAC-OS has few impurities or defects (such as oxygen vacancies) and has a dense structure with high crystallinity. This can suppress the source electrode or drain electrode from extracting oxygen from the oxide 230b. As a result, even if a heat treatment is performed, the extraction of oxygen from the oxide 230b can be reduced, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0085] Here, the conduction band minimum changes gradually at the junction between the oxide 230a and the oxide 230b. In other words, the conduction band minimum at the junction between the oxide 230a and the oxide 230b can be said to change continuously or to be a continuous junction. To achieve this, it is preferable to reduce the defect level density of the mixed layer formed at the interface between the oxide 230a and the oxide 230b.

[0086] Specifically, the oxide 230a and the oxide 230b have a common element other than oxygen as a main component, so that a mixed layer with a low density of defect states can be formed. For example, when the oxide 230b is an In-M-Zn oxide, the oxide 230a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0087] Specifically, the oxide 230a may be a metal oxide having a composition of In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto. The oxide 230b may be a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto, or In:M:Zn=5:1:3 [atomic ratio] or a composition close thereto. The composition close thereto includes a range of ±30% of the desired atomic ratio. It is preferable to use gallium as the element M.

[0088] In addition, when a metal oxide film is formed by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0089] By configuring the oxide 230a and the oxide 230b as described above, the defect state density at the interface between the oxide 230a and the oxide 230b can be reduced, so that the effect of interface scattering on carrier conduction is reduced, and the transistor 200 can obtain a large on-current and high frequency characteristics.

[0090] At least one of the insulators 212, 214, 272, 252, 282, 283, 284, and 286 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200 to the transistor 200. Therefore, at least one of the insulators 212, 214, 272, 252, 282, 283, 284, and 286 is preferably made of an insulating material that has a function of suppressing diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (through which the above impurities are difficult to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (through which the above oxygen is difficult to permeate).

[0091] In this specification, a barrier insulating film refers to an insulating film having a barrier property. In this specification, the barrier property means a function of suppressing the diffusion of a corresponding substance (also called low permeability) or a function of capturing and fixing a corresponding substance (also called gettering).

[0092] For the insulators 212, 214, 272, 252, 282, 283, 284, and 286, it is preferable to use insulators having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, it is preferable to use silicon nitride or the like having a higher hydrogen barrier property for the insulators 212, 272, 252, 283, and 286. For example, it is preferable to use aluminum oxide or magnesium oxide or the like having a high function of capturing and fixing hydrogen for the insulators 214, 282, and 284. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through the insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film disposed outside the insulator 286 to the transistor 200 side. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side through the insulator 212 and the insulator 214. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 280 or the like to an upper side than the transistor 200 through the insulator 282 or the like. In this manner, it is preferable to have a structure in which the transistor 200 is surrounded by the insulators 212, 214, 272, 252, 282, 283, 284, and 286, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0093] Here, it is preferable to use an oxide having an amorphous structure as the insulators 212, 214, 272, 252, 282, 283, 284, and 286. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as y (y is any number greater than 0). In such a metal oxide having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, hydrogen contained in the transistor 200 or hydrogen present around the transistor 200 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 200. By using a metal oxide having an amorphous structure as a component of the transistor 200 or providing it around the transistor 200, a transistor 200 and a semiconductor device having good characteristics and high reliability can be manufactured.

[0094] Furthermore, the insulators 212, 214, 272, 252, 282, 283, 284, and 286 preferably have an amorphous structure, but may have a polycrystalline region in a portion thereof. The insulators 212, 214, 272, 252, 282, 283, 284, and 286 may have a multilayer structure in which a layer of an amorphous structure and a layer of a polycrystalline structure are stacked. For example, they may have a stacked structure in which a layer of a polycrystalline structure is formed on a layer of an amorphous structure.

[0095] The insulators 212, 214, 272, 252, 282, 283, 284, and 286 may be formed by, for example, a sputtering method. Since the sputtering method does not require the use of hydrogen as a film formation gas, the hydrogen concentration of the insulators 212, 214, 272, 252, 282, 283, 284, and 286 can be reduced. Note that the film formation method is not limited to the sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may be used as appropriate.

[0096] It may also be preferable to reduce the resistivity of the insulators 212, 272, 283, and 286. For example, it may be preferable to reduce the resistivity of the insulators 212, 272, 283, and 286 to approximately 1×10 13 By setting the resistivity at Ωcm, the insulator 212, the insulator 272, the insulator 283, and the insulator 286 may be able to reduce charge-up of the conductor 205, the conductor 242, the conductor 260, or the conductor 246 during treatment using plasma or the like in a semiconductor device manufacturing process. The resistivity of the insulator 212, the insulator 272, the insulator 283, and the insulator 286 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0097] The insulators 216, 219, 274, and 280 preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having vacancies, or the like may be used as appropriate for the insulators 216, 219, 274, and 280.

[0098] The conductor 205 is disposed so as to overlap the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided by being embedded in an opening formed in the insulator 216. Also, a configuration in which a part of the conductor 205 is embedded in the insulator 214 may be used.

[0099] The conductor 205 includes conductor 205a, conductor 205b, and conductor 205c. The conductor 205a is provided in contact with the bottom surface and side wall of the opening. The conductor 205b is provided so as to be embedded in a recess formed in the conductor 205a. Here, the upper surface of the conductor 205b is lower than the upper surface of the conductor 205a and the upper surface of the insulator 216. The conductor 205c is provided in contact with the upper surface of the conductor 205b and the side surface of the conductor 205a. Here, the height of the upper surface of the conductor 205c is approximately the same as the height of the upper surface of the conductor 205a and the height of the upper surface of the insulator 216. In other words, the conductor 205b is configured to be wrapped in the conductor 205a and the conductor 205c.

[0100] Here, the conductor 205a and the conductor 205c are preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0101] By using a conductive material having a function of reducing hydrogen diffusion for the conductor 205a and the conductor 205c, it is possible to prevent impurities such as hydrogen contained in the conductor 205b from diffusing into the oxide 230 via the insulator 224 and the like. In addition, by using a conductive material having a function of suppressing oxygen diffusion for the conductor 205a and the conductor 205c, it is possible to suppress the conductor 205b from being oxidized and its conductivity from decreasing. As the conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like. Therefore, the conductor 205a may be a single layer or a multilayer of the above conductive material. For example, the conductor 205a may be made of titanium nitride.

[0102] The conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0103] The conductor 205 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205 can increase the Vth of the transistor 200 and reduce the off-current. Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to not applying a negative potential.

[0104] The electrical resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the film thickness of the conductor 205 is set according to the electrical resistivity. The film thickness of the insulator 216 is approximately the same as that of the conductor 205. Here, it is preferable to make the film thicknesses of the conductor 205 and the insulator 216 thin within the range permitted by the design of the conductor 205. By making the film thickness of the insulator 216 thin, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, and therefore the diffusion of the impurities into the oxide 230 can be reduced.

[0105] As shown in FIG. 1C, the conductor 205 preferably extends in a region outside the ends of the oxide 230a and the oxide 230b in the channel width direction. In other words, outside the side surface of the oxide 230 in the channel width direction, the conductor 205 and the conductor 260 preferably overlap each other via an insulator. With this configuration, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate and the second gate is called a surrounded channel (S-channel) structure.

[0106] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a fin type structure and a planar type structure. By adopting the S-channel structure, it is possible to improve resistance to the short channel effect, in other words, to make a transistor in which the short channel effect is unlikely to occur.

[0107] 1C, the conductor 205 is extended to function as wiring. However, the present invention is not limited to this, and a conductor functioning as wiring may be provided below the conductor 205. Also, it is not necessary to provide one conductor 205 for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0108] Note that, in the transistor 200, the conductor 205 has a stacked structure of the conductor 205a, the conductor 205b, and the conductor 205c, but the present invention is not limited to this. For example, the conductor 205 may have a single layer, a two-layer, or a four or more layer stacked structure.

[0109] Insulator 222 and insulator 224 function as gate insulators.

[0110] The insulator 222 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 222 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 222 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 224.

[0111] The insulator 222 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. As the insulator, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing silicon (hafnium silicate), or the like. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 to the substrate side, or the diffusion of impurities such as hydrogen from the periphery of the transistor 200 to the oxide 230. Thus, by providing the insulator 222, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200 and to suppress the generation of oxygen vacancies in the oxide 230. In addition, it is possible to suppress the reaction of the conductor 205 with oxygen contained in the insulator 224 or the oxide 230.

[0112] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Alternatively, these insulators may be nitrided. The insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0113] The insulator 222 may be a single layer or a multilayer of insulators containing so-called high-k materials, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), (Ba,Sr)TiO3 (BST), etc. As transistors become smaller and more highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness.

[0114] The insulator 224 in contact with the oxide 230 may be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0115] In addition, in the manufacturing process of the transistor 200, it is preferable to perform heat treatment while the surface of the oxide 230 is exposed. The heat treatment may be performed, for example, at a temperature of 100° C. or higher and 600° C. or lower, more preferably 350° C. or higher and 550° C. or lower. Note that the heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230 to reduce oxygen deficiencies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen after the heat treatment in a nitrogen gas or inert gas atmosphere. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in order to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas in succession to a heat treatment in a nitrogen gas or inert gas atmosphere.

[0116] By subjecting the oxide 230 to the above-mentioned heat treatment, the oxygen vacancies in the oxide 230 are repaired by the supplied oxygen. In other words, O In addition, the reaction of the hydrogen remaining in the oxide 230 with the oxygen supplied can be promoted, and the hydrogen can be removed as H2O (dehydrated). As a result, the hydrogen remaining in the oxide 230 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0117] The insulator 222 and the insulator 224 may have a laminated structure of two or more layers. In this case, the laminated structure is not limited to being made of the same material, and may be made of different materials. The insulator 224 may be formed in an island shape by overlapping with the oxide 230a. In this case, the insulator 272 is configured to contact the side surface of the insulator 224 and the upper surface of the insulator 222.

[0118] The conductor 242a and the conductor 242b are preferably spaced apart from each other and each are provided in contact with a part of the top surface of the oxide 230. The conductor 242a and the conductor 242b function as a source electrode and a drain electrode of the transistor 200, respectively.

[0119] As the conductor 242 (conductor 242a and conductor 242b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, or the like may be used. These materials are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.

[0120] Note that hydrogen contained in the oxide 230b etc. may diffuse into the conductor 242a or the conductor 242b. In particular, by using a nitride containing tantalum for the conductor 242a and the conductor 242b, hydrogen contained in the oxide 230b etc. is likely to diffuse into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b etc. may be absorbed by the conductor 242a or the conductor 242b.

[0121] The insulator 272 is provided to cover the insulator 219 and the conductor 242. It is preferable that the insulator 272 has a function of capturing hydrogen and fixing hydrogen. In that case, it is preferable that the insulator 272 includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, for example, aluminum oxide or magnesium oxide.

[0122] By providing the insulator 272 as described above, the conductor 242 can be wrapped in an insulator having a barrier property against oxygen. In other words, it is possible to prevent oxygen contained in the insulator 280 from diffusing into the conductor 242. This makes it possible to suppress a situation in which the conductor 242 is directly oxidized by the oxygen contained in the insulator 280, causing an increase in resistivity and a decrease in on-current.

[0123] The insulator 250 is disposed so that at least a portion of it is sandwiched between the conductor 260 and the oxide 230b, and functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230b. The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

[0124] It is preferable that the insulator 250 (insulator 250a and insulator 250b) has a reduced concentration of impurities such as water and hydrogen in the insulator 250, similar to the insulator 224. The thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less. In particular, it is preferable that the thickness of the insulator 250a is 0.5 nm or more and 15.0 nm or less.

[0125] As shown in FIG. 1B and FIG. 1C, when the insulator 250 has a two-layer laminated structure, it is preferable that the lower insulator 250a is formed using an insulator that easily transmits oxygen, and the upper insulator 250b is formed using an insulator that has a function of suppressing the diffusion of oxygen. With such a configuration, it is possible to suppress the diffusion of oxygen contained in the insulator 250a to the conductor 260. In other words, it is possible to suppress the decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulator 250a is provided using a material that can be used for the insulator 250 described above, and the insulator 250b is preferably an insulator containing one or both of oxides of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing aluminum and silicon (hafnium silicate), or the like can be used. In addition, the insulator 250b may have a laminated structure. For example, silicon nitride may be disposed on an insulator containing an oxide of one or both of aluminum and hafnium. With such a configuration, oxidation of the conductor 260 can be suppressed. Also, it is possible to suppress the hydrogen contained in the conductor 260 from penetrating into the oxide 230 via the insulator 250. In this embodiment, hafnium oxide is used as the insulator 250b. Also, the film thickness of the insulator 250b is set to 0.5 nm or more and 5.0 nm or less, preferably 1.0 nm or more and 5.0 nm or less, and more preferably 1.0 nm or more and 3.0 nm or less.

[0126] The insulator 250a is preferably formed by the PEALD method using a gas (precursor) that contains silicon and does not contain hydrocarbons, and an oxidizing gas (reactant). In addition, a rare gas such as helium, neon, argon, krypton, or xenon may be added to the reactant.

[0127] The ALD method includes a thermal ALD method in which the reaction between a precursor and a reactant is carried out using only thermal energy, and a plasma enhanced ALD (PEALD) method in which a plasma excited reactant is used.

[0128] In addition, the ALD method utilizes the self-regulating nature of atoms to deposit atoms one layer at a time, and thus has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures. In the PEALD method, the use of plasma can be preferable because it allows films to be formed at lower temperatures. Note that some precursors used in the ALD method contain carbon. For this reason, films formed by the ALD method may contain more impurities such as carbon than films formed by other film formation methods. Note that the amount of impurities can be quantified using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0129] In this embodiment, the PEALD method is used. As the gas containing silicon and not containing hydrocarbon, SiH4, Si2H6, SiF4, SiCl4, SiBr4, SiH2Cl2, SiH2I2, etc. can be used. As the oxidizing gas, O2, O3, N2O, NO 2、 H2O or the like can be used. In this embodiment, SiH4 is used as the gas containing silicon and not containing hydrocarbons, and N2O is used as the oxidizing gas.

[0130] When silicon oxide or silicon oxynitride is used for the insulator 250a, the insulator 250b may be an insulating material that is a high-k material with a high dielectric constant. The gate insulator can be made into a laminated structure of the insulators 250a and 250b, which is stable against heat and has a high dielectric constant. This makes it possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It also makes it possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.

[0131] Furthermore, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. In other words, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Furthermore, oxidation of the conductor 260 due to oxygen from the insulator 250 can be suppressed.

[0132] The metal oxide may be configured to function as a part of the first gate electrode. For example, the metal oxide that can be used as the oxide 230 may be used as the metal oxide. In this case, the electric resistance value of the metal oxide can be reduced to make it a conductor by forming the conductor 260a by a sputtering method. This can be called an OC (Oxide Conductor) electrode.

[0133] By including the metal oxide, the on-current of the transistor 200 can be improved without weakening the effect of the electric field from the conductor 260. Furthermore, by maintaining a distance between the conductor 260 and the oxide 230 due to the physical thickness of the insulator 250 and the metal oxide, it is possible to suppress leakage current between the conductor 260 and the oxide 230. Furthermore, by providing a stacked structure of the insulator 250 and the metal oxide, it is possible to easily and appropriately adjust the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230.

[0134] The conductor 260 functions as a first gate electrode of the transistor 200. The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. As shown in FIG. 1B and FIG. 1C, the top surface of the conductor 260 is substantially flush with the top surface of the insulator 250. Note that, although the conductor 260 is shown as a two-layer structure of the conductor 260a and the conductor 260b in FIG. 1B and FIG. 1C, the conductor 260 may be a single-layer structure or a stacked structure of three or more layers.

[0135] The conductor 260a is preferably made of a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0136] Furthermore, since the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b caused by oxygen contained in the insulator 250. As a conductive material having a function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0137] In addition, since the conductor 260 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 260b can be a conductive material mainly composed of tungsten, copper, or aluminum. The conductor 260b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0138] Moreover, in the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fill an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in the region between the conductor 242a and the conductor 242b without alignment.

[0139] As shown in FIG. 1C, in the channel width direction of the transistor 200, the height of the bottom surface of the conductor 260 in the region where the conductor 260 and the oxide 230b do not overlap is preferably lower than the height of the bottom surface of the oxide 230b when the bottom surface of the insulator 222 is used as a reference. The conductor 260, which functions as a gate electrode, is configured to cover the side and upper surface of the channel formation region of the oxide 230b via the insulator 250 or the like, so that the electric field of the conductor 260 can be easily applied to the entire channel formation region of the oxide 230b. This makes it possible to increase the on-current of the transistor 200 and improve the frequency characteristics. When the bottom surface of the insulator 222 is used as a reference, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230a and the oxide 230b do not overlap with the conductor 260 and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0140] The insulator 280 is provided on the insulator 272, and has openings formed in the areas where the insulator 250 and the conductor 260 are provided. The upper surface of the insulator 280 may be flattened.

[0141] The insulator 280 that functions as an interlayer film preferably has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced. The insulator 280 is preferably formed using, for example, the same material as the insulator 216. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.

[0142] The insulator 280 preferably has a reduced concentration of impurities such as water and hydrogen in the insulator 280. For example, the insulator 280 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0143] The insulator 282 and the insulator 284 preferably function as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above into the insulator 280, and preferably have a function of capturing impurities such as hydrogen. The insulator 282 and the insulator 284 preferably function as a barrier insulating film that suppresses the transmission of oxygen. The insulator 282 and the insulator 284 may be an insulator such as a metal oxide having an amorphous structure, for example, aluminum oxide. By providing the insulator 282 and the insulator 284, which are in contact with the insulator 280 and have a function of capturing impurities such as hydrogen, in the region sandwiched between the insulator 212 and the insulator 283, the impurities such as hydrogen contained in the insulator 280 can be captured, and the amount of hydrogen in the region can be made constant. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 282 and the insulator 284, since hydrogen can be more effectively captured or fixed. As a result, a transistor 200 and a semiconductor device having favorable characteristics and high reliability can be manufactured.

[0144] The insulator 283 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 280. The insulator 283 is disposed on the insulator 284. As the insulator 283, it is preferable to use a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 283 may be a silicon nitride film formed by a sputtering method. By forming the insulator 283 by a sputtering method, a silicon nitride film that is high in density and unlikely to form voids can be formed. In addition, as the insulator 283, a silicon nitride film formed by a PEALD method or a CVD method may be stacked on top of the silicon nitride film formed by the sputtering method.

[0145] The conductor 240a and the conductor 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 240a and the conductor 240b may have a layered structure.

[0146] In addition, when the conductor 240 has a laminated structure, it is preferable to use a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen for the conductor in contact with the insulator 283, the insulator 284, the insulator 282, the insulator 280, and the insulator 272. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. In addition, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a laminated layer. In addition, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 283 from being mixed into the oxide 230 through the conductor 240a and the conductor 240b.

[0147] The insulator 241a and the insulator 241b may be, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulator 241a and the insulator 241b are provided in contact with the insulator 274, the insulator 283, the insulator 284, the insulator 282, the insulator 280, and the insulator 272, and therefore can prevent impurities such as water and hydrogen contained in the insulator 280 from being mixed into the oxide 230 through the conductor 240a and the conductor 240b. Silicon nitride is particularly suitable because it has high barrier properties against hydrogen. In addition, it can prevent oxygen contained in the insulator 280 from being absorbed by the conductor 240a and the conductor 240b.

[0148] Conductors 246 (conductors 246a and 246b) may be disposed in contact with the upper surface of conductor 240a and the upper surface of conductor 240b to function as wiring. Conductor 246 is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductor may have a laminated structure, for example, a laminate of titanium or titanium nitride and the above conductive material. The conductor may be formed so as to be embedded in an opening provided in an insulator.

[0149] The insulator 286 is provided on the conductor 246 and on the insulator 284. As a result, the upper surface and the side surface of the conductor 246 contact the insulator 286, and the lower surface of the conductor 246 contacts the insulator 284. In other words, the conductor 246 can be configured to be wrapped in the insulators 284 and 286. With such a configuration, it is possible to suppress the permeation of oxygen from the outside and prevent oxidation of the conductor 246. This is also preferable because it is possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 246.

[0150] <Materials for semiconductor devices> The following describes constituent materials that can be used in the semiconductor device.

[0151] <<Substrate>> The substrate on which the transistor 200 is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate. Examples of semiconductor substrates include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide. Examples of semiconductor substrates include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate. Examples of conductive substrates include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Examples of substrates include a substrate having a metal nitride, a substrate having a metal oxide, and the like. Examples of substrates include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate. Alternatively, a substrate having elements provided thereon may be used. The elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.

[0152] <<Insulators>> Examples of the insulator include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.

[0153] For example, as transistors become smaller and more highly integrated, problems such as leakage current can occur due to thinner gate insulators. By using a high-k material for the insulator that functions as the gate insulator, it is possible to reduce the voltage required for transistor operation while maintaining the physical film thickness. On the other hand, by using a material with a low dielectric constant for the insulator that functions as the interlayer film, it is possible to reduce the parasitic capacitance that occurs between wiring. Therefore, it is best to select materials according to the function of the insulator.

[0154] Further, examples of insulators with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0155] Examples of insulators with a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with voids, or resin.

[0156] In addition, the transistor using metal oxide can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen. As the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.

[0157] The insulator that functions as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated for.

[0158] <<Conductors>> As the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, oxide containing lanthanum and nickel are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxygen is absorbed, so they are preferable. Furthermore, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0159] A plurality of conductive layers formed of the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen. A stacked structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen. A stacked structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0160] In addition, when an oxide is used for the channel formation region of a transistor, a conductor functioning as a gate electrode preferably has a stacked structure in which a material containing a metal element and a conductive material containing oxygen are combined. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

[0161] In particular, it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor functioning as a gate electrode. A conductive material containing the above-mentioned metal element and nitrogen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may also be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide to which silicon is added may also be used. Indium gallium zinc oxide containing nitrogen may also be used. By using such a material, hydrogen contained in the metal oxide in which the channel is formed may be captured. Alternatively, hydrogen mixed in from an external insulator may be captured.

[0162] <<Metal oxides>> It is preferable to use a metal oxide that functions as a semiconductor (oxide semiconductor) as the oxide 230. Hereinafter, metal oxides that can be applied to the oxide 230 according to the present invention will be described.

[0163] The metal oxide preferably contains at least indium or zinc. In particular, it is preferable that the metal oxide contains indium and zinc. In addition to these, it is preferable that the metal oxide contains aluminum, gallium, yttrium, tin, etc. In addition, it may contain one or more elements selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0164] Here, the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc is considered. The element M is aluminum, gallium, yttrium, or tin. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt. However, there are cases where the element M may be a combination of multiple elements mentioned above.

[0165] In this specification and the like, metal oxides containing nitrogen may also be collectively referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0166] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 5A. Fig. 5A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0167] As shown in FIG. 5A, oxide semiconductors are broadly classified into "Amorphous", "Crystalline", and "Crystal". "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and poly crystal). "Crystalline" excludes single crystal, poly crystal, and completely amorphous. "Crystal" includes single crystal and poly crystal.

[0168] The structure in the bold frame shown in Fig. 5A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure is completely different from the energetically unstable "Amorphous" or "Crystal".

[0169] The crystal structure of the film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Figure 5B shows an XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of the CAAC-IGZO film classified as "Crystalline". The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by the GIXD measurement shown in Figure 5B will be simply referred to as the XRD spectrum. The vertical axis of Figure 5B is the intensity, and the horizontal axis is 2θ. The composition of the CAAC-IGZO film shown in Figure 5B is in the vicinity of In:Ga:Zn=4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 5B is 500 nm.

[0170] As shown in Figure 5B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ=31° in the XRD spectrum of the CAAC-IGZO film. Note that, as shown in Figure 5B, the peak near 2θ=31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0171] The crystal structure of the film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 5C. Figure 5C shows a diffraction pattern observed by NBED, which causes an electron beam to be incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 5C is approximately In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

[0172] As shown in Figure 5C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0173] <<Structure of oxide semiconductor>> In addition, when focusing on the crystal structure, oxide semiconductors may be classified differently from that shown in FIG. 5A. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OS), amorphous oxide semiconductors, and the like.

[0174] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0175] [CAAC-OS] CAAC-OS is an oxide semiconductor having a plurality of crystalline regions, each of which has a c-axis aligned in a specific direction. The specific direction is the thickness direction of the CAAC-OS film, the normal direction of the surface on which the CAAC-OS film is formed, or the normal direction of the surface of the CAAC-OS film. The crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, the crystalline region is also a region with a uniform lattice arrangement. CAAC-OS has a region in which a plurality of crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a portion in which the direction of the lattice arrangement changes between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement in the region in which the plurality of crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor having a c-axis aligned and no clear orientation in the ab-plane direction.

[0176] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be about several tens of nm.

[0177] In addition, in an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter, (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Thus, the (M, Zn) layer may contain indium. Also, the In layer may contain element M. Note that the In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0178] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD device, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metal elements constituting the CAAC-OS.

[0179] For example, a plurality of bright points (spots) are observed in the electron diffraction pattern of the CAAC-OS film, and the two spots are observed at positions symmetrical to each other with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0180] When the crystal region is observed from the specific direction, the lattice arrangement in the crystal region is based on a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The above distortion may have a lattice arrangement such as a pentagon or heptagon. In addition, in the CAAC-OS, no clear grain boundary can be confirmed even in the vicinity of the distortion. That is, it can be seen that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the fact that the arrangement of oxygen atoms is not dense in the ab-plane direction or the bond distance between atoms changes due to the substitution of metal atoms.

[0181] A crystal structure in which clear grain boundaries are observed is called a polycrystal. The grain boundaries are likely to become recombination centers and capture carriers, causing a decrease in the on-current of a transistor and a decrease in field effect mobility. Therefore, CAAC-OS in which clear grain boundaries are not observed is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. In order to form a CAAC-OS, a structure containing Zn is preferable. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the occurrence of grain boundaries more than In oxide.

[0182] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies). Therefore, the physical properties of an oxide semiconductor having the CAAC-OS are stable. Therefore, an oxide semiconductor having the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, the use of the CAAC-OS in an OS transistor can increase the degree of freedom in the manufacturing process.

[0183] [nc-OS] The nc-OS has periodic atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has minute crystals. Note that the size of the minute crystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the minute crystals are also called nanocrystals. In addition, the nc-OS does not show regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from an a-like OS and an amorphous oxide semiconductor depending on the analysis method. For example, when the structure of the nc-OS film is analyzed using an XRD device, no peak indicating crystallinity is detected in the out-of-plane XRD measurement using θ / 2θ scanning. In addition, when the nc-OS film is subjected to electron diffraction (also called selected area electron diffraction) using an electron beam with a probe diameter larger than that of the nanocrystals (for example, 50 nm or more), a diffraction pattern like a halo pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter (e.g., 1 nm to 30 nm) that is close to the size of a nanocrystal or smaller than the nanocrystal, an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on the direct spot may be obtained.

[0184] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Moreover, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0185] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, with reference to its material composition.

[0186] [CAC-OS] CAC-OS is, for example, a material configuration in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. In the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and the regions having the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0187] Furthermore, CAC-OS is a composite metal oxide in which the material is separated into a first region and a second region, forming a mosaic structure, and the first region is distributed throughout the film (hereinafter, also referred to as a cloud structure). In other words, CAC-OS is a composite metal oxide in which the first region and the second region are mixed together.

[0188] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are represented as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. Also, the second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. Also, the second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0189] Specifically, the first region is a region mainly composed of indium oxide, indium zinc oxide, etc., and the second region is a region mainly composed of gallium oxide, gallium zinc oxide, etc. In other words, the first region can be rephrased as a region mainly composed of In, and the second region can be rephrased as a region mainly composed of Ga.

[0190] In addition, there are cases where a clear boundary between the first region and the second region cannot be observed.

[0191] For example, in the case of a CAC-OS of an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) has confirmed that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0192] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, giving the CAC-OS a switching function (On / Off function). In other words, CAC-OS has a conductive function in part of the material and an insulating function in other parts of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, it is possible to maximize both functions. Therefore, by using CAC-OS in a transistor, it is possible to achieve a high on-current (I on ), high field effect mobility (μ), and good switching behavior can be achieved.

[0193] Oxide semiconductors have a variety of structures and have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0194] <Transistor Having Oxide Semiconductor> Next, the case where the oxide semiconductor is used for a transistor will be described.

[0195] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0196] For the channel formation region of the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 17 cm -3 Less than or equal to 1×10 15 cm -3 Less than 1×10, more preferably 13 cm -3 Less than or equal to 1×10 11 cm -3 Less than 1×10, more preferably 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, an oxide semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0197] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states might also be low.

[0198] In addition, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave as if they are fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0199] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in a nearby film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, and the like.

[0200] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0201] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. For this reason, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon near the interface with the channel formation region of the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are set to 2×10 18 atoms / cm 3 Less than or equal to 2×10 17 atoms / cm 3 The following applies.

[0202] In addition, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 18 atoms / cm 3 Less than or equal to 2×10 16 atoms / cm 3 To the following:

[0203] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5×10, more preferably 17 atoms / cm 3 To the following:

[0204] Furthermore, hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. In addition, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce hydrogen in the channel formation region of the oxide semiconductor as much as possible. Specifically, the hydrogen concentration measured by SIMS in the channel formation region of the oxide semiconductor is 1×10 20 atoms / cm 3 Less than 5 x 10 19 atoms / cm 3 less than 1×10 19 atoms / cm 3 less than 5×10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0205] When an oxide semiconductor in which impurities are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0206] <<Other semiconductor materials>> The semiconductor material that can be used for the oxide 230 is not limited to the above-mentioned metal oxides. A semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide 230. For example, a semiconductor of a single element such as silicon, a compound semiconductor such as gallium arsenide, or a layered material (also called an atomic layer material, a two-dimensional material, etc.) that functions as a semiconductor is preferably used for the semiconductor material. In particular, it is preferable to use a layered material that functions as a semiconductor for the semiconductor material.

[0207] Here, in this specification and the like, the layered material is a general term for a group of materials having a layered crystal structure. The layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. The layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0208] Layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements in group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Chalcogenides include transition metal chalcogenides and group 13 chalcogenides.

[0209] It is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor as the oxide 230. Specific examples of transition metal chalcogenides that can be used as the oxide 230 include molybdenum sulfide (representatively MoS2), molybdenum selenide (representatively MoSe2), molybdenum tellurium (representatively MoTe2), tungsten sulfide (representatively WS2), tungsten selenide (representatively WSe2), tungsten tellurium (representatively WTe2), hafnium sulfide (representatively HfS2), hafnium selenide (representatively HfSe2), zirconium sulfide (representatively ZrS2), and zirconium selenide (representatively ZrSe2).

[0210] <Method for manufacturing semiconductor device> Next, a manufacturing method of the semiconductor device illustrated in FIGS. 1A to 1C which is one embodiment of the present invention will be described with reference to FIGS. 6A to 23C.

[0211] A in each figure shows a top view. B in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A1-A2 in A in each figure, and is also a cross-sectional view in the channel length direction of the transistor 200. C in each figure is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in A in each figure, and is also a cross-sectional view in the channel width direction of the transistor 200. Note that in the top view of A in each figure, some elements are omitted for clarity.

[0212] In the following, insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed as films using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.

[0213] There are three types of sputtering: RF sputtering, which uses a high-frequency power source for the sputtering power supply, DC sputtering, which uses a direct current power source, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used when depositing insulating films, while DC sputtering is mainly used when depositing metal conductive films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0214] CVD methods can be classified into plasma CVD (PECVD) methods that use plasma, thermal CVD (TCVD: Thermal CVD) methods that use heat, photo CVD (Photo CVD) methods that use light, etc. They can also be further classified into metal CVD (MCVD: Metal CVD) methods and metal organic CVD (MOCVD: Metal Organic CVD) methods depending on the source gas used.

[0215] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Moreover, the thermal CVD method is a film formation method that can reduce plasma damage to the object to be processed because it does not use plasma. For example, wiring, electrodes, elements (transistors, capacitive elements, etc.) included in a semiconductor device may be charged up by receiving electric charge from plasma. At this time, the wiring, electrodes, elements, etc. included in the semiconductor device may be destroyed by the accumulated electric charge. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur, so the yield of the semiconductor device can be increased. Furthermore, in the thermal CVD method, plasma damage does not occur during film formation, so a film with few defects can be obtained.

[0216] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0217] The CVD method and the ALD method are different from the film formation method in which particles emitted from a target or the like are deposited, and are film formation methods in which a film is formed by a gas phase reaction on the surface of a workpiece. Therefore, they are film formation methods that are not easily affected by the shape of the workpiece and have good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as the CVD method, which has a fast film formation speed.

[0218] In addition, in the CVD method, a film of any composition can be formed by changing the flow rate ratio of the raw material gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the raw material gases while forming a film. When forming a film while changing the flow rate ratio of the raw material gases, the time required for film formation can be shortened compared to the case of forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0219] In addition, in the ALD method, multiple precursors with different compositions can be introduced simultaneously, or multiple precursors with different compositions can be introduced by controlling the number of times each precursor is introduced during one cycle, making it possible to deposit a film of any composition.

[0220] First, a substrate (not shown) is prepared, and the insulator 212 is formed on the substrate (see FIGS. 6A to 6C). The insulator 212 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 212 can be reduced. However, the method for forming the insulator 212 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may be used as appropriate.

[0221] In this embodiment, a silicon nitride film is formed as the insulator 212 by pulsed DC sputtering using a silicon target in an atmosphere containing nitrogen gas. By using pulsed DC sputtering, the generation of particles due to arcing on the target surface can be suppressed, making the film thickness distribution more uniform. In addition, by using a pulsed voltage, the rise and fall of the discharge can be made steeper than with a high-frequency voltage. This allows power to be supplied to the electrodes more efficiently, improving the sputtering rate and film quality.

[0222] By using an insulator such as silicon nitride through which impurities such as water and hydrogen do not easily permeate, it is possible to suppress the diffusion of impurities such as water and hydrogen contained in layers below the insulator 212. Furthermore, by using an insulator such as silicon nitride through which copper does not easily permeate as the insulator 212, even if a metal that easily diffuses, such as copper, is used for a conductor in a layer (not shown) below the insulator 212, it is possible to suppress the diffusion of the metal upward through the insulator 212.

[0223] Next, the insulator 214 is deposited over the insulator 212 (see FIGS. 6A to 6C). The insulator 214 is preferably deposited by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 214 can be reduced. However, the deposition of the insulator 214 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0224] In this embodiment, an aluminum oxide film is formed as the insulator 214 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen injected into the layer below the insulator 214 can be controlled by the magnitude of the RF power applied to the substrate. The RF power is set to 0 W / cm. 2Above 1.86W / cm 2 The following is set forth. In other words, the amount of oxygen suitable for the transistor characteristics can be changed and injected by adjusting the RF power when forming the insulator 214. Therefore, it is possible to inject an amount of oxygen suitable for improving the reliability of the transistor. In addition, the RF frequency is preferably 10 MHz or higher. Typically, it is 13.56 MHz. The higher the RF frequency, the less damage can be caused to the substrate.

[0225] It is preferable to use a metal oxide having an amorphous structure, such as aluminum oxide, which has a high function of trapping and fixing hydrogen, as the insulator 214. This makes it possible to trap or fix hydrogen contained in the insulator 216 and the like and prevent the hydrogen from diffusing into the oxide 230. In particular, it is preferable to use aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 214, because hydrogen can be more effectively trapped or fixed. This makes it possible to manufacture a transistor 200 and a semiconductor device having excellent characteristics and high reliability.

[0226] Next, the insulator 216 is deposited over the insulator 214. The insulator 216 is preferably deposited by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. However, the deposition of the insulator 216 is not limited to the sputtering method, and a CVD method, an MBE method, a PLD method, an ALD method, or the like may also be used as appropriate.

[0227] In this embodiment, a silicon oxide film is formed by pulsed DC sputtering using a silicon target in an atmosphere containing oxygen gas as the insulator 216. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved.

[0228] It is preferable that the insulators 212, 214, and 216 are successively formed without exposure to the air. For example, a multi-chamber film formation apparatus can be used. This allows the insulators 212, 214, and 216 to be formed with reduced hydrogen in the films, and further reduces the incorporation of hydrogen into the films between each film formation process.

[0229] Next, an opening is formed in the insulator 216, reaching the insulator 214. The opening may be, for example, a groove or a slit. The opening may be an area where the opening is formed. The opening may be formed by wet etching, but dry etching is preferable for fine processing. For the insulator 214, it is preferable to select an insulator that functions as an etching stopper film when the insulator 216 is etched to form the groove. For example, when silicon oxide or silicon oxynitride is used for the insulator 216 that forms the groove, the insulator 214 may be silicon nitride, aluminum oxide, or hafnium oxide.

[0230] As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can be configured to apply a high frequency voltage to one of the parallel plate electrodes. Alternatively, it can be configured to apply a plurality of different high frequency voltages to one of the parallel plate electrodes. Alternatively, it can be configured to apply a high frequency voltage of the same frequency to each of the parallel plate electrodes. Alternatively, it can be configured to apply high frequency voltages of different frequencies to each of the parallel plate electrodes. Alternatively, a dry etching apparatus having a high density plasma source can be used. As the dry etching apparatus having a high density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0231] After the openings are formed, the conductive film 205A is formed (see FIGS. 6A to 6C). The conductive film 205A preferably includes a conductor having a function of suppressing oxygen transmission. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, the conductive film 205A may be a stacked film of a conductor having a function of suppressing oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film 205A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0232] In this embodiment, titanium nitride is formed as the conductive film 205A. By using such a metal nitride as the lower layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 216 or the like. Even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205a.

[0233] Next, a conductive film 205B is formed (see FIGS. 6A to 6C). As the conductive film 205B, tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is formed as the conductive film 205B.

[0234] Next, a CMP process is performed to remove a portion of the conductive film 205A and the conductive film 205B, thereby exposing the insulator 216 (see FIGS. 7A to 7C). As a result, the conductor 205a and the conductor 205b remain only in the openings. Note that the CMP process may remove a portion of the insulator 216.

[0235] Next, the upper portion of the conductor 205b is removed by etching (see FIGS. 8A to 8C). As a result, the upper surface of the conductor 205b becomes lower than the upper surfaces of the conductor 205a and the insulator 216. The conductor 205b can be etched by dry etching or wet etching, but dry etching is preferable for fine processing.

[0236] Next, the conductive film 205C is formed over the insulator 216, the conductor 205a, and the conductor 205b (see FIGS. 9A to 9C). The conductive film 205C preferably includes a conductor having a function of suppressing oxygen permeation, similar to the conductive film 205A.

[0237] In this embodiment, titanium nitride is formed as the conductive film 205C. By using such a metal nitride as the upper layer of the conductor 205b, it is possible to prevent the conductor 205b from being oxidized by the insulator 222 or the like. Even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing out of the conductor 205c.

[0238] Next, a part of the conductive film 205C is removed by performing CMP processing to expose the insulator 216 (see FIG. 10A to FIG. 10C). As a result, the conductor 205a, the conductor 205b, and the conductor 205c remain only in the openings. This allows the conductor 205 to be formed with a flat upper surface. Furthermore, the conductor 205b is configured to be surrounded by the conductor 205a and the conductor 205c. This prevents impurities such as hydrogen from the conductor 205b from diffusing out of the conductor 205a and the conductor 205c, and prevents oxygen from entering from outside the conductor 205a and the conductor 205c and oxidizing the conductor 205b. Note that the CMP processing may remove a part of the insulator 216.

[0239] Next, the insulator 222 is formed on the insulator 216 and the conductor 205 (see FIGS. 11A to 11C). As the insulator 222, an insulator containing one or both of an oxide of aluminum and hafnium may be formed. Note that as the insulator containing one or both of an oxide of aluminum and hafnium, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing silicon and hafnium (hafnium silicate), or the like. An insulator containing one or both of an oxide of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator 222 has a barrier property against hydrogen and water, the hydrogen and water contained in the structure provided around the transistor 200 are prevented from diffusing into the inside of the transistor 200 through the insulator 222, and the generation of oxygen vacancies in the oxide 230 can be suppressed.

[0240] The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In this embodiment, hafnium oxide is formed as the insulator 222 by an ALD method.

[0241] It is preferable to carry out a heat treatment subsequently. The heat treatment may be carried out at 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be carried out under reduced pressure. Alternatively, the heat treatment may be carried out in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or higher, 1% or higher, or 10% or higher of an oxidizing gas to compensate for the desorbed oxygen.

[0242] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulator 222 as much as possible.

[0243] In this embodiment, after the insulator 222 is formed, heat treatment is performed at a flow rate ratio of nitrogen gas and oxygen gas of 4 slm:1 slm at a temperature of 400° C. for one hour. The heat treatment can remove impurities such as water and hydrogen contained in the insulator 222. When an oxide containing hafnium is used as the insulator 222, the heat treatment may cause part of the insulator 222 to crystallize. The heat treatment can also be performed at a timing such as after the insulator 224 is formed.

[0244] Next, the insulator 219 is deposited over the insulator 222 (see FIGS. 11A to 11C). The insulator 219 can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is deposited as the insulator 219 by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 219 can be reduced.

[0245] Next, an opening is formed in the insulator 219 by lithography, reaching the insulator 222 (see FIGS. 12A to 12C). The opening may be formed by wet etching, but dry etching is preferable for fine processing.

[0246] After the openings are formed, the insulating film 224A is formed (see FIGS. 13A to 13C). The insulating film 224A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, silicon oxide is formed by a sputtering method as the insulating film 224A. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulating film 224A can be reduced.

[0247] Next, oxide film 230A and oxide film 230B are sequentially formed on insulating film 224A (see FIGS. 13A to 13C). Note that oxide film 230A and oxide film 230B are preferably formed successively without being exposed to the air environment. By forming the films without being exposed to the air, it is possible to prevent impurities or moisture from the air environment from adhering to oxide film 230A and oxide film 230B, and it is possible to keep the vicinity of the interface between oxide film 230A and oxide film 230B clean.

[0248] The oxide film 230A and the oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film 230A and the oxide film 230B are preferably formed by ALD because a film of uniform thickness can be formed even in a groove or opening with a large aspect ratio. The PEALD method is also preferable because the oxide film 230A and the oxide film 230B can be formed at a lower temperature than the thermal ALD method. In this embodiment, the oxide film 230A and the oxide film 230B are formed by sputtering.

[0249] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed can be increased. In addition, when the oxide film is formed by sputtering, the above-mentioned In-M-Zn oxide target can be used.

[0250] In particular, during the formation of the oxide film 230A, a portion of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas may be set to 70% or more, preferably 80% or more, and more preferably 100%.

[0251] When the oxide film 230B is formed by a sputtering method, an oxygen-excessive oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excessive oxide semiconductor for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film 230B is formed by a sputtering method, an oxygen-deficient oxide semiconductor is formed when the ratio of oxygen contained in the sputtering gas is more than or equal to 1% and less than or equal to 30%, preferably 5% to 20%,. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility. When the oxide film is formed while the substrate is heated, the crystallinity of the oxide film can be improved.

[0252] In this embodiment, the oxide film 230A is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. The oxide film 230B is formed by sputtering using an oxide target with an atomic ratio of In:Ga:Zn=4:2:4.1, an oxide target with an atomic ratio of In:Ga:Zn=1:1:1, or an oxide target with an atomic ratio of In:Ga:Zn=1:1:0.5. Each oxide film may be formed according to the characteristics required for the oxide 230a and the oxide 230b by appropriately selecting the film formation conditions and atomic ratio.

[0253] Next, it is preferable to perform a heat treatment. The heat treatment may be performed in a temperature range in which the oxide film 230A and the oxide film 230B are not polycrystallized, and may be performed at 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas may be about 20%. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere of nitrogen gas or an inert gas, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to compensate for the desorbed oxygen.

[0254] In addition, it is preferable that the gas used in the heat treatment is highly purified. For example, the amount of moisture contained in the gas used in the heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By using a highly purified gas to perform the heat treatment, it is possible to prevent moisture and the like from being taken into the oxide film 230A, the oxide film 230B, etc. as much as possible.

[0255] In this embodiment, the heat treatment is performed in a nitrogen atmosphere at 400°C for 1 hour, followed by another heat treatment in an oxygen atmosphere at 400°C for 1 hour. This heat treatment can remove impurities such as water and hydrogen from the oxide film 230A and the oxide film 230B. Furthermore, this heat treatment can improve the crystallinity of the oxide film 230B, resulting in a denser and more compact structure. This can reduce the diffusion of oxygen or impurities in the oxide film 230B.

[0256] Next, the insulating film 224A, the oxide film 230A, and the oxide film 230B are partially removed by performing a CMP process, and the insulator 219 is exposed (see FIGS. 14A to 14C). As a result, the insulating film 224A, the oxide film 230A, and the oxide film 230B remain only in the opening, and the insulator 224, the oxide 230a, and the oxide 230b are formed, respectively. This makes it possible to form a stack of the insulator 224 and the oxide 230, which has a flat upper surface. Note that although the CMP process may remove a portion of the insulator 219, the insulator 224, the oxide 230a, and the oxide 230b are simultaneously formed, so that the upper surfaces of the insulator 219, the insulator 224, the oxide 230a, and the oxide 230b are formed at approximately the same height in a cross-sectional view. Note that approximately the same height includes, for example, a range of ±10 nm with respect to the upper surface of the oxide 230a.

[0257] By forming the oxide 230 without using a dry etching method in this way, it is possible to suppress the generation of contaminants resulting from the reaction product between the etching gas and the oxide 230. In addition, since an etching mask is not used, there is no occurrence of shrinkage or recession of the etching mask during etching, so the amount of deviation between the finished value and the design value can be suppressed. This is advantageous for miniaturization. In addition, since the insulator and the oxide are simultaneously processed and formed by the CMP process, it is possible to reduce the number of masks, which may be advantageous in terms of cost.

[0258] In this embodiment, an example of performing heat treatment before CMP processing is shown, but the present invention is not limited to this. Heat treatment may be performed after CMP processing. By performing heat treatment after CMP processing, moisture and the like attached by CMP processing can be removed. In addition, if the CMP processing causes damage to the oxide 230, the damaged layer can be removed by performing heat treatment after CMP processing.

[0259] Next, a conductive film to be the conductive layer 242B is formed over the insulator 219, the insulator 224, and the oxide 230 (see FIGS. 15A to 15C). The conductive film to be the conductive layer 242B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, tantalum nitride may be formed by a sputtering method as the conductive film to be the conductive layer 242B. Note that heat treatment may be performed before the conductive film to be the conductive layer 242B is formed. The heat treatment may be performed under reduced pressure, and the conductive film to be the conductive layer 242B may be formed continuously without exposure to the air. By performing such treatment, moisture and hydrogen adsorbed on the surfaces of the insulator 219, the insulator 224, and the oxide 230 can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the heat treatment temperature is 200°C.

[0260] Next, the conductive film to be the conductive layer 242B is processed by lithography to form the conductive layer 242B (see FIGS. 15A to 15C). Note that the conductive layer 242B is preferably disposed so as to overlap with the oxide 230.

[0261] Next, the insulator 272 is formed on the insulator 219 and the conductive layer 242B (see FIGS. 15A to 15C). The insulator 272 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 272 can be made of silicon nitride, aluminum oxide, or the like. The insulator 272 may have a stacked structure. For example, a silicon nitride film may be formed and then an aluminum oxide film may be formed on the silicon nitride, or an aluminum oxide film may be formed and then a silicon nitride film may be formed on the aluminum oxide. In this embodiment, a silicon nitride film is formed as the insulator 272 by a sputtering method.

[0262] Next, an insulating film to be the insulator 280 is formed on the insulator 272. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film may be formed by a sputtering method as the insulating film. The insulating film to be the insulator 280 can be formed by a sputtering method in an atmosphere containing oxygen, thereby forming the insulator 280 containing excess oxygen. In addition, the hydrogen concentration in the insulator 280 can be reduced by using a sputtering method that does not require hydrogen as a deposition gas. Note that a heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be formed continuously without exposure to the atmosphere. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the insulator 272 and the like can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b, and the insulator 224 can be further reduced. The heat treatment conditions described above can be used for the heat treatment.

[0263] Next, the insulating film that becomes the insulator 280 is subjected to CMP processing to form the insulator 280 with a flat upper surface (see FIGS. 16A to 16C). Note that a silicon nitride film may be formed on the insulator 280 by, for example, a sputtering method, and the CMP processing may be performed until the silicon nitride reaches the insulator 280.

[0264] Next, a part of the insulator 280, a part of the insulator 272, and a part of the conductive layer 242B are processed to form an opening that reaches the oxide 230b. The opening is preferably formed so as to overlap the conductor 205. By forming the opening, the conductor 242a and the conductor 242b are formed (see FIGS. 16A to 16C).

[0265] When forming the opening, the upper part of the oxide 230b may be removed. By removing a part of the oxide 230b, a groove portion is formed in the oxide 230b. Depending on the depth of the groove portion, the groove portion may be formed in the process of forming the opening, or may be formed in a process different from the process of forming the opening.

[0266] Furthermore, a part of the insulator 280, a part of the insulator 272, and a part of the conductive layer 242B can be processed by dry etching or wet etching. Processing by dry etching is suitable for fine processing. Moreover, the processing may be performed under different conditions. For example, a part of the insulator 280 may be processed by dry etching, a part of the insulator 272 may be processed by wet etching, and a part of the conductive layer 242B may be processed by dry etching. Moreover, a part of the insulator 280 and a part of the conductive layer 242B may be processed under different conditions.

[0267] Here, it is preferable to remove impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused therein. It is also preferable to remove damaged areas formed on the surface of the oxide 230b by the dry etching. The impurities include those originating from components contained in the insulator 280, the insulator 272, and the conductive layer 242B, components contained in the members used in the device used to form the opening, and components contained in the gas or liquid used in the etching. The impurities include, for example, aluminum, silicon, tantalum, fluorine, and chlorine.

[0268] In particular, impurities such as aluminum or silicon inhibit the oxide 230b from becoming a CAAC-OS. Therefore, it is preferable that impurity elements such as aluminum or silicon that inhibit the CAAC-OS formation are reduced or removed. For example, the concentration of aluminum atoms in the oxide 230b and its vicinity may be 5.0 atomic % or less, preferably 2.0 atomic % or less, more preferably 1.5 atomic % or less, even more preferably 1.0 atomic % or less, and even more preferably less than 0.3 atomic %.

[0269] In addition, the region of the metal oxide in which the CAAC-OS formation is inhibited by impurities such as aluminum or silicon and which becomes an amorphous-like oxide semiconductor (a-like OS) is sometimes called a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced, so the V O A large amount of H is formed, which makes the transistor more likely to be normally on. Therefore, it is preferable that the non-CAAC region of the oxide 230b is reduced or eliminated.

[0270] In contrast, it is preferable that the oxide 230b has a layered CAAC structure. In particular, it is preferable that the oxide 230b has the CAAC structure up to the lower end of the drain. Here, in the transistor 200, the conductor 242a or the conductor 242b and its vicinity function as the drain. In other words, it is preferable that the oxide 230b near the lower end of the conductor 242a (conductor 242b) has the CAAC structure. In this way, even at the drain end, which significantly affects the drain breakdown voltage, the damaged region of the oxide 230b is removed, and by having the CAAC structure, the fluctuation in the electrical characteristics of the transistor 200 can be further suppressed. In addition, the reliability of the transistor 200 can be improved.

[0271] In order to remove the above-mentioned impurities, a cleaning process is performed. The cleaning method includes wet cleaning using a cleaning solution, plasma processing using plasma, cleaning by heat treatment, and the like, and the above cleaning methods may be combined appropriately. Note that the above-mentioned grooves may become deeper due to the cleaning process.

[0272] For wet cleaning, a cleaning process may be performed using an aqueous solution of ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water, pure water, carbonated water, or the like. Alternatively, ultrasonic cleaning may be performed using these aqueous solutions, pure water, or carbonated water. Alternatively, these cleaning methods may be combined as appropriate.

[0273] In this specification, an aqueous solution of hydrofluoric acid diluted with pure water may be called diluted hydrofluoric acid, and an aqueous solution of ammonia water diluted with pure water may be called diluted ammonia water. The concentration and temperature of the aqueous solution may be appropriately adjusted depending on the impurities to be removed and the configuration of the semiconductor device to be cleaned. The ammonia concentration of the diluted ammonia water may be 0.01% or more and 5% or less, preferably 0.1% or more and 0.5% or less. The hydrogen fluoride concentration of the diluted hydrofluoric acid may be 0.01 ppm or more and 100 ppm or less, preferably 0.1 ppm or more and 10 ppm or less.

[0274] In addition, it is preferable to use a frequency of 200 kHz or more, and more preferably 900 kHz or more, for ultrasonic cleaning. By using such a frequency, damage to the oxide 230b and the like can be reduced.

[0275] The above cleaning process may be performed multiple times, and the cleaning solution may be changed for each cleaning process. For example, a first cleaning process may be performed using diluted hydrofluoric acid or diluted ammonia water, and a second cleaning process may be performed using pure water or carbonated water.

[0276] In the present embodiment, as the cleaning process, wet cleaning is performed using diluted hydrofluoric acid, followed by wet cleaning using pure water or carbonated water. By performing this cleaning process, impurities attached to the surfaces of the oxide 230a, the oxide 230b, etc. or diffused inside can be removed. Furthermore, the crystallinity of the oxide 230b can be improved.

[0277] After the etching or cleaning, a heat treatment may be performed. The heat treatment may be performed at a temperature of 100° C. to 450° C., preferably 350° C. to 400° C. The heat treatment is performed in an atmosphere of nitrogen gas or an inert gas, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 230a and the oxide 230b, thereby reducing the oxygen vacancy V. OIn addition, by performing such a heat treatment, the crystallinity of the oxide 230b can be improved. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in an oxygen atmosphere, the heat treatment may be performed in a nitrogen atmosphere without exposure to the air.

[0278] Next, an insulating film that becomes the insulator 252 is formed. The insulating film that becomes the insulator 252 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon nitride film is formed by the ALD method.

[0279] Next, the insulating film that becomes the insulator 252 is anisotropically etched by dry etching to form the insulator 252 that contacts the ends of the conductor 242a, the conductor 242b, the insulator 272, and the insulator 280 (see FIGS. 17A to 17C). Note that it is preferable that the insulator 252 contacts at least the ends of the conductor 242a and the conductor 242b.

[0280] By having the insulator 252 in contact with the end of the conductor 242a and the end of the conductor 242b, oxidation of the conductor 242a and the conductor 242b can be suppressed.

[0281] Next, the insulating film 250A that becomes the insulator 250a is formed (see FIGS. 18A to 18C). A heat treatment may be performed before the formation of the insulating film 250A, and the heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the atmosphere. The heat treatment is preferably performed in an atmosphere containing oxygen. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower.

[0282] The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film 250A is preferably formed by a film formation method using a gas in which hydrogen atoms are reduced or removed. This allows the hydrogen concentration of the insulating film 250A to be reduced. Since the insulating film 250A becomes the insulator 250 that contacts the oxide 230b in a later process, it is preferable that the hydrogen concentration is reduced in this manner.

[0283] In addition, the insulating film 250A is preferably formed by the PEALD method using a gas (precursor) containing silicon and not containing hydrocarbon, and an oxidizing gas (reactant). The thickness of the insulator 250 functioning as the gate insulating film of the miniaturized transistor 200 needs to be extremely thin (for example, about 5 nm to 30 nm) and have small variations. In contrast, the PEALD method is a film formation method in which a precursor and a reactant (oxidizing agent) are alternately introduced, and the film thickness can be adjusted by the number of times this cycle is repeated, so that precise film thickness adjustment is possible. Therefore, the precision of the gate insulating film required by the miniaturized transistor 200 can be achieved. In addition, as shown in FIG. 18B and FIG. 18C, the insulating film 250A needs to be formed with good coverage on the bottom and side surfaces of the opening formed by the insulator 280 and the like. Since layers of atoms can be deposited one by one on the bottom and side surfaces of the opening, the insulating film 250A can be formed with good coverage on the opening. Furthermore, by using the PEALD method, the film can be formed at a relatively low substrate temperature.

[0284] In addition, by using a gas (precursor) containing silicon and not containing hydrocarbons, and an oxidizing gas (reactant), it is possible to suppress the intrusion of hydrogen into the insulating film 250A and the oxide 230b. In addition, since a precursor containing impurities such as carbon, for example an organic precursor having a CH group, is not used, it is possible to suppress the intrusion of impurities such as carbon, hydrocarbons, etc. into the insulating film 250A. In this way, a denser film not containing impurities can be formed, and therefore the diffusion of In from the oxide 230b to the insulating film 250A can be prevented.

[0285] Next, the insulating film 250B that becomes the insulator 250b is formed (see FIG. 18A to FIG. 18C). The insulating film 250B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 250B is preferably formed by using an insulator that has a function of suppressing oxygen diffusion. With such a configuration, it is possible to suppress the oxygen contained in the insulator 250a from diffusing into the conductor 260. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. In addition, it is possible to suppress the oxidation of the conductor 260 due to the oxygen contained in the insulator 250a. For example, the insulating film 250A can be provided by using a material that can be used for the insulator 250 described above, and the insulating film 250B can be provided by using a material similar to that of the insulator 222.

[0286] Specifically, the insulating film 250B may be a metal oxide containing one or more of hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used as the oxide 230. In particular, it is preferable to use an insulator containing an oxide of one or both of aluminum and hafnium.

[0287] The insulating film 250B may have a laminated structure. For example, silicon nitride may be laminated on an insulator containing an oxide of one or both of aluminum and hafnium. With such a structure, it is possible to prevent oxidation of the conductor 260 formed in the subsequent process. It is also possible to prevent hydrogen contained in the conductor 260 from penetrating into the oxide 230 via the insulator 250.

[0288] In this embodiment, the insulating film 250A is formed of silicon oxynitride by a PECVD method, and the insulating film 250B is formed of hafnium oxide by a thermal ALD method.

[0289] Next, microwave processing is performed in an atmosphere containing oxygen (see Figs. 18A to 18C). Here, the dotted lines shown in Figs. 18B and 18C indicate microwaves, high frequency such as RF, oxygen plasma, or oxygen radicals. For the microwave processing, it is preferable to use a microwave processing device having a power source that generates high density plasma using microwaves. The microwave processing device may also have a power source that applies RF to the substrate side. By using high density plasma, high density oxygen radicals can be generated. By applying RF to the substrate side, oxygen ions generated by high density plasma can be efficiently introduced into the oxide 230b. The microwave processing is preferably performed under reduced pressure, with the pressure being 60 Pa or more, preferably 133 Pa or more, more preferably 200 Pa or more, and even more preferably 400 Pa or more. The oxygen flow rate ratio (O2 / O2+Ar) is preferably 50% or less, preferably 10% or more and 30% or less. The processing temperature may be 750°C or less, preferably 500°C or less, for example, about 400°C. Furthermore, after the oxygen plasma treatment, a heat treatment may be performed successively without exposure to the outside air.

[0290] As shown in Figures 18B and 18C, by performing microwave processing in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. At this time, microwaves or high frequency waves such as RF can also be irradiated to the region 230bc. In other words, microwaves, high frequency waves such as RF, oxygen plasma, etc. can be applied to the region 230bc shown in Figure 4. The action of the plasma, microwaves, etc. increases the V of the region 230bc. O H can be split off and hydrogen H can be removed from the region 230bc. O H→H+V O " occurs, and the hydrogen concentration in the region 230bc can be reduced. Therefore, the oxygen vacancies in the region 230bc and the V O By supplying oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator 250 to the oxygen vacancies formed in the region 230bc, the oxygen vacancies in the region 230bc can be further reduced, and the carrier concentration can be reduced.

[0291] On the other hand, conductors 242a and 242b are provided on regions 230ba and 230bb shown in Fig. 4. As shown in Fig. 18B and Fig. 18C, conductors 242a and 242b block the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like, so that these effects do not reach regions 230ba and 230bb. As a result, V O Since there is no reduction in H and no excessive supply of oxygen, a decrease in the carrier concentration can be prevented.

[0292] In this manner, oxygen vacancies and V are selectively formed in the oxide semiconductor region 230bc. OBy removing H, the region 230bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 230ba and 230bb that function as source and drain regions can be suppressed, and the n-type can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 200, and suppresses variations in the electrical characteristics of the transistor 200 within the substrate surface.

[0293] Therefore, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device having good electrical characteristics.

[0294] Moreover, the microwave treatment may be performed after the formation of the insulating film 250 A. Moreover, the microwave treatment may be performed after the formation of the insulating film 250 A, but it is not necessary to perform the microwave treatment after the formation of the insulating film 250 B.

[0295] Also, after the formation of the insulating film 250A and after the formation of the insulating film 250B, a heating treatment may be performed while maintaining the reduced pressure state after each microwave treatment. By performing such a treatment, hydrogen in the insulating film 250A, the insulating film 250B, the oxide 230b, and the oxide 230a can be efficiently removed. Also, some of the hydrogen may be gettered to the conductor 242 (the conductor 242a and the conductor 242b). Alternatively, a step of performing a heating treatment may be repeated multiple times while maintaining the reduced pressure state after the microwave treatment. By repeatedly performing the heating treatment, hydrogen in the insulating film 250A, the oxide 230b, and the oxide 230a can be more efficiently removed. Note that the heating treatment temperature is preferably 300° C. or more and 500° C. or less.

[0296] Furthermore, by modifying the film quality of the insulating film 250A and the insulating film 250B by microwave processing, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. Therefore, it is possible to suppress the diffusion of hydrogen, water, impurities, etc. into the oxide 230b, the oxide 230a, etc. through the insulator 250 by a post-process such as film formation of a conductive film that becomes the conductor 260, or a post-process such as heat treatment.

[0297] Next, a conductive film that becomes the conductor 260a and a conductive film that becomes the conductor 260b are formed in this order. The conductive film that becomes the conductor 260a and the conductive film that becomes the conductor 260b can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film that becomes the conductor 260a is formed using the ALD method, and the conductive film that becomes the conductor 260b is formed using the CVD method.

[0298] Next, the insulating film 250A, the insulating film 250B, the conductive film to be the conductor 260a, and the conductive film to be the conductor 260b are polished by CMP until the insulator 280 is exposed, thereby forming the insulator 250a, the insulator 250b, and the conductor 260 (the conductor 260a and the conductor 260b) (see FIGS. 19A to 19C). As a result, the insulator 250 is disposed so as to cover the opening that reaches the oxide 230b and the inner wall (side wall and bottom surface) of the groove of the oxide 230b. The conductor 260 is disposed so as to fill the opening and the groove through the insulator 250.

[0299] Next, heat treatment may be performed under the same conditions as the above heat treatment. In this embodiment, the treatment is performed in a nitrogen atmosphere at a temperature of 400° C. for 1 hour. The heat treatment can reduce the moisture and hydrogen concentrations in the insulators 250 and 280. Note that after the heat treatment, the insulator 282 may be formed without exposure to the air.

[0300] Next, the insulator 282a and the insulator 282b are successively formed over the insulator 250, the conductor 260, and the insulator 280 (see FIGS. 20A to 20C). The insulator 282a and the insulator 282b can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 282a and the insulator 282b are preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 282a and the insulator 282b can be reduced.

[0301] In this embodiment, aluminum oxide is deposited as the insulators 282a and 282b by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. In addition, the RF power applied to the substrate is 1.86 W / cm. 2 Less than or equal to 0 W / cm 2 More than 0.31W / cm 2 By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. In this embodiment, the insulator 282a is formed by applying an RF power of 0 W / cm2 to the substrate. 2 The insulator 282b is formed as follows: RF power applied to the substrate is 0.31 W / cm 2 A film is formed as follows.

[0302] Next, the insulators 282a, 282b, 280, 272, 219, 222, and 216 are processed until they reach the top surface of the insulator 214 (see FIGS. 21A to 21C). This processing may be performed by wet etching, but dry etching is preferable for fine processing.

[0303] Next, a heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. to 650° C., preferably 400° C. to 600° C. In addition, the heat treatment is preferably performed at a temperature lower than the heat treatment temperature performed after the oxide film 243A is formed. The heat treatment is performed in a nitrogen gas or inert gas atmosphere. By performing the heat treatment, the oxygen contained in the insulator 280 and the hydrogen bonded to the oxygen can be released to the outside from the side of the insulator 280 formed by processing the insulators 282a, 282b, 280, 272, 219, 222, and 216. In addition, the oxygen contained in the insulator 280 and the hydrogen bonded to the oxygen can be released to the outside. The hydrogen bonded to the oxygen is released as water. Therefore, the unnecessary oxygen and hydrogen contained in the insulator 280 can be reduced.

[0304] Next, the insulator 283 is formed over the insulator 282b (see FIGS. 22A to 22C). The insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 283 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 283 can be reduced. The insulator 283 may have a multilayer structure. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed on the silicon nitride by an ALD method. The transistor 200 is surrounded by the insulator 283 and the insulator 214, which have high barrier properties, to prevent moisture and hydrogen from entering from the outside.

[0305] Next, the insulator 274 is formed over the insulator 283. The insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulator 274 by a CVD method.

[0306] Next, the insulator 274 is polished by CMP until the insulator 283 is exposed, thereby planarizing the upper surface of the insulator 274 (see FIGS. 22A to 22C). The CMP process may remove a part of the upper surface of the insulator 283.

[0307] Next, the insulator 284 is formed over the insulator 274 and the insulator 283 (see FIGS. 22A to 22C). The insulator 284 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 284 is preferably formed by a sputtering method. By using a sputtering method that does not require hydrogen as a deposition gas, the hydrogen concentration in the insulator 284 can be reduced.

[0308] In this embodiment, an aluminum oxide film is formed as the insulator 284 by pulsed DC sputtering using an aluminum target in an atmosphere containing oxygen gas. By using the pulsed DC sputtering method, the film thickness distribution can be made more uniform, and the sputtering rate and film quality can be improved. In addition, the RF power applied to the substrate is 0.62 W / cm. 2 Less than or equal to 0 W / cm 2 More than 0.31W / cm 2 The RF power applied to the substrate is preferably greater than the RF power applied to the substrate during deposition of the insulator 282.

[0309] Next, openings are formed in the insulators 272, 280, 282, 283, and 284, reaching the conductor 242 (see FIGS. 23A and 23B). The openings may be formed by using a lithography method. Note that, although the shape of the openings is circular in top view in FIG. 23A, the shape is not limited to this. For example, the openings may be substantially circular such as an ellipse, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners in top view.

[0310] Next, an insulating film that will become the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241 (see FIG. 23B). The insulating film that will become the insulator 241 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. As the insulating film that will become the insulator 241, it is preferable to use an insulating film that has a function of suppressing oxygen permeation. For example, it is preferable to form an aluminum oxide film by the ALD method. Alternatively, it is preferable to form a silicon nitride film by the PEALD method. Silicon nitride is preferable because it has high barrier properties against hydrogen.

[0311] Moreover, for example, a dry etching method may be used as the anisotropic etching of the insulating film that becomes the insulator 241. By providing the insulator 241 on the sidewall of the opening, it is possible to suppress the permeation of oxygen from the outside and prevent the oxidation of the conductor 240a and the conductor 240b to be formed next. It is also possible to prevent impurities such as water and hydrogen from diffusing to the outside from the conductor 240a and the conductor 240b.

[0312] Next, a conductive film that becomes the conductor 240a and the conductor 240b is formed. The conductive film that becomes the conductor 240a and the conductor 240b is preferably a laminated structure including a conductor that has a function of suppressing the permeation of impurities such as water and hydrogen. For example, it can be a laminated structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. The conductive film that becomes the conductor 240 can be formed by using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

[0313] Next, a CMP process is performed to remove parts of the conductive film that will become the conductors 240a and 240b, exposing the upper surface of the insulator 284. As a result, the conductive film remains only in the openings, forming the conductors 240a and 240b with flat upper surfaces (see FIG. 23B). Note that the CMP process may remove part of the upper surface of the insulator 286.

[0314] Next, a conductive film is formed to become the conductor 246. The conductive film to become the conductor 246 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0315] Next, the conductive film that becomes the conductor 246 is processed by lithography to form the conductor 246a in contact with the top surface of the conductor 240a and the conductor 246b in contact with the top surface of the conductor 240b. At this time, a part of the insulator 284 in the region where the conductor 246a and the conductor 246b do not overlap with the insulator 286 may be removed.

[0316] Next, the insulator 286 is formed on the conductor 246 and the insulator 284. The insulator 286 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator 286 may also be a multi-layered structure. For example, a silicon nitride film may be formed by a sputtering method, and a silicon nitride film may be formed on the silicon nitride by a CVD method.

[0317] 1A to 1C can be manufactured. As shown in FIGS. 6A to 23C, the transistor 200 can be manufactured by the manufacturing method of a semiconductor device described in this embodiment.

[0318] <Microwave processing equipment> A microwave processing apparatus that can be used in the above-described method for manufacturing a semiconductor device will be described below.

[0319] First, the configuration of a manufacturing apparatus that reduces the inclusion of impurities during the manufacture of semiconductor devices and the like will be described with reference to FIGS.

[0320] 24 is a schematic top view of a single-wafer multi-chamber manufacturing apparatus 2700. The manufacturing apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 having a cassette port 2761 for accommodating a substrate and an alignment port 2762 for aligning the substrate, an atmosphere-side substrate transfer chamber 2702 for transferring the substrate from the atmosphere-side substrate supply chamber 2701, a load lock chamber 2703a for loading the substrate and for reducing the pressure in the chamber from atmospheric pressure or from reduced pressure to atmospheric pressure, an unload lock chamber 2703b for unloading the substrate and for switching the pressure in the chamber from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring the substrate in a vacuum, a chamber 2706a, a chamber 2706b, a chamber 2706c, and a chamber 2706d.

[0321] The atmospheric side substrate transfer chamber 2702 is connected to a load lock chamber 2703a and an unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to a transfer chamber 2704, and the transfer chamber 2704 is connected to a chamber 2706a, a chamber 2706b, a chamber 2706c, and a chamber 2706d.

[0322] A gate valve GV is provided at the connection between each chamber, and each chamber can be independently maintained in a vacuum state, except for the atmosphere side substrate supply chamber 2701 and the atmosphere side substrate transfer chamber 2702. A transfer robot 2763a is provided in the atmosphere side substrate transfer chamber 2702, and a transfer robot 2763b is provided in the transfer chamber 2704. Substrates can be transferred within the manufacturing apparatus 2700 by the transfer robot 2763a and the transfer robot 2763b.

[0323] The back pressure (total pressure) of the transfer chamber 2704 and each chamber is, for example, 1×10 -4 Pa or less, preferably 3×10 -5 Pa or less, more preferably 1×10 -5 The partial pressure of gas molecules (atoms) with a mass-to-charge ratio (m / z) of 18 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 28 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 The partial pressure of gas molecules (atoms) with m / z of 44 in the transfer chamber 2704 and each chamber is, for example, 3×10 -5 Pa or less, preferably 1×10 -5 Pa or less, more preferably 3×10 -6 Pa or less.

[0324] The total pressure and partial pressure in the transfer chamber 2704 and each chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also called Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

[0325] In addition, it is desirable that the transfer chamber 2704 and each chamber have a configuration with little external or internal leakage. For example, the leak rate of the transfer chamber 2704 and each chamber is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 18 is 1×10 -7 Pa·m 3 / s or less, preferably 3×10 -8 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 28 is 1×10 -5 Pa·m 3 / s or less, preferably 1×10 -6 Pa·m 3 / s or less. For example, the leak rate of a gas molecule (atom) with m / z of 44 is 3×10 -6 Pa·m 3 / s or less, preferably 1×10 -6Pa·m 3 / s or less.

[0326] The leak rate can be derived from the total pressure and partial pressure measured using the mass spectrometer mentioned above. The leak rate depends on external and internal leaks. External leaks are caused by gas flowing in from outside the vacuum system due to tiny holes or poor sealing. Internal leaks are caused by leakage from partitions such as valves in the vacuum system or gas released from internal components. To keep the leak rate below the above values, measures must be taken from both the external and internal leaks perspective.

[0327] For example, the opening and closing parts of the transfer chamber 2704 and each chamber may be sealed with a metal gasket. The metal gasket is preferably made of a metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. In addition, by using a passivated metal coated with iron fluoride, aluminum oxide, chromium oxide, or the like, the release of gas containing impurities from the metal gasket is suppressed, and internal leakage can be reduced.

[0328] In addition, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits less gas containing impurities, is used as a member constituting the manufacturing apparatus 2700. In addition, the above-mentioned metals which emit less gas containing impurities may be used by coating an alloy containing iron, chromium, nickel, etc. Alloys containing iron, chromium, nickel, etc. are rigid, heat-resistant, and suitable for processing. Here, if the surface irregularities of the members are reduced by polishing or the like in order to reduce the surface area, the amount of emitted gas can be reduced.

[0329] Alternatively, the components of the manufacturing apparatus 2700 described above may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

[0330] It is preferable that the components of the manufacturing apparatus 2700 are constructed solely from metal as much as possible. For example, even if a viewing window made of quartz or the like is installed, it is advisable to thinly coat the surface with iron fluoride, aluminum oxide, chromium oxide, or the like to suppress outgassing.

[0331] The adsorbed matter present in the transfer chamber 2704 and each chamber does not affect the pressure of the transfer chamber 2704 and each chamber because it is adsorbed to the inner walls, but it causes gas emission when the transfer chamber 2704 and each chamber are evacuated. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with high exhaust capacity to desorb as much of the adsorbed matter present in the transfer chamber 2704 and each chamber and evacuate them in advance. In addition, the transfer chamber 2704 and each chamber may be baked to promote the desorption of the adsorbed matter. By baking, the desorption speed of the adsorbed matter can be increased by about 10 times. Baking may be performed at 100°C or higher and 450°C or lower. At this time, if the adsorbed matter is removed while introducing an inert gas into the transfer chamber 2704 and each chamber, the desorption speed of water and the like that is difficult to desorb by only exhausting can be further increased. In addition, the desorption speed of the adsorbed matter can be further increased by heating the inert gas introduced to the same temperature as the baking temperature. Here, it is preferable to use a rare gas as the inert gas.

[0332] Alternatively, it is preferable to increase the pressure in the transfer chamber 2704 and each chamber by introducing an inert gas such as a heated rare gas or oxygen, and then evacuate the transfer chamber 2704 and each chamber again after a certain time has passed. By introducing a heated gas, it is possible to desorb adsorbed substances in the transfer chamber 2704 and each chamber, and it is possible to reduce impurities present in the transfer chamber 2704 and each chamber. It is effective to repeat this process 2 to 30 times, preferably 5 to 15 times. Specifically, by introducing an inert gas or oxygen having a temperature of 40° C. to 400° C., preferably 50° C. to 200° C., the pressure in the transfer chamber 2704 and each chamber is set to 0.1 Pa to 10 kPa, preferably 1 Pa to 1 kPa, and more preferably 5 Pa to 100 Pa, and the period for maintaining the pressure is 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. Thereafter, the transfer chamber 2704 and each chamber are evacuated for a period of 5 to 300 minutes, preferably 10 to 120 minutes.

[0333] Next, chamber 2706b and chamber 2706c will be described with reference to the schematic cross-sectional view shown in FIG.

[0334] The chamber 2706b and the chamber 2706c are chambers capable of performing microwave processing on an object to be processed, for example. The chamber 2706b and the chamber 2706c differ only in the atmosphere during microwave processing. Since the other configurations are common, they will be described together below.

[0335] The chamber 2706b and the chamber 2706c have a slot antenna plate 2808, a dielectric plate 2809, a substrate holder 2812, and an exhaust port 2819. In addition, outside the chamber 2706b and the chamber 2706c, a gas supply source 2801, a valve 2802, a high frequency generator 2803, a waveguide 2804, a mode converter 2805, a gas pipe 2806, a waveguide 2807, a matching box 2815, a high frequency power supply 2816, a vacuum pump 2817, and a valve 2818 are provided.

[0336] The high frequency generator 2803 is connected to the mode converter 2805 via a waveguide 2804. The mode converter 2805 is connected to a slot antenna plate 2808 via a waveguide 2807. The slot antenna plate 2808 is disposed in contact with a dielectric plate 2809. The gas supply source 2801 is connected to the mode converter 2805 via a valve 2802. Gas is sent to the chambers 2706b and 2706c through a gas pipe 2806 passing through the mode converter 2805, the waveguide 2807, and the dielectric plate 2809. The vacuum pump 2817 has a function of exhausting gas and the like from the chambers 2706b and 2706c via a valve 2818 and an exhaust port 2819. The high frequency power supply 2816 is connected to the substrate holder 2812 via a matching box 2815.

[0337] The substrate holder 2812 has a function of holding the substrate 2811. For example, the substrate holder 2812 has a function of electrostatically or mechanically chucking the substrate 2811. The substrate holder 2812 also has a function as an electrode to which power is supplied from a high frequency power supply 2816. The substrate holder 2812 also has an internal heating mechanism 2813 and has a function of heating the substrate 2811.

[0338] For example, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbo molecular pump can be used as the vacuum pump 2817. A cryotrap may be used in addition to the vacuum pump 2817. The use of a cryopump and a cryotrap is particularly preferable because water can be efficiently exhausted.

[0339] The heating mechanism 2813 may be, for example, a heating mechanism that uses a resistance heating element or the like for heating. Alternatively, it may be a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. GRTA performs heating processing using high-temperature gas. An inert gas is used as the gas.

[0340] The gas supply source 2801 may be connected to a refiner via a mass flow controller. It is preferable to use a gas with a dew point of -80° C. or less, preferably -100° C. or less. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) may be used.

[0341] The dielectric plate 2809 may be made of, for example, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria). A separate protective layer may be formed on the surface of the dielectric plate 2809. The protective layer may be made of magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, or yttrium oxide. The dielectric plate 2809 is exposed to a particularly high-density region of the high-density plasma 2810 described later, and thus damage to the dielectric plate 2809 can be mitigated by providing a protective layer. As a result, an increase in particles during processing can be suppressed.

[0342] The high frequency generator 2803 has a function of generating microwaves of, for example, 0.3 GHz to 3.0 GHz, 0.7 GHz to 1.1 GHz, or 2.2 GHz to 2.8 GHz. The microwaves generated by the high frequency generator 2803 are transmitted to the mode converter 2805 via the waveguide 2804. In the mode converter 2805, the microwaves transmitted as TE mode are converted to TEM mode. Then, the microwaves are transmitted to the slot antenna plate 2808 via the waveguide 2807. The slot antenna plate 2808 is provided with a plurality of slot holes, and the microwaves pass through the slot holes and the dielectric plate 2809. Then, an electric field is generated below the dielectric plate 2809, and a high density plasma 2810 can be generated. In the high density plasma 2810, ions and radicals according to the gas species supplied from the gas supply source 2801 exist. For example, oxygen radicals and the like exist.

[0343] At this time, the film on the substrate 2811 can be modified by the ions and radicals generated by the high density plasma 2810. It may be preferable to apply a bias to the substrate 2811 side using a high frequency power supply 2816. For the high frequency power supply 2816, an RF (Radio Frequency) power supply with a frequency of, for example, 13.56 MHz or 27.12 MHz may be used. By applying a bias to the substrate side, the ions in the high density plasma 2810 can be efficiently delivered to the depths of the openings of the film on the substrate 2811.

[0344] For example, oxygen can be introduced from a gas supply source 2801 into the chamber 2706b or the chamber 2706c to perform oxygen radical treatment using a high density plasma 2810.

[0345] Next, chamber 2706a and chamber 2706d will be described with reference to the schematic cross-sectional view shown in FIG.

[0346] The chamber 2706a and the chamber 2706d are chambers capable of irradiating the object to be treated with electromagnetic waves, for example. The only difference between the chamber 2706a and the chamber 2706d is the type of electromagnetic waves. As the other configurations are largely common, they will be described together below.

[0347] The chamber 2706a and the chamber 2706d each have one or more lamps 2820, a substrate holder 2825, a gas inlet 2823, and an exhaust port 2830. In addition, a gas supply source 2821, a valve 2822, a vacuum pump 2828, and a valve 2829 are provided outside the chamber 2706a and the chamber 2706d.

[0348] The gas supply source 2821 is connected to a gas inlet 2823 via a valve 2822. The vacuum pump 2828 is connected to an exhaust port 2830 via a valve 2829. The lamp 2820 is disposed facing a substrate holder 2825. The substrate holder 2825 has a function of holding a substrate 2824. The substrate holder 2825 also has an internal heating mechanism 2826 and has a function of heating the substrate 2824.

[0349] A light source having a function of emitting electromagnetic waves such as visible light or ultraviolet light may be used as the lamp 2820. For example, a light source having a function of emitting electromagnetic waves having a peak wavelength of 10 nm to 2500 nm, 500 nm to 2000 nm, or 40 nm to 340 nm may be used.

[0350] For example, lamp 2820 may be a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp.

[0351] For example, the electromagnetic waves emitted from the lamps 2820 can be absorbed in part or in whole by the substrate 2824 to modify a film on the substrate 2824. For example, defects can be generated or reduced, or impurities can be removed. If the process is performed while the substrate 2824 is heated, defects can be generated or reduced, or impurities can be removed efficiently.

[0352] Alternatively, for example, the substrate holder 2825 may be heated by electromagnetic waves emitted from the lamps 2820, thereby heating the substrate 2824. In that case, the substrate holder 2825 does not need to have the heating mechanism 2826 inside.

[0353] For the vacuum pump 2828, refer to the description of the vacuum pump 2817. For the heating mechanism 2826, refer to the description of the heating mechanism 2813. For the gas supply source 2821, refer to the description of the gas supply source 2801.

[0354] The microwave processing device that can be used in this embodiment is not limited to the above. A microwave processing device 2900 shown in FIG. 27 can be used. The microwave processing device 2900 has a quartz tube 2901, an exhaust port 2819, a gas supply source 2801, a valve 2802, a high-frequency generator 2803, a waveguide 2804, a gas pipe 2806, a vacuum pump 2817, and a valve 2818. The microwave processing device 2900 also has a substrate holder 2902 that holds a plurality of substrates 2811 (2811_1 to 2811_n, n is an integer of 2 or more) in the quartz tube 2901. The microwave processing device 2900 may also have a heating means 2903 on the outside of the quartz tube 2901.

[0355] Microwaves generated by a high frequency generator 2803 are irradiated to a substrate provided in a quartz tube 2901 through a waveguide 2804. A vacuum pump 2817 is connected to an exhaust port 2819 through a valve 2818, and can adjust the pressure inside the quartz tube 2901. A gas supply source 2801 is connected to a gas pipe 2806 through a valve 2802, and can introduce a desired gas into the quartz tube 2901. A heating means 2903 can heat a substrate 2811 in the quartz tube 2901 to a desired temperature. Alternatively, the heating means 2903 may heat a gas supplied from the gas supply source 2801. The microwave processing device 2900 can simultaneously perform a heat treatment and a microwave treatment on the substrate 2811. Also, a microwave treatment can be performed after the substrate 2811 is heated. Also, a heat treatment can be performed on the substrate 2811 after the microwave treatment.

[0356] The substrates 2811_1 to 2811_n may all be processing substrates for forming semiconductor devices or memory devices, or some of the substrates may be dummy substrates. For example, the substrates 2811_1 and 2811_n may be dummy substrates, and the substrates 2811_2 to 2811_n-1 may be processing substrates. Also, the substrates 2811_1, 2811_2, 2811_n-1, and 2811_n may be dummy substrates, and the substrates 2811_3 to 2811_n-2 may be processing substrates. By using a dummy substrate, a plurality of processing substrates are uniformly processed during microwave processing or heat processing, and the variation between the processing substrates can be reduced, which is preferable. For example, by arranging a dummy substrate on the processing substrate closest to the high frequency generator 2803 and the waveguide 2804, the processing substrate can be prevented from being directly exposed to microwaves, which is preferable.

[0357] By using the above manufacturing apparatus, it is possible to modify the film while suppressing the inclusion of impurities in the processed object.

[0358] <Modification 1 of the semiconductor device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 2A to 2C. FIG.

[0359] Fig. 2A shows a top view of the semiconductor device. Fig. 2B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 2A. Fig. 2C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 2A. Some elements are omitted from the top view of Fig. 2A for clarity.

[0360] 2A to 2C, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration example of semiconductor device> are denoted by the same reference numerals. Note that, in this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the materials constituting the semiconductor device.

[0361] The semiconductor device shown in Figures 2A to 2C is a modified example of the semiconductor device shown in Figures 1A to 1C. The semiconductor device shown in Figures 2A to 2C differs from the semiconductor device shown in Figures 1A to 1C in that it does not have an insulator 252 but has an oxide 230c. As shown in Figures 17A to 17C in <Method of manufacturing a semiconductor device>, an insulating film that becomes the insulator 252 is formed and anisotropic etching is performed to form the insulator 252, but in this modified example, an oxide film that becomes the oxide 230c is formed.

[0362] The oxide film that becomes the oxide 230c can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. The oxide film that becomes the oxide 230c is preferably formed by ALD because a film of uniform thickness can be formed even in a groove or opening with a large aspect ratio. In addition, the PEALD is preferably formed because the oxide film that becomes the oxide 230c can be formed at a lower temperature than the thermal ALD. In this embodiment, the oxide film that becomes the oxide 230c is formed by sputtering.

[0363] Oxide 230c is formed by polishing, by CMP processing, the oxide film that will become oxide 230c, insulating film 250A, insulating film 250B, the conductive film that will become conductor 260a, and the conductive film that will become conductor 260b until insulator 280 is exposed.

[0364] 2B, the oxide 230c is provided in contact with at least the end of the conductor 242a and the end of the conductor 242b, and therefore can suppress oxidation of the conductor 242a and the conductor 242b. The thickness of the oxide 230c is preferably 0.5 nm to 5 nm, and more preferably 1 nm to 3 nm.

[0365] <Modification 2 of Semiconductor Device> An example of a semiconductor device which is one embodiment of the present invention will be described below with reference to FIGS. 3A to 3C. FIG.

[0366] Fig. 3A shows a top view of the semiconductor device. Fig. 3B is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in Fig. 3A. Fig. 3C is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in Fig. 3A. Some elements are omitted from the top view of Fig. 3A for clarity.

[0367] 3A to 3C, structures having the same functions as those of the structures constituting the semiconductor device shown in <Configuration example of semiconductor device> are denoted by the same reference numerals. Note that, in this section, the materials described in detail in <Configuration example of semiconductor device> can be used as the materials constituting the semiconductor device.

[0368] The semiconductor device shown in Figures 3A to 3C is a modified example of the semiconductor device shown in Figures 1A to 1C. The semiconductor device shown in Figures 3A to 3C is different from the semiconductor device shown in Figures 1A to 1C in the shape of the insulator 224 of the transistor 200.

[0369] As shown in FIGS. 3A to 3C , the transistor 200 includes an insulator 216 on an insulator 214, conductors 205 (conductors 205a, 205b, and 205c) disposed so as to be embedded in the insulator 214 or the insulator 216, an insulator 222 on the insulator 216 and on the conductor 205, an insulator 224 on the insulator 222, an insulator 219 on the insulator 224, and an oxide 230 (oxides 230a, conductor 242a and conductor 242b on insulator 219 and oxide 230, insulator 252 and insulator 250a on oxide 230, insulator 250b on insulator 250a, conductor 260 (conductor 260a and conductor 260b) located on insulator 250b and overlapping with part of oxide 230, and insulator 272 arranged on insulator 219 and conductor 242 (conductor 242a and conductor 242b).

[0370] Moreover, the conductor 242 has a region that contacts a part of the upper surface of the oxide 230b. Moreover, the insulator 252 contacts at least the side surface of the conductor 242. Here, as shown in FIG. 3B and FIG. 3C, the upper surface of the conductor 260 is disposed so as to substantially coincide with the upper surfaces of the insulator 250 and the insulator 280. Moreover, the insulator 282 contacts the upper surfaces of the conductor 260, the insulator 250, and the insulator 280.

[0371] Hereinafter, steps different from those in the method for manufacturing a semiconductor device shown in FIGS. 1A to 1C and described in <Method for Manufacturing a Semiconductor Device> will be described.

[0372] An insulator 224 is formed on the insulator 222, and an insulator 219 is formed on the insulator 224. Next, an opening is formed in the insulator 219 by lithography, reaching the insulator 224. The opening may be formed by wet etching, but dry etching is preferable for fine processing. After the opening is formed, an oxide film 230A and an oxide film 230B are formed in this order. For the method and material of the oxide film 230A and the oxide film 230B, refer to <Method of manufacturing a semiconductor device>.

[0373] Next, heat treatment is preferably performed. Regarding the conditions of the heat treatment, refer to <Method for manufacturing a semiconductor device>.

[0374] Next, the oxide film 230A and the oxide film 230B are partially removed by performing a CMP process to expose the insulator 219. As a result, the oxide film 230A and the oxide film 230B remain only in the openings, and the oxide 230a and the oxide 230b are formed, respectively. This allows the oxide 230 to be formed with a flat upper surface. Note that the CMP process may remove a portion of the insulator 219.

[0375] By forming the oxide 230 without using a dry etching method in this way, it is possible to suppress the generation of contaminants resulting from the reaction product between the etching gas and the oxide 230. In addition, since an etching mask is not used, there is no occurrence of shrinkage or recession of the etching mask during etching, and therefore the deviation from the design value can be suppressed. This is therefore advantageous for miniaturization. For other manufacturing methods, please refer to <Manufacturing method of semiconductor device>.

[0376] <Applications of semiconductor devices> 28A and 28B, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention, which is different from those described in the above <Structural example of semiconductor device> and the above <Modification of semiconductor device>, will be described below. Note that in the semiconductor device shown in FIG. 28A and FIG. 28B, structures having the same functions as those of the semiconductor device shown in <Structural example of semiconductor device> (see FIG. 1A to FIG. 1C) are denoted by the same reference numerals. Note that in this section, the materials described in detail in <Structural example of semiconductor device> can be used as the materials for forming the transistor 200.

[0377] 28A and 28B show a configuration in which a plurality of transistors 200_1 to 200_n are encapsulated by an insulator 283 and an insulator 214. Note that although the transistors 200_1 to 200_n appear to be aligned in the channel length direction in FIGS. 28A and 28B, this is not the only possible arrangement. The transistors 200_1 to 200_n may be aligned in the channel width direction or may be arranged in a matrix. Furthermore, the transistors 200_1 to 200_n may be arranged without any regularity depending on the design.

[0378] 28A, a portion where the insulator 283 and the insulator 214 contact each other (hereinafter, may be referred to as a sealing portion 265) is formed outside the plurality of transistors 200_1 to 200_n. The sealing portion 265 is formed so as to surround the plurality of transistors 200_1 to 200_n. With this structure, the plurality of transistors 200_1 to 200_n can be enclosed by the insulator 283 and the insulator 214. Thus, a plurality of transistor groups surrounded by the sealing portion 265 are provided on the substrate.

[0379] Also, dicing lines (which may be called scribe lines, division lines, or cutting lines) may be provided overlapping the sealing portion 265. Since the substrate is divided along the dicing lines, a group of transistors surrounded by the sealing portion 265 is taken out as one chip.

[0380] In addition, although Fig. 28A shows an example in which the plurality of transistors 200_1 to 200_n are surrounded by one sealing portion 265, the present invention is not limited to this. As shown in Fig. 28B, the plurality of transistors 200_1 to 200_n may be surrounded by a plurality of sealing portions. In Fig. 28B, the plurality of transistors 200_1 to 200_n are surrounded by a sealing portion 265a and further surrounded by an outer sealing portion 265b.

[0381] In this manner, by using a structure in which the multiple transistors 200_1 to 200_n are surrounded by multiple sealing portions, the number of areas in which the insulator 283 and the insulator 214 are in contact with each other increases, thereby improving the adhesion between the insulator 283 and the insulator 214. This makes it possible to more reliably seal the multiple transistors 200_1 to 200_n.

[0382] In this case, a dicing line may be provided so as to overlap sealing portion 265a or sealing portion 265b, or a dicing line may be provided between sealing portion 265a and sealing portion 265b.

[0383] Note that although the transistor illustrated in FIGS. 28A and 28B has a structure in which the insulator 283 and the insulator 214 are in contact with each other, the insulator 283 and the insulator 212 may be in contact with each other.

[0384] According to one embodiment of the present invention, a semiconductor device with little variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with large on-state current can be provided. According to one embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0385] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0386] (Embodiment 2) In this embodiment mode, one mode of a semiconductor device will be described with reference to FIGS.

[0387] [Storage device 1] 29 illustrates an example of a semiconductor device (memory device) according to one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, a transistor 200 is provided above a transistor 300, and a capacitor 100 is provided above the transistors 300 and 200. Note that the transistor 200 described in the above embodiment can be used as the transistor 200.

[0388] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be retained for a long time by using the transistor 200 in a memory device. In other words, a refresh operation is not required or the frequency of the refresh operation is extremely low, so that the power consumption of the memory device can be sufficiently reduced.

[0389] 29, a wiring 1001 is electrically connected to a source of a transistor 300, and a wiring 1002 is electrically connected to a drain of the transistor 300. A wiring 1003 is electrically connected to one of a source and a drain of the transistor 200, a wiring 1004 is electrically connected to a first gate of the transistor 200, and a wiring 1006 is electrically connected to a second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are electrically connected to one electrode of the capacitor 100, and a wiring 1005 is electrically connected to the other electrode of the capacitor 100.

[0390] Moreover, the memory device shown in FIG. 29 can be arranged in a matrix to form a memory cell array.

[0391] <Transistor 300> The transistor 300 is provided on a substrate 311 and includes a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 formed of a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b functioning as a source region or a drain region. The transistor 300 may be either a p-channel type or an n-channel type.

[0392] Here, in the transistor 300 shown in FIG. 29, a semiconductor region 313 (a part of a substrate 311) in which a channel is formed has a convex shape. A conductor 316 is provided so as to cover the side and top surface of the semiconductor region 313 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN type transistor because it uses a convex portion of a semiconductor substrate. Note that an insulator that contacts the upper portion of the convex portion and functions as a mask for forming the convex portion may be provided. Note that, although a case where a convex portion is formed by processing a part of a semiconductor substrate has been shown here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

[0393] Note that the transistor 300 illustrated in FIG. 29 is just an example, and the present invention is not limited to this structure. An appropriate transistor may be used depending on the circuit configuration or driving method.

[0394] <Capacitive element 100> The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric. Here, the insulator 130 is preferably an insulator that can be used as the insulator 286 described in the above embodiment.

[0395] For example, the conductor 112 and the conductor 110 over the conductor 246 can be formed at the same time. Note that the conductor 112 functions as a plug or a wiring electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

[0396] 29, the conductor 112 and the conductor 110 are shown to have a single layer structure, but are not limited to this configuration and may have a laminated structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0397] The insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer.

[0398] For example, it is preferable to use a laminated structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitance element 100 can ensure sufficient capacitance by having an insulator with high dielectric constant (high-k), and the capacitance element 100 can have improved dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitance element 100.

[0399] Examples of high dielectric constant (high-k) material insulators (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.

[0400] On the other hand, materials with high dielectric strength (materials with low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide or resin with voids, etc.

[0401] <Wiring layer> Between each structure, a wiring layer having an interlayer film, wiring, plugs, etc. may be provided. Also, a plurality of wiring layers may be provided according to the design. Here, a conductor having a function as a plug or wiring may be collectively given the same symbol as a plurality of structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.

[0402] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film over the transistor 300. A conductor 328, a conductor 330, and the like that are electrically connected to the capacitor 100 or the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326. The conductor 328 and the conductor 330 function as plugs or wirings.

[0403] The insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath. For example, the top surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to enhance flatness.

[0404] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in Fig. 29, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. Furthermore, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

[0405] Similarly, a conductor 218, a conductor constituting the transistor 200 (conductor 205), and the like are embedded in the insulators 210, 212, 214, and 216. Note that the conductor 218 functions as a plug or wiring electrically connected to the capacitor 100 or the transistor 300. Furthermore, an insulator 150 is provided over the conductor 120 and the insulator 130.

[0406] Here, similarly to the insulator 241 shown in the above embodiment, the insulator 217 is provided in contact with the side surface of the conductor 218 functioning as a plug. The insulator 217 is provided in contact with the inner wall of the opening formed in the insulators 210, 212, 214, and 216. In other words, the insulator 217 is provided between the conductor 218 and the insulators 210, 212, 214, and 216. Note that the conductor 205 can be formed in parallel with the conductor 218, and therefore the insulator 217 may be formed in contact with the side surface of the conductor 205.

[0407] As the insulator 217, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator 217 is provided in contact with the insulator 210, the insulator 212, the insulator 214, and the insulator 222, it is possible to prevent impurities such as water or hydrogen from the insulator 210 or the insulator 216 from being mixed into the oxide 230 through the conductor 218. In particular, silicon nitride is preferable because it has a high barrier property against hydrogen. In addition, it is possible to prevent oxygen contained in the insulator 210 or the insulator 216 from being absorbed by the conductor 218.

[0408] The insulator 217 can be formed by a method similar to that of the insulator 241. For example, a silicon nitride film is formed by a PEALD method, and an opening reaching the conductor 356 is formed by anisotropic etching.

[0409] Examples of insulators that can be used as the interlayer film include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.

[0410] For example, by using a material with a low dielectric constant for the insulator that functions as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select a material according to the function of the insulator.

[0411] For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, etc. preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably has silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, silicon oxide having voids, or resin. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having voids, and resin. Silicon oxide and silicon oxynitride are thermally stable, so that a laminated structure that is thermally stable and has a low relative dielectric constant can be obtained by combining them with a resin. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.

[0412] Furthermore, when a transistor using an oxide semiconductor is surrounded by an insulator that has a function of suppressing the permeation of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stabilized. Therefore, the insulators 214, 212, and 350 can be made of insulators that have a function of suppressing the permeation of oxygen and impurities such as hydrogen.

[0413] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum may be used in a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride may be used.

[0414] Conductors that can be used for wiring and plugs include materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, etc. Also, semiconductors with high electrical conductivity, typified by polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0415] For example, the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, etc. can be formed of a single layer or a stack of conductive materials such as metal materials, alloy materials, metal nitride materials, or metal oxide materials formed from the above materials. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to form the conductor from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.

[0416] <Wiring or plug of layer provided with oxide semiconductor> Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

[0417] 29, for example, an insulator 241 may be provided between the insulator 224 and the insulator 280 having excess oxygen and the conductor 240. By providing the insulator 241 in contact with the insulator 222, the insulator 282, and the insulator 283, the insulator 224 and the transistor 200 can be sealed with an insulator having barrier properties.

[0418] In other words, the insulator 241 can prevent excess oxygen contained in the insulator 224 and the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can prevent hydrogen, which is an impurity, from diffusing into the transistor 200 through the conductor 240.

[0419] As the insulator 241, an insulating material having a function of suppressing the diffusion of impurities such as water or hydrogen, and oxygen, may be used. For example, it is preferable to use silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide. In particular, silicon nitride is preferable because it has high barrier properties against hydrogen. In addition, other metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide may be used.

[0420] As described in the above embodiment, the transistor 200 may be sealed with the insulators 212, 214, 282, and 283. Such a structure can reduce the intrusion of hydrogen contained in the insulators 274, 150, and the like into the insulator 280 and the like.

[0421] Here, the conductor 240 penetrates the insulator 283 and the insulator 282, and the conductor 218 penetrates the insulator 214 and the insulator 212, but as described above, the insulator 241 is provided in contact with the conductor 240, and the insulator 217 is provided in contact with the conductor 218. This makes it possible to reduce hydrogen that is mixed into the inside of the insulators 212, 214, 282, and 283 through the conductors 240 and 218. In this way, the transistor 200 is sealed with the insulators 212, 214, 282, 283, 241, and 217, making it possible to reduce impurities such as hydrogen contained in the insulator 274, etc., from the outside.

[0422] <Dicing line> In the following, a dicing line (sometimes called a scribe line, a dividing line, or a cutting line) that is provided when a large-area substrate is divided into individual semiconductor elements to extract multiple semiconductor devices in chip form will be described. As a dividing method, for example, first, grooves (dicing lines) for dividing the semiconductor elements are formed in the substrate, and then the substrate is cut along the dicing lines to divide (split) the substrate into multiple semiconductor devices.

[0423] 29, for example, it is preferable to design the region where the insulator 283 and the insulator 214 contact each other so as to overlap the dicing line. That is, openings are provided in the insulators 282, 280, 272, 224, 222, and 216 near the region that will become the dicing line provided on the outer edge of the memory cell having the multiple transistors 200.

[0424] That is, insulator 214 and insulator 283 are in contact with each other through openings provided in insulators 282 , 280 , 272 , 224 , 222 , and 216 .

[0425] Also, for example, openings may be provided in the insulator 282, the insulator 280, the insulator 272, the insulator 224, the insulator 222, the insulator 216, and the insulator 214. With this configuration, the insulator 212 and the insulator 283 are in contact with each other through the openings provided in the insulator 282, the insulator 280, the insulator 272, the insulator 224, the insulator 222, the insulator 216, and the insulator 214. At this time, the insulator 212 and the insulator 283 may be formed using the same material and the same method. By providing the insulator 212 and the insulator 283 using the same material and the same method, adhesion can be improved. For example, it is preferable to use silicon nitride.

[0426] With this structure, the transistor 200 can be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283. At least one of the insulator 212, the insulator 214, the insulator 282, and the insulator 283 has a function of suppressing diffusion of oxygen, hydrogen, and water, and therefore, even if the substrate is divided into a plurality of chips by dividing the substrate into each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as hydrogen or water can be prevented from entering from the side direction of the divided substrate and diffusing into the transistor 200.

[0427] This structure can prevent excess oxygen in the insulator 280 and the insulator 224 from diffusing to the outside. Therefore, the excess oxygen in the insulator 280 and the insulator 224 is efficiently supplied to the oxide in which a channel is formed in the transistor 200. The oxygen can reduce oxygen vacancies in the oxide in which a channel is formed in the transistor 200. As a result, the oxide in which a channel is formed in the transistor 200 can be an oxide semiconductor with low density of defect states and stable characteristics. That is, fluctuations in the electrical characteristics of the transistor 200 can be suppressed and reliability can be improved.

[0428] In the memory device shown in Fig. 29, the shape of the capacitor 100 is a planar type, but the memory device shown in this embodiment is not limited to this. For example, the shape of the capacitor 100 may be a cylindrical type as shown in Fig. 30. In the memory device shown in Fig. 30, the configuration below the insulator 150 is similar to that of the semiconductor device shown in Fig. 29.

[0429] 30 includes an insulator 150 on an insulator 130, an insulator 142 on the insulator 150, a conductor 115 disposed in an opening formed in the insulator 150 and the insulator 142, an insulator 145 on the conductor 115 and the insulator 142, a conductor 125 on the insulator 145, and an insulator 152 on the conductor 125 and the insulator 145. Here, at least a portion of the conductor 115, the insulator 145, and the conductor 125 are disposed in the opening formed in the insulator 150 and the insulator 142.

[0430] The conductor 115 functions as the lower electrode of the capacitance element 100, the conductor 125 functions as the upper electrode of the capacitance element 100, and the insulator 145 functions as the dielectric of the capacitance element 100. The capacitance element 100 has a configuration in which the upper electrode and the lower electrode face each other across the dielectric not only on the bottom surface but also on the side surface in the openings of the insulators 150 and 142, and the capacitance per unit area can be increased. Therefore, the deeper the opening is, the larger the capacitance of the capacitance element 100 can be. Increasing the capacitance per unit area of ​​the capacitance element 100 in this way can promote miniaturization or high integration of semiconductor devices.

[0431] The insulator 152 may be made of an insulator that can be used for the insulator 280. The insulator 142 preferably functions as an etching stopper when forming an opening in the insulator 150, and may be made of an insulator that can be used for the insulator 214.

[0432] The shape of the openings formed in the insulator 150 and the insulator 142 when viewed from above may be a rectangle, a polygon other than a rectangle, a polygon with curved corners, or a circle including an ellipse. Here, it is preferable that the area of ​​the opening overlapping with the transistor 200 is large when viewed from above. With such a configuration, the occupation area of ​​a semiconductor device including the capacitor 100 and the transistor 200 can be reduced.

[0433] The conductor 115 is disposed in contact with the insulator 142 and an opening formed in the insulator 150. The upper surface of the conductor 115 preferably approximately coincides with the upper surface of the insulator 142. The lower surface of the conductor 115 is in contact with the conductor 110 through the opening of the insulator 130. The conductor 115 is preferably formed by an ALD method, a CVD method, or the like, and may be, for example, a conductor that can be used for the conductor 205.

[0434] The insulator 145 is disposed so as to cover the conductor 115 and the insulator 142. For example, the insulator 145 is preferably formed by an ALD method, a CVD method, or the like. The insulator 145 may be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer. For example, the insulator 145 can be an insulating film stacked in this order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0435] Moreover, it is preferable to use a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material for the insulator 145. Alternatively, a laminated structure of a material with high dielectric strength and a material with high dielectric constant (high-k) may be used.

[0436] Examples of insulators made of high dielectric constant (high-k) materials (materials with high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium. By using such high-k materials, the capacitance of the capacitance element 100 can be sufficiently secured even if the insulator 145 is made thick. By making the insulator 145 thick, the leakage current occurring between the conductor 115 and the conductor 125 can be suppressed.

[0437] On the other hand, materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with vacancies, and resin. For example, silicon nitride (SiN x ), silicon oxide (SiO x ), and silicon nitride (SiN x ) can be used. Alternatively, an insulating film can be used in which zirconium oxide, silicon oxide formed by the ALD method, and zirconium oxide are laminated in this order. By using such an insulator with high dielectric strength, the dielectric strength is improved and electrostatic breakdown of the capacitor element 100 can be suppressed.

[0438] The conductor 125 is disposed so as to fill the openings formed in the insulator 142 and the insulator 150. The conductor 125 is electrically connected to the wiring 1005 via the conductor 140 and the conductor 153. The conductor 125 is preferably formed by an ALD method, a CVD method, or the like, and may be formed using a conductor that can be used for the conductor 205, for example.

[0439] The conductor 153 is provided over the insulator 154 and is covered with the insulator 156. The conductor 153 may be any conductor that can be used for the conductor 112, and the insulator 156 may be any insulator that can be used for the insulator 152. Here, the conductor 153 is in contact with the top surface of the conductor 140 and functions as a terminal of the capacitor 100, the transistor 200, or the transistor 300.

[0440] [Storage device 2] An example of a semiconductor device (memory device) according to one embodiment of the present invention is illustrated in FIGS. 31A and 31B.

[0441] <Memory device configuration example 1> Fig. 31A is a cross-sectional view of a semiconductor device including a memory device 290. The memory device 290 shown in Fig. 31A includes a capacitor device 292 in addition to the transistor 200 shown in Fig. 1A to Fig. 1C. Fig. 31A corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0442] The capacitance device 292 has a conductor 242b, an insulator 272 provided in contact with the upper surface of the conductor 242b and the side surface of the conductor 242b, and a conductor 294 on the insulator 272. That is, the capacitance device 292 constitutes an MIM (Metal-Insulator-Metal) capacitance. Note that one of a pair of electrodes of the capacitance device 292, i.e., the conductor 242b, can also serve as a source electrode of a transistor. Also, the dielectric layer of the capacitance device 292 can also serve as a protective layer provided in the transistor, i.e., the insulator 272. Therefore, a part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitance device 292, so that a semiconductor device with high productivity can be obtained. Also, one of a pair of electrodes of the capacitance device 292, i.e., the conductor 242b, also serves as a source electrode of the transistor, so that the area in which the transistor and the capacitance device are arranged can be reduced.

[0443] Note that the conductor 294 may be made of, for example, a material that can be used for the conductor 242.

[0444] <Memory device configuration example 2> Fig. 31B is a cross-sectional view of a semiconductor device having a memory device 290 having a structure different from that shown in Fig. 31A. The memory device 290 shown in Fig. 31B has a capacitance device 292 in addition to the transistor 200 shown in Figs. 1A to 1C. Here, unlike the capacitance device 292 shown in Fig. 31A, a part of the capacitance device 292 shown in Fig. 31B is provided in an opening formed in the insulator 280 and the insulator 272. Note that Fig. 31B corresponds to a cross-sectional view of the transistor 200 in the channel length direction.

[0445] The capacitance device 292 has a conductor 242b, an insulator 293 provided on the conductor 242b, and a conductor 294 provided on the insulator 293. Here, the insulator 293 and the conductor 294 are disposed in an opening formed in the insulator 280 and the insulator 272. The insulator 293 is provided in contact with the bottom surface and side wall of the opening. That is, the insulator 293 is in contact with the upper surface of the conductor 242b, the side surface of the insulator 272, and the side surface of the insulator 280. The insulator 293 is provided so as to form a recess along the shape of the opening. The conductor 294 is disposed in contact with the upper surface and side surface of the insulator 293 so as to fill the recess. Note that the height of the upper surfaces of the insulator 293 and the conductor 294 may be approximately the same as the height of the upper surfaces of the insulator 280, the insulator 250, and the conductor 260.

[0446] Here, the conductor 242b functions as a lower electrode of the capacitance device 292, the conductor 294 functions as an upper electrode of the capacitance device 292, and the insulator 293 functions as a dielectric of the capacitance device 292. In this manner, the capacitance device 292 constitutes an MIM capacitance. Note that one of the pair of electrodes of the capacitance device 292, i.e., the conductor 242b, can also serve as a source electrode of a transistor. Therefore, a part of the manufacturing process of the transistor can be used in the manufacturing process of the capacitance device 292, so that a semiconductor device with high productivity can be obtained. In addition, since the insulator 293 can be provided separately from the configuration of the transistor 200, the structure and material of the insulator 293 can be appropriately selected according to the performance required for the capacitance device 292. In addition, since one of the pair of electrodes of the capacitance device 292, i.e., the conductor 242b, also serves as a source electrode of the transistor, it is possible to reduce the area in which the transistor and the capacitance device are arranged.

[0447] The insulator 293 is preferably made of a high-dielectric constant (high-k) material. Examples of insulators of high-dielectric constant (high-k) materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, or nitrides having silicon and hafnium. Alternatively, the insulator 293 may be made of a laminate of films of these high-dielectric constant materials. For example, the insulator 293 may be made of an insulating film laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide.

[0448] The conductor 294 may be made of, for example, a material that can be used for the conductor 260. The conductor 294 may have a layered structure similar to the conductor 260.

[0449] 19. The insulator 293 and the conductor 294 can be formed in a manner similar to that used for forming the insulator 250 and the conductor 260. That is, openings are formed in the insulator 280 and the insulator 272, a laminated film that will become the insulator 293 and the conductor 294 is formed so as to fill the openings, and a portion of the laminated film is removed using CMP processing to form the insulator 293 and the conductor 294.

[0450] <Modifications of memory device> Hereinafter, an example of a semiconductor device having a transistor 200 according to one embodiment of the present invention and a capacitance device 292, which is different from that shown in the above <Configuration example 1 of memory device>, will be described with reference to FIGS. 32A, 32B, 33, and 34. Note that in the semiconductor devices shown in FIGS. 32A, 32B, 33, and 34, structures having the same functions as those of the semiconductor device (see FIG. 31A) shown in the above embodiment and <Configuration example 1 of memory device> are denoted by the same reference numerals. Note that in this section, the materials for the transistor 200 and the capacitance device 292 can be the materials described in detail in the above embodiment and <Configuration example 1 of memory device>. Note that in FIGS. 32A, 32B, 33, and 34, the memory device shown in FIG. 31A is used as the memory device, but the present invention is not limited thereto. For example, the memory device shown in FIG. 31B may be used.

[0451] <<Memory Device Variation 1>> Below, an example of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitor device 292a, and a capacitor device 292b according to one embodiment of the present invention will be described with reference to FIG. 32A.

[0452] 32A is a cross-sectional view in the channel length direction of a semiconductor device 600 including a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b. Here, the capacitance device 292a includes a conductor 242a, an insulator 272 in contact with an upper surface of the conductor 242a and a side surface of the conductor 242a, and a conductor 294a on the insulator 272. The capacitance device 292b includes a conductor 242b, an insulator 272 in contact with an upper surface of the conductor 242b and a side surface of the conductor 242b, and a conductor 294b on the insulator 272.

[0453] As shown in FIG. 32A, the semiconductor device 600 has a linear symmetrical configuration with the dashed line A3-A4 as the axis of symmetry. One of the source electrode or drain electrode of the transistor 200a and one of the source electrode or drain electrode of the transistor 200b are both served by the conductor 242c. In addition, the conductor 246 functioning as wiring and the connection between the transistor 200a and the transistor 200b are also served by the conductor 240 functioning as a plug. In this way, by configuring the two transistors, the two capacitance devices, and the connections between the wiring and the plugs as described above, a semiconductor device that can be miniaturized or highly integrated can be provided.

[0454] The configuration and effects of each of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b can be referred to the configuration example of the semiconductor device shown in FIG. 31A.

[0455] <<Memory Device Modification 2>> In the above, the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b are given as examples of the configuration of the semiconductor device, but the semiconductor device shown in this embodiment is not limited to this. For example, as shown in FIG. 32B, a configuration may be adopted in which a semiconductor device 600 and a semiconductor device having a similar configuration to the semiconductor device 600 are connected via a capacitance portion. In this specification, a semiconductor device having the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b is referred to as a cell. For the configurations of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b, the above description of the transistor 200a, the transistor 200b, the capacitance device 292a, and the capacitance device 292b can be referred to.

[0456] FIG. 32B is a cross-sectional view of a semiconductor device 600 having a transistor 200a, a transistor 200b, a capacitance device 292a, and a capacitance device 292b, and a cell having a similar configuration to the semiconductor device 600, connected via a capacitance portion.

[0457] As shown in FIG. 32B, the conductor 294b functioning as one electrode of the capacitance device 292b of the semiconductor device 600 is configured to also serve as one electrode of the capacitance device of the semiconductor device 601 having the same configuration as the semiconductor device 600. Although not shown, the conductor 294a functioning as one electrode of the capacitance device 292a of the semiconductor device 600 also serves as one electrode of the capacitance device of the semiconductor device adjacent to the left side of the semiconductor device 600, that is, in FIG. 32B, in the A1 direction. The same configuration is also applied to the right side of the semiconductor device 601, that is, in FIG. 32B, in the A2 direction. That is, a cell array (also called a memory device layer) can be configured. By configuring the cell array in this way, the interval between adjacent cells can be reduced, so that the projection area of ​​the cell array can be reduced, and high integration is possible. Also, by arranging the cell array configuration shown in FIG. 32B in a matrix, a matrix-shaped cell array can be configured.

[0458] As described above, by forming transistor 200a, transistor 200b, capacitance device 292a, and capacitance device 292b in the configuration shown in this embodiment, the cell area can be reduced, and miniaturization or high integration of a semiconductor device having a cell array can be achieved.

[0459] Moreover, the cell array may be configured not only in a plane but also in a stacked configuration. Fig. 33 shows a cross-sectional view of a configuration in which the cell array 610 is stacked in n layers. As shown in Fig. 33, by stacking a plurality of cell arrays (cell arrays 610_1 to 610_n), the cells can be integrated and arranged without increasing the occupied area of ​​the cell array. In other words, a 3D cell array can be configured.

[0460] <Memory Device Modification 3> FIG. 34 shows an example in which a memory unit 470 includes a transistor layer 413 including a transistor 200T and four memory device layers 415 (memory device layers 415_1 to 415_4).

[0461] Each of the memory device layers 415_1 to 415_4 includes a plurality of memory devices 420.

[0462] The memory device 420 is electrically connected to a memory device 420 in a different memory device layer 415 and a transistor 200T in a transistor layer 413 via a conductor 424 and a conductor 205.

[0463] The memory unit 470 is sealed by the insulator 212, the insulator 214, the insulator 282, and the insulator 283 (hereinafter, for convenience, this is referred to as a sealing structure). The insulator 274 is provided around the insulator 283. Furthermore, the conductor 440 is provided on the insulator 274, the insulator 283, and the insulator 212, and is electrically connected to the element layer 411.

[0464] Further, an insulator 280 is provided inside the sealing structure. The insulator 280 has a function of releasing oxygen when heated. Alternatively, the insulator 280 has an excess oxygen region.

[0465] Note that the insulators 212 and 283 are preferably made of a material having a high barrier property against hydrogen. The insulators 214 and 282 are preferably made of a material having a function of capturing hydrogen or fixing hydrogen.

[0466] For example, the material having a high barrier property against hydrogen includes silicon nitride, silicon nitride oxide, etc. Furthermore, the material having a function of capturing or fixing hydrogen includes aluminum oxide, hafnium oxide, and oxide containing aluminum and hafnium (hafnium aluminate), etc.

[0467] Note that the crystal structure of the materials used for the insulators 212, 214, 282, and 283 is not particularly limited, and may be an amorphous or crystalline structure. For example, an amorphous aluminum oxide film is preferably used as a material having a function of trapping or fixing hydrogen. Amorphous aluminum oxide may trap and fix a larger amount of hydrogen than aluminum oxide with high crystallinity.

[0468] Here, the following model can be considered for the diffusion of excess oxygen in the insulator 280 and hydrogen in the oxide semiconductor in contact with the insulator 280.

[0469] Hydrogen present in the oxide semiconductor diffuses to other structures through the insulator 280 in contact with the oxide semiconductor. Due to the diffusion of hydrogen, excess oxygen in the insulator 280 reacts with hydrogen in the oxide semiconductor to form OH bonds, and diffuses through the insulator 280. When the hydrogen atom having the OH bond reaches a material (typically the insulator 282) having a function of capturing or fixing hydrogen, the hydrogen atom reacts with an oxygen atom bonded to an atom (e.g., a metal atom, etc.) in the insulator 282, and is captured or fixed in the insulator 282. On the other hand, it is presumed that the oxygen atom of the excess oxygen having the OH bond remains in the insulator 280 as excess oxygen. In other words, there is a high probability that the excess oxygen in the insulator 280 plays a bridging role in the diffusion of hydrogen.

[0470] In order to satisfy the above model, the manufacturing process of the semiconductor device is one of the important factors.

[0471] As an example, the insulator 280 containing excess oxygen is formed in an oxide semiconductor, and then the insulator 282 is formed. After that, heat treatment is preferably performed. Specifically, the heat treatment is performed in an atmosphere containing oxygen, an atmosphere containing nitrogen, or an atmosphere containing a mixture of oxygen and nitrogen at a temperature of 350° C. or higher, preferably 400° C. or higher. The heat treatment time is 1 hour or longer, preferably 4 hours or longer, and more preferably 8 hours or longer.

[0472] By the above heat treatment, hydrogen in the oxide semiconductor can diffuse outward through the insulator 280 and the insulator 282. That is, the absolute amount of hydrogen present in the oxide semiconductor and in the vicinity of the oxide semiconductor can be reduced.

[0473] After the heat treatment, the insulator 283 is formed. The insulator 283 is a material having a high barrier property against hydrogen, and therefore can prevent hydrogen diffused to the outside or hydrogen present on the outside from entering the inside, specifically, the oxide semiconductor or the insulator 280 side.

[0474] Note that the above heat treatment is performed after the insulator 282 is formed, but is not limited thereto. For example, the heat treatment may be performed after the transistor layer 413 is formed or after the memory device layers 415_1 to 415_3 are formed. When hydrogen is diffused outward by the heat treatment, hydrogen is diffused upward or laterally of the transistor layer 413. Similarly, when the heat treatment is performed after the memory device layers 415_1 to 415_3 are formed, hydrogen is diffused upward or laterally.

[0475] By using the above manufacturing process, the insulator 214 and the insulator 283 are bonded to each other, thereby forming the above-described sealing structure.

[0476] As described above, by using the above structure and manufacturing process, a semiconductor device including an oxide semiconductor in which the hydrogen concentration is reduced can be provided. Therefore, a semiconductor device with high reliability can be provided. According to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided.

[0477] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0478] (Embodiment 3) In this embodiment, a transistor using an oxide as a semiconductor (hereinafter may be referred to as an OS transistor) and a memory device including a capacitor (hereinafter may be referred to as an OS memory device) according to one embodiment of the present invention will be described with reference to FIGS. 35A, 35B, and 36A to 36H. The OS memory device is a memory device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

[0479] <Storage device configuration example> 35A shows an example of the configuration of an OS memory device. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0480] The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging the wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

[0481] A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are supplied to the memory device 1400 from the outside as power supply voltages. In addition, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are input from the outside to the memory device 1400. The address signal ADDR is input to a row decoder and a column decoder, and the data signal WDATA is input to a write circuit.

[0482] The control logic circuit 1460 processes control signals (CE, WE, RE) input from the outside to generate control signals for the row decoder and column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to these, and other control signals may be input as necessary.

[0483] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, etc. The number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC in one row, etc.

[0484] 35A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but the present embodiment is not limited to this. For example, as shown in FIG. 35B, the memory cell array 1470 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap the memory cell array 1470 below.

[0485] 36A to 36H will be used to explain examples of the configuration of a memory cell that can be applied to the above-mentioned memory cell MC.

[0486] [DOSRAM] 36A to 36C show circuit configuration examples of a DRAM memory cell. In this specification and the like, a DRAM using a memory cell having one OS transistor and one capacitor may be called a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in FIG. 36A includes a transistor M1 and a capacitor CA. Note that the transistor M1 includes a gate (sometimes called a top gate) and a back gate.

[0487] A first terminal of the transistor M1 is connected to a first terminal of the capacitance element CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, a back gate of the transistor M1 is connected to a wiring BGL, and a second terminal of the capacitance element CA is connected to a wiring LL.

[0488] The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, the wiring LL may be set to a ground potential or a low-level potential. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0489] 36A corresponds to the memory device shown in FIG 31A and FIG 31B. That is, the transistor M1 corresponds to the transistor 200, and the capacitance element CA corresponds to the capacitance device 292.

[0490] The memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may be configured such that the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1472 shown in FIG. 36B. For example, the memory cell MC may be configured as a single-gate transistor, that is, a memory cell configured with a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 36C.

[0491] When the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 292 or the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, written data can be held by the transistor M1 for a long time, so that the frequency of refreshing the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary. Furthermore, since the leakage current is very small, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0492] Furthermore, in the DOSRAM, if a sense amplifier is provided so as to overlap under the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance and the storage capacitance of the memory cell.

[0493] [NOSRAM] 36D to 36G show circuit configuration examples of a gain cell type memory cell having two transistors and one capacitor. The memory cell 1474 shown in FIG. 36D has a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a top gate (sometimes simply called a gate) and a back gate. In this specification and the like, a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 may be called a nonvolatile oxide semiconductor RAM (NOSRAM).

[0494] A first terminal of the transistor M2 is connected to a first terminal of the capacitance element CB, a second terminal of the transistor M2 is connected to the wiring WBL, a gate of the transistor M2 is connected to the wiring WOL, and a back gate of the transistor M2 is connected to the wiring BGL. A second terminal of the capacitance element CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to the first terminal of the capacitance element CB.

[0495] The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB. When writing data and when reading data, it is preferable to apply a high-level potential to the wiring CAL. Also, when data is being held, it is preferable to apply a low-level potential to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2 can be increased or decreased by applying an arbitrary potential to the wiring BGL.

[0496] Here, the memory cell 1474 shown in Fig. 36D corresponds to the memory device shown in Fig. 29 and Fig. 30. That is, the transistor M2 corresponds to the transistor 200, the capacitor CB corresponds to the capacitor 100, the transistor M3 corresponds to the transistor 300, the wiring WBL corresponds to the wiring 1003, the wiring WOL corresponds to the wiring 1004, the wiring BGL corresponds to the wiring 1006, the wiring CAL corresponds to the wiring 1005, the wiring RBL corresponds to the wiring 1002, and the wiring SL corresponds to the wiring 1001.

[0497] Moreover, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may be configured such that the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL, as in the memory cell 1475 shown in FIG. 36E. For example, the memory cell MC may be configured such that the transistor M2 has a single gate structure, that is, a transistor M2 without a back gate, as in the memory cell 1476 shown in FIG. 36F. For example, the memory cell MC may be configured such that the wiring WBL and the wiring RBL are combined into a single wiring BIL, as in the memory cell 1477 shown in FIG. 36G.

[0498] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor CB can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made very small. As a result, written data can be held by the transistor M2 for a long time, so that the frequency of refreshing the memory cell can be reduced. In addition, the refresh operation of the memory cell can be made unnecessary. In addition, since the leakage current is very small, multi-level data or analog data can be held in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0499] Note that the transistor M3 may be a transistor having silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have a higher field-effect mobility than an OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a read transistor. By using a Si transistor as the transistor M3, the transistor M2 can be stacked on the transistor M3, thereby reducing the area occupied by the memory cell and achieving high integration of the memory device.

[0500] In addition, the transistor M3 may be an OS transistor. When the transistors M2 and M3 are OS transistors, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0501] FIG. 36H shows an example of a gain cell type memory cell having three transistors and one capacitor. A memory cell 1478 shown in FIG. 36H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to a wiring BIL, a wiring RWL, a wiring WWL, a wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to a wiring RBL and a wiring WBL instead of the wiring BIL.

[0502] The transistor M4 is an OS transistor having a backgate, and the backgate is electrically connected to the wiring BGL. The backgate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 does not necessarily have to have a backgate.

[0503] Note that the transistors M5 and M6 may be n-channel Si transistors or p-channel Si transistors, or the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured as a circuit using only n-type transistors.

[0504] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistors M5 and M6 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely small.

[0505] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, and the like shown in this embodiment are not limited to those described above. The arrangement or functions of these circuits, and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary. The memory device of one embodiment of the present invention has high operating speed and can retain data for a long period of time.

[0506] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0507] (Embodiment 4) In this embodiment, an example of a chip 1200 on which the semiconductor device of the present invention is mounted is shown with reference to Figures 37A and 37B. A plurality of circuits (systems) are mounted on the chip 1200. A technology for integrating a plurality of circuits (systems) on a single chip in this manner is sometimes called a system on chip (SoC).

[0508] As shown in FIG. 37A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog computing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0509] Chip 1200 is provided with bumps (not shown) and is connected to a first surface of package substrate 1201 as shown in Fig. 37B. In addition, a plurality of bumps 1202 are provided on the back surface of package substrate 1201 relative to the first surface and are connected to motherboard 1203.

[0510] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DRAM 1221 may be the DOSRAM described in the above embodiment. For example, the flash memory 1222 may be the NOSRAM described in the above embodiment.

[0511] The CPU 1211 preferably has a plurality of CPU cores. The GPU 1212 preferably has a plurality of GPU cores. The CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The memory may be the above-mentioned NOSRAM or DOSRAM. The GPU 1212 is suitable for parallel calculation of a large amount of data and may be used for image processing or multiplication and accumulation. By providing the GPU 1212 with an image processing circuit or a multiplication and accumulation circuit using an oxide semiconductor according to one embodiment of the present invention, it becomes possible to perform image processing and multiplication and accumulation with low power consumption.

[0512] In addition, by providing the CPU 1211 and GPU 1212 on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.

[0513] The analog calculation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.

[0514] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222 .

[0515] The interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller includes a mouse, a keyboard, a game controller, etc. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), etc. can be used.

[0516] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network), and may also include a circuit for network security.

[0517] The above circuits (systems) can be formed in the same manufacturing process in the chip 1200. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0518] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided, can be referred to as a GPU module 1204.

[0519] The GPU module 1204 has the chip 1200 using SoC technology, so that its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles. In addition, a multiply-and-accumulate circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so that the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.

[0520] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0521] (Embodiment 5) This embodiment mode describes an example of an electronic component or electronic device in which the memory device or the like described in the above embodiment mode is incorporated.

[0522] <Electronic components> First, an example of an electronic component incorporating a memory device 720 will be described with reference to FIGS. 38A and 38B.

[0523] Fig. 38A shows a perspective view of electronic component 700 and a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in Fig. 38A has memory device 720 in mold 711. Part of electronic component 700 is omitted in Fig. 38A to show the inside of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to memory device 720 by wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0524] The memory device 720 includes a driver circuit layer 721 and a memory circuit layer 722 .

[0525] 38B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in package) or MCM (Multi Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of memory devices 720 provided on interposer 731.

[0526] In the electronic component 730, an example is shown in which the storage device 720 is used as a high bandwidth memory (HBM). Also, the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, a GPU, or an FPGA.

[0527] The package substrate 732 may be a ceramic substrate, a plastic substrate, a glass epoxy substrate, etc. The interposer 731 may be a silicon interposer, a resin interposer, etc.

[0528] The interposer 731 has a plurality of wirings and functions to electrically connect a plurality of integrated circuits having different terminal pitches. The plurality of wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer may be called a "rewiring substrate" or an "intermediate substrate." In addition, a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode. In addition, in a silicon interposer, a TSV (Through Silicon Via) may be used as the through electrode.

[0529] It is preferable to use a silicon interposer as the interposer 731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of the silicon interposer can be formed by a semiconductor process, it is easy to form fine wiring, which is difficult to form with a resin interposer.

[0530] In HBM, many wirings need to be connected to realize a wide memory bandwidth. For this reason, the interposer that mounts HBM requires fine and high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer that mounts HBM.

[0531] In addition, in SiP or MCM using silicon interposers, deterioration of reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, connection failure between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged side by side on the interposer.

[0532] A heat sink (heat dissipation plate) may be provided so as to overlap the electronic component 730. When providing a heat sink, it is preferable to align the height of an integrated circuit provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the height of the memory device 720 and the height of the semiconductor device 735.

[0533] In order to mount the electronic component 730 on another substrate, electrodes 733 may be provided on the bottom of the package substrate 732. Fig. 38B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized. The electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.

[0534] The electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as Staggered Pin Grid Array (SPGA), Land Grid Array (LGA), Quad Flat Package (QFP), Quad Flat J-leaded package (QFJ), and Quad Flat Non-leaded package (QFN).

[0535] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0536] (Embodiment 6) In this embodiment, an application example of a storage device using the semiconductor device described in the previous embodiment will be described. The semiconductor device described in the previous embodiment can be applied to storage devices of various electronic devices (for example, information terminals, computers, smartphones, electronic book terminals, digital cameras (including video cameras), recording and reproducing devices, navigation systems, and the like). Note that the computer here includes a large computer such as a server system, in addition to tablet computers, notebook computers, and desktop computers. Alternatively, the semiconductor device described in the previous embodiment can be applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives). FIGS. 39A to 39E are schematic diagrams showing some configuration examples of removable storage devices. For example, the semiconductor device described in the previous embodiment is processed into a packaged memory chip and used in various storage devices and removable memories.

[0537] 39A is a schematic diagram of a USB memory. A USB memory 1100 has a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The board 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the board 1104. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like.

[0538] FIG. 39B is a schematic diagram of the appearance of an SD card, and FIG. 39C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. The capacity of the SD card 1110 can be increased by providing a memory chip 1114 on the back side of the substrate 1113 as well. In addition, a wireless chip having a wireless communication function may be provided on the substrate 1113. This makes it possible to read and write data from and to the memory chip 1114 by wireless communication between the host device and the SD card 1110. The semiconductor device shown in the above embodiment can be incorporated into the memory chip 1114 or the like.

[0539] FIG. 39D is a schematic diagram of the appearance of an SSD, and FIG. 39E is a schematic diagram of the internal structure of the SSD. SSD 1150 has a housing 1151, a connector 1152, and a board 1153. Board 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are attached to board 1153. Memory chip 1155 is a work memory for controller chip 1156, and may be, for example, a DOSRAM chip. By providing memory chip 1154 on the back side of board 1153, the capacity of SSD 1150 can be increased. The semiconductor device shown in the previous embodiment can be incorporated into memory chip 1154 or the like.

[0540] The structures and methods described in this embodiment can be used in appropriate combination with other structures and methods described in this embodiment or structures and methods described in other embodiments.

[0541] (Embodiment 7) The semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU, or a chip. Specific examples of electronic devices including a processor such as a CPU or a GPU, or a chip according to one embodiment of the present invention are shown in FIG.

[0542] <Electronic equipment and systems> The GPU or chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of electronic devices include electronic devices with relatively large screens, such as television devices, monitors for desktop or notebook information terminals, digital signage, large game machines such as pachinko machines, digital cameras, digital video cameras, digital photo frames, electronic book terminals, mobile phones, portable game machines, portable information terminals, and audio playback devices. Moreover, by providing the GPU or chip according to one embodiment of the present invention in an electronic device, it is possible to mount artificial intelligence on the electronic device.

[0543] The electronic device of one embodiment of the present invention may have an antenna. By receiving a signal through the antenna, images, information, or the like can be displayed on a display portion. In addition, when the electronic device has an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0544] An electronic device according to one embodiment of the present invention may have a sensor (including a function of measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0545] An electronic device according to one embodiment of the present invention can have various functions. For example, the electronic device can have a function of displaying various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of executing various software (programs), a wireless communication function, a function of reading out a program or data recorded in a recording medium, etc. Examples of electronic devices are shown in Fig. 40A to Fig. 40H.

[0546] [Information terminal] 40A illustrates a mobile phone (smartphone), which is a type of information terminal. The information terminal 5100 includes a housing 5101 and a display unit 5102. As an input interface, a touch panel is provided on the display unit 5102, and buttons are provided on the housing 5101.

[0547] By applying the chip of one embodiment of the present invention, the information terminal 5100 can execute applications using artificial intelligence. Examples of applications using artificial intelligence include an application that recognizes a conversation and displays the conversation content on the display unit 5102, an application that recognizes characters, figures, and the like input by a user to a touch panel provided in the display unit 5102 and displays them on the display unit 5102, and an application that performs biometric authentication such as fingerprints or voiceprints.

[0548] 40B illustrates a notebook type information terminal 5200. The notebook type information terminal 5200 includes a main body 5201 of the information terminal, a display unit 5202, and a keyboard 5203.

[0549] The notebook type information terminal 5200 can execute an application using artificial intelligence by applying a chip according to one embodiment of the present invention, similar to the above-described information terminal 5100. Examples of applications using artificial intelligence include design support software, text correction software, and automatic menu generation software. In addition, the notebook type information terminal 5200 can be used to develop new artificial intelligence.

[0550] In the above description, a smartphone and a notebook type information terminal are illustrated in Fig. 40A and Fig. 40B as examples of electronic devices, but information terminals other than smartphones and notebook type information terminals can also be applied. Examples of information terminals other than smartphones and notebook type information terminals include PDAs (Personal Digital Assistants), desktop type information terminals, and workstations.

[0551] [Game consoles] FIG. 40C illustrates a portable game machine 5300 which is an example of a game machine. The portable game machine 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connection unit 5305, an operation key 5306, and the like. The housing 5302 and the housing 5303 can be detached from the housing 5301. When the connection unit 5305 of the housing 5301 is attached to another housing (not shown), a video displayed on the display unit 5304 can be displayed on another video device (not shown). In this case, the housing 5302 and the housing 5303 can each function as an operation unit. This allows a plurality of players to play a game at the same time. The chips described in the above embodiments can be incorporated in the chips provided on the substrates of the housings 5301, 5302, and 5303.

[0552] 40D shows a stationary game machine 5400, which is an example of a game machine. A controller 5402 is connected to the stationary game machine 5400 wirelessly or via a wire.

[0553] A game machine with low power consumption can be realized by applying a GPU or a chip of one embodiment of the present invention to a game machine such as a portable game machine 5300 or a stationary game machine 5400. Furthermore, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0554] Furthermore, by applying a GPU or a chip of one embodiment of the present invention to the portable game console 5300, the portable game console 5300 can have artificial intelligence.

[0555] Originally, the expression of the progress of a game, the behavior of creatures appearing in the game, and phenomena occurring in the game are determined by the program of the game, but by applying artificial intelligence to the portable game device 5300, it becomes possible to express things that are not limited to the program of the game. For example, it becomes possible to express things such as changes in the questions asked by the player, the progress of the game, the time, and the behavior of people appearing in the game.

[0556] In addition, when playing a game on the portable game console 5300 that requires multiple players, the game players can be personified using artificial intelligence, so that the game can be played by one person by making the opponent a game player based on artificial intelligence.

[0557] 40C and 40D show a portable game machine and a stationary game machine as examples of game machines, but the game machine to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of game machines to which the GPU or chip of one embodiment of the present invention is applied include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0558] [Mainframe computers] The GPU or chip of one embodiment of the present invention can be applied to a large computer.

[0559] 40E is a diagram showing a supercomputer 5500, which is an example of a large computer. FIG. 40F is a diagram showing a rack-mounted calculator 5502 included in the supercomputer 5500.

[0560] A supercomputer 5500 includes a rack 5501 and a plurality of rack-mounted computers 5502. The plurality of computers 5502 are stored in the rack 5501. The computer 5502 is provided with a plurality of boards 5504, and the GPU or chip described in the above embodiment can be mounted on the board.

[0561] The supercomputer 5500 is a large-scale computer mainly used for scientific and technological calculations. In scientific and technological calculations, huge amounts of calculations need to be processed at high speed, and therefore power consumption is high and chips generate a lot of heat. By applying a GPU or chip according to one embodiment of the present invention to the supercomputer 5500, a supercomputer with low power consumption can be realized. Furthermore, low power consumption can reduce heat generation from a circuit, and therefore the influence of heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

[0562] 40E and 40F show a supercomputer as an example of a large computer, but the large computer to which the GPU or chip of one embodiment of the present invention is applied is not limited to this. Examples of large computers to which the GPU or chip of one embodiment of the present invention is applied include computers that provide services (servers) and large general-purpose computers (mainframes).

[0563] [Mobile object] The GPU or chip according to one embodiment of the present invention can be applied to automobiles, which are moving objects, and to the area around the driver's seat of an automobile.

[0564] Fig. 40G is a diagram showing the periphery of the windshield in the interior of an automobile, which is an example of a moving body, Fig. 40G shows display panel 5701, display panel 5702, and display panel 5703 attached to the dashboard, as well as display panel 5704 attached to a pillar.

[0565] The display panels 5701 to 5703 can provide various information by displaying a speedometer, a tachometer, a mileage, a fuel gauge, a gear state, an air conditioner setting, and the like. In addition, the display items or layouts displayed on the display panels can be changed as appropriate according to the user's preferences, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

[0566] The display panel 5704 can complement the field of view (blind spot) blocked by the pillar by displaying an image from an imaging device (not shown) installed in the vehicle. That is, by displaying an image from an imaging device installed outside the vehicle, blind spots can be complemented and safety can be improved. In addition, by displaying an image that complements the invisible part, safety can be confirmed more naturally and without discomfort. The display panel 5704 can also be used as a lighting device.

[0567] Since the GPU or chip of one embodiment of the present invention can be used as a component of artificial intelligence, the chip can be used, for example, in an automatic driving system for an automobile. The chip can also be used in a system that performs road guidance, risk prediction, etc. The display panels 5701 to 5704 may be configured to display information such as road guidance and risk prediction.

[0568] In the above description, an automobile is described as an example of a moving object, but the moving object is not limited to an automobile. For example, the moving object may be a train, a monorail, a ship, an aircraft (helicopter, unmanned aerial vehicle (drone), airplane, rocket), etc., and the chip of one embodiment of the present invention may be applied to these moving objects to provide a system using artificial intelligence.

[0569] [electric appliances] 40H shows an example of an electric appliance, an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 has a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0570] An electric refrigerator-freezer 5800 having artificial intelligence can be realized by applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800. By using artificial intelligence, the electric refrigerator-freezer 5800 can have a function of automatically generating a menu based on ingredients stored in the electric refrigerator-freezer 5800 and the expiration date of the ingr...

Claims

[Claim 1] A first insulator; a second insulator having an opening on the first insulator; a third insulator provided within the opening and having a first recess; a first oxide provided within the first recess and having a second recess; a second oxide provided inside the second recess; a first conductor and a second conductor electrically connected to the second oxide and spaced apart from each other; a fourth insulator on the second oxide; and a third conductor having a region overlapping with the second oxide and sandwiching the fourth insulator therebetween; the second oxide has, in a top view, a first region, a second region, and a third region sandwiched between the first region and the second region; the first conductor has a first region and a region overlapping with the second insulator, the second conductor has the second region and a region overlapping with the second insulator, the third conductor has a region overlapping with the third region; Semiconductor device.

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