Photoelectric conversion device and photoelectric conversion system

Abstract

To provide a photoelectric conversion device and a photoelectric conversion system with which it is possible to easily improve a dynamic range and an S / N ratio in accordance with the operating voltage of pixels.SOLUTION: The photoelectric conversion device comprises a photoelectric conversion unit for generating electric charges by photoelectric conversion, a floating diffusion unit for holding the electric charge transferred from the photoelectric conversion unit, and an output unit for outputting a signal corresponding to the amount of the electric charge held by the floating diffusion unit, and further includes a pixel constituted to be capable of switching the capacitance value of the floating diffusion unit and a control unit for switching the capacitance value of the floating diffusion unit. The control unit sets the floating diffusion unit to a first capacitance value when the absolute value of the power supply voltage supplied to the output unit equals a first voltage, and sets the floating diffusion unit to a second capacitance value which is larger than the first capacitance value when the absolute value of the power supply voltage equals a second voltage which is lower than the first voltage.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a photoelectric conversion device and a photoelectric conversion system. [Background technology]

[0002] Patent Document 1 describes a solid-state imaging device configured to suppress an increase in power consumption by operating pixels at a voltage lower than the power supply voltage. Patent Document 2 describes a solid-state imaging device configured to expand the dynamic range by connecting a capacitance-adding transistor to a floating diffusion. Patent Document 3 describes a solid-state imaging element configured to expand the dynamic range by connecting charge-voltage conversion regions of multiple pixels and increasing the number of saturated electrons in the entire connected charge-voltage conversion region. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2014-033402 A [Patent Document 2] JP 2010-124418 A [Patent Document 3] JP 2020-145699 A Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the technology described in Patent Document 1, when the pixel is driven in a power saving mode in which the pixel operates at a voltage lower than the power supply voltage, the dynamic range of the floating diffusion may decrease. Also, in the technologies described in Patent Documents 2 and 3, the dynamic range can be secured by increasing the capacitance of the floating diffusion, but increasing the capacitance of the floating diffusion decreases the charge-voltage conversion coefficient, which in turn decreases the S / N ratio and may degrade the image quality.

[0005] An object of the present invention is to provide a photoelectric conversion device and a photoelectric conversion system that can easily expand the dynamic range and improve the S / N ratio in accordance with the operating voltage of the pixels. [Means for solving the problem]

[0006] According to one disclosure of the present specification, there is provided a photoelectric conversion device comprising: a photoelectric conversion unit that generates charge by photoelectric conversion, a floating diffusion unit that holds charge transferred from the photoelectric conversion unit, and an output unit that outputs a signal corresponding to the amount of charge held by the floating diffusion unit, the pixel being configured to be able to switch the capacitance value of the floating diffusion unit; and a control unit that switches the capacitance value of the floating diffusion unit, the control unit setting the floating diffusion unit to a first capacitance value when the absolute value of the power supply voltage supplied to the output unit is a first voltage, and setting the floating diffusion unit to a second capacitance value larger than the first capacitance value when the absolute value of the power supply voltage is a second voltage lower than the first voltage. Effect of the Invention

[0007] According to the present invention, it is possible to realize a photoelectric conversion device and a photoelectric conversion system that can easily expand the dynamic range and improve the S / N ratio in accordance with the operating voltage of the pixel. [Brief description of the drawings]

[0008] [Figure 1] 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. [Diagram 2] 2 is an equivalent circuit diagram showing an example of the configuration of a pixel of the photoelectric conversion device according to the first embodiment. FIG. [Diagram 3] 1 is a schematic diagram showing a configuration example of a photoelectric conversion device according to a first embodiment. [Figure 4] 4 is a timing chart showing a method for driving the photoelectric conversion device according to the first embodiment. FIG. [Diagram 5] FIG. 11 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a second embodiment. [Figure 6] FIG. 11 is a potential diagram of a pixel of a photoelectric conversion device according to a third embodiment. [Figure 7] FIG. 11 is a potential diagram of a pixel of a photoelectric conversion device according to a third embodiment. [Figure 8] FIG. 11 is a potential diagram of a pixel of a photoelectric conversion device according to a third embodiment. [Figure 9] FIG. 11 is a potential diagram of a pixel of a photoelectric conversion device according to a third embodiment. [Figure 10] FIG. 13 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a fourth embodiment. [Figure 11] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a fourth embodiment. [Figure 12] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a fourth embodiment. [Figure 13] FIG. 13 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a fifth embodiment. [Figure 14] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a fifth embodiment. [Figure 15] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a fifth embodiment. [Figure 16] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a fifth embodiment. [Figure 17] FIG. 13 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a sixth embodiment. [Figure 18] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a sixth embodiment. [Figure 19] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a sixth embodiment. [Figure 20] FIG. 13 is an equivalent circuit diagram showing an example of the configuration of a pixel of a photoelectric conversion device according to a seventh embodiment. [Figure 21] FIG. 13 is a diagram for explaining a wiring capacitance in a pixel configuration according to a sixth embodiment. [Figure 22] FIG. 23 is a diagram for explaining a wiring capacitance in a pixel configuration according to a seventh embodiment. [Figure 23] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to the seventh embodiment. [Figure 24]FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to the seventh embodiment. [Diagram 25] FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to the seventh embodiment. [Figure 26] FIG. 13 is a block diagram showing a schematic configuration of a photoelectric conversion system according to an eighth embodiment. [Figure 27] FIG. 13 is a diagram illustrating an example of the configuration of a photoelectric conversion system and a moving object according to a ninth embodiment. [Figure 28] FIG. 23 is a block diagram showing a schematic configuration of an apparatus according to a tenth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] [First embodiment] A photoelectric conversion device and a driving method thereof according to a first embodiment of the present invention will be described with reference to Figs. 1 to 4. Fig. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment. Fig. 2 is an equivalent circuit diagram showing an example of the configuration of a pixel in a photoelectric conversion device according to this embodiment. Fig. 3 is a schematic diagram showing an example of the configuration of a photoelectric conversion device according to this embodiment. Fig. 4 is a timing chart showing a method of driving a photoelectric conversion device according to this embodiment.

[0010] First, a schematic configuration of a photoelectric conversion device according to the present embodiment will be described with reference to Fig. 1. The photoelectric conversion device 100 according to the present embodiment includes a pixel array section 10, a vertical scanning circuit 20, a readout circuit 30, a reference signal output circuit 44, a counter circuit 54, a horizontal scanning circuit 60, a signal processing circuit 70, and a timing generation section 80, as shown in Fig. 1.

[0011] The pixel array section 10 is provided with a plurality of pixels 12 arranged in a matrix across a plurality of rows and a plurality of columns. Each pixel 12 includes a photoelectric conversion unit made of a photoelectric conversion element such as a photodiode, and outputs a pixel signal according to the amount of incident light. Although a total of 16 pixels 12 arranged in 4 rows and 4 columns are shown in FIG. 1, typically, tens of millions of pixels 12 are arranged in the pixel array section 10. Note that the number of rows and columns of the pixel array arranged in the pixel array section 10 is not particularly limited. In addition, in addition to effective pixels that output pixel signals according to the amount of incident light, optical black pixels in which the photoelectric conversion units are shielded, dummy pixels that do not output signals, etc. may be arranged in the pixel array section 10.

[0012] In each row of the pixel array section 10, a control line 14 is arranged extending in a first direction (the horizontal direction in FIG. 1). Each of the control lines 14 is connected to the pixels 12 aligned in the first direction, and serves as a signal line common to these pixels 12. The first direction in which the control lines 14 extend may be called the row direction or horizontal direction. The control lines 14 are connected to a vertical scanning circuit 20. Note that the control lines 14 in each row may include multiple signal lines.

[0013] In each column of the pixel array section 10, a vertical output line 16 is arranged to extend in a second direction (vertical direction in FIG. 1) intersecting the first direction. The vertical output lines 16 in each column are connected to the pixels 12 arranged in the second direction, respectively, and form a common signal line for these pixels 12. The second direction in which the vertical output lines 16 extend may be called the column direction or vertical direction. The vertical output lines 16 are connected to a readout circuit 30. A current source 18 is connected to the vertical output line 16 in each column. Note that a plurality of vertical output lines 16 may be arranged in each column of the pixel array section 10.

[0014] The vertical scanning circuit 20 has a function of receiving a control signal from the timing generation unit 80, generating a control signal for driving the pixels 12, and outputting the control signal to the pixels 12 via the control line 14. The vertical scanning circuit 20 may include logic circuits such as a shift register and an address decoder. The vertical scanning circuit 20 sequentially outputs control signals to the control line 14 of each row, and sequentially drives the pixels 12 of the pixel array unit 10 row by row. The signals read out from the pixels 12 row by row are input to the readout circuit 30 via the vertical output line 16 arranged in each column of the pixel array unit 10.

[0015] The readout circuit 30 has a number of column circuits 32 corresponding to the number of vertical output lines 16. The column circuits 32 have a role of analog-digital conversion (AD conversion) of the output signals of the pixels 12. Each of the column circuits 32 has a comparator 40 and a memory 50. The comparator 40 has two input nodes and one output node. The memory 50 has three input nodes and one output node. A first input node of the comparator 40 is connected to the corresponding vertical output line 16. A second input node of the comparator 40 is connected to a reference signal output circuit 44 via a reference signal line 42. An output node of the comparator 40 is connected to a first input node of the memory 50. A second input node of the memory 50 is connected to a counter circuit 54 via a count signal line 52. A third input node of the memory 50 is connected to a horizontal scanning circuit 60. An output node of the memory 50 is connected to a signal processing circuit 70 via a horizontal output line 56.

[0016] The reference signal output circuit 44 has a role of generating a reference signal used for AD conversion and outputting it to the comparator 40 of each column via the reference signal line 42. The reference signal used for AD conversion may be a signal having a predetermined amplitude according to the range of the pixel signal, and the signal level of which changes over time. The reference signal is not particularly limited, but for example, a ramp signal whose signal level monotonically increases or decreases over time can be applied. The change in the signal level does not necessarily have to be continuous, and may be step-like. Furthermore, the change in the signal level does not necessarily have to be linear with respect to time, and may be curved with respect to time (for example, a sine wave or a cosine wave).

[0017] The counter circuit 54 has a role of counting the clock pulse signals CLK supplied from a clock pulse supply unit (not shown) in response to a control signal from the timing generation unit 80, and outputting a count signal CNT indicating the count value to the memory 50 of each column. The counter circuit 54 starts a counting operation in synchronization with the timing at which the signal level of the reference signal output from the reference signal output circuit 44 starts to change.

[0018] The horizontal scanning circuit 60 receives a control signal from the timing generation unit 80, generates a control signal for reading out pixel signals from the column circuits 32 of the readout circuit 30, and outputs the control signal to the readout circuit 30. The horizontal scanning circuit 60 sequentially scans the column circuits 32 of each column of the readout circuit 30, and sequentially outputs the pixel signals held in each memory 50 to the signal processing circuit 70 via the horizontal output line 56. The horizontal scanning circuit 60 may include logic circuits such as a shift register and an address decoder.

[0019] The signal processing circuit 70 is a processing circuit that is composed of a buffer amplifier, a differential amplifier, etc., and executes a predetermined signal processing on the pixel signals of the column selected by the horizontal scanning circuit 60, and outputs the processed pixel data. The external interface circuit provided in the signal processing circuit 70 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit can be applied to the external interface circuit. The SerDes transmission circuit is, for example, an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit.

[0020] The timing generation unit 80 is a control circuit for generating control signals for controlling the operations and timings of the vertical scanning circuit 20, the comparator 40, the reference signal output circuit 44, the memory 50, the counter circuit 54, the horizontal scanning circuit 60, and the signal processing circuit 70, and for supplying the control signals to each functional block. Note that at least some of the control signals supplied to these functional blocks may be supplied from outside the photoelectric conversion device 100.

[0021] Each of the pixels 12 constituting the pixel array section 10 may be composed of a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, a selection transistor M4, and a capacitance adding transistor M5, for example, as shown in FIG. 2.

[0022] The photoelectric conversion element PD may be, for example, a photodiode. The photoelectric conversion element PD has an anode connected to a ground voltage node and a cathode connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2, the gate of the amplification transistor M3, and the drain of the capacitance-adding transistor M5. A node FD to which the drain of the transfer transistor M1, the source of the reset transistor M2, the gate of the amplification transistor M3, and the drain of the capacitance-adding transistor M5 are connected is a so-called floating diffusion portion. The floating diffusion portion includes a capacitance component (floating diffusion capacitance) and has a function as a charge holding portion. The floating diffusion capacitance may include the gate capacitance of a transistor, the pn junction capacitance, the wiring capacitance, and the like. The source of the capacitance-adding transistor M5 is connected to a floating node. Note that "connected to a floating node" means that the source of the capacitance-adding transistor M5 is in an electrically floating state, and does not necessarily have to be electrically connected to another member. The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a node to which a power supply voltage (voltage SVDD) is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the vertical output line 16.

[0023] In the case of the pixel configuration of FIG. 2, the control line 14 of each row includes four signal lines connected to the gate of the transfer transistor M1, the gate of the reset transistor M2, the gate of the selection transistor M4, and the gate of the additional capacitance transistor M5. A control signal PTX is supplied from the vertical scanning circuit 20 to the gate of the transfer transistor M1. A control signal PRES is supplied from the vertical scanning circuit 20 to the gate of the reset transistor M2. A control signal PSEL is supplied from the vertical scanning circuit 20 to the gate of the selection transistor M4. A control signal PFDINC is supplied from the vertical scanning circuit 20 to the gate of the additional capacitance transistor M5. When each transistor is an N-type MOS transistor, when a high-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned on. When a low-level control signal is supplied from the vertical scanning circuit 20, the corresponding transistor is turned off.

[0024] In this embodiment, the description will be made on the assumption that, of the electron-hole pairs generated in the photoelectric conversion element PD by the incidence of light, the electrons are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 12 may be composed of an N-type MOS transistor arranged in a P-well. However, the signal charges are not limited to electrons, and holes may be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is the opposite conductivity type to that described in this embodiment. In addition, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this embodiment may be called by the opposite names.

[0025] The photoelectric conversion element PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion) and accumulates the generated charge. When the transfer transistor M1 is turned on, it transfers the charge held by the photoelectric conversion element PD to the node FD. The charge transferred from the photoelectric conversion element PD is held in the capacitance component (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of charge transferred from the photoelectric conversion element PD through charge-voltage conversion by the floating diffusion capacitance.

[0026] The capacitance-adding transistor M5 has a role of switching the capacitance value of the floating diffusion section. That is, when the capacitance-adding transistor M5 is turned on, its channel capacitance is added to the capacitance of the node FD, so that the capacitance value of the floating diffusion section when the capacitance-adding transistor M5 is turned on is larger than the capacitance value of the floating diffusion section when the capacitance-adding transistor M5 is turned off. In this way, the pixel 12 of this embodiment is configured to be able to switch the capacitance value of the floating diffusion section by the capacitance-adding transistor M5. The capacitance-adding transistor M5 is controlled by a control signal PFDINC from the vertical scanning circuit 20. That is, the vertical scanning circuit 20 can be said to be a control section that switches the capacitance value of the floating diffusion section.

[0027] The reset transistor M2 has a role of controlling a reset operation for resetting the node FD serving as a charge holding unit. That is, the reset transistor M2 is a reset unit that resets the node FD to a voltage corresponding to the voltage SVDD by being turned on.

[0028] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the vertical output line 16. The amplification transistor M3 has a configuration in which a voltage SVDD is supplied to its drain and a bias current is supplied to its source from a current source 18 via the selection transistor M4, forming an amplification section (source follower circuit) with its gate as an input node. As a result, the amplification transistor M3 outputs a signal based on the potential of the node FD to the vertical output line 16 via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are an output section that outputs a pixel signal according to the amount of charge held in the node FD.

[0029] A pixel signal (hereinafter referred to as a pixel output signal PIXOUT) output from the pixel 12 via the vertical output line 16 is input to a first input node of the comparator 40. A reference signal VRAMP output from a reference signal output circuit 44 via a reference signal line 42 is input to a second input node of the comparator.

[0030] The comparator 40 compares the level of the pixel output signal PIXOUT with the level of the reference signal VRAMP, and outputs a signal according to the relationship of magnitude between them. For example, when the level of the reference signal VRAMP is lower than the level of the pixel output voltage PIXOUT, the comparator 40 outputs a high-level signal COMPOUT. On the other hand, when the level of the reference signal VRAMP is higher than the level of the pixel output voltage PIXOUT, the comparator 40 outputs a low-level signal COMPOUT. Note that the relationship between the magnitude of the input signal and the level of the output signal may be reversed.

[0031] The counter circuit 54 starts counting the clock pulse signal CLK when the reference signal VRAMP output from the reference signal output circuit 44 starts to change depending on time, and outputs a count signal CNT indicating the count value. That is, the counter circuit 54 counts the clock pulse signal CLK in parallel with the change in the potential of the reference signal VRAMP, and generates and outputs the count signal CNT.

[0032] A signal COMPOUT output from the comparator 40 is input to a first input node of the memory 50. A count signal CNT output from the counter circuit 54 via a count signal line 52 is input to a second input node of the memory 50. The memory 50 holds the count value indicated by the count signal CNT output from the counter circuit 54 at the timing when the level of the signal COMPOUT output from the comparator 40 is inverted, as a digital signal of the pixel output signal PIXOUT. The memory 50 can hold a digital signal obtained by AD converting a reset level signal (hereinafter, N signal) and a digital signal obtained by AD converting a signal obtained by superimposing a signal of the photoelectric conversion element PD on the N signal of the node FD (hereinafter, S signal).

[0033] The digital signals held in the memory 50 are transferred sequentially for each column to the signal processing circuit 70 via the horizontal output line 56 in response to a control signal supplied from the horizontal scanning circuit 60. The signal processing circuit 70 performs correction processing to remove noise components by subtracting the N signal from the S signal, and outputs the processed signal to the outside of the photoelectric conversion device 100.

[0034] The photoelectric conversion device 100 of this embodiment may be configured such that all of the above-mentioned functional blocks are arranged on one substrate, or may be configured as a stacked photoelectric conversion device in which the above-mentioned functional blocks are separately produced on multiple substrates and these substrates are bonded together and electrically connected.

[0035] 3(a) is a schematic diagram of a case where a pixel substrate 110 and a circuit substrate 120 are laminated. For example, a pixel array section 10 can be arranged on the pixel substrate 110. For example, a vertical scanning circuit 20, a readout circuit 30, a reference signal output circuit 44, a counter circuit 54, a horizontal scanning circuit 60, a signal processing circuit 70, and a timing generation section 80 can be arranged on the circuit substrate 120. By arranging the pixel substrate 110 and the circuit substrate 120 on separate substrates, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10.

[0036] 3(b) is a schematic diagram of a case where the pixel substrate 110 and the circuit substrates 120 and 130 are laminated. For example, the pixel array section 10 can be arranged on the pixel substrate 110. For example, the vertical scanning circuit 20, the readout circuit 30, the reference signal output circuit 44, the counter circuit 54, the horizontal scanning circuit 60, the signal processing circuit 70, and the timing generation section 80 can be arranged on the circuit substrates 120 and 130. Even in this case, it is possible to reduce the size of the photoelectric conversion device 100 without sacrificing the area of ​​the pixel array section 10.

[0037] It should be noted that the circuit elements constituting one functional block do not necessarily have to be arranged on the same substrate, and may be arranged on separate substrates.

[0038] Next, a method for driving the photoelectric conversion device according to this embodiment will be described in more detail with reference to Fig. 4. The photoelectric conversion device 100 according to this embodiment may have two operation modes: a power saving mode and a normal mode. Here, the power saving mode is a mode in which the voltage level of the voltage SVDD is lowered compared to the normal mode and signals of the pixels 12 are read out. The voltage level of the voltage SVDD may be changed by switching the value of the power supply voltage input to the photoelectric conversion device 100 by an external system, or may be changed by a transformer circuit provided in the photoelectric conversion device 100.

[0039] Fig. 4 is a timing diagram showing an example of a pixel signal readout operation in the power saving mode. Fig. 4 shows waveforms of the control signals PSEL, PRES, PTX, PFDINC, pixel output signal PIXOUT, reference signal VRAMP, signal COMPOUT, signal COMPRES, and horizontal scanning signal of the row to which the pixel 12 to be read belongs. The signal COMPRES is a control signal for controlling the reset operation of the comparator 40. The horizontal scanning signal is a control signal supplied from the horizontal scanning circuit 60 to the memory 50 of each column.

[0040] In the period before time t10, the control signals PSEL and PTX are at a low level, and the control signals PRES and PFDINC are at a high level. As a result, the capacitance-adding transistor M5 is turned on, and a capacitance (capacitance value Cinc1) generated by the channel of the capacitance-adding transistor M5 is added to the capacitance of the node FD. In addition, the reset transistor M2 is turned on, and the node FD is reset to a voltage corresponding to the voltage SVDD. The reference signal VRAMP is at a predetermined initial voltage. When the photoelectric conversion device is operated in normal mode, the control signal PFDINC is set to a low level, and the capacitance-adding transistor M5 is kept off.

[0041] At time t10, the vertical scanning circuit 20 controls the control signal PSEL to change from low level to high level. This turns on the selection transistor M4 of the row to which the pixel 12 to be read belongs. That is, the row is selected. This causes a signal (pixel output signal PIXOUT) of a level corresponding to the reset voltage of the node FD to be output to the vertical output line 16 via the selection transistor M4.

[0042] At the next time t11, the vertical scanning circuit 20 controls the control signal PRES to change from high to low. This turns off the reset transistor M2 and releases the reset state of the node FD. When the control signal PRES changes from high to low, the voltage of the node FD decreases due to the capacitive coupling between the gate and source of the reset transistor M2, and the level of the pixel output signal PIXOUT also decreases accordingly. The pixel output signal PIXOUT after the signal level has stabilized is referred to here as a pixel reset level signal. The pixel reset level signal is a signal that includes noise components that the pixel 12 has.

[0043] For a predetermined period from time t12 after the potential of the vertical output line 16 has been stabilized, the timing generation section 80 controls the control signal COMPRES to a high level. This resets the comparator 40, and initializes the comparator 40.

[0044] At time t13 after the control signal COMPRES transitions to a low level, the reference signal output circuit 44 starts a slope operation to gradually decrease the voltage of the reference signal VRAMP over time. The counter circuit 54 starts counting up in synchronization with the start of the slope operation, and outputs a count signal CNT indicating the count value to the memory 50 of each column via the count signal line 52.

[0045] The comparator 40 of each column compares the signal level of the pixel output signal PIXOUT with the signal level of the reference signal VRAMP, and outputs a signal COMPOUT according to the comparison result. That is, the signal level of the signal COMPOUT is inverted at the timing when the magnitude relationship between the signal level of the pixel output voltage PIXOUT and the signal level of the reference signal VRAMP changes. For example, as shown in FIG. 4, if the signal level of the reference signal VRAMP falls below the signal level of the pixel output signal PIXOUT at time t14, the signal level of the signal COMPOUT transitions from low level to high level at this timing. The memory 50 holds the count value indicated by the count signal CNT at the timing when the signal level of the signal COMPOUT changes as digital data of the pixel reset level (a value obtained by AD converting the N signal).

[0046] At the next time t15, the reference signal output circuit 44 stops changing the signal level of the reference signal VRAMP and resets the reference signal VRAMP to the initial voltage. The counter circuit 54 stops counting the clock pulses and returns the count value to the initial value. The signal level of the signal COMPOUT output from the comparator 40 returns to the low level in accordance with the initialization of the reference signal VRAMP.

[0047] In the subsequent period from time t16 to time t17, the vertical scanning circuit 20 controls the control signal PTX to a high level. This turns on the transfer transistor M1, and the charge accumulated in the photoelectric conversion element PD during the predetermined exposure period is transferred to the node FD. The voltage of the node FD decreases according to the amount of charge transferred from the photoelectric conversion element PD. The amplification transistor M3 outputs a pixel output signal PIXOUT according to the potential of the node FD to which the charge generated by the photoelectric conversion element PD has been transferred, to the vertical output line 16 via the selection transistor M4. The pixel output signal PIXOUT at this time is a pixel signal at the optical signal level of the pixel 12.

[0048] At time t18 after the potential of the vertical output line 16 has settled, the reference signal output circuit 44 restarts the slope operation of gradually decreasing the voltage of the reference signal VRAMP over time. The counter circuit 54 starts counting up in synchronization with the start of the slope operation, and outputs a count signal CNT indicating the count value to the memory 50 of each column via the count signal line 52.

[0049] The comparator 40 of each column compares the signal level of the pixel output signal PIXOUT with the signal level of the reference signal VRAMP, and outputs a signal COMPOUT according to the comparison result. For example, as shown in Fig. 4, if the signal level of the reference signal VRAMP falls below the signal level of the pixel output signal PIXOUT at time t19, the signal level of the signal COMPOUT transitions from low to high at this timing. The memory 50 holds the count value indicated by the count signal CNT at the timing when the signal level of the signal COMPOUT changes as digital data of the optical signal level (a value obtained by AD converting the S signal).

[0050] At the next time t20, the reference signal output circuit 44 stops changing the signal level of the reference signal VRAMP and resets the reference signal VRAMP to the initial voltage. The counter circuit 54 stops counting the clock pulses and returns the count value to the initial value. The signal level of the signal COMPOUT output from the comparator 40 returns to the low level in accordance with the initialization of the reference signal VRAMP.

[0051] At the following time t21, the timing generation unit 80 starts a horizontal transfer operation of digital data from the readout circuit 30 to the signal processing circuit 70. The horizontal scanning circuit 60 sequentially outputs horizontal scanning signals to the memory 50 of each column under the control of the timing generation unit 80. The memory 50 that receives the horizontal scanning signal from the horizontal scanning circuit 60 transfers the digital data of the N signal and the digital data of the S signal to the signal processing circuit 70 via the horizontal output line 56. The signal processing circuit 70 calculates a differential signal level (optical component) by subtracting the N signal from the S signal, and outputs it to the outside of the photoelectric conversion device 100.

[0052] In the power saving mode, as described above, the voltage level of the voltage SVDD is lowered compared to the normal mode to perform the pixel signal readout operation. However, lowering the voltage SVDD narrows the range of available signal voltages, which reduces the dynamic range on the floating diffusion region (node ​​FD) and on the vertical output line 16.

[0053] In this regard, in this embodiment, the capacitance value of the floating diffusion is increased by turning on the capacitive transistor M5 in the power saving mode. For example, if the capacitance value Cfd of the node FD when the capacitive transistor M5 is off is the same as the capacitance value Cinc1 of the capacitance generated by turning on the capacitive transistor M5, the capacitance value is doubled by turning on the capacitive transistor M5. Since the potential of the node FD is proportional to the amount of signal charge and the inverse of the capacitance value of the floating diffusion, if the capacitance value of the floating diffusion is doubled, the signal amplitude at the node FD of the signal generated by the signal charge from the photoelectric conversion element PD is halved. In addition, since the amplifying transistor M3 outputs a signal based on the potential of the node FD to the vertical output line 16, if the signal amplitude generated on the node FD is halved, the signal amplitude generated on the vertical output line 16 is also halved.

[0054] In this way, in the power saving mode, the voltage SVDD is lowered and the capacitance-adding transistor M5 is turned on to increase the capacitance value of the floating diffusion section. This narrows the signal amplitude on the node FD and the vertical output line 16 to ensure a dynamic range and to read out all the signal charges held by the photoelectric conversion element PD. In addition, lowering the voltage level of the voltage SVDD can reduce power consumption, which reduces image quality deterioration due to heat generation and increases the number of still images that can be captured and the continuous video capture time when there are limitations on the battery capacity.

[0055] As described above, according to this embodiment, it is possible to realize a photoelectric conversion device that can easily expand the dynamic range and improve the S / N ratio in accordance with the operating voltage of the pixel.

[0056] [Second embodiment] A photoelectric conversion device and a driving method thereof according to a second embodiment of the present invention will be described with reference to Fig. 5. Components similar to those in the photoelectric conversion device according to the first embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 5 is an equivalent circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment.

[0057] The photoelectric conversion device according to the present embodiment is similar to the photoelectric conversion device according to the first embodiment except for the configuration of the pixel 12. In this embodiment, the differences from the photoelectric conversion device according to the first embodiment will be mainly described, and the description of the similarities to the photoelectric conversion device according to the first embodiment will be omitted as appropriate.

[0058] 5, the pixel 12 of the photoelectric conversion device according to this embodiment further includes a capacitance-addition transistor M6 in addition to the transfer transistor M1, the reset transistor M2, the amplifying transistor M3, and the capacitance-addition transistor M5. The drain of the capacitance-addition transistor M6 is connected to the node FD. The source of the capacitance-addition transistor M6 is connected to a floating node. That is, the capacitance-addition transistors M5 and M6 are connected in parallel between the node FD and the floating node. A control signal PFDINC1 is input to the gate of the capacitance-addition transistor M5 from the vertical scanning circuit 20 via the control line 14, and a control signal PFDINC2 is input to the gate of the capacitance-addition transistor M6 from the vertical scanning circuit 20 via the control line 14.

[0059] The capacitive transistor M6, like the capacitive transistor M5, has a role of switching the capacitance value of the floating diffusion part. That is, when the capacitive transistor M6 is turned on, its channel capacitance is added to the capacitance of the node FD, so that the capacitance value of the floating diffusion part when the capacitive transistor M6 is on is larger than the capacitance value of the floating diffusion part when the capacitive transistor M6 is off. The capacitive transistor M5 and the capacitive transistor M6 can be controlled independently.

[0060] Here, the capacitance value of the node FD when the capacitive transistors M5 and M6 are off is Cfd. The capacitance value of the capacitance generated when the capacitive transistor M5 is on is Cinc1, and the capacitance value of the capacitance generated when the capacitive transistor M6 is on is Cinc2. When the capacitance values ​​Cfd, Cinc1, and Cinc2 are the same, the floating diffusion capacitance can take three types of capacitance values ​​depending on the driving states of the capacitive transistors M5 and M6.

[0061] In this case, the capacitance value of the floating diffusion when only one of the capacitive transistors M5, M6 is turned on is twice the capacitance value Cfd of the floating diffusion when the capacitive transistors M5, M6 are off, and the signal amplitude generated on the node FD is 1 / 2. The capacitance value of the floating diffusion when both the capacitive transistors M5, M6 are turned on is three times the capacitance value Cfd of the floating diffusion when the capacitive transistors M5, M6 are off, and the signal amplitude generated on the node FD is 1 / 3.

[0062] Therefore, according to this configuration, it is possible to set two types of power saving modes that consume less power than the normal mode. That is, in power saving mode 1, in which the voltage SVDD is lowered and only one of the capacitive transistors M5 and M6 is turned on, the signal amplitude on the node FD and the vertical output line 16 can be narrowed to 1 / 2. In power saving mode 2, in which the voltage SVDD is further lowered and both the capacitive transistors M5 and M6 are turned on, the signal amplitude on the node FD and the vertical output line 16 can be narrowed to 1 / 3. This can reduce power consumption, reduce deterioration of image quality due to heat, and increase the number of still images that can be captured or the continuous shooting time of videos when there is a limit to the battery capacity.

[0063] As described above, according to this embodiment, it is possible to realize a photoelectric conversion device that can easily expand the dynamic range and improve the S / N ratio in accordance with the operating voltage of the pixel.

[0064] [Third embodiment] A photoelectric conversion device and a driving method thereof according to a third embodiment of the present invention will be described with reference to Fig. 6 to Fig. 9. Components similar to those of the photoelectric conversion device according to the first or second embodiment are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 6 to Fig. 9 are potential diagrams of pixels of the photoelectric conversion device according to this embodiment.

[0065] In the second embodiment, the capacitance of the floating diffusion section is increased by the capacitive transistors M5 and M6 to narrow the signal amplitude on the FD and the vertical output line 16, thereby ensuring the dynamic range and reading out all the signal charges of the photoelectric conversion element PD. However, if the voltage SVDD is made too low, it may not be possible to read out all the signal charges accumulated in the photoelectric conversion element PD. In this embodiment, an example of the configuration of a photoelectric conversion device that can achieve both reduced power consumption and complete transfer of the signal charges from the photoelectric conversion element PD to the node FD will be described.

[0066] Before describing the specific contents of this embodiment, the mechanism by which all the signal charges of the photoelectric conversion element PD cannot be read out by lowering the voltage level of the voltage SVDD will be described with reference to FIGS.

[0067] 6 shows the potentials in the pixel of the second embodiment when the capacitance-adding transistors M5 and M6 are turned off to reduce the capacitance value of the floating diffusion portion. In the figure, PD indicates the potential of the photoelectric conversion element PD, M1 indicates the potential under the gate of the transfer transistor M1, and FD indicates the potential of the node FD. M5 indicates the potential under the gate of the capacitance-adding transistor M5, M6 indicates the potential under the gate of the capacitance-adding transistor M6, and M2 indicates the potential under the gate of the reset transistor M2. SVDD indicates the potential of the voltage SVDD supplied to the drain of the reset transistor M2. In the figure, the downward direction is the direction of positive potential.

[0068] 6A shows the potential when signal charges are accumulated in the photoelectric conversion element PD. When signal charges are accumulated in the photoelectric conversion element PD, the transfer transistor M1 is turned off and the signal charges are accumulated in the photoelectric conversion element PD.

[0069] Figure 6(b) shows the potential after the signal charge is transferred from the photoelectric conversion element PD to the node FD. When the transfer transistor M1 is turned on, the potential barrier between the photoelectric conversion element PD and the node FD is lowered to the position indicated by the dashed line. As a result, the signal charge accumulated in the photoelectric conversion element PD is transferred to the node FD. At this time, the capacitive transistors M5 and M6 are off and the capacitance value of the floating diffusion is small, but by increasing the voltage level of the voltage SVDD, it is possible to transfer all the signal charge accumulated in the photoelectric conversion element PD to the node FD.

[0070] 7 shows the potential in the pixel of the second embodiment when the voltage level of the voltage SVDD is lowered and both of the capacitance-adding transistors M5 and M6 are turned on to increase the capacitance of the floating diffusion region. The symbols and directions of the potential in the figure are the same as those in FIG.

[0071] Figure 7(a) shows the potential when signal charge is accumulated in the photoelectric conversion element PD. When signal charge is accumulated in the photoelectric conversion element PD, the transfer transistor M1 is off, and the signal charge is accumulated in the photoelectric conversion element PD. Both capacitance-adding transistors M5 and M6 are on, and the capacitance value of the floating diffusion is Cfd+Cinc1+Cinc2. In addition, the signal level of the voltage SVDD is lower than in Figure 6, and the potential of the node FD is also lower than in Figure 6.

[0072] FIG. 7(b) shows the potential after the signal charge is transferred from the photoelectric conversion element PD to the node FD. When the transfer transistor M1 is turned on, the potential barrier between the photoelectric conversion element PD and the node FD is lowered to the position of the dashed line. As a result, the signal charge accumulated in the photoelectric conversion element PD is transferred to the node FD. If the capacitance values ​​Cfd, Cinc1, and Cinc2 are the same, that is, if the capacitance value of the floating diffusion is assumed to be three times that in FIG. 6, the change in the potential at the node FD is one-third that in FIG. 6. By turning on the capacitance-adding transistors M5 and M6 to increase the capacitance value of the floating diffusion and reduce the voltage amplitude at the node FD, it is possible to transfer all the signal charges accumulated in the photoelectric conversion element PD to the node FD even if the voltage level of the voltage SVDD is lowered.

[0073] Fig. 8 shows the potential in the pixel of the second embodiment when the voltage level of the voltage SVDD is further reduced compared to Fig. 7 and both of the capacitance-adding transistors M5 and M6 are turned on to increase the capacitance of the floating diffusion region. The symbols and directions of the potential in the figure are the same as those in Fig. 6.

[0074] Figure 8(a) shows the potential when signal charge is accumulated in the photoelectric conversion element PD. When signal charge is accumulated in the photoelectric conversion element PD, the transfer transistor M1 is off, and the signal charge is accumulated in the photoelectric conversion element PD. Both capacitance-adding transistors M5 and M6 are on, and the capacitance value of the floating diffusion is Cfd+Cinc1+Cinc2. In addition, the signal level of the voltage SVDD is further lower than in Figure 7, and the potential of the node FD is also lower than in Figure 7.

[0075] FIG. 8(b) shows the potential after the signal charge is transferred from the photoelectric conversion element PD to the node FD. When the transfer transistor M1 is turned on, the potential barrier between the photoelectric conversion element PD and the node FD is lowered to the position indicated by the dashed line. As a result, part of the signal charge accumulated in the photoelectric conversion element PD is transferred to the node FD. However, because the voltage level of the voltage SVDD is too low, not all of the charge accumulated in the photoelectric conversion element PD can be transferred to the node FD, even though the capacitance value of the floating diffusion is three times that in the case of FIG. 6, and the signal charge remains in the photoelectric conversion element PD.

[0076] Next, a method for driving the photoelectric conversion device according to the present embodiment will be described with reference to Fig. 9. Fig. 9 shows the potential when the voltage level of the P-well in which the pixel 12 is arranged is changed from the ground voltage to a negative voltage in the state of Fig. 8. The symbols and potential directions in the figure are the same as those in Fig. 6.

[0077] 9(a) shows the potential when signal charge is accumulated in the photoelectric conversion element PD. When signal charge is accumulated in the photoelectric conversion element PD, the transfer transistor M1 is off and the signal charge is accumulated in the photoelectric conversion element PD. Both capacitance-adding transistors M5 and M6 are on and the capacitance value of the floating diffusion is Cfd+Cinc1+Cinc2.

[0078] Since the voltage SVDD is applied to the drain of the reset transistor M2, even if a negative voltage is applied to the P-well in which the pixel 12 is arranged, the voltage level of the drain of the reset transistor M2 does not change from that in Figure 8. In addition, since the node FD is reset to a potential according to the voltage SVDD via the reset transistor M2, the voltage level of the node FD also does not change from that in Figure 8.

[0079] On the other hand, in the photoelectric conversion element PD, the capacitive coupling with the P-well is dominant, so the potential of the photoelectric conversion element PD shifts to the negative side by the amount of the negative voltage applied to the P-well. Also, because the channel region of the transfer transistor M1 has strong capacitive coupling with the gate of the transfer transistor M1, the low level that turns off the transfer transistor M1 shifts to the negative side of the ground voltage by the amount of the negative voltage applied to the P-well. As with the transfer transistor M1, the low level that turns off the reset transistor M2 also shifts to the negative side of the ground voltage by the amount of the negative voltage applied to the P-well.

[0080] For example, if the low level for turning off the transfer transistor M1 was originally set to -1 V, when the voltage applied to the P-well in which the pixel 12 is arranged is lowered from 0 V to -1 V, the low level for turning off the transfer transistor M1 is also lowered by 1 V to -2 V. In addition, if the low level for turning off the reset transistor M2 was originally 0.5 V, the low level for turning off the reset transistor M2 is also lowered by 1 V to -0.5 V, as in the case of the transfer transistor M1.

[0081] FIG. 9(b) shows the potential after the signal charge is transferred from the photoelectric conversion element PD to the node FD. When the transfer transistor M1 is turned on, the potential barrier between the photoelectric conversion element PD and the node FD is lowered to the position indicated by the dashed line. When a negative voltage is applied to the P-well in which the pixel 12 is arranged, the potential of the photoelectric conversion element PD becomes relatively higher than the potential of the node FD, and all of the signal charge held in the photoelectric conversion element PD can be transferred to the node FD. It is also possible to further reduce the voltage level of the voltage SVDD and further reduce power consumption.

[0082] In this way, by applying a negative voltage to the P-well in which the pixel 12 is arranged, it is possible to suppress the remaining signal charge in the photoelectric conversion element PD that may occur as the voltage SVDD decreases, which makes it possible to further lower the voltage level of the voltage SVDD and further reduce power consumption.

[0083] In this embodiment, the potential relationships have been described assuming that the transistors constituting the pixel 12 are N-type transistors, but the potential relationships will be the opposite of those described above if the transistors constituting the pixel 12 are P-type transistors. If we express this in terms of the case of P-type transistors as well, we can say that when the absolute value of the voltage SVDD is lowered to reduce power consumption, a voltage of the opposite polarity to the voltage SVDD is applied to the well in which the pixel is disposed.

[0084] As described above, according to this embodiment, it is possible to realize a photoelectric conversion device that can easily expand the dynamic range and improve the S / N ratio in accordance with the operating voltage of the pixel.

[0085] [Fourth embodiment] A photoelectric conversion device and a driving method thereof according to a fourth embodiment of the present invention will be described with reference to Figs. 10 to 12. Components similar to those of the photoelectric conversion devices according to the first to third embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 10 is an equivalent circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Figs. 11 and 12 are timing charts showing a driving method of the photoelectric conversion device according to this embodiment.

[0086] The photoelectric conversion device according to this embodiment is similar to the photoelectric conversion devices according to the first to third embodiments, except for the configuration of the pixel 12. In this embodiment, the differences from the photoelectric conversion devices according to the first to third embodiments will be mainly described, and descriptions of the similarities to the photoelectric conversion devices according to the first to third embodiments will be omitted as appropriate.

[0087] 10, the pixel 12 of the photoelectric conversion device according to this embodiment is different from the pixel of the first embodiment in the connection location of the capacitance-addition transistor M5. That is, in the first embodiment, the capacitance-addition transistor M5 is connected between the node FD and a floating node, whereas in this embodiment, the capacitance-addition transistor M5 is connected between the source of the reset transistor M2 and the node FD. That is, the source of the capacitance-addition transistor M5 is connected to the node FD, and the drain of the capacitance-addition transistor M5 is connected to the source of the reset transistor M2. A control signal PFDINC is input to the gate of the capacitance-addition transistor M5 from the vertical scanning circuit 20 via a control line 14.

[0088] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 11 and Fig. 12. Fig. 11 is a timing diagram in a power saving mode, and Fig. 12 is a timing diagram in a normal mode. In Fig. 11 and Fig. 12, the same times as in Fig. 6 are used for timings for performing operations similar to those in the timing diagram of Fig. 6.

[0089] The operation in the power saving mode, that is, when a pixel signal is read out with the channel capacitance of the capacitance-adding transistor M5 added to the node FD, is basically the same as the operation in the first embodiment shown in Fig. 6, as shown in Fig. 11. That is, the control signal PFDINC is fixed to a high level, and the reset operation of the node FD is performed by driving the reset transistor M2 with the control signal PRES. Other operations are also similar to those in the power saving mode described in the first embodiment.

[0090] By setting the control signal PFDINC to a high level, the capacitive transistor M5 is turned on, and a capacitance value Cinc1 is added to the node FD, as in the first embodiment. If it is assumed that the capacitance value Cfd of the floating diffusion when the capacitive transistor M5 is off is the same as the capacitance value Cinc1 of the capacitance generated by turning on the capacitive transistor M5, the capacitance value of the floating diffusion is doubled. This makes it possible to halve the signal amplitude on the node FD and on the vertical output line 16. Therefore, as in the first embodiment, it is possible to reduce power consumption by lowering the voltage level of the voltage SVDD.

[0091] In normal mode, that is, when a pixel signal is read out without adding the channel capacitance of the capacitive transistor M5 to the node FD, the control signal PRES is fixed to a high level, and the reset operation of the node FD is controlled by the control signal PFDINC, as shown in Fig. 12. In the period from time t10 to time t11, the reset transistor M2 and the capacitive transistor M5 are both turned on, and the node FD is reset to a potential corresponding to the voltage SVDD. At time t11, the control signal PFDINC goes low, turning off the capacitive transistor M5, and releasing the reset state of the node FD.

[0092] In the pixel configuration of the first embodiment, even if the reset transistor M2 and the capacitive transistor M5 are off when the pixel signal is read out, the gate-source capacitance of these MOS transistors is added to the node FD. In contrast, in the pixel configuration of this embodiment, the only capacitance added to the node FD is the gate-source capacitance of the capacitive transistor M5. Therefore, according to this embodiment, the capacitance value of the floating diffusion portion when the capacitive transistor M5 is off can be reduced. As a result, the charge-voltage conversion coefficient at the node FD can be increased when the capacitive transistor M5 is off, and a signal with a high S / N ratio can be read out.

[0093] As described above, according to this embodiment, it is possible to realize a photoelectric conversion device that can easily expand the dynamic range and improve the S / N ratio in accordance with the operating voltage of the pixel.

[0094] [Fifth embodiment] A photoelectric conversion device and a driving method thereof according to a fifth embodiment of the present invention will be described with reference to Figs. 13 to 16. The same components as those in the photoelectric conversion devices according to the first to fourth embodiments are given the same reference numerals, and their description will be omitted or simplified. Fig. 13 is an equivalent circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Figs. 14 to 16 are timing charts showing a driving method of the photoelectric conversion device according to this embodiment.

[0095] The photoelectric conversion device according to the present embodiment is similar to the photoelectric conversion devices according to the first to fourth embodiments, except for the configuration of the pixel 12. In this embodiment, the differences from the photoelectric conversion devices according to the first to fourth embodiments will be mainly described, and descriptions of the similarities to the photoelectric conversion devices according to the first to fourth embodiments will be omitted as appropriate.

[0096] 13, the pixel 12 of the photoelectric conversion device according to this embodiment further includes a capacitance-addition transistor M6 in addition to the pixel 12 of the photoelectric conversion device according to the fourth embodiment. The capacitance-addition transistor M6 is connected in series between the reset transistor M2 and the capacitance-addition transistor M5. That is, the source of the capacitance-addition transistor M6 is connected to the drain of the capacitance-addition transistor M5, and the drain of the capacitance-addition transistor M6 is connected to the source of the reset transistor M2. A control signal PFDINC1 is input to the gate of the capacitance-addition transistor M5 from the vertical scanning circuit 20 via the control line 14, and a control signal PFDINC2 is input to the gate of the capacitance-addition transistor M6 from the vertical scanning circuit 20 via the control line 14.

[0097] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Fig. 14 to Fig. 16. Fig. 14 is a timing diagram in power saving mode 2, Fig. 15 is a timing diagram in power saving mode 1, and Fig. 16 is a timing diagram in normal mode. In Fig. 14 to Fig. 16, the same times as in Fig. 6 are used for timings for performing operations similar to those in the timing diagram of Fig. 6.

[0098] In power saving mode 2, that is, an operation mode in which the capacitance value of the floating diffusion is maximized to read out pixel signals, the control signals PFDINC1 and PFDINC2 are fixed to a high level as shown in Fig. 14. The reset operation of node FD is performed by controlling the control signal PRES. Other operations are the same as those in the power saving mode described in the first embodiment.

[0099] By setting the control signals PFDINC1 and PFDINC2 to a high level to turn on the capacitance-adding transistors M5 and M6, the channel capacitances of these transistors are added to the capacitance of the node FD. Assuming that the capacitance value Cfd of the floating diffusion when the capacitance-adding transistor M5 is off is the same as the capacitance values ​​Cinc1 and Cinc2 of the capacitances generated by turning on the capacitance-adding transistors M5 and M6, the capacitance value of the floating diffusion becomes three times larger. This makes it possible to reduce the signal amplitude on the node FD and the vertical output line 16 to one-third. Therefore, as in the second embodiment, it is possible to reduce power consumption by lowering the voltage level of the voltage SVDD.

[0100] In power saving mode 1, that is, an operation mode in which only the capacitive transistor M5 is turned on to read out pixel signals, the control signals PRES and PFDINC1 are fixed to a high level as shown in Fig. 16. The reset operation of the node FD is performed by controlling the control signal PFDINC2. Other operations are the same as those in the power saving mode described in the first embodiment.

[0101] By setting the control signal PFDINC1 to a high level to turn on the capacitance-adding transistor M5, the channel capacitance of the capacitance-adding transistor M5 is added to the capacitance of the node FD. At this time, by setting the control signal PFDINC2 to a low level, the capacitance added to the floating diffusion capacitance is only the channel capacitance of the capacitance-adding transistor M5. Assuming that the capacitance value Cfd of the floating diffusion when the capacitance-adding transistor M5 is off is the same as the capacitance value Cinc1 of the capacitance generated by turning on the capacitance-adding transistor M5, the capacitance value of the floating diffusion is doubled. This makes it possible to halve the signal amplitude on the node FD and the vertical output line 16. Therefore, as in the second embodiment, it is possible to reduce power consumption by lowering the voltage level of the voltage SVDD.

[0102] In the normal mode, that is, in the operation mode in which pixel signals are read out without adding the channel capacitance of the capacitive transistors M5 and M6 to the node FD, the control signals PRES and PFDINC2 are fixed to a high level as shown in Fig. 16. The reset operation of the node FD is controlled by the control signal PFDINC. In the period from time t10 to time t11, the reset transistor M2 and the capacitive transistors M5 and M6 are turned on, so that the node FD is reset to a potential corresponding to the voltage SVDD. At time t11, the control signal PFDINC1 goes low, turning off the capacitive transistor M5, and releasing the reset state of the node FD.

[0103] In the pixel configuration of the second embodiment, even if the reset transistor M2 and the capacitive transistors M5 and M6 are off when the pixel signal is read out, the gate-source capacitances of these MOS transistors are added to the node FD. In contrast, in the pixel configuration of this embodiment, the only capacitance added to the node FD is the gate-source capacitance of the capacitive transistor M5. Therefore, according to this embodiment, the capacitance value of the floating diffusion portion when the capacitive transistor M5 is off can be reduced. As a result, the charge-voltage conversion coefficient at the node FD can be increased when the capacitive transistor M5 is off, and a signal with a high S / N ratio can be read out.

[0104] In the pixel configurations of the fourth and fifth embodiments, when the voltage SVDD is lowered to save power, it may happen that the signal charge held by the photoelectric conversion element PD cannot be transferred to the node FD, as in the first and second embodiments. In such a case, as described in the third embodiment, it is effective to apply a negative voltage to the P-well in which the pixel 12 is arranged. By applying a negative voltage to the P-well in which the pixel 12 is arranged, it becomes possible to read out all the signal charge held by the photoelectric conversion element PD even when the voltage SVDD is lowered. It is also possible to further reduce the voltage level of the voltage SVDD and further reduce power consumption.

[0105] As described above, according to this embodiment, it is possible to realize a photoelectric conversion device that can easily expand the dynamic range and improve the S / N ratio in accordance with the operating voltage of the pixel.

[0106] [Sixth embodiment] A photoelectric conversion device according to a sixth embodiment of the present invention and a driving method thereof will be described with reference to Figs. 17 to 19. The same components as those in the photoelectric conversion devices according to the first to fifth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 17 is an equivalent circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Figs. 18 and 19 are timing charts showing a driving method of the photoelectric conversion device according to this embodiment.

[0107] The photoelectric conversion device according to the present embodiment is similar to the photoelectric conversion devices according to the first to fifth embodiments, except for the configuration of the pixel 12. In this embodiment, the differences from the photoelectric conversion devices according to the first to fifth embodiments will be mainly described, and descriptions of the similarities to the photoelectric conversion devices according to the first to fifth embodiments will be omitted as appropriate.

[0108] As shown in FIG. 17, the pixel 12 of the photoelectric conversion device according to this embodiment has an FD-connection transistor M7 instead of the capacitance-adding transistors M5 and M6 in the pixel 12 of the photoelectric conversion device according to the first or second embodiment. The FD-connection transistor M7 is connected between the nodes FD of the pixels 12 adjacent to each other in the column direction. For example, the pixel 12 in the Nth row has an FD-connection transistor M7 whose drain is connected to the node FD of the pixel 12 in the Nth row and whose source is connected to the node FD of the pixel 12 in the N+1th row. The pixel 12 in the N+1th row has an FD-connection transistor M7 whose drain is connected to the node FD of the pixel 12 in the N+1th row and whose source is connected to the node FD of the pixel 12 in the N+2th row. The pixel 12 in the N+2th row has an FD-connection transistor M7 whose drain is connected to the node FD of the pixel 12 in the N+2th row and whose source is connected to the node FD of the pixel 12 in the N+3th row (not shown). A control signal PFDSW is input from the vertical scanning circuit 20 via a control line 14 to the gate of the FD connection transistor M7.

[0109] The FD connection transistor M7 is provided between the floating diffusion and the floating diffusion of another pixel, and serves as a switch circuit for controlling the connection therebetween. When the FD connection transistor M7 of each pixel 12 is off, the floating diffusions of the pixels 12 are independent of each other, and the capacitance value of the floating diffusions is minimized. Therefore, the charge-voltage conversion coefficient at the node FD becomes large, and it becomes possible to read out the pixel signal with a high S / N ratio. In addition, by setting the number of on-state FD connection transistors M7 connected to the node FD of a pixel 12 to a desired number, the capacitance value of the floating diffusion of the pixel 12 can be set to a desired value according to the desired number.

[0110] Here, the capacitance value of the floating diffusion when there is no FD connection transistor M7 in the ON state connected to the node FD is Cfd, and the channel capacitance when the FD connection transistor M7 is ON is Cfdsw. In this case, if there is one FD connection transistor M7 in the ON state connected to a certain node FD, two nodes FD are connected via the FD connection transistor M7, and the capacitance value of the entire floating diffusion is 2×Cfd+1×Cfdsw. If there are two FD connection transistors M7 in the ON state connected to a certain node FD, three nodes FD are connected via two FD connection transistors M7, and the capacitance value of the entire floating diffusion is 3×Cfd+2×Cfdsw. That is, the more the number of FD connection transistors M7 in the ON state connected to the node FD is increased, the larger the capacitance value of the entire floating diffusion can be.

[0111] Next, a method for driving the photoelectric conversion device according to this embodiment will be described with reference to Figs. 18 and 19. Fig. 18 is a timing diagram for reading out pixel signals by connecting the nodes FD of two pixels 12, and Fig. 19 is a timing diagram for reading out pixel signals by connecting the nodes FD of three pixels 12. In Figs. 18 and 19, the same times as in Fig. 6 are used for timings for performing operations similar to those in the timing diagram of Fig. 6. In Figs. 18 and 19, (N), (N+1), and (N+2) added to the symbols of the control signals PTX, PSEL, PRES, and PFDSW indicate the pixel rows to which these control signals are supplied.

[0112] 18, an operation is assumed in which the FD connection transistor M7 of the pixel 12 in the Nth row, which is a selected row, is turned on to connect the node FD of the pixel 12 in the Nth row to the node FD of the pixel 12 in the (N+1)th row. Operations such as outputting a pixel reset level signal after releasing the reset of the node FD, and outputting a pixel signal of an optical signal level after pulse driving the control signal PTX are similar to the operations of the first embodiment described using FIG. 6, and therefore detailed explanations will be omitted here.

[0113] At time t10, the vertical scanning circuit 20 controls the control signal PFDSW(N) to change from low level to high level. This turns on the FD connection transistor M7 of the pixel 12 in the Nth row, and the node FD of the pixel 12 in the Nth row and the node FD of the pixel 12 in the (N+1)th row are connected via the FD connection transistor M7 of the pixel 12 in the Nth row. As a result, the capacitance of the node FD of the pixel 12 in the Nth row, the capacitance of the node FD of the pixel 12 in the (N+1)th row, and the channel capacitance of the FD connection transistor M7 of the pixel 12 in the Nth row are connected in parallel to form one capacitance (floating diffusion capacitance) as a whole.

[0114] At the next time t11, the vertical scanning circuit 20 changes the control signals PRES(N) and PRES(N+1) from high to low to release the floating diffusion capacitance from the reset state. This allows the floating diffusion capacitance including the capacitance of the node FD of the two pixels 12 and the channel capacitance of the FD-connecting transistor M7 to be used as a charge-voltage converter for the signal charge transferred from the photoelectric conversion element PD of the pixel in the Nth row, to read out the pixel signal.

[0115] 19, an operation is assumed in which the FD connection transistors M7 of the pixels 12 in the selected row, the Nth row, and the next N+1th row are turned on to connect the nodes FD of the pixels 12 in the Nth row, the N+1th row, and the N+2th row. Operations such as outputting a pixel reset level signal after releasing the reset of the node FD, and outputting a pixel signal of an optical signal level after pulse driving the control signal PTX are similar to those in the first embodiment described using FIG. 6, and therefore detailed explanations will be omitted here.

[0116] At time t10, the vertical scanning circuit 20 controls the control signals PFDSW(N) and PFDSW(N+1) to change from low level to high level. This causes the FD connection transistor M7 of the pixel 12 in the Nth row to be turned on, and the node FD of the pixel 12 in the Nth row and the node FD of the pixel 12 in the N+1th row are connected via the FD connection transistor M7 of the pixel 12 in the Nth row. In addition, the FD connection transistor M7 of the pixel 12 in the N+1th row is turned on, and the node FD of the pixel 12 in the N+1th row and the node FD of the pixel 12 in the N+2th row are connected via the FD connection transistor M7 of the pixel 12 in the N+1th row. As a result, the capacitances of the nodes FD of the pixels 12 in the Nth, N+1th, and N+2th rows and the channel capacitances of the FD connection transistors M7 of the pixels 12 in the Nth and N+1th rows are connected in parallel to form one capacitance (floating diffusion capacitance) as a whole.

[0117] At the next time t11, the vertical scanning circuit 20 changes the control signals PRES(N), PRES(N+1), and PRES(N+2) from high to low to release the floating diffusion capacitance from the reset state. This allows the floating diffusion capacitance including the capacitances of the nodes FD of the three pixels 12 and the channel capacitances of the two FD-connecting transistors M7 to be used as a charge-voltage converter for the signal charges transferred from the photoelectric conversion elements PD of the pixels in the Nth row, to read out the pixel signals.

[0118] In this manner, in this embodiment, the capacitance value of the floating diffusion can be adjusted by appropriately setting the number of FD-connecting transistors M7 in the on state connected to the node FD of the pixel 12 to be read out. By turning on the FD-connecting transistor M7 to increase the floating diffusion capacitance of the pixel 12 to be read out, the signal amplitude on the node FD and the vertical output line 16 can be narrowed to ensure a dynamic range, and the voltage SVDD can also be lowered. This also enables appropriate driving that balances image quality and power.

[0119] As described above, according to this embodiment, it is possible to realize a photoelectric conversion device that can easily expand the dynamic range and improve the S / N ratio in accordance with the operating voltage of the pixel.

[0120] [Seventh embodiment] A photoelectric conversion device according to a seventh embodiment of the present invention and a driving method thereof will be described with reference to Figs. 20 to 25. The same components as those in the photoelectric conversion devices according to the first to sixth embodiments are given the same reference numerals, and descriptions thereof will be omitted or simplified. Fig. 20 is an equivalent circuit diagram showing an example of the configuration of a pixel in the photoelectric conversion device according to this embodiment. Fig. 21 is a diagram explaining the wiring capacitance in the pixel configuration of the sixth embodiment. Fig. 22 is a diagram explaining the wiring capacitance in the pixel configuration of this embodiment. Figs. 23 to 25 are timing charts showing a driving method of the photoelectric conversion device according to this embodiment.

[0121] The photoelectric conversion device according to the present embodiment is similar to the photoelectric conversion devices according to the first to sixth embodiments, except for the configuration of the pixel 12. In this embodiment, the differences from the photoelectric conversion devices according to the first to sixth embodiments will be mainly described, and descriptions of the similarities to the photoelectric conversion devices according to the first to sixth embodiments will be omitted as appropriate.

[0122] As shown in FIG. 20, the pixel 12 of the photoelectric conversion device according to this embodiment has FD-connection transistors M7 and M8 instead of the capacitance-adding transistor M5 in the pixel 12 of the photoelectric conversion device according to the fourth embodiment. The FD-connection transistor M7 is connected in series between the reset transistor M2 and the node FD. That is, the source of the FD-connection transistor M7 is connected to the node FD. The drain of the FD-connection transistor M7 is connected to the source of the reset transistor M2. The FD-connection transistor M8 is connected between the connection node between the FD-connection transistor M7 and the reset transistor M2 of the pixels 12 adjacent in the column direction. For example, the drain of the FD-connection transistor M8 of the pixel 12 in the (N+1)th row is connected to the connection node between the FD-connection transistor M7 and the reset transistor M2 in the pixel 12 in the Nth row and the source of the FD-connection transistor M8 of the pixel 12 in the Nth row. The drain of the FD connection transistor M8 of the pixel 12 in the (N+2)th row is connected to the connection node between the FD connection transistor M7 and the reset transistor M2 of the pixel 12 in the (N+1)th row, and to the source of the FD connection transistor M8 of the pixel 12 in the (N+1)th row. The drain of the FD connection transistor M8 of the pixel 12 in the (N+3)th row is connected to the connection node between the FD connection transistor M7 and the reset transistor M2 of the pixel 12 in the (N+2)th row, and to the source of the FD connection transistor M8 of the pixel 12 in the (N+2)th row. A control signal PFDSW1 is input to the gate of the FD connection transistor M7 from the vertical scanning circuit 20 via the control line 14, and a control signal PFDSW2 is input to the gate of the FD connection transistor M8 from the vertical scanning circuit 20 via the control line 14.

[0123] Focusing on the pixel 12 in the Nth row and the pixel 12 in the N+1th row, an FD-connecting transistor M7, a wiring, an FD-connecting transistor M7, and an FD-connecting transistor M8 are connected in series between the node FD of the pixel in the Nth row and the node FD of the pixel in the N+1th row. These elements function as a switch circuit for controlling the connection between the floating diffusion of the pixel 12 in the Nth row and the floating diffusion of the pixel 12 in the N+1th row. Each of the FD-connecting transistors M7 and M8 is a switch disposed between the floating diffusion of the pixel 12 in the Nth row and the floating diffusion of the pixel 12 in the N+1th row.

[0124] In the pixel configuration of the sixth embodiment, as shown in Fig. 21, the node FD and the source of the FD-connecting transistor M7 of the adjacent pixel 12 are directly connected by a wire. Therefore, even when the FD-connecting transistor M7 is off, the wiring capacitance Cwire of the wire is added to the capacitance Cfd of the node FD, and the floating diffusion capacitance increases accordingly. As a result, depending on the magnitude of the wiring capacitance Cwire, it may not be possible to sufficiently increase the charge-voltage conversion coefficient when the FD-connecting transistor M7 is off, and it may not be possible to obtain a signal with a high S / N ratio.

[0125] In contrast, in the pixel configuration of the present embodiment, by turning off the FD connection transistor M7, the node FD can be separated from the wiring that connects adjacent pixels 12 in the column direction via the FD connection transistor M8. As a result, when the FD connection transistor M7 is off, as shown in FIG. 22, it is possible to prevent the wiring capacitance Cwire of the wiring from being added to the capacitance Cfd of the node FD, thereby reducing the floating diffusion capacitance.

[0126] Next, a method for driving the photoelectric conversion device according to the present embodiment will be described with reference to FIGS. 23 to 25. FIG. 23 is a timing diagram showing a case where pixel signals are read out without connecting the nodes FD of two or more pixels 12. FIG. 24 is a timing diagram showing a case where pixel signals are read out by connecting the nodes FD of two pixels 12. FIG. 25 is a timing diagram showing a case where pixel signals are read out by connecting the nodes FD of three pixels 12. In FIGS. 23 to 25, the same time as in FIG. 6 is given to the timing of operations similar to those in the timing diagram of FIG. 6. In addition, in FIGS. 23 to 25, (N), (N+1), (N+2), and (N+3) added to the symbols of the control signals PTX, PSEL, PRES, PFDSW1, and PFDSW2 indicate pixel rows to which these control signals are supplied. In addition, it is assumed here that the Nth row is a selected row, and a pixel signal based on the signal charge accumulated in the photoelectric conversion element PD of the pixel 12 in the Nth row is output.

[0127] Fig. 23 shows an example of an operation mode in which the floating diffusion capacitance of the pixel 12 during signal readout is minimized, i.e., the normal mode described above. Operations such as outputting a pixel reset level signal after releasing the reset of the node FD, and outputting a pixel signal of an optical signal level after pulse driving the control signal PTX are similar to those in the first embodiment described using Fig. 6, and therefore detailed explanations will be omitted here.

[0128] 23, the control signal PRES is fixed to a high level, and the control signal PFDSW1 of the Nth row is driven to reset and release the node FD from reset. During the period from time t10 to time t11, the reset transistor M2 and the FD connection transistor M7 of the selected row are both turned on, and the node FD is reset to a potential according to the voltage SVDD. At time t11, the control signal PFDSW1 goes to a low level, turning off the FD connection transistor M7, and releasing the reset state of the node FD.

[0129] When pixel signals corresponding to the period from time t11 to time t22 are read out, the control signal PFDSW1 is fixed at a low level to turn off the FD-connecting transistor M7. This causes only the gate-source capacitance of the FD-connecting transistor M7 to be applied to the node FD of the pixel 12 in the selected row, thereby making it possible to reduce the capacitance value of the node FD when pixel signals are read out.

[0130] Fig. 24 shows an example of an operation mode in which the nodes FD of two pixels 12 are connected to read out pixel signals, that is, an operation example corresponding to the above-mentioned power saving mode. Operations such as outputting a pixel reset level signal after releasing the reset of the node FD, and outputting a pixel signal at an optical signal level after pulse driving the control signal PTX are similar to the operations of the first embodiment described using Fig. 6, and therefore detailed explanations will be omitted here.

[0131] In this operation mode, as shown in FIG. 24, the control signal PFDSW1 is fixed to a high level, and the control signal PRES of the Nth row and the N+1th row is driven to reset and release the reset of the node FD of the pixel 12 of the Nth row and the N+1th row. During the period from time t10 to time t11, the reset transistor M2 and the FD connection transistor M7 of the pixel 12 of the Nth row and the N+1th row are both turned on, so that the node FD is reset to a potential corresponding to the voltage SVDD. At time t11, the control signal PRES becomes a low level and the reset transistor M2 is turned off, so that the reset state of the node FD is released. During the period from time t10 to time t22, the control signal PFSW2 of the N+1th row is fixed to a high level, so that the node FD of the Nth row and the node FD of the N+1th row are connected via the FD connection transistors M7 and M8.

[0132] When reading out pixel signals corresponding to the period from time t11 to time t22, the control signals PRES and PFDSW2 for the Nth row are set to low level, and the control signal PFDSW1 is set to high level. Also, the control signal PRES for the (N+1)th row is set to low level, and the control signals PFDSW1 and PFDSW2 are set to high level. Also, the control signals PRES and PFDSW1 for the (N+2)th row are set to high level, and the control signal PFDSW2 is set to low level.

[0133] As a result, the node FD of the pixel 12 in the Nth row and the node FD of the pixel 12 in the N+1th row are connected via the FD-connecting transistors M7 and M8 of each pixel 12. As a result, the total capacitance value of the floating diffusion capacitance connected to the node FD of the pixel 12 in the Nth row is 2×Cfd+2×Cwire+2×Cfdsw1+1×Cfdsw2. Here, Cfd is the capacitance value of the node FD when the FD-connecting transistor M7 is off, and Cwire is the wiring capacitance of the wiring connecting the drain of the FD-connecting transistor M7 and the drain of the FD-connecting transistor M8. Also, Cfdsw1 is the channel capacitance when the FD-connecting transistor M7 is on, and Cfdsw2 is the channel capacitance when the FD-connecting transistor M8 is on.

[0134] Fig. 25 shows an example of an operation mode in which the nodes FD of three pixels 12 are connected to read out pixel signals, that is, an operation example corresponding to the above-mentioned power saving mode. Operations such as outputting a pixel reset level signal after releasing the reset of the node FD, and outputting a pixel signal at an optical signal level after pulse driving the control signal PTX are similar to the operations of the first embodiment described using Fig. 6, and therefore detailed explanations will be omitted here.

[0135] In this operation mode, as shown in Fig. 25, the control signal PFDSW1 is fixed to a high level, and the control signals PRES of the Nth, N+1th, and N+2th rows are driven to reset and release the nodes FD of the pixels 12 of the Nth, N+1th, and N+2th rows. During the period from time t10 to time t11, the reset transistors M2 and the FD connection transistors M7 of the pixels 12 of the Nth, N+1th, and N+2th rows are both turned on, so that the nodes FD of the pixels 12 of these rows are reset to a potential corresponding to the voltage SVDD. At time t11, the control signal PRES goes to a low level, turning off the reset transistor M2, and releasing the reset state of the node FD. During the period from time t10 to time t22, the control signal PFSW2 in the N+1th row and the N+2th row is fixed to a high level, so that the nodes FD of the pixels 12 in the Nth row, the N+1th row, and the N+2th row are connected via the FD connecting transistors M7 and M8.

[0136] When reading out pixel signals corresponding to the period from time t11 to time t22, the control signals PRES and PFDSW2 for the Nth row are set to low level, and the control signal PFDSW1 is set to high level. Also, the control signals PRES for the (N+1)th and (N+2)th rows are set to low level, and the control signals PFDSW1 and PFDSW2 are set to high level. Also, the control signals PRES and PFDSW1 for the (N+3)th row are set to high level, and the control signal PFDSW2 is set to low level.

[0137] As a result, the node FD of the pixel 12 in the Nth row, the node FD of the pixel 12 in the N+1th row, and the node FD of the pixel 12 in the N+2th row are connected via the FD connection transistors M7 and M8 of each pixel 12. As a result, the total capacitance value of the floating diffusion capacitance connected to the node FD of the pixel 12 in the Nth row is 3×Cfd+3×Cwire+3×Cfdsw1+2×Cfdsw2.

[0138] In this manner, in this embodiment, the capacitance value of the floating diffusion section can be adjusted by appropriately setting the number of FD connection transistors M7 and M8 in the ON state connected to the node FD of the pixel 12 to be read out. By turning on the FD connection transistors M7 and M8 to increase the floating diffusion capacitance of the pixel 12 to be read out, the signal amplitude on the node FD and the vertical output line 16 can be narrowed to ensure the dynamic range, and the voltage SVDD can also be lowered. In addition, by turning off the FD connection transistor M7 of the pixel 12 to be read out, it is possible to prevent unnecessary parasitic capacitance from being connected to the node FD. This makes it possible to reduce the floating diffusion capacitance of the pixel 12 to be read out, and to read out a signal with a good S / N ratio. In addition, these make it possible to perform appropriate driving that balances image quality and power.

[0139] As described above, according to this embodiment, it is possible to realize a photoelectric conversion device that can easily expand the dynamic range and improve the S / N ratio in accordance with the operating voltage of the pixel.

[0140] [Eighth embodiment] A photoelectric conversion system according to an eighth embodiment of the present invention will be described with reference to Fig. 26. Fig. 26 is a block diagram showing a schematic configuration of the photoelectric conversion system according to this embodiment.

[0141] The photoelectric conversion device 100 described in the first to seventh embodiments is applicable to various photoelectric conversion systems. Examples of the applicable photoelectric conversion system include digital still cameras, digital camcorders, security cameras, copiers, fax machines, mobile phones, car-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in the photoelectric conversion system. FIG. 26 illustrates a block diagram of a digital still camera as an example of these.

[0142] 26 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that varies the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any one of the first to seventh embodiments, and converts the optical image formed by the lens 202 into image data.

[0143] The photoelectric conversion system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 generates image data from a digital signal output from the imaging device 201. The signal processing unit 208 also performs various corrections and compression as necessary to output image data. The imaging device 201 may include an AD conversion unit that generates a digital signal to be processed by the signal processing unit 208. The AD conversion unit may be formed in a semiconductor layer (semiconductor substrate) in which the photoelectric conversion unit of the imaging device 201 is formed, or may be formed in a semiconductor substrate different from the semiconductor layer in which the photoelectric conversion unit of the imaging device 201 is formed. The signal processing unit 208 may also be formed in the same semiconductor substrate as the imaging device 201.

[0144] The photoelectric conversion system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The photoelectric conversion system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out on the recording medium 214. The recording medium 214 may be built into the photoelectric conversion system 200, or may be removable.

[0145] Furthermore, the photoelectric conversion system 200 has an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the image capture device 201 and the signal processing unit 208. Here, the timing signals and the like may be input from outside, and the photoelectric conversion system 200 only needs to have at least the image capture device 201 and the signal processing unit 208 that processes the output signal output from the image capture device 201.

[0146] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201, and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0147] In this manner, according to this embodiment, a photoelectric conversion system to which the photoelectric conversion device 100 according to the first to fifth embodiments is applied can be realized.

[0148] [Ninth embodiment] A photoelectric conversion system and a moving object according to a ninth embodiment of the present invention will be described with reference to Fig. 27. Fig. 27 is a diagram showing the configuration of a photoelectric conversion system and a moving object according to this embodiment.

[0149] FIG. 27(a) shows an example of a photoelectric conversion system related to an on-vehicle camera. The photoelectric conversion system 300 has an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to seventh embodiments. The photoelectric conversion system 300 has an image processing unit 312 that performs image processing on a plurality of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference of parallax images) from the plurality of image data acquired by the photoelectric conversion system 300. The photoelectric conversion system 300 also has a distance acquisition unit 316 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire distance information to an object. That is, the distance information is information on the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may determine the possibility of a collision using any of these pieces of distance information. The distance information acquisition means may be realized by dedicated hardware, or may be realized by a software module. In addition, it may be realized by a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or the like, or may be realized by a combination of these.

[0150] The photoelectric conversion system 300 is connected to a vehicle information acquisition device 320, and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 318. The photoelectric conversion system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the judgment result of the collision judgment unit 318. For example, when the judgment result of the collision judgment unit 318 indicates that there is a high possibility of a collision, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0151] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the photoelectric conversion system 300. Fig. 27(b) shows the photoelectric conversion system when imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the photoelectric conversion system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0152] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from lanes, etc. Furthermore, the photoelectric conversion system is not limited to vehicles such as the vehicle itself, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the present invention can be applied not only to moving bodies, but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0153] [Tenth embodiment] The device according to the tenth embodiment of the present invention will be described with reference to Fig. 28. Fig. 28 is a block diagram showing a schematic configuration of the device according to this embodiment.

[0154] FIG. 28 is a schematic diagram showing an apparatus EQP including a photoelectric conversion device APR. The photoelectric conversion device APR has the functions of the photoelectric conversion device 100 according to any one of the first to seventh embodiments. All or a part of the photoelectric conversion device APR is a semiconductor device IC. The photoelectric conversion device APR of this example can be used as, for example, an image sensor, an AF (Auto Focus) sensor, a photometry sensor, or a distance measurement sensor. The semiconductor device IC has a pixel area PX in which pixel circuits PXC including photoelectric conversion units are arranged in a matrix. The semiconductor device IC can have a peripheral area PR around the pixel area PX. Circuits other than pixel circuits can be arranged in the peripheral area PR.

[0155] The photoelectric conversion device APR may have a structure (a chip stacking structure) in which a first semiconductor chip provided with a plurality of photoelectric conversion units and a second semiconductor chip provided with peripheral circuits are stacked. The peripheral circuits in the second semiconductor chip may be column circuits corresponding to the pixel columns of the first semiconductor chip. The peripheral circuits in the second semiconductor chip may be matrix circuits corresponding to the pixels or pixel blocks of the first semiconductor chip. The first and second semiconductor chips may be connected to each other by through-hole vias (TSVs), inter-chip wiring by direct bonding of a conductor such as copper, connection by microbumps between chips, connection by wire bonding, or the like.

[0156] The photoelectric conversion device APR may include a package PKG that houses the semiconductor device IC in addition to the semiconductor device IC. The package PKG may include a base to which the semiconductor device IC is fixed, a cover such as glass that faces the semiconductor device IC, and connection members such as bonding wires and bumps that connect terminals provided on the base and terminals provided on the semiconductor device IC.

[0157] The equipment EQP may further include at least one of an optical device OPT, a control device CTRL, a processing device PRCS, a display device DSPL, a memory device MMRY, and a mechanical device MCHN. The optical device OPT corresponds to the photoelectric conversion device APR as a photoelectric conversion device, and is, for example, a lens, a shutter, or a mirror. The control device CTRL controls the photoelectric conversion device APR, and is, for example, a semiconductor device such as an ASIC. The processing device PRCS processes a signal output from the photoelectric conversion device APR, and constitutes an AFE (analog front end) or a DFE (digital front end). The processing device PRCS is a semiconductor device such as a CPU (central processing unit) or an ASIC (application specific integrated circuit). The display device DSPL is an EL display device or a liquid crystal display device that displays information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a magnetic device or a semiconductor device that stores information (images) obtained by the photoelectric conversion device APR. The memory device MMRY is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive. The mechanical device MCHN has a moving part or a propulsion part such as a motor or an engine. In the device EQP, the signal output from the photoelectric conversion device APR is displayed on the display device DSPL, and is transmitted to the outside by a communication device (not shown) provided in the device EQP. For this purpose, the device EQP preferably further includes a memory device MMRY and a processing device PRCS in addition to the memory circuit unit and the arithmetic circuit unit provided in the photoelectric conversion device APR.

[0158] The device EQP shown in FIG. 28 may be an electronic device such as an information terminal having a photographing function (e.g., a smartphone or a wearable device) or a camera (e.g., an interchangeable lens camera, a compact camera, a video camera, or a surveillance camera). The mechanical device MCHN in the camera can drive components of the optical device OPT for zooming, focusing, and shutter operation. The device EQP may also be a transportation device (moving object) such as a vehicle, a ship, or an aircraft. The device EQP may also be a medical device such as an endoscope or a CT scanner.

[0159] The mechanical device MCHN in the transportation equipment can be used as a moving device. The device EQP as a transportation equipment is suitable for transporting the photoelectric conversion device APR and for assisting and / or automating driving (operation) by using a photographing function. The processing device PRCS for assisting and / or automating driving (operation) can perform processing for operating the mechanical device MCHN as a moving device based on information obtained by the photoelectric conversion device APR.

[0160] The photoelectric conversion device APR according to this embodiment can provide high value to its designer, manufacturer, seller, purchaser and / or user. Therefore, if the photoelectric conversion device APR is installed in equipment EQP, the value of the equipment EQP can also be increased. Therefore, when manufacturing and selling equipment EQP, deciding to install the photoelectric conversion device APR of this embodiment in the equipment EQP is advantageous in increasing the value of the equipment EQP.

[0161] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0162] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0163] In addition, in the first to seventh embodiments, the capacitance values ​​Cfd, Cinc1, and Cinc2 are the same, but the capacitance values ​​Cfd, Cinc1, and Cinc2 do not necessarily have to be the same and can be set appropriately depending on the degree of power saving, the number of power saving modes, etc.

[0164] In the second embodiment, an example is shown in which two capacitance-adding transistors M5 and M6 are connected in parallel to the node FD, and in the fifth embodiment, an example is shown in which two capacitance-adding transistors M5 and M6 are connected in series between the node FD and the reset transistor M2. However, the number of capacitance-adding transistors connected to the node FD may be three or more.

[0165] In the sixth embodiment, the nodes FD of adjacent pixels 12 in the column direction are connected to each other to increase the floating diffusion capacitance of the pixel to be read out, but a configuration in which only the wiring capacitance Cwire is added to the capacitance Cfd may be used. In this case, the FD connection transistors M7 of the pixels 12 in the selected row are turned on, and the FD connection transistors M7 of the pixels 12 in the other rows are turned off, and the number of FD connection transistors M8 to be turned on is appropriately set according to the capacitance value required for the floating diffusion capacitance.

[0166] In the sixth and seventh embodiments, the nodes FD of adjacent pixels 12 in the column direction are connected to each other to increase the floating diffusion capacitance of the pixel to be read out, but the nodes FD of adjacent pixels 12 in the row direction may be connected to each other. Also, the nodes FD of adjacent pixels 12 in the column direction and adjacent pixels 12 in the row direction may be connected to each other.

[0167] In the sixth and seventh embodiments, the driving example in which the signal charge held by the photoelectric conversion element PD of one pixel 12 is read out has been shown, but the signal charges held by the photoelectric conversion elements PD of a plurality of pixels 12 may be added and read out on the node FD. For example, in the driving example of FIG. 24, the control signal PTX of the N+1th row may be driven at the same timing as the control signal PTX of the Nth row. This allows the signal charge held in the photoelectric conversion element PD of the pixel 12 of the Nth row and the signal charge held in the photoelectric conversion element PD of the pixel 12 of the Nth row to be simultaneously read out to the node FD of the pixel 12 of the Nth row. In this case, since the signal amplitude on the node FD becomes large, it is desirable to read out the signal by increasing the voltage SVDD from the viewpoint of ensuring the dynamic range.

[0168] Moreover, the pixel configuration of the sixth or seventh embodiment may further include capacitance-adding transistors M5 and M6 similar to those of the first or second embodiment. In this case, both the capacitance adjustment by the connection between the nodes FD and the capacitance adjustment by the capacitance-adding transistors M5 and M6 become possible, and the floating diffusion capacitance can be adjusted more finely. Moreover, the power consumption can be reduced by lowering the voltage SVDD according to the floating diffusion capacitance.

[0169] Also, in the pixel configuration of the sixth or seventh embodiment, as in the pixel configurations of the first and second embodiments, if the voltage SVDD is made too low to save power, it may happen that the signal charge cannot be transferred from the photoelectric conversion element PD to the node FD. In such a case, as explained in the third embodiment, by applying a negative voltage to the P-well in which the pixel 12 is arranged, it becomes possible to read out all the signal charge of the photoelectric conversion element PD while lowering the voltage SVDD. This allows further reduction in power consumption.

[0170] Furthermore, the photoelectric conversion systems shown in the above eighth and ninth embodiments are examples of photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied, and photoelectric conversion systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 27 and 28(a).

[0171] The present invention can also be realized by a process in which a program for implementing one or more of the functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in a computer of the system or device read and execute the program. The present invention can also be realized by a circuit (e.g., ASIC) that implements one or more of the functions.

[0172] It should be noted that the above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted as being limited by these embodiments. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

[0173] The disclosure of the above embodiment includes the following configurations. (Configuration 1) a pixel including a photoelectric conversion unit that generates electric charges by photoelectric conversion, a floating diffusion unit that holds the electric charges transferred from the photoelectric conversion unit, and an output unit that outputs a signal according to an amount of electric charges held by the floating diffusion unit, the pixel being configured to be able to switch a capacitance value of the floating diffusion unit; a control unit that switches the capacitance value of the floating diffusion unit, The control unit sets the floating diffusion unit to a first capacitance value when an absolute value of a power supply voltage supplied to the output unit is a first voltage, and sets the floating diffusion unit to a second capacitance value larger than the first capacitance value when an absolute value of the power supply voltage is a second voltage lower than the first voltage. A photoelectric conversion device comprising: (Configuration 2) The pixel further comprises a transistor connected to the floating diffusion; The control unit sets the floating diffusion unit to the first capacitance value by controlling the transistor to be off, and sets the floating diffusion unit to the second capacitance value by controlling the transistor to be on. 2. The photoelectric conversion device according to configuration 1. (Configuration 3) The transistor is connected between the floating diffusion and a floating node. 3. The photoelectric conversion device according to configuration 2. (Configuration 4) A plurality of the transistors are connected in parallel between the floating diffusion portion and a floating node. 4. The photoelectric conversion device according to configuration 3. (Configuration 5) a reset unit that resets the floating diffusion unit to a potential corresponding to the power supply voltage, The transistor is connected between the reset portion and the floating diffusion portion. 3. The photoelectric conversion device according to configuration 2. (Configuration 6) The reset section and the floating diffusion section are connected in series to each other. 6. The photoelectric conversion device according to configuration 5. (Configuration 7) The control unit sets the capacitance value of the floating diffusion region by controlling the number of transistors to be turned on among the plurality of transistors. 7. The photoelectric conversion device according to configuration 4 or 6. (Configuration 8) The control unit sets the floating diffusion unit to a third capacitance value greater than the second capacitance value when an absolute value of the power supply voltage is a third voltage lower than the second voltage. 8. The photoelectric conversion device according to configuration 7. (Configuration 9) A plurality of the pixels are provided, Each of the plurality of pixels further includes a switch circuit provided between the floating diffusion portion of one pixel and the floating diffusion portion of another pixel, The control unit sets the capacitance value of the floating diffusion unit of the one pixel by controlling the switch circuit. 2. The photoelectric conversion device according to configuration 1. (Configuration 10) The control unit sets the floating diffusion of the one pixel to the first capacitance value by turning off the switch circuit to separate the floating diffusion of the one pixel from the floating diffusion of the other pixel, and sets the second capacitance value of the floating diffusion of the one pixel by turning on the switch circuit to connect the floating diffusion of the one pixel to the floating diffusion of the other pixel. 10. The photoelectric conversion device according to claim 9. (Configuration 11) The control unit sets the capacitance value of the floating diffusion portion of the one pixel by controlling the number of the other pixels whose floating diffusion portions are connected to the floating diffusion portion of the one pixel by the switch circuit. 11. The photoelectric conversion device according to configuration 9 or 10. (Configuration 12) the switch circuit includes a first switch, a line, and a second switch, in this order, between the floating diffusion of the one pixel and the floating diffusion of the other pixel; The control unit sets the floating diffusion of the one pixel to the first capacitance value by setting the first switch and the second switch to off and disconnecting the wiring from the floating diffusion of the one pixel. 10. The photoelectric conversion device according to claim 9. (Configuration 13) the switch circuit includes a first switch, a line, and a second switch, in this order, between the floating diffusion of the one pixel and the floating diffusion of the other pixel; The control unit sets the floating diffusion of the one pixel to the second capacitance value by setting the first switch on and the second switch off to apply a parasitic capacitance of the wiring to the floating diffusion of the one pixel. 10. The photoelectric conversion device according to configuration 9. (Configuration 14) The switch circuit is configured to connect the floating diffusion portion to the floating diffusion portion of the other pixel adjacent to the floating diffusion portion in the column direction. 14. The photoelectric conversion device according to any one of configurations 9 to 13. (Configuration 15) The switch circuit is configured to connect the floating diffusion portion to the floating diffusion portion of the other pixel adjacent to the floating diffusion portion in the row direction. 15. The photoelectric conversion device according to any one of configurations 9 to 14. (Configuration 16) When the power supply voltage is set to the second voltage, a voltage having a polarity opposite to that of the power supply voltage is applied to a well in which the pixel is disposed. 16. The photoelectric conversion device according to any one of configurations 1 to 15. (Configuration 17) The voltage of the reverse polarity is set so that, when charges are transferred from the photoelectric conversion section to the floating diffusion section, all charges held in the photoelectric conversion section are transferred to the photoelectric conversion section. 17. The photoelectric conversion device according to configuration 16. (Configuration 18) A photoelectric conversion device according to any one of structures 1 to 17; a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising: (Configuration 19) A mobile object, A photoelectric conversion device according to any one of structures 1 to 17; a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising: (Configuration 20) A photoelectric conversion device according to any one of structures 1 to 17; an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on information obtained by the photoelectric conversion device; A display device that displays information obtained by the photoelectric conversion device; and a storage device for storing information obtained by the photoelectric conversion device; An apparatus comprising: [Explanation of symbols]

[0174] M1: Transfer transistor M2: Reset transistor M3: Amplification transistor M4: Selection transistor M5, M6: Capacitive transistor M7, M8…FD connection transistor PD: Photoelectric conversion section 12…pixels 14…Control line 16...Vertical output line 18…Current source 20...Vertical scanning circuit 100...Photoelectric conversion unit

Claims

1. a pixel including a photoelectric conversion unit that generates electric charges by photoelectric conversion, a floating diffusion unit that holds the electric charges transferred from the photoelectric conversion unit, and an output unit that outputs a signal according to an amount of electric charges held by the floating diffusion unit, the pixel being configured to be able to switch a capacitance value of the floating diffusion unit; a control unit that switches the capacitance value of the floating diffusion unit, The control unit sets the floating diffusion unit to a first capacitance value when an absolute value of a power supply voltage supplied to the output unit is a first voltage, and sets the floating diffusion unit to a second capacitance value larger than the first capacitance value when an absolute value of the power supply voltage is a second voltage lower than the first voltage. A photoelectric conversion device comprising:

2. The pixel further comprises a transistor connected to the floating diffusion; The control unit sets the floating diffusion region to the first capacitance value by controlling the transistor to be off, and sets the floating diffusion region to the second capacitance value by controlling the transistor to be on.

2. The photoelectric conversion device according to claim 1.

3. The transistor is connected between the floating diffusion and a floating node.

3. The photoelectric conversion device according to claim 2.

4. A plurality of the transistors are connected in parallel between the floating diffusion and the floating node.

4. The photoelectric conversion device according to claim 3.

5. a reset unit that resets the floating diffusion unit to a potential corresponding to the power supply voltage, The transistor is connected between the reset portion and the floating diffusion portion.

3. The photoelectric conversion device according to claim 2.

6. The reset section and the floating diffusion section are connected in series to each other.

6. The photoelectric conversion device according to claim 5.

7. The control unit sets the capacitance value of the floating diffusion region by controlling the number of transistors to be turned on among the plurality of transistors.

5. The photoelectric conversion device according to claim 4.

8. The control unit sets the floating diffusion unit to a third capacitance value greater than the second capacitance value when an absolute value of the power supply voltage is a third voltage lower than the second voltage.

8. The photoelectric conversion device according to claim 7.

9. A plurality of the pixels are provided, Each of the plurality of pixels further includes a switch circuit provided between the floating diffusion portion of one pixel and the floating diffusion portion of another pixel, The control unit sets the capacitance value of the floating diffusion unit of the one pixel by controlling the switch circuit.

2. The photoelectric conversion device according to claim 1.

10. The control unit sets the floating diffusion of the one pixel to the first capacitance value by turning off the switch circuit to separate the floating diffusion of the one pixel from the floating diffusion of the other pixel, and sets the second capacitance value of the floating diffusion of the one pixel by turning on the switch circuit to connect the floating diffusion of the one pixel to the floating diffusion of the other pixel.

10. The photoelectric conversion device according to claim 9.

11. The control unit sets the capacitance value of the floating diffusion portion of the one pixel by controlling the number of the other pixels whose floating diffusion portions are connected to the floating diffusion portion of the one pixel by the switch circuit.

10. The photoelectric conversion device according to claim 9.

12. the switch circuit includes a first switch, a line, and a second switch, in this order, between the floating diffusion region of the one pixel and the floating diffusion region of the other pixel; The control unit sets the floating diffusion of the one pixel to the first capacitance value by setting the first switch and the second switch to off and disconnecting the wiring from the floating diffusion of the one pixel.

10. The photoelectric conversion device according to claim 9.

13. the switch circuit includes a first switch, a line, and a second switch, in this order, between the floating diffusion region of the one pixel and the floating diffusion region of the other pixel; The control unit sets the floating diffusion of the one pixel to the second capacitance value by setting the first switch on and the second switch off to provide a parasitic capacitance of the wiring to the floating diffusion of the one pixel.

10. The photoelectric conversion device according to claim 9.

14. The switch circuit is configured to connect the floating diffusion portion to the floating diffusion portion of the other pixel adjacent to the floating diffusion portion in the column direction.

14. The photoelectric conversion device according to claim 9, wherein the first and second electrodes are arranged in a first direction.

15. The switch circuit is configured to connect the floating diffusion portion to the floating diffusion portion of the other pixel adjacent to the floating diffusion portion in the row direction.

14. The photoelectric conversion device according to claim 9, wherein the first and second electrodes are arranged in a first direction.

16. When the power supply voltage is set to the second voltage, a voltage having a polarity opposite to that of the power supply voltage is applied to a well in which the pixel is disposed.

14. The photoelectric conversion device according to claim 1,

17. The voltage of the reverse polarity is set so that, when charges are transferred from the photoelectric conversion section to the floating diffusion section, all charges held in the photoelectric conversion section are transferred to the photoelectric conversion section.

17. The photoelectric conversion device according to claim 16.

18. The photoelectric conversion device according to any one of claims 1 to 13, a signal processing device that processes a signal output from the photoelectric conversion device; A photoelectric conversion system comprising:

19. A mobile object, The photoelectric conversion device according to any one of claims 1 to 13, a distance information acquiring means for acquiring distance information to an object from a parallax image based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object comprising:

20. The photoelectric conversion device according to any one of claims 1 to 13, an optical device corresponding to the photoelectric conversion device; A control device for controlling the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a mechanical device controlled based on information obtained by the photoelectric conversion device; A display device that displays information obtained by the photoelectric conversion device; and a storage device for storing information obtained by the photoelectric conversion device; An apparatus comprising:

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