Power conversion device

Abstract

To provide a power conversion device that can reduce surge voltage and switching loss even when a turn-off current difference is large due to characteristic variations between semiconductor switching elements.SOLUTION: A power conversion device has a configuration in which multiple electrical paths each including a semiconductor switching element and a reflux diode are connected in parallel. Among the multiple electrical paths, in a semiconductor switching element of the electrical path in which a turn-off current of each of the multiple semiconductor switching elements is the largest, a dynamic avalanche voltage generated between a collector and emitter of itself is smaller than a dynamic avalanche voltage generated between the collectors and emitters of the semiconductor switching elements included in the other electrical paths.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] In recent years, in the field of power electronics, power conversion devices for electric powertrains, such as hybrid vehicles and electric vehicles, have been increasing the power capacity they can handle by connecting multiple semiconductor switching elements, such as IGBTs (Insulated Gate Bipolar Transistors), in parallel and switching them simultaneously. In this type of power conversion device, due to differences in characteristics between multiple semiconductor switching elements connected in parallel, wiring inductance, etc., an imbalance occurs in which the magnitude of the current flowing through the semiconductor switching elements and the surge voltage caused by the time rate of change (dI / dt) of the current flowing through the wiring inductance differ between the multiple semiconductor switching elements.

[0003] For example, when a semiconductor switching element transitions from an on state to an off state, at turn-off, if the semiconductor switching element has a large current to interrupt, a high surge voltage is generated between the collector and emitter of the semiconductor switching element due to L×dI / dt that occurs in the wiring inductance component L at the time of interruption.If this surge voltage exceeds the withstand voltage of the semiconductor switching element, an overcurrent will flow, and the semiconductor switching element may be destroyed. In order to avoid these problems and to reduce the maximum anticipated surge voltage, it is generally necessary to set the power converter to low-speed switching rather than high-speed switching, allowing a large loss in switching loss, but the larger the switching loss, the larger the required area of ​​the semiconductor switching element becomes, and the higher the product cost becomes.

[0004] Therefore, as a means for suppressing the imbalance between the current and surge voltage flowing between semiconductor switching elements, a method has been introduced in which a free wheel diode whose own voltage drop is smaller than the voltage drop of the other free wheel diodes is placed in the electrical path in which the impedance is maximum when a free wheel current flows among multiple electrical paths each of which includes a semiconductor switching element and a free wheel diode connected in inverse parallel, thereby reducing the imbalance caused by different current magnitudes among multiple electrical paths (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6866768 Summary of the Invention [Problem to be solved by the invention]

[0006] With reference to Patent Document 1, by arranging a semiconductor switching element whose on-voltage Von, which is the amount of voltage drop when an on-current flows through a semiconductor switching element, is smaller than the other elements in the electrical path with the largest impedance among multiple electrical paths, it is possible to reduce the current imbalance among multiple semiconductor switching elements connected in parallel and to reduce the worst value of the surge voltage during switching.

[0007] However, the cause of the imbalance in the current and its rate of change over time (dI / dt) at turn-off among multiple semiconductor switching elements connected in parallel is not only the on-voltage Von, but also the variations in the characteristics of the gate threshold voltage Vth, which is the boundary between the gate on and off, the resistance component Rg of the gate wiring resistance, and the gate input capacitance Cies, which is the sum of the gate-collector capacitance and the gate-emitter capacitance among the parasitic capacitances of the gate. Therefore, the method described in Patent Document 1 alone poses the problem that it is not possible to sufficiently suppress the surge voltage imbalance and the resulting increase in switching loss.

[0008] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a power conversion device that can reduce surge voltage imbalance and switching loss caused by a large difference in current flowing at turn-off between multiple semiconductor switching elements connected in parallel due to variation in characteristics. [Means for solving the problem]

[0009] The power conversion device according to the present disclosure comprises: A power conversion device comprising a plurality of semiconductor switching elements and a plurality of free wheel diodes connected in anti-parallel to each of the plurality of semiconductor switching elements, and a plurality of electrical paths each including the semiconductor switching elements and the free wheel diodes are connected in parallel, Among the multiple electrical paths, a semiconductor switching element in an electrical path in which the current flowing through each of the multiple semiconductor switching elements is maximum when the element is turned off is characterized in that the dynamic avalanche voltage generated between its own collector and emitter is smaller than the dynamic avalanche voltage generated between the collector and emitter of the semiconductor switching elements included in the other electrical paths. Effect of the Invention

[0010] According to the present disclosure, a power conversion device can be obtained that can reduce surge voltage imbalance and switching loss caused by a large difference in current flowing between multiple semiconductor switching elements connected in parallel at turn-off due to characteristic variations. [Brief description of the drawings]

[0011] [Figure 1] FIG. 1 is a schematic configuration diagram showing a power conversion device according to first to fifth embodiments. [Diagram 2] 2 is a detailed circuit diagram of a semiconductor switching element group 3 in the power conversion device shown in FIG. [Diagram 3]3 is a diagram illustrating current waveforms of semiconductor switching elements 3a and 3b shown in FIG. 2 in the power conversion devices according to the first to third embodiments. FIG. [Figure 4] 3 is a diagram showing an example of voltage waveforms of semiconductor switching elements 3a and 3b shown in FIG. 2 in the power conversion devices according to the first to third embodiments. FIG. [Diagram 5] 10 is a diagram illustrating current waveforms of semiconductor switching elements 3a and 3b shown in FIG. 2 in a power conversion device according to a fourth embodiment. FIG. [Figure 6] 10 is a diagram illustrating voltage waveforms of semiconductor switching elements 3a and 3b shown in FIG. 2 in a power conversion device according to a fourth embodiment. FIG. [Figure 7] 11 is a diagram illustrating current waveforms of semiconductor switching elements 3a and 3b shown in FIG. 2 in a power conversion device according to a fifth embodiment. FIG. [Figure 8] 10 is a diagram illustrating voltage waveforms of semiconductor switching elements 3a and 3b shown in FIG. 2 in a power conversion device according to a fifth embodiment. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, the present embodiment will be described with reference to the drawings. In each drawing, the same reference numerals indicate the same or corresponding parts. Note that Figs. 1 to 8 are related to one embodiment, and the present disclosure is not limited to these drawings.

[0013] Fig. 1 is a schematic configuration diagram showing a power conversion device according to all of the first to fifth embodiments. In Fig. 1, the power conversion device shows an inverter circuit, with a DC input power source 1 connected to the input side and a motor 9 as a load connected to the output side. The DC input power source 1 as a battery supplies a DC voltage. Here, when the power conversion device of the present disclosure is applied to an electric vehicle or a hybrid vehicle, the DC input power source 1 is typically composed of a secondary battery such as a nickel-metal hydride or lithium ion battery.

[0014] The inverter circuit is a three-phase inverter circuit having a smoothing capacitor 2 for removing voltage ripple and noise at the input stage, and a plurality of semiconductor switching element groups 3-8 connected in parallel. The three-phase inverter circuit outputs the output voltage of the smoothing capacitor 2 to three-phase output terminals Vu, Vv, and Vw as three-phase AC. The three-phase output terminals are connected to a motor 9 consisting of a generator, an electric motor, or the like, and supply the three-phase AC. Each of the semiconductor switching element groups 3-8 is configured to include a plurality of semiconductor switching elements.

[0015] Furthermore, in order to acquire the input voltage, the inverter circuit has a voltage sensor circuit 20 provided in parallel with the smoothing capacitor 2 in the input stage, and the voltage sensor value is taken into the control unit 10 via a signal line 31a. In addition, in order to acquire the output current, current sensor circuits 21a, 21b, and 21c are provided in each phase of the output stage up to the motor 9, and the current sensor values ​​are taken into the control unit 10 via signal lines 31b, 31c, and 31d.

[0016] The control unit 10 is a gate driver circuit, and the gates of the semiconductor switching element groups 3-8 are controlled by control lines 32a-32f to perform on / off control with a predetermined dead time between them. The semiconductor switching element group 3 is controlled by control line 32a, the semiconductor switching element group 4 is controlled by control line 32b, the semiconductor switching element group 5 is controlled by control line 32c, the semiconductor switching element group 6 is controlled by control line 32d, the semiconductor switching element group 7 is controlled by control line 32e, and the semiconductor switching element group 8 is controlled by control line 32f to perform switching operations.

[0017] Fig. 2 is a detailed circuit diagram of the semiconductor switching element group 3 of the power conversion device shown in Fig. 1. In Fig. 2, the semiconductor switching element group 3 is composed of a plurality of semiconductor switching elements, and here, an example is shown in which the semiconductor switching element group 3 is composed of semiconductor switching element 3a and semiconductor switching element 3b. Freewheeling diodes 3c and 3d are connected in anti-parallel between the collector and emitter of each of the semiconductor switching elements 3a and 3b. Then, between the collector-side coupling 51 and the emitter-side coupling 52, an electrical path including the semiconductor switching element 3a and the freewheeling diode 3c and an electrical path including the semiconductor switching element 3b and the freewheeling diode 3d are connected in parallel, and in the drawing, the left side is Phase A and the right side is Phase B.

[0018] Each of the semiconductor switching elements 3a and 3b has a parasitic capacitance 3e between the collector and emitter, between the gate and collector, and between the gate and emitter. The sum of the parasitic capacitances 3e between the gate and collector and between the gate and emitter is called the input capacitance Cies. Furthermore, in each of the semiconductor switching elements 3a and 3b, parasitic wiring inductances 41a and 41b exist on the wiring on the collector side, respectively, and parasitic wiring inductances 42a and 42b exist on the wiring on the emitter side, respectively. Here, the wiring inductances 41a, 42a of the semiconductor switching element 3a refer to the wiring inductance parasitic on the main wiring that forms the electrical path including the semiconductor switching element 3a and the freewheel diode 3c, and the wiring inductances 41b, 42b of the semiconductor switching element 3b refer to the wiring inductance parasitic on the main wiring that forms the electrical path including the semiconductor switching element 3b and the freewheel diode 3d.

[0019] Although each of the semiconductor switching elements 3a, 3b is also affected by the wiring inductance existing between the coupling parts 51, 52 and the smoothing capacitor 2 shown in Fig. 1, it is the wiring inductances 41a, 42a, 41b, 42b that affect the imbalance of the surge voltage between the semiconductor switching elements 3a and 3b. The wiring inductance of the main wiring exists mainly between the multiple semiconductor switching elements connected in parallel, and due to the structure of the bus bar that electrically connects the multiple semiconductor switching element groups and the smoothing capacitor 2.

[0020] The gate driver circuit of the control unit 10 is connected to each of the semiconductor switching elements 3a and 3b. The gate wiring resistance 11a of the semiconductor switching element 3a refers to the resistance component Rg that exists between the gate terminal of the semiconductor switching element 3a and the gate wiring joint 12, and the gate wiring resistance 11b of the semiconductor switching element 3b refers to the resistance component Rg that exists between the gate terminal of the semiconductor switching element 3b and the gate wiring joint 12. Although each semiconductor switching element 3a, 3b is also affected by the resistance component existing between the gate wiring coupling portion 12 and the control portion 10, it is the gate wiring resistances 11a, 11b that affect the imbalance in surge voltage between the semiconductor switching elements 3a and 3b.

[0021] Hereinafter, features of the semiconductor switching element groups mounted on the power conversion devices according to the first to fifth embodiments will be described with reference to Figures 3 to 8. Figures 3, 5, and 7 are diagrams illustrating examples of collector-emitter current waveforms, and Figures 4, 6, and 8 are diagrams illustrating examples of collector-emitter voltage waveforms. It is known that when an IGBT is turned off at a speed above a certain level, a phenomenon called dynamic avalanche occurs, and the surge voltage, which normally increases with increasing switching speed, saturates at a constant value independent of the switching speed. The voltage generated between the collector and emitter of the semiconductor switching element at this time is defined as the dynamic avalanche voltage Vda. 3 to 8, points X, Y, and Z indicate the portions where the solid and dashed waveforms overlap, and for ease of explanation, the dashed lines are shifted upward to distinguish between the solid and dashed lines.

[0022] Embodiment 1 The features of the semiconductor switching element group in the power conversion device according to the first embodiment will be described with reference to Figs. 3 and 4. When a gate voltage is applied to the semiconductor switching element group, the resistance value between the collector and the emitter varies, and the IGBT switches between the on state and the off state. The gate voltage at which this switching occurs is defined as the gate threshold voltage Vth. In the configuration shown in FIG. 2 in which a plurality of semiconductor switching elements 3a, 3b are connected in parallel, a difference occurs in the gate threshold voltage Vth of each of the semiconductor switching elements 3a, 3b due to variation in the finishing characteristics, and, for example, a configuration is assumed in which the gate threshold voltage Vth of the B-phase semiconductor switching element 3b is greater than the gate threshold voltage Vth of the A-phase semiconductor switching element 3a.

[0023] In this configuration, an example of the waveform of a current that flows when the semiconductor switching element group 3 is turned off is shown in Figure 3. The solid line corresponds to the waveform of the A-phase semiconductor switching element 3a, and the dashed line corresponds to the waveform of the B-phase semiconductor switching element 3b. Figure 4 shows an example of a voltage waveform when the semiconductor switching element group 3 is turned off. The solid line corresponds to the waveform of the A-phase semiconductor switching element 3a, and the dashed line corresponds to the waveform of the B-phase semiconductor switching element 3b. In this configuration, when the semiconductor switching element group 3 is turned off, the semiconductor switching element 3b, which has a larger gate threshold voltage Vth, starts to turn off first, so that current flows concentratedly in the semiconductor switching element 3a, which has a smaller gate threshold voltage Vth, as shown by the solid line in FIG. 3. Since dI / dt becomes large when the current is cut off, a large surge voltage is generated in the semiconductor switching element 3a, as shown by the solid line in FIG. 4.

[0024] In the case of a single semiconductor switching element rather than a configuration in which multiple semiconductor switching elements are connected in parallel, the smaller the gate threshold voltage Vth of the element, the smaller the dI / dt when current is interrupted. However, in a configuration example according to the present disclosure in which multiple semiconductor switching elements are connected in parallel and the current to be interrupted is large and the switching speed is fast, the effect of a small gate threshold voltage Vth and a small dI / dt is outweighed by the effect of a large current at the time of interruption and an increase in dI / dt. As a result, a large surge voltage often occurs in a semiconductor switching element with a small gate threshold voltage Vth. In other words, if the gate threshold voltages Vth differ among multiple semiconductor switching elements due to variations in characteristics, then arranging a semiconductor switching element that does not cause the dynamic avalanche phenomenon will result in switching losses equivalent to this large surge voltage.

[0025] Therefore, as the semiconductor switching element group used in the power conversion device according to the first embodiment, the semiconductor switching elements having a small gate threshold voltage Vth and which are likely to experience a large surge voltage at turn-off due to current concentration are arranged so that they have a smaller dynamic avalanche voltage Vda than the other elements. In the configuration example of Fig. 2, this corresponds to the gate threshold voltage Vth of the semiconductor switching element 3a being smaller than the gate threshold voltage Vth of the semiconductor switching element 3b, and the dynamic avalanche voltage Vda of the semiconductor switching element 3a being smaller than the dynamic avalanche voltage Vda of the semiconductor switching element 3b. With this configuration, even in a situation where a large surge voltage would normally occur, the dynamic avalanche phenomenon occurs between t1 and t2 as shown by the dotted line in Figure 4, and the surge voltage is rate-limited by the dynamic avalanche voltage Vda, making it possible to reduce the peak value of the surge voltage during switching. As a result, it is possible to reduce the switching loss of the semiconductor switching element 3a, which would otherwise have had the largest switching loss.

[0026] According to the first embodiment, in order to effectively reduce the peak value of the surge voltage and the switching loss during switching, it is preferable to arrange a semiconductor switching element whose gate threshold voltage Vth is small and whose dynamic avalanche voltage Vda is smaller than the dynamic avalanche voltage Vda of a semiconductor switching element included in another electrical path in an electrical path in which the current flowing at the time of turn-off is maximum. With this configuration, the peak value of the surge voltage can be reduced to the lowest level, and the effect of reducing switching loss is maximized. Incidentally, if a semiconductor switching element that causes the dynamic avalanche phenomenon is located in the electrical path through which the current flowing at turn-off is the largest, then even if an element with a dynamic avalanche voltage Vda that is not smaller than the others is placed in the electrical path, it is possible to expect the effect of lowering the peak value of the surge voltage and reducing switching losses. However, in order to maximize the effect of reducing chip size by reducing switching losses, it is necessary to place an element with a dynamic avalanche voltage Vda smaller than the others.

[0027] Embodiment 2 The characteristics of the semiconductor switching element group in the power conversion device according to the second embodiment will be described with reference to Figs. 3 and 4. In the configuration in which the semiconductor switching elements 3a and 3b shown in Fig. 2 are connected in parallel, the gate wiring resistors 11a and 11b vary in characteristics due to finish variations in the gate resistor elements connected to the gate wiring at the end of the branch on the wiring connected from the gate driver circuit of the control unit 10 to the gates of the semiconductor switching elements 3a and 3b, and variations in the thickness and shape of the gate wiring. When an example of a current waveform that flows when the semiconductor switching element group 3 is turned off is described with reference to Fig. 3, the solid line corresponds to the waveform of the semiconductor switching element 3a of phase A, and the dashed line corresponds to the waveform of the semiconductor switching element 3b of phase B. An example of a voltage waveform when the semiconductor switching element group 3 is turned off is shown in Fig. 4, where the solid line corresponds to the waveform of the semiconductor switching element 3a of phase A, and the dashed line corresponds to the waveform of the semiconductor switching element 3b of phase B.

[0028] For example, if the gate wiring resistance 11b of phase B is smaller than the gate wiring resistance 11a of phase A, when the semiconductor switching element group 3 is turned off, the semiconductor switching element 3b connected to the smaller gate wiring resistance 11b will start to turn off first, and as shown by the solid line in FIG. 3, current will flow concentratedly in the semiconductor switching element 3a connected to the larger gate wiring resistance 11a, and since the dI / dt at the time of current interruption will be large, a large surge voltage will be generated in the semiconductor switching element 3a as shown by the solid line in FIG. 4.

[0029] Regarding the second embodiment, in the case of only a single semiconductor switching element rather than a configuration in which multiple semiconductor switching elements are connected in parallel as in the first embodiment, the larger the gate wiring resistance of the element, the smaller the dI / dt when current is interrupted. However, in the configuration example of the present disclosure in which multiple semiconductor switching elements are connected in parallel and the current to be interrupted is large and the switching speed is fast, the effect of large gate wiring resistance and small dI / dt is outweighed by the effect of large current at interruption and increased dI / dt. As a result, a large surge voltage often occurs in a semiconductor switching element with large gate wiring resistance. In other words, if the gate wiring resistance connected to the gate differs among multiple semiconductor switching elements due to variations in characteristics, arranging a semiconductor switching element that does not cause the dynamic avalanche phenomenon will result in switching losses equivalent to this large surge voltage.

[0030] Therefore, as a group of semiconductor switching elements used in the power conversion device according to the second embodiment, semiconductor switching elements that have a large gate wiring resistance and are prone to have a large surge voltage at turn-off due to current concentration are arranged so that they have a smaller dynamic avalanche voltage Vda than the other elements. In the configuration example of Fig. 2, this corresponds to the fact that the gate wiring resistance 11a of semiconductor switching element 3a is larger than the gate wiring resistance 11b of semiconductor switching element 3b, and the dynamic avalanche voltage Vda of semiconductor switching element 3a is smaller than the dynamic avalanche voltage Vda of semiconductor switching element 3b. With this configuration, even in a situation where a large surge voltage would normally occur, the dynamic avalanche phenomenon occurs between t1 and t2 as shown by the dotted line in Figure 4, and the surge voltage is rate-limited by the dynamic avalanche voltage Vda, making it possible to reduce the peak value of the surge voltage during switching. As a result, it is possible to reduce the switching loss of the semiconductor switching element 3a, which would otherwise have had the largest switching loss.

[0031] According to the second embodiment, in order to efficiently reduce the peak value of the surge voltage during switching and the switching loss, it is preferable to arrange a semiconductor switching element whose dynamic avalanche voltage Vda is smaller than the dynamic avalanche voltage Vda of a semiconductor switching element included in another electrical path in an electrical path in which the gate wiring resistance connected to the gate terminal of the semiconductor switching element is large and the current flowing at the time of turn-off is maximum. With this configuration, the peak value of the surge voltage can be reduced the most, and the effect of reducing switching loss is maximized.

[0032] Embodiment 3 The characteristics of the semiconductor switching element group in the power conversion device according to the third embodiment will be described with reference to Figs. 3 and 4. The switching speed when turning off the semiconductor switching element depends on the capacitance parasitic to the semiconductor switching element, particularly the gate input capacitance Cies, which is the sum of the gate-collector capacitance and the gate-emitter capacitance. Even when the semiconductor switching element is driven by the same gate voltage and gate wiring resistance, the larger the input capacitance Cies, the slower the switching speed becomes, and conversely, the smaller the input capacitance Cies, the faster the switching speed becomes. In the configuration shown in Fig. 2 in which a plurality of semiconductor switching elements 3a and 3b are connected in parallel, the input capacitance Cies of the semiconductor switching elements 3a and 3b varies due to the variation in the finished characteristics of the semiconductor switching elements 3a and 3b.

[0033] An example of a current waveform that flows when the semiconductor switching element group 3 is turned off is explained using Figure 3, where the solid line corresponds to the waveform of the semiconductor switching element 3a of phase A and the dashed line corresponds to the waveform of the semiconductor switching element 3b of phase B. An example of a voltage waveform when the semiconductor switching element group 3 is turned off is shown in Figure 4, where the solid line corresponds to the waveform of the semiconductor switching element 3a of phase A and the dashed line corresponds to the waveform of the semiconductor switching element 3b of phase B.

[0034] For example, if the input capacitance Cies of phase B is smaller than the input capacitance Cies of phase A, when the semiconductor switching element group 3 is turned off, the semiconductor switching element 3b, which has the smaller input capacitance Cies, starts to turn off first. As a result, as shown by the solid line in Figure 3, current flows concentratedly in the semiconductor switching element 3a, which has the larger input capacitance Cies, and dI / dt at the time of current interruption becomes large, so that a large surge voltage is generated in the semiconductor switching element 3a, as shown by the solid line in Figure 4. In other words, if the gate input capacitances Cies differ among multiple semiconductor switching elements due to variations in characteristics, then arranging a semiconductor switching element that does not cause the dynamic avalanche phenomenon will result in switching losses equivalent to this large surge voltage.

[0035] Therefore, as a group of semiconductor switching elements used in the power conversion device according to the third embodiment, semiconductor switching elements having large gate input capacitances Cies and which are prone to large surge voltages at turn-off due to current concentration are arranged so that they have smaller dynamic avalanche voltages Vda than the other elements. In the configuration example of Fig. 2, this corresponds to the input capacitance Cies of semiconductor switching element 3a being larger than the input capacitance Cies of semiconductor switching element 3b, and the dynamic avalanche voltage Vda of semiconductor switching element 3a being smaller than the dynamic avalanche voltage Vda of semiconductor switching element 3b. With this configuration, even in a situation where a large surge voltage would normally occur, the dynamic avalanche phenomenon occurs between t1 and t2 as shown by the dotted line in Figure 4, and the surge voltage is rate-limited by the dynamic avalanche voltage Vda, making it possible to reduce the peak value of the surge voltage during switching. As a result, it is possible to reduce the switching loss of the semiconductor switching element 3a, which would otherwise have had the largest switching loss.

[0036] According to the third embodiment, in order to efficiently reduce the peak value of the surge voltage during switching and the switching loss, it is preferable to place a semiconductor switching element in an electrical path in which the input capacitance Cies of the semiconductor switching element is large and the current flowing at the time of turn-off is maximum, and the dynamic avalanche voltage Vda of the semiconductor switching element is smaller than the dynamic avalanche voltage Vda of the semiconductor switching element included in the other electrical path. With this configuration, the peak value of the surge voltage can be reduced to the greatest extent, and the effect of reducing switching loss is maximized.

[0037] Embodiment 4 The features of the semiconductor switching element group in the power conversion device according to the fourth embodiment will be described with reference to Figs. 5 and 6. When an on-current flows through a semiconductor switching element that is in an on-state due to a gate voltage, the voltage drop amount caused by a resistance component on the current path of the element is defined as an on-voltage Von. In the configuration in which a plurality of semiconductor switching elements 3a, 3b are connected in parallel as shown in Fig. 2, there may be cases where the on-voltage Von generated in the semiconductor switching element 3b of phase B is larger than the on-voltage Von generated in the semiconductor switching element 3a of phase A due to variations in the finish characteristics of the semiconductor switching elements 3a, 3b.

[0038] In this case, the current flowing through semiconductor switching element 3a becomes larger than the current flowing through semiconductor switching element 3b, as shown by the solid line in Fig. 5. As a result, when the group of semiconductor switching elements 3 is turned off, the current flows concentratedly through semiconductor switching element 3a, which has a small on-voltage Von, and dI / dt at the time of current interruption becomes large, generating a large surge voltage in semiconductor switching element 3a, as shown by the solid line in Fig. 6. In other words, if the on-voltage Von when the on-current flows differs among multiple semiconductor switching elements due to variation in characteristics, then arranging a semiconductor switching element that does not cause the dynamic avalanche phenomenon will result in switching losses equivalent to this large surge voltage.

[0039] Therefore, as a group of semiconductor switching elements used in the power conversion device according to embodiment 4, semiconductor switching elements that have a small on-voltage Von and are prone to have a large surge voltage at turn-off due to current concentration are arranged so that they have a smaller dynamic avalanche voltage Vda than the other elements. In the configuration example of Fig. 2, this corresponds to the on-voltage Von of semiconductor switching element 3a being smaller than the on-voltage Von of semiconductor switching element 3b, and the dynamic avalanche voltage Vda of semiconductor switching element 3a being smaller than the dynamic avalanche voltage Vda of semiconductor switching element 3b. With this configuration, even in a situation where a large surge voltage would normally occur, the dynamic avalanche phenomenon occurs between t1 and t2 as shown by the dotted line in Figure 6, and the surge voltage is rate-limited by the dynamic avalanche voltage Vda, making it possible to reduce the peak value of the surge voltage during switching. As a result, it is possible to reduce the switching loss of the semiconductor switching element 3a, which would otherwise have had the largest switching loss.

[0040] According to the fourth embodiment, in order to efficiently reduce the peak value of the surge voltage during switching and the switching loss, it is preferable to place a semiconductor switching element whose own dynamic avalanche voltage Vda is smaller than the dynamic avalanche voltage Vda of a semiconductor switching element included in another electrical path in an electrical path in which the on-voltage Von is small when an on-current flows through the semiconductor switching element and the current flowing at the time of turning off is maximum. With this configuration, the peak value of the surge voltage can be reduced the most, and the effect of reducing switching loss is maximized.

[0041] In the first to fourth embodiments, the factors that cause an imbalance in the current and its rate of change over time (dI / dt) at turn-off among multiple semiconductor switching elements are focused on the differences in the gate threshold voltage Vth, the resistance component Rg of the gate wiring resistance, the gate input capacitance Cies, and the on-voltage Von, which is the amount of voltage drop, due to characteristic variations. However, even if a configuration focuses on the differences in wiring inductance due to characteristic variations among multiple electrical paths connected in parallel, the peak value of the surge voltage during switching and the switching loss can be efficiently reduced, as in the first to fourth embodiments. As will be explained below as embodiment 5, a semiconductor switching element whose own dynamic avalanche voltage Vda is smaller than the dynamic avalanche voltage Vda of semiconductor switching elements included in other electrical paths may be arranged in an electrical path among multiple electrical paths connected in parallel that has a large wiring inductance and is estimated to have the largest surge voltage during switching.

[0042] Embodiment 5. The characteristics of the semiconductor switching element group in the power conversion device according to the fifth embodiment will be described with reference to Figs. 7 and 8. In the configuration in which a plurality of semiconductor switching elements 3a, 3b are connected in parallel as shown in Fig. 2, an imbalance in wiring inductance may occur between phase A and phase B due to the asymmetry of the electrical path and structural reasons such as the connection to the smoothing capacitor 2 shown in Fig. 1. Furthermore, when the thickness and shape of the wiring vary, the value of the wiring inductance of each phase varies. As a result, a difference occurs in the surge voltage generated during switching between the semiconductor switching elements 3a and 3b included in the semiconductor switching element group 3.

[0043] Figure 7 shows an example of the waveform of the current that flows when the semiconductor switching element group 3 is turned off. The solid line corresponds to the waveform of the A-phase semiconductor switching element 3a, and the dashed line corresponds to the waveform of the B-phase semiconductor switching element 3b. Figure 8 shows an example of the voltage waveform when the semiconductor switching element group 3 is turned off. The solid line corresponds to the waveform of the A-phase semiconductor switching element 3a, and the dashed line corresponds to the waveform of the B-phase semiconductor switching element 3b.

[0044] When the wiring inductance present on the A-phase electrical path is larger than the wiring inductance present on the B-phase electrical path, even if there is no difference between the A-phase and B-phase current waveforms shown in FIG. 7, a surge voltage larger than the surge voltage applied to the B-phase semiconductor switching element 3b shown by the dashed line in FIG. 8 will be generated in the A-phase semiconductor switching element 3a, as shown by the solid line in FIG. 8. In other words, if the wiring inductances of multiple electrical paths connected in parallel differ due to variations in characteristics, then placing a semiconductor switching element that does not cause the dynamic avalanche phenomenon will result in switching losses equivalent to this large surge voltage.

[0045] Therefore, in the power conversion device according to the fifth embodiment, a semiconductor switching element with a smaller dynamic avalanche voltage Vda than the others is arranged in an electrical path with a large wiring inductance and a high surge voltage. In the configuration example of Fig. 2, this corresponds to the sum of wiring inductances 41a and 42a being larger than the sum of wiring inductances 41b and 42b, and the dynamic avalanche voltage Vda of semiconductor switching element 3a being smaller than the dynamic avalanche voltage Vda of semiconductor switching element 3b. With this configuration, even in a situation where a large surge voltage would normally occur, the dynamic avalanche phenomenon occurs between t1 and t2 as shown by the dotted line in Figure 8, and the surge voltage is rate-limited by the dynamic avalanche voltage Vda, making it possible to reduce the peak value of the surge voltage during switching. As a result, it is possible to reduce the switching loss of the semiconductor switching element 3a, which would otherwise have had the largest switching loss.

[0046] According to the fifth embodiment, in order to efficiently reduce the peak value of the surge voltage during switching and the switching loss, it is preferable to place a semiconductor switching element whose dynamic avalanche voltage Vda is smaller than the dynamic avalanche voltage Vda of the semiconductor switching element included in the other electric paths in an electric path where the wiring inductance is large and where the surge voltage during switching is estimated to be the largest. With this configuration, the peak value of the surge voltage can be reduced the most, and the effect of reducing switching loss is maximized.

[0047] As described above, the power conversion devices according to embodiments 1 to 5 can be configured regardless of the magnitude of the current flowing through the main wiring, but may also be configured using semiconductor switching elements that cause a dynamic avalanche phenomenon only when an overcurrent larger than the rated current set for the power conversion device flows. The dynamic avalanche phenomenon is caused by the local generation of a strong electric field region due to charge accumulation inside a semiconductor switching element, so it depends on the magnitude of the current flowing through the semiconductor switching element. Some semiconductor switching elements may not cause the dynamic avalanche phenomenon until they are turned off at a certain current value or higher. By performing appropriate circuit design, it is possible to suppress unexpected increases in element temperature even when current flows intensively for a short period of time through a semiconductor switching element with a smaller dynamic avalanche voltage Vda than others.

[0048] In other words, if a power conversion device is configured using semiconductor switching elements that do not cause a dynamic avalanche phenomenon within the rated current range of the power conversion device, but that cause a dynamic avalanche phenomenon only when an overcurrent flows through the power conversion device, the effect of reducing switching losses within the rated current range as described in embodiments 1 to 5 cannot be obtained, but the surge voltage generated by L×dI / dt when an overcurrent is interrupted can be suppressed, and the effect of protecting the power conversion device, such as the semiconductor switching elements and inverter circuits, from overvoltage and improving reliability can be obtained. Furthermore, there is no concern that the element temperature may unexpectedly rise due to current concentration in the semiconductor switching element caused by the dynamic avalanche phenomenon within the rated current range, and this has the effect of facilitating thermal design.

[0049] In addition, the semiconductor switching elements of the power conversion devices according to the first to fifth embodiments are assumed to have a configuration in which the IGBT and the free wheel diode are provided separately, but may be configured using an RC-IGBT (Reverse Conducting IGBT) in which the IGBT and the free wheel diode are integrated into the same chip. Since the RC-IGBT incorporates the IGBT and the free wheel diode into the same chip, the wiring path of the main wiring is short, resulting in a configuration with small wiring inductance.

[0050] When the wiring inductance of the main wiring is small, even if the switching speed is increased, the surge voltage may not increase, so in order to minimize switching loss, the switching speed of the semiconductor switching elements is often designed to be high. The higher the switching speed, the more significant the effect on surge voltage caused by the difference in current between multiple semiconductor switching elements connected in parallel and the difference in wiring inductance on the wiring path becomes, so the effect of suppressing surge voltage and reducing switching loss by using RC-IGBT can be further enhanced.

[0051] In the power conversion devices according to the first to fifth embodiments, the devices are configured with a focus on parameters such as the gate threshold voltage Vth of the semiconductor switching element, the resistance component Rg of the gate wiring resistance, the gate input capacitance Cies, the on-voltage Von which is the amount of voltage drop due to the on-current, or the wiring inductance of the electrical path. However, the devices may be configured by combining a number of parameters that have a large effect on the imbalance of the surge voltage, such as by arranging a semiconductor switching element with a smaller dynamic avalanche voltage Vda in an electrical path in which a semiconductor switching element with a large gate threshold voltage Vth and a small on-voltage Von is arranged, and a semiconductor switching element with a smaller dynamic avalanche voltage Vda in an electrical path in which the surge voltage is estimated to be maximum may be arranged.

[0052] The degree to which the surge voltage during switching depends on each parameter varies depending on the configuration and operating conditions of the power conversion device. Therefore, by estimating in advance the parameters that are expected to have a large effect on each power conversion device and determining where to place the semiconductor switching elements with smaller dynamic avalanche voltage Vda than the others depending on the magnitude of those parameters, it is possible to efficiently suppress the surge voltage and reduce switching losses.

[0053] The power conversion devices according to the first to fifth embodiments have been described as inverter circuits, but this is not limited thereto and may be converter circuits, and as long as they include a configuration in which a plurality of semiconductor switching elements are connected in parallel, they can achieve the same problem-solving effects as those of the respective embodiments. In addition, the power conversion devices according to embodiments 1 to 5 have been described as having a two-parallel configuration of multiple semiconductor switching elements, but this is not limited to this, and similar effects can be achieved with a three-parallel or more parallel configuration as long as multiple semiconductor switching elements are connected in parallel.

[0054] Furthermore, in the power conversion devices according to the first to fifth embodiments, a configuration using a plurality of semiconductor switching elements and a plurality of free wheel diodes has been described, but this is not limited thereto, and a configuration using a power module in which each semiconductor switching element is incorporated as a pair with each free wheel diode may also be used. In this case, the plurality of power modules are configured in parallel, or the plurality of semiconductor switching elements and the plurality of free wheel diodes are built into a single power module as a whole or in part, and even if one or a plurality of power modules are used, the same problem-solving effects as those of the respective embodiments can be achieved. Furthermore, in the power conversion devices according to embodiments 1 to 5, the configuration has been described as being for the semiconductor switching element group on the upper arm side, but the configuration may also be for the semiconductor switching element group on the lower arm side, or for both the upper arm and the lower arm, and similar effects can be achieved.

[0055] Although the present disclosure describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments are not limited to application to a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not exemplified are assumed within the scope of the technology disclosed in this specification, including, for example, modifying, adding, or omitting at least one component, and further, extracting at least one component and combining it with a component of another embodiment. Various aspects of the present disclosure are summarized below as appendices.

[0056] (Appendix 1) A power conversion device comprising: a plurality of semiconductor switching elements; and a plurality of free wheel diodes connected in anti-parallel to each of the plurality of semiconductor switching elements, wherein a plurality of electrical paths each including the semiconductor switching elements and the free wheel diodes are connected in parallel, A power conversion device characterized in that, among the plurality of electrical paths, a semiconductor switching element of the electrical path in which a current flowing through each of the plurality of semiconductor switching elements is maximum when the semiconductor switching elements are turned off has a dynamic avalanche voltage generated between its own collector and emitter that is smaller than the dynamic avalanche voltage generated between the collector and emitter of the semiconductor switching elements included in the other electrical paths. (Appendix 2) The power conversion device described in Appendix 1, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than the others has a gate threshold voltage that is smaller than the gate threshold voltages of the other semiconductor switching elements included in the electrical path. (Appendix 3) The power conversion device described in Appendix 1, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than the others has a gate wiring resistance connected to its gate that is greater than the gate wiring resistance connected to the gate of the other semiconductor switching elements included in the electrical path. (Appendix 4) The power conversion device described in Appendix 1, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than the others has a sum of its own gate-collector capacitance and gate-emitter capacitance greater than the sum of the gate-collector capacitance and gate-emitter capacitance of the other semiconductor switching elements included in the electrical path. (Appendix 5) The power conversion device described in Appendix 1, characterized in that when an on-current flows through each of the multiple semiconductor switching elements, the semiconductor switching element having a smaller dynamic avalanche voltage than the others has a smaller voltage drop amount than the voltage drop amounts of the other semiconductor switching elements included in the electrical path. (Appendix 6) A power conversion device comprising: a plurality of semiconductor switching elements; and a plurality of free wheel diodes connected in anti-parallel to each of the plurality of semiconductor switching elements, wherein a plurality of electrical paths each including the semiconductor switching elements and the free wheel diodes are connected in parallel, A power conversion device characterized in that, among a plurality of the electrical paths, a semiconductor switching element of an electrical path in which the wiring inductance that is maximum among the respective wiring inductances exists has a dynamic avalanche voltage generated between its own collector-emitter that is smaller than the dynamic avalanche voltage generated between the collector-emitter of the semiconductor switching element included in the other electrical paths. (Appendix 7) The power conversion device according to any one of claims 1 to 6, wherein the semiconductor switching element and the free wheel diode are RC-IGBTs formed as a pair within a single semiconductor chip. (Appendix 8) A power conversion device as described in any one of Supplementary Note 1 to Supplementary Note 7, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than the others causes a dynamic avalanche phenomenon only when a current exceeding a rated current of the power conversion device flows through each of the multiple electrical paths. (Appendix 9) A power conversion device comprising: a plurality of semiconductor switching elements; and a plurality of free wheel diodes connected in anti-parallel to each of the plurality of semiconductor switching elements, wherein a plurality of electrical paths each including the semiconductor switching elements and the free wheel diodes are connected in parallel, A power conversion device characterized in that a semiconductor switching element whose dynamic avalanche voltage generated between its own collector-emitter is smaller than the dynamic avalanche voltage generated between the collector-emitter of the semiconductor switching element included in the other electrical paths is disposed in the electrical path in which the current flowing when the semiconductor switching element is turned off is maximized based on at least one parameter selected from a plurality of parameters including the gate threshold voltage of each of the plurality of semiconductor switching elements, the gate wiring resistance, the gate input capacitance, and the amount of voltage drop due to the on-current. (Appendix 10) The power conversion device described in Appendix 9, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than others is arranged in the electrical path in which the current flowing when the semiconductor switching element is turned off is maximized by a combination of two or more parameters from among the plurality of parameters. (Appendix 11) The power conversion device described in Appendix 9, characterized in that the multiple parameters include the wiring inductance of each of the multiple electrical paths, and the electrical path in which the semiconductor switching element having the dynamic avalanche voltage smaller than others is arranged is the electrical path in which the current flowing when the semiconductor switching element is turned off is the maximum, or the electrical path in which the wiring inductance that is the maximum among the wiring inductances is located. (Appendix 12) The power conversion device according to any one of appendix 9 to appendix 11, wherein the plurality of semiconductor switching elements and the plurality of free wheel diodes are each paired as a plurality of power modules individually incorporated or as a single power module incorporated as a whole. (Appendix 13) The power conversion device according to any one of Supplementary Note 9 to Supplementary Note 12, wherein the power conversion device operates as an inverter circuit or a converter circuit. [Explanation of symbols]

[0057] 1: DC input power supply, 2: smoothing capacitor, 3-8: semiconductor switching element group, 3a, 3b: semiconductor switching elements, 3c, 3d: freewheeling diode, 3e: capacitance, 9: motor, 10: control unit, 11a, 11b: gate wiring resistance, 12: coupling portion, 20: voltage sensor circuit, 21a-21c: current sensor circuit, 31a-31d: signal lines, 32a-32f: control lines, 41a, 41b, 42a, 42b: wiring inductance, 51, 52: coupling portion, X, Y, Z: locations.

Claims

1. A power conversion device comprising: a plurality of semiconductor switching elements; and a plurality of free wheel diodes connected in anti-parallel to each of the plurality of semiconductor switching elements, wherein a plurality of electrical paths each including the semiconductor switching elements and the free wheel diodes are connected in parallel, A power conversion device characterized in that, among the plurality of electrical paths, a semiconductor switching element of an electrical path in which a current flowing through each of the plurality of semiconductor switching elements is maximum when the semiconductor switching elements are turned off has a dynamic avalanche voltage generated between its own collector and emitter that is smaller than the dynamic avalanche voltage generated between the collector and emitter of the semiconductor switching elements included in the other electrical paths.

2. The power conversion device according to claim 1, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than the others has a gate threshold voltage that is smaller than the gate threshold voltages of the other semiconductor switching elements included in the electrical path.

3. The power conversion device according to claim 1, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than the others has a gate wiring resistance connected to its gate that is larger than the gate wiring resistance connected to the gate of the other semiconductor switching elements included in the electrical path.

4. The power conversion device according to claim 1, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than the others has a sum of its own gate-collector capacitance and gate-emitter capacitance greater than the sum of the gate-collector capacitance and gate-emitter capacitance of the other semiconductor switching elements included in the electrical path.

5. The power conversion device according to claim 1, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than the others has a voltage drop amount that is smaller than the voltage drop amounts of the other semiconductor switching elements included in the electrical path when an on-current flows through each of the multiple semiconductor switching elements.

6. A power conversion device comprising: a plurality of semiconductor switching elements; and a plurality of free wheel diodes connected in anti-parallel to each of the plurality of semiconductor switching elements, wherein a plurality of electrical paths each including the semiconductor switching elements and the free wheel diodes are connected in parallel, A power conversion device characterized in that, among a plurality of the electrical paths, a semiconductor switching element of an electrical path in which the wiring inductance that is maximum among the respective wiring inductances exists has a dynamic avalanche voltage generated between its own collector-emitter that is smaller than the dynamic avalanche voltage generated between the collector-emitter of the semiconductor switching element included in the other electrical paths.

7. 7. The power conversion device according to claim 1, wherein the semiconductor switching element and the free wheel diode are RC-IGBTs formed as a pair on the same semiconductor chip.

8. A power conversion device as described in any one of claims 1 to 6, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than the others causes a dynamic avalanche phenomenon only when a current exceeding a rated current of the power conversion device flows through each of the multiple electrical paths.

9. A power conversion device comprising: a plurality of semiconductor switching elements; and a plurality of free wheel diodes connected in anti-parallel to each of the plurality of semiconductor switching elements, wherein a plurality of electrical paths each including the semiconductor switching elements and the free wheel diodes are connected in parallel, A power conversion device characterized in that a semiconductor switching element whose dynamic avalanche voltage generated between its collector and emitter is smaller than the dynamic avalanche voltage generated between the collector and emitter of the semiconductor switching element included in the other electrical paths is disposed in the electrical path in which the current flowing at the time of turning off of the semiconductor switching element is maximized based on at least one parameter selected from a plurality of parameters including the gate threshold voltage of each of the plurality of semiconductor switching elements, the gate wiring resistance, the gate input capacitance, and the amount of voltage drop due to the on-current.

10. The power conversion device according to claim 9, characterized in that the semiconductor switching element having a smaller dynamic avalanche voltage than others is arranged in the electrical path in which the current flowing when the semiconductor switching element is turned off is maximized by a combination of two or more parameters from among the plurality of parameters.

11. The power conversion device of claim 9, characterized in that the multiple parameters include wiring inductances of each of the multiple electrical paths, and the electrical path in which the semiconductor switching element having the dynamic avalanche voltage smaller than others is arranged is the electrical path in which the current flowing when the semiconductor switching element is turned off is the maximum, or the electrical path in which the wiring inductance that is the maximum among the wiring inductances is located.

12. The power conversion device according to claim 9, wherein the plurality of semiconductor switching elements and the plurality of free wheel diodes are each paired as a plurality of power modules individually assembled or as a single power module assembled as a whole.

13. The power conversion device according to claim 9 , wherein the power conversion device operates as an inverter circuit or a converter circuit.

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