Semiconductor apparatus, method, and program

Abstract

To provide a semiconductor apparatus, a method, and a program for replacing data stored in a ROM.SOLUTION: A semiconductor apparatus according to the present disclosure comprises: a ROM (Read Only Memory) in which data is stored; a non-volatile memory in which replacement data for at least a portion of the data is stored; and a controller for, in response to a request to read data from a processor, either reading data from the ROM or reading the replacement data from the non-volatile memory.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device, a method, and a program, and, for example, to a semiconductor device, a method, and a program that enable replacement of data stored in a ROM. [Background technology]

[0002] Patent Document 1 discloses a microcomputer that is provided with a patch load ROM (Read Only Memory) that stores a patch load program and is selected by a start-up selection signal from a start-up selection circuit, thereby enabling patch correction. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2002-149431 A Summary of the Invention [Problem to be solved by the invention]

[0004] Not only in the microcomputer disclosed in Patent Document 1, but in semiconductor devices in general, it is required to make it possible to replace data stored in ROM.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present disclosure includes a ROM (Read Only Memory) in which data is stored, a non-volatile memory in which replacement data for at least a portion of the data is stored, and a controller that, in response to a data read request from a processor, either reads the data from the ROM or reads the replacement data from the non-volatile memory.

[0007] In a method according to one aspect of the present disclosure, a semiconductor device receives a read request for data stored in a Read Only Memory (ROM), and in response to the read request, either reads the data from the ROM or reads the replacement data from a non-volatile memory in which replacement data for at least a portion of the data is stored.

[0008] A program according to one aspect of the present disclosure causes a computer to receive a read request for data stored in a Read Only Memory (ROM) and, in response to the read request, either read the data from the ROM or read the replacement data from a non-volatile memory in which replacement data for at least a portion of the data is stored. Effect of the Invention

[0009] The present disclosure can provide a semiconductor device, a method, and a program that enable replacement of data stored in a ROM. [Brief description of the drawings]

[0010] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device that has been previously examined; [Diagram 2] 1 is a block diagram showing a configuration example of a semiconductor device according to a first embodiment; [Figure 3A] 4 is a flowchart showing an example of a representative process of the semiconductor device according to the first embodiment. [Figure 3B] 4 is a flowchart showing an example of a representative process of the semiconductor device according to the first embodiment. [Figure 4] FIG. 11 is a block diagram showing a configuration example of a semiconductor device according to a second embodiment. [Figure 5A] 11 is a flowchart showing an example of a representative process of the semiconductor device according to the second embodiment. [Figure 5B]11 is a flowchart showing an example of a representative process of the semiconductor device according to the second embodiment. [Figure 5C] 11 is a flowchart showing an example of a representative process of the semiconductor device according to the second embodiment. [Figure 5D] 11 is a flowchart showing an example of a representative process of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Hereinafter, the embodiments will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be interpreted narrowly based on the description in the drawings. Also, the same elements are given the same reference numerals, and duplicated explanations will be omitted.

[0012] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to the specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0013] Furthermore, in the following embodiments, the components (including operation steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of the components, etc., it is intended to include those that are substantially similar or similar to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, values, amounts, ranges, etc.).

[0014] Furthermore, the configurations or processes described in each embodiment can be combined with the configurations or processes described in other embodiments as appropriate.

[0015] <Preliminary review by inventors, etc.> Before describing the semiconductor device according to the present embodiment, a semiconductor device previously examined by the present inventors will be described.

[0016] In recent years, technologies such as connected cars and ADAS (Advanced Driver-Assistance Systems) have been developed in the automotive field. With the development of such technologies, many in-vehicle electronic devices such as in-vehicle cameras, drive recorders, and car navigation systems are installed in vehicles and connected to networks. When in-vehicle electronic devices are connected to a network, the risk of the in-vehicle electronic devices being exposed to cyber attacks from crackers and the like increases. Therefore, it has become even more important to improve the security of semiconductor devices installed in in-vehicle electronic devices.

[0017] Generally, among the codes stored in semiconductor devices, if a vulnerability is found in the code, the vulnerability is addressed by updating the code using a technology such as OTA (Over The Air). However, if a vulnerability is found in the code stored in a memory that cannot be changed after shipment, such as a Read Only Memory (ROM), it is difficult to fix the code.

[0018] 1 is a block diagram showing a configuration example of a semiconductor device S1 that has been previously examined to solve such a problem. The semiconductor device S1 includes a ROM 10, a ROM controller 20, a bus 30, and a CPU (Central Processing Unit) 40.

[0019] The ROM 10 stores an instruction code D1 to be executed by the CPU 40. The instruction code D1 stored in the ROM 10 cannot be modified, such as by overwriting. The ROM 10 is connected to an input terminal of a multiplexer 24 of the ROM controller 20. When the ROM 10 receives a command from the CPU 40 or the like, it outputs data on the ROM 10 corresponding to an address requested by the command to the ROM controller 20.

[0020] The ROM controller 20 has an address storage register 21, an AND circuit 22, a code storage register 23, and a multiplexer 24. The address storage register 21 stores information on an address AD1 at which a code to be replaced in the instruction code D1 is stored among the addresses stored in the ROM 10. The AND circuit 22 receives the read address RA output from the CPU 40 via the bus 30 and the address AD1 output from the address storage register 21. The AND circuit 22 outputs "1" as an output value when the input read address RA and address AD1 match, and outputs "0" as an output value when they do not match.

[0021] The code storage register 23 stores a replacement code CD1 used as a substitute for the code to be replaced in the instruction code D1. The replacement code CD1 is replacement data for part or all of the instruction code D1. The multiplexer 24 receives the instruction code D1 output from the ROM 10 and the replacement code CD1 output from the address storage register 21. The multiplexer 24 also receives the output value of the AND circuit 22 as a selection signal. When the selection signal is "0", the multiplexer 24 outputs the instruction code D1 as read data RD. On the other hand, when the selection signal is "1", the multiplexer 24 outputs the replacement code CD1 as read data RD.

[0022] The bus 30 connects the ROM controller 20 and the CPU 40. When the CPU 40 executes a read from a specific storage address of the instruction code D1, the CPU 40 outputs information on the storage address to be read as a read address RA. Then, as a result of outputting the read address RA, the CPU 40 acquires the read data RD output from the ROM controller 20 via the bus 30.

[0023] It is assumed that after the shipment of the semiconductor device S1, a vulnerability problem is discovered in the instruction code D1 in the ROM 10, and it becomes necessary to replace a part of it. In this case, after the semiconductor device S1 is started, an operation is performed in which the replacement code CD1 to be replaced is written into the code storage register 23, and the address AD1 of the replacement code CD1 is written into the address storage register 21. By performing this operation, when the CPU 40 reads the address AD1, the read destination of the ROM controller 20 is changed from the ROM 10 to the code storage register 23. Therefore, the CPU 40 reads the replacement code CD1 for the address AD1. This makes it possible to solve the vulnerability problem.

[0024] However, the technique shown in FIG. 1 has the following problems. (1) After the semiconductor device S1 is started once, the semiconductor device S1 needs to write to the address storage register 21 and the code storage register 23. Therefore, the semiconductor device S1 cannot replace the code that is read by the CPU 40 at the time of startup.

[0025] As a general security measure, it is considered to introduce a secure boot function to a semiconductor device, which checks the reliability of software executed on the semiconductor device before the software is executed. The secure boot function is executed by a code on a ROM (hereinafter, also referred to as BootROM code) pre-installed in the semiconductor device. However, with the technology shown in Fig. 1, when it becomes necessary to replace a part of the BootROM code, it is considered difficult to perform the replacement.

[0026] Furthermore, the technique shown in FIG. 1 also has the following problems. (2) Generally, a register has a small area, and therefore a small amount of data can be stored in the code storage register 23. Therefore, the code capacity that can be replaced in the instruction code D1 is small.

[0027] A semiconductor device described in the following embodiments can solve the above problems.

[0028] <Embodiment 1> [Configuration Description] 2 is a block diagram showing an example of a configuration of a semiconductor device S10 according to embodiment 1. The semiconductor device S10 includes a ROM 110, an NVM 120, a ROM controller 130, a bus 140, a CPU 150, and a PLC (Programmable Logic Controller) 160.

[0029] The ROM 110 stores an instruction code D11 to be executed by the CPU 150. The instruction code D11 stored in the ROM 110 cannot be modified, such as by overwriting. The instruction code D11 may be, for example, a Boot ROM code, but is not limited to this. When the ROM 110 receives a command from the CPU 150 or the like, it outputs data on the ROM 110 corresponding to an address requested by the command to the ROM controller 130. Hereinafter, the area in which the instruction code D11 is stored is also referred to as the area D11. The area D11 of the ROM 110 is connected to a first input terminal of the multiplexer 132.

[0030] The NVM (Non-Volatile Memory) 120 is a non-volatile memory that retains memory even when power is not supplied. The NVM 120 stores a replacement code RC1 used as a substitute for a code to be replaced in the instruction code D11. The replacement code RC1 is replacement data for a part or all of the instruction code D11. The NVM 120 also stores information on a replacement address RA1 (first address information) as an address in the storage address of the ROM 110 where the code to be replaced in the instruction code D11 is stored. Hereinafter, the area where the replacement code RC1 is stored is also referred to as an area RC1, and the area where the replacement address RA1 is stored is also referred to as an area RA1. The areas RC1 and RA1 are also collectively referred to as a patch area. The area RC1 of the NVM 120 is connected to a second input terminal of the multiplexer 132, and the area RA1 is connected to a first input terminal of the AND circuit 131.

[0031] After the semiconductor device S10 is manufactured, the data stored in the NVM 120 can be rewritten using the PLC 160. The NVM 120 may be, for example, a one-time programmable (OTP) memory that can be rewritten only once, but a specific example of the NVM 120 is not limited thereto.

[0032] The ROM controller 130 includes a circuit having an AND circuit 131 and a multiplexer 132. The area RA1 is connected to a first input terminal of the AND circuit 131, and the bus 140 is connected to a second input terminal of the AND circuit 131. Therefore, the read address RA output from the CPU 150 via the bus 140 and the replacement address RA1 read from the area RA1 are input to the AND circuit 131. If the input read address RA and the replacement address RA1 match, the AND circuit 131 outputs "1" as an output value, and if they do not match, the AND circuit 131 outputs "0" as an output value.

[0033] A first input terminal of the multiplexer 132 is connected to the area D11, and a second input terminal of the multiplexer 132 is connected to the area RC1. Therefore, the multiplexer 132 receives the instruction code D11 output from the ROM 110 and the replacement code RC1 output from the NVM 120. The multiplexer 132 also receives the output value of the AND circuit 131 as a selection signal. When the selection signal is "0", the multiplexer 132 outputs the instruction code D11 as the read data RD. On the other hand, when the selection signal is "1", the multiplexer 132 outputs the replacement code RC1 as the read data RD.

[0034] The bus 140 connects the ROM controller 130, the CPU 150, and the PLC 160 to one another. When the CPU 150 executes reading from a specific storage address in the ROM 110, the CPU 150 outputs information on the storage address to be read as a read address RA. Then, as a result of outputting the read address RA, the CPU 150 acquires the read data RD output from the ROM controller 130 via the bus 140.

[0035] The PLC 160 is a write sequencer that rewrites any data stored in the NVM 120 when a command from the CPU 150 or the like is received.

[0036] [Processing flow explanation] 3A and 3B are flowcharts showing an example of a typical process of the semiconductor device S10, and an overview of the process of the semiconductor device S10 will be described with reference to these flowcharts. Note that the description of each process that has already been described will be omitted as appropriate.

[0037] 3A, PLC 160 writes replacement address RA1 to area RA1 of NVM 120. PLC 160 also writes replacement code RC1, which is used as a substitute for the code to be replaced, to area RC1 of NVM 120 (step S11). PLC 160 executes the correction process described in step S11 in response to a command from CPU 150, for example, at the time of shipment of semiconductor device S10 or after shipment.

[0038] Next, the process performed after the start-up of the semiconductor device S10 after step S11 will be described with reference to Fig. 3B. When reading data from the ROM 110, the CPU 150 outputs information on the address to be read as a read address RA to the bus 140, thereby outputting a read request to the ROM controller 130 (step S12).

[0039] The ROM controller 130 changes its operation depending on whether the read address RA for which a read request is made matches the replacement address RA1 (step S13). If the read address RA matches the replacement address RA1 (Yes in step S13), the ROM controller 130 reads data from the area RC1 of the NVM 120, not from the ROM 110. The ROM controller 130 outputs the read replacement code RC1 to the bus 140 as read data RD (step S14).

[0040] On the other hand, if the read address RA does not match the replacement address RA1 (No in step S13), the ROM controller 130 reads data from the ROM 110. The ROM controller 130 outputs the read instruction code D11 as read data RD to the bus 140 (step S15).

[0041] [Effect description] As described above, the semiconductor device S10 is equipped with the NVM 120 to which data can be written even after the semiconductor device is shipped. When a read request is received, the ROM controller 130 reads and outputs the contents stored in the area RC1 of the NVM 120 instead of the data to be replaced among the instruction codes D11 stored in the ROM 110. Therefore, even if a defect such as a vulnerability is found in the code used at the start-up of the semiconductor device S10 after the shipment of the semiconductor device S10, the CPU 150 can obtain replacement data instead of the data to be replaced. In other words, the semiconductor device S10 can perform replacement processing using a patch to correct the Boot ROM code, and the problem (1) can be solved.

[0042] [Variation Description] In the first embodiment, the PLC 160 can also execute the following processes. Either a normal mode (first mode) or a special mode for testing (second mode) may be specified for the PLC 160 from outside the PLC 160, such as the CPU 150.

[0043] When the normal mode is specified, the PLC 160 does not execute the operation of writing the information of the replacement address RA1 or the replacement code RC1, or the information of the replacement address RA1 and the replacement code RC1, to the patch area of ​​the NVM 120. In the normal mode, even if a command to write to the patch area is sent to the PLC 160, the command is not executed and is invalid.

[0044] On the other hand, when the special mode is specified, the PLC 160 executes an operation of writing the information of the replacement address RA1 or the replacement code RC1, or the information of the replacement address RA1 and the replacement code RC1, to the patch area of ​​the NVM 120. The special mode is specified, for example, when a vulnerability is found in the semiconductor device S10 and the CPU 150 executes writing of replacement data.

[0045] In the variations described above, writing to the patch area is restricted in normal mode. Therefore, even if there is no need to write to the patch area, it is possible to prevent a situation in which instruction code is illegally replaced by writing to the patch area. In other words, it is possible to prevent abuse of the function of writing to the patch area.

[0046] <Embodiment 2> [Configuration Description] 4 is a block diagram showing a configuration example of a semiconductor device S20 according to embodiment 2. The semiconductor device S20 includes a ROM 210, an NVM 220, a ROM controller 230, a bus 240, a CPU 250, and a PLC 260. In the following description of the semiconductor device S20, the points already described in the description of the semiconductor device S10 will be omitted as appropriate.

[0047] The ROM 210 stores an instruction code D21 to be executed by the CPU 250 and an entry table E1 (first jump destination information) used for the CPU 250 to jump to an additional code area on the NVM 220. The instruction code D21 may be, for example, a Boot ROM code, but is not limited thereto. The entry table E1 includes a code to be read by the CPU 250. When the CPU 250 reads this code, the CPU 250 reads an address indicated in the jump destination table JT (second address information) stored in the NVM 220 and jumps to the read address. When the ROM 210 receives a command from the CPU 250 or the like, the ROM 210 outputs data on the ROM 210 corresponding to the address requested by the command to the ROM controller 230. Hereinafter, the area in which the instruction code D21 is stored is also referred to as an area D21. The area D21 of the ROM 210 is connected to a first input terminal of the multiplexer 232.

[0048] The NVM 220 is a non-volatile memory that retains memory even when power is not supplied. The NVM 220 stores a replacement code RC2 used as a substitute for the code to be replaced in the instruction code D21. The replacement code RC2 is a code (second jump destination information) of a relative jump instruction to the entry table E1 stored in the ROM 210. The NVM 220 also stores information on a replacement address RA2 (first address information) as an address in the storage addresses of the ROM 210 where the code to be replaced in the instruction code D21 read by the CPU 250 is stored. Hereinafter, the area where the replacement code RC2 is stored is also referred to as the area RC2, and the area where the replacement address RA2 is stored is also referred to as the area RA2. The areas RC2 and RA2 are also collectively referred to as the patch area (second area). The area RC2 of the NVM 120 is connected to a second input terminal of the multiplexer 132, and the area RA2 is connected to a first input terminal of the AND circuit 131.

[0049] Furthermore, NVM220 stores additional code AC, which is executed in place of code to be replaced in instruction code D21 when instruction code D21 is executed. Additional code AC is replacement data for part or all of instruction code D21. Furthermore, in NVM220, an entry address of additional code AC is stored in jump destination table JT. Hereinafter, the area of ​​NVM220 in which jump destination table JT is stored will also be referred to as area JT, and the area of ​​NVM220 in which additional code AC is stored will also be referred to as area AC. Furthermore, area JT and area AC will also be collectively referred to as additional code area (first area).

[0050] After the semiconductor device S20 is manufactured, it is possible to rewrite the data stored in the NVM 220 using the PLC 260. The NVM 220 may be, for example, an OTP memory, but a specific example of the NVM 220 is not limited to this.

[0051] The ROM controller 230 includes a circuit having an AND circuit 231 and a multiplexer 232. The configurations and operations of the AND circuit 231 and the multiplexer 232 are similar to those of the AND circuit 131 and the multiplexer 132 described in the first embodiment, and therefore detailed description thereof will be omitted.

[0052] The configurations and operations of the bus 240, the CPU 250, and the PLC 260 are similar to those of the bus 140, the CPU 150, and the PLC 160 shown in the first embodiment, and therefore a detailed description thereof will be omitted.

[0053] [Processing flow explanation] 5A to 5D are flowcharts showing an example of a typical process of the semiconductor device S20, and an overview of the process of the semiconductor device S20 will be described with reference to these flowcharts. Note that the description of each process that has already been described will be omitted as appropriate.

[0054] First, as shown in FIG. 5A, at the manufacturing stage of the semiconductor device S20, an entry table E1 is stored in the ROM 210 (step S21).

[0055] Next, the process performed after step S11 will be described with reference to Fig. 5B. The PLC 260 writes the replacement address RA2 to the area RA2 of the NVM 220. The PLC 260 also writes the code of the relative jump instruction as the replacement code RC2 to the area RC2 of the NVM 220 (step S22).

[0056] The PLC 260 writes the jump destination table JT including the entry address of the additional code AC into the area JT, and writes the additional code AC into the area AC (step S23). At this time, the PLC 260 writes a return command into the area AC so that the CPU 250 jumps to a predetermined position in the ROM 210 and reads data of the jump destination after the reading of the additional code AC is completed. The predetermined position may be, for example, the next command of the code replaced by the replacement code RC2 in the instruction code D21. Alternatively, the predetermined position may be the end of the function of the code replaced by the replacement code RC2. The PLC 260 executes the correction work process described in steps S22 and S23 in response to a command from the CPU 250, for example, at the time of shipping or after the shipping of the semiconductor device S20.

[0057] Next, the process performed after the start-up of the semiconductor device S10 after step S23 will be described with reference to Figures 5C and 5D. The CPU 250 outputs a read request to the ROM controller 230 (step S24). The details are the same as those of step S12.

[0058] The ROM controller 230 changes the operation depending on whether the read address RA for which a read request is made matches the replacement address RA2 (step S25). If the read address RA matches the replacement address RA2 (Yes in step S25), the ROM controller 230 reads the replacement code RC2 from the area RC2 instead of reading the instruction code D21 from the ROM 210. The ROM controller 230 outputs the replacement code RC2 to the bus 240 as read data RD (step S26). The details are the same as those of steps S13 and S14.

[0059] On the other hand, if the read address RA does not match the replacement address RA2 (No in step S25), the ROM controller 230 reads the instruction code D21 from the ROM 210 and outputs it as read data RD to the bus 240 (step S27). The details are the same as in step S15.

[0060] Next, the details of the process executed by the CPU 250 when step S26 is executed will be described with reference to Fig. 5B. As shown in Fig. 5A, when the read address RA matches the replacement address RA2, the replacement code RC2 is output as the read data RD to the bus 240. The CPU 250 reads out the replacement code RC2 (step S31).

[0061] The CPU 250 jumps to the entry table E1 stored in the ROM 210 by reading the replacement code RC2 (step S32). The CPU 250 reads the code included in the entry table E1 to read the entry address of the additional code AC from the jump destination table JT stored in the NVM 220 (step S33), and further jumps to the additional code AC indicated by the read entry address (step S34).

[0062] The CPU 250 reads and executes the additional code AC stored in the jump destination (step S35). By executing the additional code AC, a function is added to the instruction code D21, or a defect such as a vulnerability is dealt with. The CPU 250 jumps to a predetermined position in the ROM 210 by reading a return command from the area AC, and executes reading of the data of the jump destination (step S36).

[0063] [Effect description] For the same reason as in the semiconductor device S10 of the first embodiment, even if a defect such as vulnerability is found in the BootROM code after the semiconductor device S20 is shipped, the CPU 250 can obtain replacement data in place of the data to be replaced. Moreover, in the semiconductor device S20, it is possible to increase the code capacity of the replacement data compared to the case where the replacement data is stored in a register. Therefore, the problems (1) and (2) can be solved.

[0064] Also, the ROM 210 of the semiconductor device S20 stores an entry table E1 for jumping to an additional code area of ​​the NVM 220. A replacement code RC2 for jumping to the entry table E1 is stored in the patch area of ​​the NVM 220, and an additional code AC is stored in the additional code area. When the read address RA matches the replacement address RA2, the CPU 250 accesses the entry table E1 by referring to the replacement code RC2, accesses the additional code AC by referring to the entry table E1, and reads out the additional code AC. In this way, by using the entry table E1, the PLC 160 can make the CPU 250 jump to any location in the NVM 220 simply by writing a one-word instruction to the replacement code RC2.

[0065] When the additional code AC is a large-capacity code, the PLC 160 may not be able to store the additional code AC in the patch area, and may have to store the additional code AC in the additional code area outside the patch area. The additional code area may be outside the area where a relative jump is possible as viewed from the ROM 210. Even in such a case, the CPU 250 can jump to any location in the additional code area by using the entry table E1. Therefore, the semiconductor device S20 can use not only the patch area, but also the additional code area capable of storing a large-capacity code for storing the additional code. Therefore, since a large-capacity additional code can be introduced into the semiconductor device S20, the semiconductor device S20 can more flexibly respond to correction of instruction codes or addition of functions of instruction codes.

[0066] In addition, in the second embodiment, all data required for replacement can be stored in the ROM 210 and the NVM 220, and there is no need to provide other memories separately. Therefore, the number of circuit components required for the replacement process can be reduced. In other words, the configuration of the semiconductor device S20 can reduce the cost of the semiconductor device.

[0067] Moreover, the CPU 250 reads an entry address of the additional code AC from the jump destination table JT stored in the NVM 220 by referring to the entry table E1 stored in the ROM 210, and further jumps to the additional code AC indicated by the read entry address. Here, even if additional codes AC with different contents are required at multiple locations in the instruction code D21, the CPU 250 can read the additional code AC corresponding to the location of the instruction code D21 by setting the jump destination table JT for each additional code AC. Therefore, it becomes possible to flexibly introduce various additional codes AC into the semiconductor device S20.

[0068] Moreover, the additional code area is not connected to the ROM controller 230, and the patch area is connected to the ROM controller 230. Even in such a case, the CPU 250 can obtain the additional code AC stored in a portion of the NVM 220 that is not connected to the ROM controller 230. This makes it possible to freely change the connection configuration between the NVM 220 and the ROM controller 230, thereby increasing the degree of freedom in the circuit configuration of the semiconductor device S20.

[0069] The present disclosure is not limited to the above-described embodiment, and can be modified as appropriate without departing from the spirit and scope of the present disclosure.

[0070] For example, in the semiconductor device S10 in the first embodiment, any type of processor may be used instead of the CPU 150. In the ROM controller 130, any circuit element capable of executing the process shown in the above flowchart may be provided instead of the AND circuit and the multiplexer. In the semiconductor device S10, for example, at least one of the bus 140 and the PLC 160 may not be provided. The above-mentioned variations are similarly applicable to the semiconductor device S20 in the second embodiment.

[0071] Although the semiconductor device described in the above embodiment can be mounted in an in-vehicle electronic device such as an in-vehicle camera, a drive recorder, or a car navigation system, the devices in which the semiconductor device can be mounted are not limited to these.

[0072] Furthermore, in the present disclosure, a part or all of the processing executed by the ROM controller 130 or the ROM controller 230 can be realized by causing a CPU (Central Processing Unit) to execute a computer program.

[0073] The above-mentioned program includes a set of instructions (or software code) for making the computer perform one or more functions described in the embodiment when the program is loaded into the computer. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or the tangible storage medium includes a random-access memory (RAM), a read-only memory (ROM), a flash memory, a solid-state drive (SSD) or other memory technology, a CD-ROM, a digital versatile disc (DVD), a Blu-ray® disk or other optical disk storage, a magnetic cassette, a magnetic tape, a magnetic disk storage or other magnetic storage device. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or the communication medium includes an electrical, optical, acoustic, or other form of propagating signal.

[0074] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0075] S10, S20 Semiconductor device 110, 210 ROM 120, 220 NVM 130, 230 ROM controller 131, 231 AND circuit 132, 232 Multiplexer 140, 240 Bus 150, 250 CPUs 160, 260 PLC

Claims

1. A ROM (Read Only Memory) in which data is stored, a non-volatile memory storing replacement data for at least a portion of the data; a controller that executes, in response to a data read request from a processor, either reading the data from the ROM or reading the replacement data from the non-volatile memory. Semiconductor device.

2. the non-volatile memory further stores first address information indicating a storage address of the at least part of the data in the ROM; the controller reads the replacement data from the non-volatile memory when the address indicated by the read request is the same as the storage address indicated by the first address information; The semiconductor device according to claim 1 .

3. a sequencer which does not write the replacement data when a first mode is designated from the outside to an area in the non-volatile memory where the replacement data is stored, and which writes the replacement data when a second mode is designated from the outside to the area; The semiconductor device according to claim 1 .

4. the ROM stores first jump destination information for jumping to a first area of ​​the nonvolatile memory; a second area in the non-volatile memory stores second jump destination information for jumping to the first jump destination information, and the first area stores the replacement data; When the controller reads the replacement data from the non-volatile memory, the processor accesses the first jump destination information by referring to the second jump destination information stored in the second area, accesses the replacement data by referring to the first jump destination information, and reads the replacement data. The semiconductor device according to claim 1 .

5. the first area further stores second address information indicating a storage address of the replacement data; the processor accesses the second address information by referring to the first jump destination information, and reads the replacement data by referring to the second address information; The semiconductor device according to claim 4.

6. the first area of ​​the non-volatile memory is not connected to the controller, and the second area of ​​the non-volatile memory is connected to the controller; The semiconductor device according to claim 4.

7. Accepts a request to read data stored in a ROM (Read Only Memory); In response to the read request, the data is read from the ROM, or the replacement data is read from a non-volatile memory in which replacement data for at least a part of the data is stored. The method that the semiconductor device performs.

8. the non-volatile memory further stores first address information indicating a storage address of the at least part of the data in the ROM; the semiconductor device reads the replacement data from the non-volatile memory when the address indicated by the read request is the same as the storage address indicated by the first address information; The method of claim 7.

9. the semiconductor device does not write the replacement data to an area in the nonvolatile memory where the replacement data is stored when a first mode is specified from the outside, and writes the replacement data to an area in the nonvolatile memory where the replacement data is stored when a second mode is specified from the outside. The method of claim 7.

10. the ROM stores first jump destination information for jumping to a first area of ​​the nonvolatile memory; a second area in the non-volatile memory stores second jump destination information for jumping to the first jump destination information, and the first area stores the replacement data; When reading the replacement data from the non-volatile memory, the semiconductor device accesses the first jump destination information by referring to the second jump destination information stored in the second area, accesses the replacement data by referring to the first jump destination information, and reads the replacement data. The method of claim 7.

11. the first area further stores second address information indicating a storage address of the replacement data; the semiconductor device accesses the second address information by referring to the first jump destination information, and reads the replacement data by referring to the second address information; The method of claim 10.

12. Accepts a request to read data stored in a ROM (Read Only Memory); and causing the computer to execute, in response to the read request, either reading the data from the ROM or reading the replacement data from a non-volatile memory in which replacement data for at least a part of the data is stored. program.

13. the non-volatile memory further stores first address information indicating a storage address of the at least part of the data in the ROM; reading the replacement data from the non-volatile memory when the address indicated by the read request is the same as the storage address indicated by the first address information. The program according to claim 12.

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