Switch circuit

Abstract

To suppress a generated current of a parasitic bipolar transistor.SOLUTION: A switch circuit (1A) includes: a switching element (10) configured by a MOSFET formed on a semiconductor substrate; a target terminal (TMa); a first wire (WR1) provided between the switching element and the target element; a gate control circuit (20) configured to control a gate potential of the switching element; a second wire (WR2) provided between the target terminal and a base of a PNP type parasitic bipolar transistor (40A) added to the switching element in the semiconductor substrate; and a rectifying element (31) provided between a ground and a particular node (ND12) on the second wire and having a forward direction from the ground to the particular node.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a switch circuit. [Background technology]

[0002] In a switch circuit having a switching element, a gate signal is applied to the switching element to turn the switching element on or off. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-188429 A

[0004] [overview] When a switch circuit is formed on a semiconductor substrate, various parasitic elements including a parasitic bipolar transistor are formed. When a current is generated in a parasitic bipolar transistor, it may have an undesirable effect on the circuit operation.

[0005] The switch circuit of the present disclosure includes a switching element constituted by a MOSFET formed on a semiconductor substrate, a target terminal, a first wiring provided between the switching element and the target terminal, a gate control circuit configured to control a gate potential of the switching element, a second wiring provided between a base of a PNP type parasitic bipolar transistor added to the switching element in the semiconductor substrate and the target terminal, and a rectifying element provided between a specific node on the second wiring and ground and having a forward direction from ground to the specific node. [Brief description of the drawings]

[0006] [Figure 1] FIG. 1 is a configuration diagram of a switch circuit according to an embodiment of the present disclosure. [Diagram 2] FIG. 2 is an external perspective view of a semiconductor substrate according to an embodiment of the present disclosure. [Diagram 3] FIG. 3 is a vertical structure diagram of a transistor (MOSFET) according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating the formation of a parasitic bipolar transistor in a vertical structure of a transistor (MOSFET) according to an embodiment of the present disclosure. [Diagram 5] FIG. 5 is a configuration diagram of an example of a switch circuit according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a vertical structural diagram of the switching transistor in the switch circuit of FIG. [Figure 7] FIG. 7 is a configuration diagram of another example of a switch circuit according to an embodiment of the present disclosure. [Figure 8] FIG. 8 is a vertical structure diagram of a transistor in a gate control circuit in the switch circuit of FIG. [Figure 9] FIG. 9 is a configuration diagram of a reference switch circuit. [Figure 10] FIG. 10 is a diagram illustrating a current generated in the reference switch circuit of FIG. 9 when a negative voltage is applied. [Figure 11] FIG. 11 is a configuration diagram of another reference switch circuit. [Figure 12] FIG. 12 is an explanatory diagram of a current generated in the reference switch circuit of FIG. 11 when a negative voltage is applied. [Figure 13] FIG. 13 is an explanatory diagram of a current generated in a switch circuit in a negative voltage application state according to a first example belonging to an embodiment of the present disclosure. [Figure 14] FIG. 14 is an explanatory diagram of a current generated in a switch circuit in a negative voltage application state according to a second example belonging to an embodiment of the present disclosure. [Figure 15] FIG. 15 is a configuration diagram of a gate control circuit according to a third embodiment of the present disclosure. [Figure 16] FIG. 16 is a schematic configuration diagram of a current sensor according to a fourth example of the embodiment of the present disclosure. [Figure 17] FIG. 17 is a partial configuration diagram of a current sensor according to a fourth example of the embodiment of the present disclosure. [Figure 18] FIG. 18 is a timing chart showing the relationship between two clock signals and the states of four switches according to a fourth example belonging to an embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram showing the states of the switches according to a fourth example of the embodiment of the present disclosure.

[0007] [Detailed Description] Hereinafter, examples of the embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings, the same parts are given the same reference numerals, and duplicated descriptions of the same parts are omitted as a rule. In this specification, for the sake of simplicity, a symbol or code referring to information, signal, physical quantity, functional part, circuit, element or part, etc. may be written, and the name of the information, signal, physical quantity, functional part, circuit, element or part, etc. corresponding to the symbol or code may be omitted or abbreviated. For example, a switching transistor referred to by "10" (see FIG. 1) described later may be written as switching transistor 10 or abbreviated as transistor 10, but they all refer to the same thing.

[0008] First, some terms used in the description of the embodiments of the present disclosure will be explained. Ground refers to a reference conductor having a reference potential of 0V (zero volts), or refers to the potential of 0V itself. The reference conductor may be formed using a conductor such as a metal. The potential of 0V may also be called ground potential. In the embodiments of the present disclosure, a voltage shown without a particular reference represents a potential seen from ground. Level refers to the level of potential, and for any signal or voltage of interest, a high level has a higher potential than a low level.

[0009] For any transistor configured as a FET (field effect transistor) such as a MOSFET, the on state refers to a state in which the drain and source of the transistor are conductive, and the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state). The same applies to transistors not classified as FETs. Unless otherwise specified, MOSFETs are understood to be enhancement-type MOSFETs. MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor." For any transistor configured as a MOSFET, the gate-source voltage refers to the potential of the gate as viewed from the potential of the source.

[0010] Any switch can be composed of one or more FETs (field effect transistors), and when a switch is in the on state, both ends of the switch are conductive, whereas when a switch is in the off state, both ends of the switch are non-conductive. Hereinafter, the on and off states of any transistor or switch may be simply expressed as on and off.

[0011] For any signal having a high or low signal level, the period during which the signal level is high is referred to as a high-level period, and the period during which the signal level is low is referred to as a low-level period. Connections between multiple parts that form a circuit, such as any circuit elements, wiring, nodes, etc., may be understood to refer to electrical connections, unless otherwise specified.

[0012] 1 shows the configuration of a switch circuit 1 according to an embodiment of the present invention. The switch circuit 1 includes a switching transistor 10 (switching element), a gate control circuit 20, an electrostatic protection circuit 30, stabilizing resistors R1 and R2, a protection resistor R3, and wirings WR1 and WR2. The electrostatic protection circuit 30 includes an electrostatic protection diode 31 and a reverse current blocking diode 32. The switching transistor 10 is inserted between terminals TMa and TMb. The terminals TMa and TMb may also be considered to be included in the components of the switch circuit 1. The switching transistor 10 is an N-channel MOSFET. The switch circuit 1 is provided in a semiconductor integrated circuit formed on a semiconductor substrate (a semiconductor substrate 600 described below).

[0013] In FIG. 1, a transistor 40 is a parasitic bipolar transistor added to any of the MOSFETs constituting the switch circuit 1. Therefore, it is understood that the parasitic bipolar transistor 40 is included in the components of the switch circuit 1. The parasitic bipolar transistor 40 is a PNP-type bipolar transistor. The emitter of the parasitic bipolar transistor 40 is connected to ground. In FIG. 1, the MOSFET to which the parasitic bipolar transistor 40 is added is not limited. Therefore, in FIG. 1, the connection destination of the collector of the parasitic bipolar transistor 40 is undefined, but a specific example of the connection destination will be described later.

[0014] In FIG. 1, diodes Dx, Dy, and Dz are parasitic diodes added to the switching transistor 10. Therefore, it is understood that the parasitic diodes Dx, Dy, and Dz are included in the components of the switch circuit 1. The semiconductor structure that generates the parasitic diodes Dx, Dy, and Dz will be described later. The backgate and source of the switching transistor 10 are shorted. The backgate of the switching transistor 10 functions as the anodes of the parasitic diodes Dx and Dz. The drain of the switching transistor 10 functions as the cathode of the parasitic diode Dx. The anode of the parasitic diode Dy is connected to ground. The cathodes of the diodes Dy and Dz are connected to each other.

[0015] The wiring WR1 is provided between the terminal TMa and the switching transistor 10, and the terminal TMa is connected to the source of the switching transistor 10 through the wiring WR1. However, a protective resistor R3 is inserted in series on the wiring WR1. Specifically, the terminal TMa is connected to a first end of the protective resistor R3, and a second end of the protective resistor R3 is connected to the source of the switching transistor 10 by the wiring WR1. The drain of the switching transistor 10 is connected to the terminal TMb.

[0016] Only when the switching transistor 10 is on, the terminals TMa and TMb are electrically connected to each other, and a signal is transmitted between the terminals TMa and TMb. In this embodiment, the signal is transmitted between the terminals TMa and TMb as a signal supplied from a signal source (not shown) to the terminal TMa, and then to the terminal TMb. In this case, the terminal TMa corresponds to an input terminal, and the terminal TMb corresponds to an output terminal. However, the signal may be transmitted between the terminals TMa and TMb as a signal supplied from a signal source (not shown) to the terminal TMb, and then to the terminal TMa. The protective resistor R3 protects the circuit including the switching transistor 10 by limiting the current flowing from the terminal TMa to the switching transistor 10. However, the protective resistor R3 may be omitted, and in this case, the terminal TMa is directly connected to the source of the switching transistor 10 through the wiring WR1.

[0017] The cathodes of the diodes Dy and Dz and the base of the parasitic bipolar transistor 40 are formed in a common semiconductor region. Therefore, the cathodes of the diodes Dy and Dz and the base of the parasitic bipolar transistor 40 are connected to each other.

[0018] The wiring WR2 is provided between the terminal TMa and the base of the parasitic bipolar transistor 40, and the terminal TMa is connected to the base of the parasitic bipolar transistor 40 through the wiring WR2. However, stabilizing resistors R1 and R2 are inserted in series on the wiring WR2 as resistors for stabilizing the potential of the common semiconductor region. Specifically, the terminal TMa is connected to a first end of the stabilizing resistor R1, and a second end of the stabilizing resistor R1 and a first end of the stabilizing resistor R2 are connected to each other at a node ND12. The second end of the stabilizing resistor R2 is connected to the base of the parasitic bipolar transistor 40 by the wiring WR2.

[0019] The electrostatic protection circuit 30 protects a circuit including the switching transistor 10 from a surge voltage such as static electricity that may be input to the terminal TMa. The electrostatic protection diode 31 is a rectifying element for achieving this protection. The anode of the electrostatic protection diode 31 is connected to the ground. The cathode of the electrostatic protection diode 31 is connected to the cathode of the reverse current blocking diode 32, and the anode of the reverse current blocking diode 32 is connected to the terminal TMa. The reverse current blocking diode 32 prevents the generation of a current (reverse current) from the ground through the electrostatic protection diode 31 to the terminal TMa. The cathodes of the electrostatic protection diode 31 and the reverse current blocking diode 32 are connected to a node ND12. Each of the electrostatic protection diode 31 and the reverse current blocking diode 32 is formed by a PN junction formed on a semiconductor substrate (a semiconductor substrate 600 described later).

[0020] The gate control circuit 20 is connected to the gate of the switching transistor 10. The wiring to which the gate of the switching transistor 10 is connected is called the gate wiring WR. G The gate control circuit 20 controls the gate potential of the switching transistor 10 by supplying a gate signal to the gate of the switching transistor 10, thereby controlling the state of the switching transistor 10 to an on state or an off state.

[0021] Here, the structure of the transistor MM that can be used in the switch circuit 1 will be described. FIG. 2 is a schematic perspective view of the exterior of a semiconductor substrate 600 on which the transistor MM is formed. FIG. 3 is a vertical structure diagram of the transistor MM. The switch circuit 1 is included in a semiconductor integrated circuit formed on the semiconductor device 600. The switch circuit 1 can be considered to be configured with the semiconductor substrate 600. For clarity of explanation, a three-dimensional orthogonal coordinate system consisting of mutually orthogonal X-axis, Y-axis, and Z-axis is defined as shown in FIG. 2. A plane parallel to the X-axis and Y-axis is called the XY plane. Any semiconductor substrate such as the semiconductor substrate 600 has two surfaces that face each other, one of which is called the main surface (or front surface) and the other is called the back surface. The main surface and the back surface are parallel to the XY plane. Each element that constitutes the switch circuit 1 is formed on the main surface side of the semiconductor substrate 600. In the vertical structure of a semiconductor integrated circuit, the direction from the back surface toward the main surface is considered to be upward, and the opposite direction is considered to be downward.

[0022] The semiconductor substrate 600 is a P-type semiconductor substrate. In FIG. 3, the hexagonal regions with diagonal hatching represent oxide films formed by LOCOS (Local Oxidation of Silicon) or the like. A buried layer 602 is formed on the main surface side of the semiconductor substrate 600. The buried layer 602 is an N-type semiconductor region. The buried layer 602 is an N + In the semiconductor substrate 600, a P-type well 604, which is a P-type semiconductor region, is formed above the buried layer 602. A transistor MM is formed on the P-type well 604. The transistor MM is an N-type semiconductor region (N + A source region 611 and a drain region 612 are P-type semiconductor regions (P + The source region 611, the drain region 612, and the back gate region 615 are formed in the well 604 at positions spaced apart from one another. The transistor MM further includes a gate oxide film 613 formed on a region of the P-type well 604 located between the source region 611 and the drain region 612, and a gate electrode E formed on the gate oxide film 613. Gand a gate electrode E G corresponds to the gate of transistor MM.

[0023] The source region 611, the drain region 612, and the back gate region 615 are exposed on the upper side of the semiconductor substrate 600. On the upper side of the semiconductor substrate 600, the source region 611, the drain region 612, and the back gate region 615 are respectively connected to a source electrode E S , drain electrode E D , back gate electrode E BG The source region 611 and the source electrode E S The source of the transistor MM is formed by the drain region 612 and the drain electrode E D The drain of the transistor MM is formed by the back gate region 615 and the back gate electrode E BG It may be understood that the P-type semiconductor region (corresponding to a part of the well 604) located between the back gate region 615 and the buried layer 602 is also included in the components of the back gate of the transistor MM.

[0024] An N-type well 621 and an N-type diffusion region 622 (N + A well 621 is formed in a region above the buried layer 602 at a position where the well 604 is not provided, and a diffusion region 622 is formed on the well 621. The diffusion region 622 is exposed on the upper side.

[0025] The multiple elements formed on the semiconductor substrate 600 and the multiple regions provided on the semiconductor substrate 600 are appropriately isolated by PN junction isolation or dielectric isolation technology. Dielectric isolation is achieved by using an oxide film such as LOCOS. Details of such isolation are well known and will not be described here.

[0026] A P-type semiconductor substrate is prepared, and various processes are performed on the P-type semiconductor substrate to form a semiconductor integrated circuit including a transistor MM on the P-type semiconductor substrate. Of the entire region of the semiconductor substrate 600, a region that remains a P-type semiconductor region before and after the various processes is called a substrate region 601. The substrate region 601 is exposed on the back side of the semiconductor substrate 600 and is connected to the ground. In other words, the substrate region 601 is a P-type semiconductor region connected to the ground, and therefore has a ground potential. An N-type buried layer 602 is provided between the substrate region 601 and a P-type well 604. In addition, in a direction parallel to the XY plane, an N-type semiconductor region (621, 622) is also provided between the substrate region 601 and the P-type well 604. Therefore, the transistor MM formed on the well 604 becomes (or can become) a floating MOSFET electrically insulated from the substrate region 601.

[0027] The above vertical structure forms a parasitic bipolar transistor BP shown in FIG. 4 in the semiconductor substrate 600. The parasitic bipolar transistor BP is a PNP-type bipolar transistor that is added to the transistor MM when the transistor MM is fabricated. In the parasitic bipolar transistor BP, the substrate region 601 functions as an emitter, the buried layer 602 functions as a base, and the well 604 functions as a collector. The well 621 and the diffusion region 622 may also be considered to be included in the components of the base of the parasitic bipolar transistor BP.

[0028] The buried layer 602, the well 621, and the diffusion region 622 form an integrated N-type semiconductor region. It is also possible to leave the N-type semiconductor regions (602, 621, 622) in an open state without connecting them to any potential point. However, stabilizing resistors R1 and R2 are provided to stabilize the potential of the N-type semiconductor regions (602, 621, 622) based on the potential of the terminal TMa. In this embodiment, as shown in FIG. 4, the diffusion region 622 is connected to the terminal TMa through the stabilizing resistors R2 and R1. As a result, the potential of the N-type semiconductor region follows the potential of the terminal TMa, so that the breakdown voltage of the transistor MM is less likely to be violated (a state in which a voltage exceeding the breakdown voltage of the transistor MM is input to the transistor MM).

[0029] More specifically, the terminal TMa is connected to a first end of the stabilizing resistor R1, the second end of the stabilizing resistor R1 and the first end of the stabilizing resistor R2 are connected to each other at a node ND12, and the second end of the stabilizing resistor R2 is connected to the diffusion region 622 by the wiring WR2. Therefore, the N-type semiconductor region (602, 621, 622) that constitutes the base of the parasitic bipolar transistor BP is connected to the terminal TMa via the stabilizing resistors R2 and R1.

[0030] 5 shows the configuration of a switch circuit 1A, which is an example of the switch circuit 1. The parasitic bipolar transistor 40 in the switch circuit 1A is particularly referred to as a parasitic bipolar transistor 40A. In the switch circuit 1A, a transistor MM is used as a switching transistor 10. In the switch circuit 1A, a parasitic bipolar transistor BP of the transistor MM serving as the switching transistor 10 is the parasitic bipolar transistor 40A.

[0031] 6 shows the vertical structure of the switching transistor 10 in the switch circuit 1A. In the switch circuit 1A, the back gate of the switching transistor 10 functions as the collector of the parasitic bipolar transistor 40A. Therefore, as shown in FIG. 5, it can be understood that the collector of the parasitic bipolar transistor 40A is connected to the back gate of the switching transistor 10. The parasitic diode Dz corresponds to the PN junction of the well 604 and the buried layer 602 in the vertical structure of the switching transistor 10 in FIG. 6. The parasitic diode Dy corresponds to the PN junction of the substrate region 601 and the buried layer 602 in the vertical structure of the switching transistor 10 in FIG. 6. The parasitic diode Dx corresponds to the PN junction of the well 604 and the drain region 612 in the vertical structure of the switching transistor 10 in FIG. 6. S and back gate electrode E BG Since the two regions are short-circuited (although the short-circuiting is not shown in FIG. 6), the parasitic diode formed by the PN junction between the well 604 and the source region 611 is ignored in the circuit diagram of FIG.

[0032] 7 shows the configuration of a switch circuit 1B which is another example of the switch circuit 1. The parasitic bipolar transistor 40 in the switch circuit 1B is particularly referred to as a parasitic bipolar transistor 40B. In the switch circuit 1B, a transistor 21 is provided in a gate control circuit 20. The transistor 21 is an N-channel MOSFET, and the transistor MM is used as the transistor 21 in the switch circuit 1B. In the switch circuit 1B, the parasitic bipolar transistor BP of the transistor MM which serves as the transistor 21 is the parasitic bipolar transistor 40B.

[0033] The gate control circuit 20 uses the transistor 21 to control the gate potential of the switching transistor 10. An example of how to incorporate the transistor 21 into the gate control circuit 20 will be described later, but here it is assumed that the drain of the transistor 21 is connected to the gate of the switching transistor 10. However, the drain of the transistor 21 may not be connected to the gate of the switching transistor 10.

[0034] 8 shows the vertical structure of the transistor 21 in the switch circuit 1B. In the switch circuit 1B, the back gate of the transistor 21 functions as the collector of the parasitic bipolar transistor 40B. Therefore, as shown in FIG. 7, it can be understood that the collector of the parasitic bipolar transistor 40B is connected to the back gate of the transistor 21. When the drain of the transistor 21 is connected to the gate of the switching transistor 10, if a current is generated in the collector of the parasitic bipolar transistor 40B, the collector current of the parasitic bipolar transistor 40B flows through the parasitic diode of the transistor 21 to the gate wiring WR. G The parasitic diode of the transistor 21 here refers to a parasitic diode between the back gate and drain of the transistor 21, and has a forward direction from the back gate of the transistor 21 to the drain.

[0035] In the switch circuit 1B, the switching transistor 10 has the same vertical structure as the transistor MM, and the buried layer 602 for the switching transistor 10 is common to the buried layer 602 for the transistor 21. Therefore, in the switch circuit 1B, the cathodes of the parasitic diodes Dy and Dz of the switching transistor 10 and the base of the parasitic bipolar transistor 40B are connected to each other as shown in Fig. 7. However, as a modification, the buried layer 602 for the switching transistor 10 and the buried layer 602 for the transistor 21 may be different from each other, in which case the cathodes of the parasitic diodes Dy and Dz of the switching transistor 10 are not connected to the base of the parasitic bipolar transistor 40B.

[0036] In principle, it is assumed that a voltage of 0V or more is supplied to the terminal TMa from a signal source (voltage source) not shown. However, in some cases, a negative voltage (i.e., a voltage lower than the ground potential) may be applied to the terminal TMa from a signal source not shown. Hereinafter, the state in which a negative voltage (i.e., a voltage lower than the ground potential) is applied to the terminal TMa is referred to as a negative voltage applied state. Note that the signal source (not shown) is connected to the ground, and a current loop is formed that passes through the signal source and the ground.

[0037] The transistor MM according to the vertical structure of FIG. 3 is a floating MOSFET (N-channel MOSFET) electrically insulated from the substrate region 601. Normally, if a floating MOSFET is used, leakage current from the substrate region 601 can be suppressed even when a negative voltage is applied. However, if the base equivalent portion of the parasitic bipolar transistor 40 is connected to the terminal TMa via a resistor (stabilizing resistors R1 and R2 in FIG. 1), a current flows through the resistor when a negative voltage is applied. This current becomes the base current of the parasitic bipolar transistor 40, and a collector current is generated in the parasitic bipolar transistor 40. The collector current of the parasitic bipolar transistor 40 may have an undesirable effect on the circuit operation.

[0038] The switch circuit 1 (1A, 1B) can suppress the collector current of the parasitic bipolar transistor 40. In order to show the usefulness of the configuration of the switch circuit 1, first and second reference configurations will be described.

[0039] [First reference configuration] 9 is a configuration diagram of a reference switch circuit 901A according to the first reference configuration. Based on the switch circuit 1A in FIG. 5, the reference switch circuit 901A is obtained by replacing the stabilizing resistors R1 and R2 with a single stabilizing resistor R901. With this replacement, the node ND12 shown in FIG. 5 disappears, and therefore the cathodes of the diodes 31 and 32 in the reference switch circuit 901A are not connected to the wiring WR2. In the switch circuit 901A, the base equivalent portion (602, 621, 622) of the parasitic bipolar transistor 40A is connected to the terminal TMa through the stabilizing resistor R901 to stabilize the potential of the base equivalent portion.

[0040] As shown in FIG. 10, consider a case where a negative voltage VTM is applied to the terminal TMa in the reference switch circuit 901A. In this case, a current 911A of "(|VTM|-VBE1) / R901" flows from the base of the parasitic bipolar transistor 40A to the terminal TMa through the stabilizing resistor R901. In this equation, VBE1 represents the base-emitter voltage of the parasitic bipolar transistor 40A, and R901 represents the resistance value of the stabilizing resistor R901. Since the current 911A is the base current of the parasitic bipolar transistor 40A, a collector current 912A proportional to the current 911A is generated in the parasitic bipolar transistor 40A. In the reference switch circuit 901A, the collector current 912A is supplied to the back gate of the switching transistor 10, and there is a concern that this may adversely affect the operation of the reference switch circuit 901A. For example, when the collector current 912A flows to the terminal TMb through the parasitic diode Dx, the component of the collector current 912A is mixed into the signal at the terminal TMb.

[0041] [Second reference configuration] Fig. 11 is a configuration diagram of a reference switch circuit 901B according to the second reference configuration. Based on the switch circuit 1B in Fig. 7, the reference switch circuit 901B is obtained by replacing the stabilizing resistors R1 and R2 with a single stabilizing resistor R901. With this replacement, the node ND12 shown in Fig. 7 disappears, and therefore the cathodes of the diodes 31 and 32 in the reference switch circuit 901B are not connected to the wiring WR2. In the switch circuit 901B, the base equivalent portion (602, 621, 622) of the parasitic bipolar transistor 40B is connected to the terminal TMa through the stabilizing resistor R901 to stabilize the potential of the base equivalent portion.

[0042] As shown in FIG. 12, consider a case where a negative voltage VTM is applied to the terminal TMa in the reference switch circuit 901B. In this case, a current 911B of "(|VTM|-VBE1) / R901" flows from the base of the parasitic bipolar transistor 40B to the terminal TMa through the stabilizing resistor R901. In this equation, VBE1 represents the base-emitter voltage of the parasitic bipolar transistor 40A, and R901 represents the resistance value of the stabilizing resistor R901. Since the current 911B is the base current of the parasitic bipolar transistor 40B, a collector current 912B proportional to the current 911B is generated in the parasitic bipolar transistor 40B. In the reference switch circuit 901B, the collector current 912B is supplied to the back gate of the transistor 21, and there is a concern that this may adversely affect the operation of the reference switch circuit 901B. For example, if the collector current 912B flows through the parasitic diode of the transistor 21 to the gate wiring WR G If the current flows into the switching transistor 10, it may not be possible to control the switching transistor 10 correctly.

[0043] Below, in a number of embodiments, examples of the operation of the switch circuit 1, application techniques, modified techniques, etc. that can address these inconveniences will be described. The matters described above in this embodiment are applied to each of the following embodiments (excluding matters related to the first and second reference configurations) unless otherwise specified and unless there is a contradiction. In the case of matters in each embodiment that contradict the matters described above, the description in each embodiment may take precedence. Furthermore, unless there is a contradiction, matters described in any of the following embodiments can also be applied to any of the other embodiments (i.e., any two or more of the embodiments can be combined).

[0044] <<First Example>> A description will now be given of a first embodiment. A switch circuit 1 according to the first embodiment is a switch circuit 1A shown in FIG.

[0045] 13, consider the case where a negative voltage VTM is applied to the terminal TMa in the switch circuit 1A. In this case, if the resistance values ​​of the stabilizing resistors R1 and R2 are represented by R1 and R2 and the forward voltage of the electrostatic protection diode 31 is represented by Vf, a forward current 610A of "(|VTM|-Vf) / R1" is generated in the electrostatic protection diode 31. At this time, if the base-emitter voltage of the parasitic bipolar transistor 40A is represented by VBE1, a current 611A of "(Vf-VBE1) / R2" flows from the base of the parasitic bipolar transistor 40A to the terminal TMa through the stabilizing resistors R1 and R2. However, it is assumed that "Vf>VBE1" is satisfied.

[0046] Since the current 611A is the base current of the parasitic bipolar transistor 40A, a collector current 612A proportional to the current 611A is generated in the parasitic bipolar transistor 40A. In the switch circuit 1A, the collector current 612A is supplied to the back gate of the switching transistor 10, but the magnitude of the collector current 612A is extremely small compared to the collector current 912A (see FIG. 10) in the reference switch circuit 901A. Therefore, the influence of the collector current of the parasitic bipolar transistor 40A is very small compared to the reference switch circuit 901A, and no substantial problem occurs or is unlikely to occur.

[0047] In order to effectively reduce the influence of the collector current of the parasitic bipolar transistor 40A, it is advisable to determine the structures of the electrostatic protection diode 31 and the switching transistor 10 and to determine the resistance values ​​of the stabilizing resistors R1 and R2 so that the forward current of the electrostatic protection diode 31 becomes larger than the base current of the parasitic bipolar transistor 40A under a negative voltage application state.

[0048] <<Second Example>> A second embodiment will now be described. The switch circuit 1 according to the second embodiment is a switch circuit 1B shown in FIG.

[0049] 14, consider the case where a negative voltage VTM is applied to the terminal TMa in the switch circuit 1B. In this case, if the resistance values ​​of the stabilizing resistors R1 and R2 are represented by R1 and R2 and the forward voltage of the electrostatic protection diode 31 is represented by Vf, a forward current 610B of "(|VTM|-Vf) / R1" is generated in the electrostatic protection diode 31. At this time, if the base-emitter voltage of the parasitic bipolar transistor 40B is represented by VBE1, a current 611B of "(Vf-VBE1) / R2" flows from the base of the parasitic bipolar transistor 40B to the terminal TMa through the stabilizing resistors R1 and R2. However, it is assumed that "Vf>VBE1" is satisfied.

[0050] Since the current 611B is the base current of the parasitic bipolar transistor 40B, a collector current 612B proportional to the current 611B is generated in the parasitic bipolar transistor 40B. In the switch circuit 1B, the collector current 612B is supplied to the back gate of the transistor 21, but the magnitude of the collector current 612B is extremely small compared to the collector current 912B (see FIG. 12) in the reference switch circuit 901B. Therefore, the influence of the collector current of the parasitic bipolar transistor 40B is extremely small compared to the reference switch circuit 901B, and no substantial problem occurs or is unlikely to occur.

[0051] In order to effectively reduce the influence of the collector current of the parasitic bipolar transistor 40B, it is advisable to determine the structures of the electrostatic protection diode 31 and the transistor 21 and to determine the resistance values ​​of the stabilizing resistors R1 and R2 so that the forward current of the electrostatic protection diode 31 is larger than the base current of the parasitic bipolar transistor 40B when a negative voltage is applied.

[0052] <<Third Example>> A third embodiment will be described. The switch circuit 1 according to the third embodiment is the switch circuit 1B shown in FIG. 7. In the third embodiment, a configuration example of the gate control circuit 20 in the switch circuit 1B is shown. FIG. 15 shows the configuration of a gate control circuit 20_1 which is the gate control circuit 20 according to the third embodiment. Note that FIG. 15 shows only a part of the configuration of the switch circuit 1B that is necessary for explaining the configuration of the gate control circuit 20_1. The gate control circuit 20_1 includes a gate drive circuit 25, a clamp circuit 26, a resistor 27, and a controller 28.

[0053] The gate drive circuit 25 is connected to the gate wiring WR via a resistor 27. G In detail, the gate drive circuit 25 has an output terminal 25a and a driver 25b, and the output terminal 25a is connected to a first terminal of a resistor 27. A second terminal of the resistor 27 is connected to the gate wiring WR G The gate wiring WR GThe gate of the switching transistor 10 is connected to the gate driver 25. The clamp circuit 26 is provided between the gate and source of the switching transistor 10. The controller 28 is connected to the gate driver 25 and outputs a control signal CNT to the gate driver 25. The control signal CNT is a binary signal having a value of "1" or "0".

[0054] The gate drive circuit 25 sets the state of the switching transistor 10 to an off state or an on state by supplying a gate signal to the gate of the switching transistor 10 based on the control signal CNT. In detail, an output signal of the driver 25b is generated at the output terminal 25a, and the output signal of the driver 25b is applied to a first terminal of the resistor 27 through the output terminal 25a. In the gate drive circuit 25, the driver 25b can output a low level signal or a high level signal from the output terminal 25a. When the control signal CNT has a value of "0", the driver 25b sets the state of the switching transistor 10 to an off state by outputting a low level signal from the output terminal 25a. When the control signal CNT has a value of "1", the driver 25b sets the state of the switching transistor 10 to an on state by outputting a high level signal from the output terminal 25a.

[0055] When the output signal of the driver 25b has a high level, the clamp circuit 26 clamps the gate-source voltage of the switching transistor 10 to a clamp voltage V CLMP The clamp circuit 26 is provided to speed up the response of the switching transistor 10 from on to off. In addition, even if a surge-like excessive voltage is transiently output from the output terminal 25a when the switching transistor 10 is switched from off to on, the withstand voltage of the switching transistor 10 is less likely to be violated (a voltage exceeding the withstand voltage of the switching transistor 10 is input).

[0056] The clamp circuit 26 is composed of a series circuit of multiple transistors provided between the gate and source of the switching transistor 10. Each transistor in the clamp circuit 26 is an N-channel MOSFET. In the example of FIG. 15, the number of MOSFETs connected in series in the clamp circuit 26 is three, but the number of series connections is arbitrary as long as it is two or more. The clamp circuit 26 in FIG. 15 is composed of transistors 26a to 26c, each of which is an N-channel MOSFET. Each of the transistors 26a to 26c may have the same vertical structure as the transistor MM.

[0057] In each of the transistors 26a to 26c, the drain and gate are shorted and the back gate and source are shorted. The transistors 26a, 26b, and 26c are connected in series in this order from the gate to the source of the switching transistor 10. More specifically, the drain and gate of the transistor 26a are connected to the gate of the switching transistor 10, the back gate and source of the transistor 26a are connected to the drain and gate of the transistor 26b, the back gate and source of the transistor 26b are connected to the drain and gate of the transistor 26c, and the back gate and source of the transistor 26c are connected to the source of the switching transistor 10. When the output signal of the driver 25b has a high level, the gate-source voltage of the switching transistor 10 is 3Vgs. 3Vgs is the sum of the gate-source voltages Vgs of the transistors 26a to 26c when the output signal of the driver 22 has a high level, and is equal to the clamp voltage V CLMP Even if the potential of the output terminal 25a becomes considerably high transiently when the output signal of the driver 22 has a high level, the transistors 26a to 26c become conductive, so that the increase in the gate-source voltage of the switching transistor 10 is limited to a voltage of 3Vgs. The voltage 3Vgs is greater than the gate threshold voltage of the switching transistor 10.

[0058] In the third embodiment, the transistor 26a in Fig. 15 corresponds to the transistor 21 in Fig. 7. Therefore, when a collector current is generated in the parasitic bipolar transistor of the transistor 26a (corresponding to the parasitic bipolar transistor 40B in Fig. 7) in a negative voltage application state, the collector current flows from the back gate of the transistor 26a through the parasitic diode of the transistor 26a to the gate wiring WR G and affecting the control of the switching transistor 10. However, because the configuration of the switch circuit 1B described above keeps the collector current of the parasitic bipolar transistor of the transistor 26a sufficiently low, no substantial problem occurs or is unlikely to occur.

[0059] Although the transistor 26a in the clamp circuit 26 is given as an example of the transistor 21 in FIG.

[0060] <<Fourth Example>> A fourth embodiment will be described. In the fourth embodiment, the application of the switch circuit 1 to a current sensor will be described. FIG. 16 shows a schematic configuration diagram of a current sensor according to the fourth embodiment. The current sensor includes a current detection amplifier 110 and a sense resistor R SNS The current detection amplifier 110 includes terminals TM1 to TM5, as well as a square wave generating circuit 111, a switch control circuit 112, a current detection signal output circuit 113, an internal power supply circuit 114, electrostatic protection circuits 115P and 115M, a clamp protection circuit 116, protection resistors RP and RM, terminals 121 and 122, and capacitors 123 and 124. The terminals TM1 to TM5 correspond to external terminals, and the terminals 121 and 122 correspond to internal terminals.

[0061] The current detection amplifier 110 is a semiconductor device (electronic component) including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a case (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the case to the outside of the current detection amplifier 110. The semiconductor device is formed by sealing the semiconductor chip in a case (package) made of resin. The circuits 111 to 114, 115P, 115M, and 116, the protective resistors RP and RM, and the capacitors 123 and 124, as well as the respective circuit elements constituting the current detection amplifier 110, are included in the semiconductor integrated circuit. Although only the terminals TM1 to TM5 are shown as the external terminals provided in the current detection amplifier 110 in FIG. 16, other external terminals may also be provided in the current detection amplifier 110.

[0062] The sense resistor R SNS A sense resistor R SNS One end of the sense resistor R SNS The other end of is connected to the terminal TM2. SNS The connection node with the voltage V CM Therefore, the terminal TM2 has a voltage V CM is added. Voltage V CM Hereinafter, this may be referred to as the common-mode voltage.

[0063] Terminal TM1 and sense resistor R SNS The connection node between the load LD and the low potential terminal TMM is connected to one end of the load LD, and the other end of the load LD is connected to the low potential terminal TMM. CM A voltage lower than the high potential terminal TMP is applied across the sense resistor R SNS Current I flows through the load LD LD Then, the sense resistor R SNS A current I LD A voltage drop occurs based on the sense resistor R SNS The voltage drop at the sense voltage V SNS Terminal TM1 is connected to the common-mode voltage V CM than the sense voltage V SNS The voltage (V CM-V SNS In the following, the voltage at terminal TM1 is represented by the symbol "V INM The voltage at terminal TM2 is sometimes referred to as “V INP Typically, the low potential end TMM may be ground, in which case the low potential end TMM has a ground potential. However, the voltage of the low potential end TMM may be a negative voltage. CM may also become negative voltage.

[0064] The current detection signal S (described later) is output from terminal TM3. OUT is output. A power supply voltage VDD is supplied to the terminal TM4. The power supply voltage VDD has a positive DC voltage value within a predetermined voltage range. The terminal TM5 is connected to the ground.

[0065] The square wave generating circuit 111 is connected to the terminal TM1 via a protective resistor RM and is also connected to the terminal TM2 via a protective resistor RP. The square wave generating circuit 111 is configured to generate a voltage V INM At the same time, the voltage V applied to terminal TM2 through the protective resistor RP INP The square wave generating circuit 111 includes a plurality of switches and receives a voltage V INP and V INM Based on the sense resistor R SNS The voltage across the SNS The square wave generating circuit 111 uses the above-mentioned multiple switches to output a square wave signal through terminals 121 and 122 (details will be described later). The terminals 121 and 122 correspond to the output terminals of the square wave generating circuit 111. The voltages applied to the terminals 121 and 122 are respectively represented by the symbol "V OUTM ", "V OUTP " for reference.

[0066] The switch control circuit 112 controls the state (on / off state) of each switch in the square wave generating circuit 111.

[0067] The current detection signal output circuit 113 detects the current of the sense resistor R SNS Current I LD Current detection signal S according to OUT and generates the current detection signal S OUT is output from terminal TM3 to an external circuit (not shown) of the current detection amplifier 110. OUT Based on the current I LD For example, the value of the current detection signal S OUT is the current I LD Alternatively, for example, the current detection signal S OUT is the current I LD A capacitor 123 is inserted between the terminal 121 and the circuit 113, and a capacitor 124 is inserted between the terminal 122 and the circuit 113. Therefore, the voltage V OUTM and V OUTP The AC components of the square wave signal output from the square wave generating circuit 111 are input to the circuit 113. The circuit 113 amplifies the AC components of the square wave signal output from the square wave generating circuit 111 to generate the current detection signal S OUT Generate and output

[0068] The internal power supply circuit 114 generates one or more internal power supply voltages based on the power supply voltage VDD supplied to the terminal TM4. Each circuit in the current detection amplifier 110 can be driven by the internal power supply voltage generated by the internal power supply circuit 114. Fig. 16 shows an internal power supply voltage Vreg as an example of the internal power supply voltage generated by the internal power supply circuit 114. The internal power supply voltage Vreg has a predetermined positive DC voltage value.

[0069] The electrostatic protection circuit 115M is connected between the terminal TM1 and ground. The electrostatic protection circuit 115M protects the square wave generating circuit 111 from static electricity that may be applied to the terminal TM1 outside the current detection amplifier 110. The electrostatic protection circuit 115P is connected between the terminal TM2 and ground. The electrostatic protection circuit 115P protects the square wave generating circuit 111 from static electricity that may be applied to the terminal TM2 outside the current detection amplifier 110.

[0070] A first end of the protective resistor RM is connected to the terminal TM1, and a second end of the protective resistor RM is connected to the node NDM. A first end of the protective resistor RP is connected to the terminal TM2, and a second end of the protective resistor RP is connected to the node NDP. The clamp protection circuit 116 is connected to the nodes NDP and NDM. The clamp protection circuit 116 cooperates with the protective resistors RP and RM to generate a current through the protective resistors RP and RM and itself when an excessive voltage is applied between the terminals TM1 and TM2, thereby suppressing the potential difference between the nodes NDP and NDM to a predetermined clamp protection voltage or less. This makes it possible to prevent an excessive voltage from being applied to the square wave generating circuit 111.

[0071] Furthermore, the protective resistor RM has a function of protecting the internal circuitry (including the square wave generating circuit 111) of the current detection amplifier 110 by limiting the current flowing between terminals TM1 and NDM when a voltage that is too high or too low with respect to the ground potential is applied to terminal TM1. Similarly, the protective resistor RP has a function of protecting the internal circuitry (including the square wave generating circuit 111) of the current detection amplifier 110 by limiting the current flowing between terminals TM2 and NDP when a voltage that is too high or too low with respect to the ground potential is applied to terminal TM2.

[0072] In the following, unless otherwise specified, it is assumed that the current detection amplifier 110 operates in a normal input state. In the normal input state, the voltage V INP and V INM is within the specified operating voltage range and the sense resistor R SNS The voltage across the SNS ) is equal to or less than a predetermined differential allowable voltage. In a normal input state, substantially no current flows through the protection resistors RP and RM, and therefore the voltages of the nodes NDM and NDP are equal to or less than the voltage V INM , V INP can be considered equal to.

[0073] 17 shows the internal configuration of the square wave generating circuit 111. The square wave generating circuit 111 includes switches SW1 to SW4. A first end of the switch SW1 and a first end of the switch SW3 are commonly connected to a node NDM. A second end of the switch SW1 is connected to a terminal 121, and a second end of the switch SW3 is connected to a terminal 122. A first end of the switch SW2 and a first end of the switch SW4 are commonly connected to a node NDP. A second end of the switch SW2 is connected to the terminal 122, and a second end of the switch SW4 is connected to the terminal 121.

[0074] The switch control circuit 112 includes a clock output circuit 130. The clock output circuit 130 generates and outputs clock signals CLK1 and CLK2. The clock signals CLK1 and CLK2 are square wave signals having a predetermined frequency and a predetermined amplitude. The frequencies of the clock signals CLK1 and CLK2 are the same, and the amplitudes of the clock signals CLK1 and CLK2 are also the same. However, the phases of the clock signals CLK1 and CLK2 are different from each other by 180°. That is, the clock signal CLK2 corresponds to an inverted signal of the clock signal CLK1. The clock signals CLK1 and CLK2 are supplied to a square wave generating circuit 111. The states (on / off states) of the switches SW1 to SW4 are individually controlled based on the clock signals CLK1 and CLK2.

[0075] 18 shows a timing chart illustrating the relationship between the clock signals CLK1 and CLK2 and the states of the switches SW1 to SW4. The clock signals CLK1 and CLK2 alternate between high and low signal levels. However, when the clock signal CLK1 is at high level, the clock signal CLK2 is at low level, and when the clock signal CLK1 is at low level, the clock signal CLK2 is at high level. The duty cycle of the clock signals CLK1 and CLK2 is arbitrary, but is assumed to be 50% here.

[0076] In each of the clock signals CLK1 and CLK2, the high level has a potential of the voltage Vreg, and the low level has a potential of 0 V. The voltage Vreg is, for example, 4 V. The sense voltage VSNS is the current I LD In Figure 18, the sense voltage V SNS is assumed to be constant.

[0077] The high level period of the clock signal CLK1 is referred to as the first period. The high level period of the clock signal CLK1 coincides with the low level period of the clock signal CLK2. The low level period of the clock signal CLK1 is referred to as the second period. The low level period of the clock signal CLK1 coincides with the high level period of the clock signal CLK2. After the supply of the power supply voltage VDD to the current detection amplifier 110 starts and a predetermined startup process is performed, the first period and the second period alternate.

[0078] FIG. 19 shows states ST1 and ST2, which are two states that the square wave generating circuit 111 can take. In the first period, the state of the square wave generating circuit 111 is state ST1, and in the second period, the state of the square wave generating circuit 111 is state ST2. In state ST1 (thus, in the first period), the switches SW1 and SW2 are in the on state, and the switches SW3 and SW4 are in the off state. In state ST2 (thus, in the second period), the switches SW1 and SW2 are in the off state, and the switches SW3 and SW4 are in the on state. That is, the switch control circuit 112 alternately switches the state of the square wave generating circuit 111 (in other words, the states of the switches SW1 to SW4) between states ST1 and ST2 by outputting the clock signals CLK1 and CLK2.

[0079] In state ST1, the voltage V at terminal TM1 INM The voltage of the node NDM, which is equal to INP A voltage of the node NDP equal to "V OUTP =V INP =V CM "And "V OUTM =V INM =V CM -V SNSIn state ST2, the voltage V INM The voltage of node NDM, which is equal to INP A voltage of the node NDP equal to "V OUTP =V INM =V CM -V SNS "And "V OUTM =V INP =V CM " is.

[0080] Voltage V OUTP and V OUTM Each of them is "V SNS / 2” as an amplitude. SNS However, the voltage V OUTP and V OUTM The phases of the terminals 121 and 122 are different from each other by 180 degrees. Therefore, a difference voltage (V OUTP -V OUTM ) is generated. OUTP -V OUTM ) is a square wave signal that represents “V SNS A square wave signal with an amplitude of 2×V SNS The current detection signal output circuit 113 outputs the difference voltage (V OUTP -V OUTM ) based on the square wave signal representing the sense voltage V SNS By extracting the information of the current I LD Current detection signal S according to OUT can be generated.

[0081] In this way, the current sense amplifier 110 SNS Using the differential voltage (V OUTP -V OUTM ) based on a square wave signal representing the current I LD The current detection signal S OUT is the current I LD The detection results are shown below.

[0082] The relationship between the current detection amplifier 110 and the switch circuit 1 will be described. First to fourth switch circuits 1 are incorporated in the current detection amplifier 110. The switching transistors 10 in the first to fourth switch circuits 1 are switches SW1 to SW4, respectively. First terminals of the switches SW1 to SW4 correspond to the sources of the switching transistors 10 in the first to fourth switch circuits 1, respectively. Second terminals of the switches SW1 to SW4 correspond to the drains of the switching transistors 10 in the first to fourth switch circuits 1, respectively.

[0083] The wiring connecting the switches SW1 and SW3 with the protective resistor RM corresponds to the wiring WR1 in the first and third switch circuits 1. The protective resistor RM corresponds to the protective resistor R3 in the first and third switch circuits 1, and the electrostatic protection circuit 115M corresponds to the electrostatic protection circuit 30 in the first and third switch circuits 1. The terminal TM1 corresponds to the terminal TMa in the first and third switch circuits 1. The wiring connecting the switches SW2 and SW4 with the protective resistor RP corresponds to the wiring WR1 in the second and fourth switch circuits 1. The protective resistor RP corresponds to the protective resistor R3 in the second and fourth switch circuits 1, and the electrostatic protection circuit 115P corresponds to the electrostatic protection circuit 30 in the second and fourth switch circuits 1. The terminal TM2 corresponds to the terminal TMa in the second and fourth switch circuits 1. The terminal 121 corresponds to the terminal TMb in the first and fourth switch circuits 1, and the terminal 122 corresponds to the terminal TMb in the second and third switch circuits 1.

[0084] The current detection amplifier 110 is provided with the stabilizing resistors R1 and R2 and the wiring WR2 shown in Fig. 1. However, to prevent the illustration from becoming complicated, the stabilizing resistors R1 and R2 and the wiring WR2 are not shown in Figs. 16, 17, and 19. The current detection amplifier 110 may be provided with sets of the stabilizing resistors R1 and R2 and the wiring WR2 for the first to fourth switch circuits 1. Alternatively, only one set of the stabilizing resistors R1 and R2 and the wiring WR2 may be provided for the first and third switch circuits 1, and the bases of the parasitic bipolar transistors 40 in the first and third switch circuits 1 may be connected to a common wiring WR2 (a wiring provided between the bases and the terminal TM1). Similarly, only one set of stabilizing resistors R1 and R2 and wiring WR2 may be provided for the second and fourth switch circuits 1, and the bases of the parasitic bipolar transistors 40 in the second and fourth switch circuits 4 may be connected to a common wiring WR2 (a wiring provided between the bases and the terminal TM2).

[0085] The gate control circuits 20 (see FIG. 1) in the first to fourth switch circuits 1 are incorporated into the switch control circuit 112. When the third and fourth embodiments are combined, a high-level clock signal CLK1 corresponds to the control signal CNT of "1" in the first and second switch circuits 1, and a low-level clock signal CLK1 corresponds to the control signal CNT of "0" in the first and second switch circuits 1. When the third and fourth embodiments are combined, a high-level clock signal CLK2 corresponds to the control signal CNT of "1" in the third and fourth switch circuits 1, and a low-level clock signal CLK2 corresponds to the control signal CNT of "0" in the third and fourth switch circuits 1.

[0086] In addition, the sense resistor R SNS The above description has been given of a configuration in which the sense resistor R SNS may be built into the current detection amplifier 110. In this case, the sense resistor R SNS The current sensor is formed by a single current detection amplifier 110 having the built-in current detection amplifier.

[0087] Also, the sense resistor R SNS The above description has been given of a configuration in which the sense resistor R is provided on the higher potential side than the load LD. SNS may be provided on the lower potential side than the load LD.

[0088] Furthermore, the voltage Vreg may be the power supply voltage VDD itself that is supplied to the terminal TM4 from outside the current detection amplifier 110. In this case, the internal power supply circuit 114 can be omitted from the current detection amplifier 110.

[0089] <<Fifth Example>> A fifth embodiment will now be described.

[0090] The switch circuit 1 or the current detection amplifier 110 can be applied to any application (for example, an analog front end of an in-vehicle sensor, an analog front end of a medical sensor, a magnetic sensor, or a pressure sensor). The switch circuit 1 or the current detection amplifier 110 may be installed in a vehicle such as an automobile, and the switch circuit 1 or the current detection amplifier 110 may be applied to any load LD in the vehicle. In in-vehicle electronic components that often require high voltage resistance, being able to handle negative voltage input is beneficial in that safety can be ensured even in cases where fluctuations occur in the ground potential. In addition, in the fourth embodiment, a semiconductor device as the current detection amplifier 110 is used as a component of a current sensor, but the application of the semiconductor device (110) is arbitrary. The semiconductor device (110) can be used as any device that detects and amplifies a differential voltage between terminals TM1 and TM2.

[0091] If an SOI (Silicon On Insulator) process is used, leakage current between the semiconductor substrate and the input terminal (corresponding to TMa, TM1, or TM2) during negative voltage input can be suppressed. However, the adoption of an SOI process complicates the structure of the semiconductor integrated circuit, which may result in an increase in the circuit area. According to the method of the present disclosure, it is possible to accommodate negative voltage input without complicating the structure of the semiconductor integrated circuit. Furthermore, when an SOI process is used, the silicon substrate becomes expensive. The method of the present disclosure is advantageous in terms of cost because it can be realized using a normal silicon substrate.

[0092] In a semiconductor, one of the N-type and P-type is a first conductivity type and the other is a second conductivity type. When forming an arbitrary circuit element (such as a MOSFET) on a semiconductor substrate, the relationship between the N-type and the P-type can be reversed from the above relationship.

[0093] For any signal or voltage, the relationship between the high level and the low level thereof may be reversed to that described above without prejudice to the spirit of the above.

[0094] The embodiments of the present disclosure can be modified in various ways as appropriate within the scope of the technical ideas set forth in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values ​​shown in the above description are merely examples, and can be changed to various numerical values ​​as a matter of course.

[0095] <<Additional Notes>> Regarding the present disclosure, specific configuration examples of which have been shown in the above-mentioned embodiments, additional notes will be provided.

[0096] A switch circuit (1A) according to one aspect of the present disclosure has a configuration (first configuration) including a switching element (10) constituted by a MOSFET formed on a semiconductor substrate, a target terminal (TMa), a first wiring (WR1) provided between the switching element and the target terminal, a gate control circuit (20) configured to control the gate potential of the switching element, a second wiring (WR2) provided between a base of a PNP-type parasitic bipolar transistor (40A) added to the switching element in the semiconductor substrate and the target terminal, and a rectifier element (31) provided between a specific node (ND12) on the second wiring and ground and having a forward direction from ground to the specific node.

[0097] When a base current flows through a PNP-type parasitic bipolar transistor added to a switching element, a collector current is generated in the parasitic bipolar transistor. The collector current of the parasitic bipolar transistor can affect the circuit operation. In the switch circuit having the above configuration, the base current (and therefore the collector current) of the parasitic bipolar transistor can be suppressed by installing a rectifier element, thereby reducing the above-mentioned effect.

[0098] In the switch circuit according to the first configuration, a first resistor (R1) and a second resistor (R2) may be inserted in series on the second wiring, the first resistor being provided between the target terminal and the specific node, and the second resistor being provided between the specific node and the base of the parasitic bipolar transistor (second configuration).

[0099] The switch circuit according to the second configuration may be configured (third configuration) to include an electrostatic protection circuit (30) that is provided between the target terminal and the ground and has the rectifying element as an electrostatic protection diode, the anode of the electrostatic protection diode being connected to the ground and the cathode of the electrostatic protection diode being connected to the specific node.

[0100] In the switch circuit according to the third configuration, the electrostatic protection circuit may be configured (fourth configuration) to further include a reverse current blocking diode (32) having an anode connected to the target terminal and a cathode connected to the specific node.

[0101] In the switch circuit according to any one of the first to fourth configurations, the semiconductor substrate may have a substrate region (601) which is a P-type semiconductor region to which a ground potential is applied, a first semiconductor region (604) which is another P-type semiconductor region, and a second semiconductor region (602) which is an N-type semiconductor region provided between the substrate region and the first semiconductor region, the switching element is formed on the first semiconductor region, a bipolar transistor formed by the substrate region, the first semiconductor region, and the second semiconductor region is added to the switching element as the parasitic bipolar transistor, a base of the parasitic bipolar transistor is formed by the second semiconductor region, and when a negative voltage is applied to the target terminal, a forward current of the rectifier element flowing from ground to the specific node and a base current of the parasitic bipolar transistor flowing from ground to the specific node are generated (fifth configuration).

[0102] When a negative voltage is applied to the target terminal, a base current may be generated in a PNP-type parasitic bipolar transistor added to the switching element. The base current generates a collector current in the parasitic bipolar transistor, and this collector current may affect the circuit operation. In the switch circuit having the above configuration, the base current (and therefore the collector current) of the parasitic bipolar transistor can be suppressed by installing a rectifier element, thereby reducing the above-mentioned effects.

[0103] The switch circuit according to the fifth configuration may be configured (sixth configuration) such that, when the negative voltage is applied to the target terminal, the forward current is larger than the base current.

[0104] In the switch circuit according to any one of the first to fourth configurations, a seventh configuration (seventh configuration) may be adopted in which, when a negative voltage is applied to the input voltage, a forward current of the rectifier element flows from ground to the specific node, and a base current of the parasitic bipolar transistor flows from ground to the specific node.

[0105] In the switch circuit according to the seventh configuration, the switch circuit may be configured (eighth configuration) such that when the negative voltage is applied to the input voltage, the forward current is larger than the base current.

[0106] A switch circuit (1B) according to another aspect of the present disclosure is a configuration (ninth configuration) including: a switching element (10) constituted by a MOSFET; a target terminal (TMa); a first wiring (WR1) provided between the switching element and the target terminal; a specific transistor (21) constituted by a MOSFET formed on a semiconductor substrate and connected to a gate of the switching element; a gate control circuit (20) configured to control a gate potential of the switching element using the specific transistor; a second wiring (WR2) provided between a base of a PNP-type parasitic bipolar transistor (40B) added to the specific transistor in the semiconductor substrate and the target terminal; and a rectifier element (31) provided between a specific node (ND12) on the second wiring and ground and having a forward direction from ground to the specific node.

[0107] When a base current flows through a PNP-type parasitic bipolar transistor added to a specific transistor, a collector current is generated in the parasitic bipolar transistor. The collector current of the parasitic bipolar transistor can affect the circuit operation. In the switch circuit having the above configuration, the base current (and therefore the collector current) of the parasitic bipolar transistor can be suppressed by installing a rectifier element, thereby reducing the above-mentioned effect.

[0108] In the switch circuit according to the ninth configuration, a first resistor (R1) and a second resistor (R2) may be inserted in series on the second wiring, the first resistor being provided between the target terminal and the specific node, and the second resistor being provided between the specific node and the base of the parasitic bipolar transistor (tenth configuration).

[0109] The switch circuit according to the tenth configuration may be configured as an eleventh configuration, further comprising an electrostatic protection circuit (30) that is provided between the target terminal and the ground and has the rectifying element as an electrostatic protection diode, the anode of the electrostatic protection diode being connected to the ground and the cathode of the electrostatic protection diode being connected to the specific node.

[0110] In the switch circuit according to the eleventh configuration, the electrostatic protection circuit may be configured (twelfth configuration) to further include a reverse current blocking diode (32) having an anode connected to the target terminal and a cathode connected to the specific node.

[0111] In the switch circuit according to any one of the ninth to twelfth configurations, the semiconductor substrate may have a substrate region (601) which is a P-type semiconductor region to which a ground potential is applied, a first semiconductor region (604) which is another P-type semiconductor region, and a second semiconductor region (602) which is an N-type semiconductor region provided between the substrate region and the first semiconductor region, the specific transistor is formed on the first semiconductor region, a bipolar transistor formed by the substrate region, the first semiconductor region, and the second semiconductor region is added to the specific transistor as the parasitic bipolar transistor, a base of the parasitic bipolar transistor is formed by the second semiconductor region, and when a negative voltage is applied to the target terminal, a forward current of the rectifier element flowing from ground to the specific node and a base current of the parasitic bipolar transistor flowing from ground to the specific node are generated (a thirteenth configuration).

[0112] When a negative voltage is applied to the target terminal, a base current may be generated in a PNP-type parasitic bipolar transistor added to a specific transistor. The base current generates a collector current in the parasitic bipolar transistor, and this collector current may affect the circuit operation. In the switch circuit having the above configuration, the base current (and therefore the collector current) of the parasitic bipolar transistor can be suppressed by installing a rectifier element, thereby reducing the above-mentioned effects.

[0113] The switch circuit according to the thirteenth configuration may be configured (fourteenth configuration) such that, when the negative voltage is applied to the target terminal, the forward current is larger than the base current.

[0114] In the switch circuit according to any one of the ninth to twelfth configurations above, when a negative voltage is applied to the input voltage, a forward current of the rectifier element flowing from ground to the specific node, and a base current of the parasitic bipolar transistor flowing from ground to the specific node may be generated (a fifteenth configuration).

[0115] The switch circuit according to the fifteenth configuration may be configured (sixteenth configuration) such that, when the negative voltage is applied to the input voltage, the forward current is larger than the base current. [Explanation of symbols]

[0116] 1, 1A, 1B Switch circuit 10 Switching transistor (switching element) 20 Gate control circuit 21 Transistors (specific transistors) 25 Gate drive circuit 25a output end 25b Driver 26 Clamp Circuit 26a~26c Transistors 27 Resistance 28 Controller 30 Electrostatic protection circuit 31 Electrostatic protection diode 32 Reverse current blocking diode 40, 40A, 40B Parasitic bipolar transistor R1, R2 stabilization resistor R3 protection resistor WR1, WR2 wiring TMa, TMb terminal Dx, Dy, Dz parasitic diodes WR G Gate wiring 600 Semiconductor Substrates 601 Board area 602 Embedding Layer 604, 621 wells 622 Diffusion Area 611 Source Region 612 Drain Region 613 Gate oxide film 615 Backgate Region E S Source electrode E D Drain electrode E G Gate electrode E BG Backgate electrode MM Transistor BP Parasitic bipolar transistor 110 Current Sense Amplifier 111 Square wave generation circuit 112 Switch control circuit 113 Current detection signal output circuit 114 Internal power supply circuit 115P, 115M Electrostatic protection circuit 116 Clamp protection circuit 121, 122 terminals (internal terminals) TM1~TM5 terminals (external terminals) TMP high potential end TMM low potential end R SNS Sense Resistor RP, RM protection resistance SW1~SW4 Switches 130 Clock output circuit VCM Common-mode voltage V SNS Sense Voltage V INP , V INM , V OUTP , V OUTM Voltage S OUT Current Detect Signal VDD Power supply voltage Vreg Internal power supply voltage 901A, 901B Reference Switch Circuit R901 Resistor

Claims

1. A switching element constituted by a MOSFET formed on a semiconductor substrate; The target terminal, A first wiring provided between the switching element and the target terminal; a gate control circuit configured to control a gate potential of the switching element; a second wiring provided between a base of a PNP-type parasitic bipolar transistor added to the switching element in the semiconductor substrate and the target terminal; a rectifying element provided between a specific node on the second wiring and ground, and having a forward direction from the ground to the specific node. , switch circuit.

2. a first resistor and a second resistor are inserted in series on the second wiring; The first resistor is provided between the target terminal and the specific node, and the second resistor is provided between the specific node and a base of the parasitic bipolar transistor.

2. The switch circuit according to claim 1.

3. an electrostatic protection circuit provided between the target terminal and the ground and having the rectifying element as an electrostatic protection diode, the anode of the electrostatic protection diode being connected to the ground and the cathode of the electrostatic protection diode being connected to the specific node; 3. The switch circuit according to claim 2.

4. The electrostatic protection circuit further includes a reverse current blocking diode having an anode connected to the target terminal and a cathode connected to the specific node.

4. The switch circuit according to claim 3.

5. the semiconductor substrate has a substrate region which is a P-type semiconductor region to which a ground potential is applied, a first semiconductor region which is another P-type semiconductor region, and a second semiconductor region which is an N-type semiconductor region provided between the substrate region and the first semiconductor region; the switching element is formed on the first semiconductor region; a bipolar transistor formed by the substrate region, the first semiconductor region, and the second semiconductor region is added to the switching element as the parasitic bipolar transistor, and a base of the parasitic bipolar transistor is formed by the second semiconductor region; When a negative voltage is applied to the target terminal, a forward current flows through the rectifier element from the ground to the specific node, and a base current flows through the parasitic bipolar transistor from the ground to the specific node.

5. A switch circuit according to claim 1.

6. When the negative voltage is applied to the target terminal, the forward current is greater than the base current.

6. The switch circuit according to claim 5.

7. When a negative voltage is applied to the input voltage, a forward current flows through the rectifier element from the ground to the specific node, and a base current flows through the parasitic bipolar transistor from the ground to the specific node.

5. A switch circuit according to claim 1.

8. When the negative voltage is applied to the input voltage, the forward current is greater than the base current.

8. The switch circuit according to claim 7.

9. A switching element constituted by a MOSFET; The target terminal, A first wiring provided between the switching element and the target terminal; a gate control circuit including a specific transistor formed on a semiconductor substrate and connected to a gate of the switching element, the specific transistor being configured to control a gate potential of the switching element; a second wiring provided between a base of a PNP-type parasitic bipolar transistor added to the specific transistor in the semiconductor substrate and the target terminal; a rectifying element provided between a specific node on the second wiring and ground, and having a forward direction from the ground to the specific node. , switch circuit.

10. a first resistor and a second resistor are inserted in series on the second wiring; The first resistor is provided between the target terminal and the specific node, and the second resistor is provided between the specific node and a base of the parasitic bipolar transistor.

10. The switch circuit according to claim 9.

11. an electrostatic protection circuit provided between the target terminal and the ground and having the rectifying element as an electrostatic protection diode, the anode of the electrostatic protection diode being connected to the ground and the cathode of the electrostatic protection diode being connected to the specific node; The switch circuit according to claim 10.

12. The electrostatic protection circuit further includes a reverse current blocking diode having an anode connected to the target terminal and a cathode connected to the specific node. The switch circuit according to claim 11 .

13. the semiconductor substrate has a substrate region which is a P-type semiconductor region to which a ground potential is applied, a first semiconductor region which is another P-type semiconductor region, and a second semiconductor region which is an N-type semiconductor region provided between the substrate region and the first semiconductor region; the specific transistor is formed on the first semiconductor region; a bipolar transistor formed by the substrate region, the first semiconductor region, and the second semiconductor region is added to the specific transistor as the parasitic bipolar transistor, and a base of the parasitic bipolar transistor is formed by the second semiconductor region; When a negative voltage is applied to the target terminal, a forward current flows through the rectifier element from the ground to the specific node, and a base current flows through the parasitic bipolar transistor from the ground to the specific node.

13. A switch circuit according to claim 9.

14. When the negative voltage is applied to the target terminal, the forward current is greater than the base current. The switch circuit according to claim 13 .

15. When a negative voltage is applied to the input voltage, a forward current flows through the rectifier element from the ground to the specific node, and a base current flows through the parasitic bipolar transistor from the ground to the specific node.

13. A switch circuit according to claim 9.

16. When the negative voltage is applied to the input voltage, the forward current is greater than the base current.

16. The switch circuit according to claim 15.

Images