Semiconductor device and writing method

Abstract

To reduce CPU's access time to a register while preventing software from becoming complicated.SOLUTION: A semiconductor device 100 includes: a decode circuit 110 that identifies a writing source processor 200; a writing permission setting storage circuit 120 that stores a writing permission setting that indicates a processor that can write to each bit of a writing destination register 310; a mask / merge circuit 130 that generates a write-back value to the writing destination register 310 based on the writing permission setting and the writing source processor 200; and a write-back circuit 140 that writes the write-back value back to the writing destination register 310.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a writing method for writing data. [Background technology]

[0002] In recent years, semiconductor devices such as in-vehicle microcontrollers are required to be equipped with multiple CPUs (Central Processing Units) and to continue to execute safety-related functions even if some kind of failure occurs. The safety-related functions include a function to avoid a chain of failures when multiple CPUs access a shared resource register. In addition, in the shared resource registers mounted on in-vehicle microcontrollers, there are cases where a single register has a bit section that is permitted to be accessed by multiple CPUs.

[0003] In the conventional technology, rewriting only permitted bit parts is realized by read-modify-write. For example, Patent Document 1 discloses a technology related to an information processing device that performs read-modify-write.

[0004] However, when performing read-modify-write, arbitration processing is required to stop access from a CPU other than the CPU accessing the register, and multiple access processing and calculation processing are required due to read-modify-write, which causes problems such as the software becoming more complex and the CPU's access time to the register increasing.

[0005] In addition, the increasing complexity of software and the increase in CPU access time are increasing the number of software development man-hours and are factors that are degrading the performance of in-vehicle microcontrollers. As a result, there is a growing need for functions and systems that can avoid a chain of hardware-related failures. Such functions and systems are called FFI (Freedom From Interface), and are also required by ISO26262. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] International Publication No. 2010 / 029682 Summary of the Invention [Problem to be solved by the invention]

[0007] As described above, it is desirable to reduce the CPU's access time to registers while preventing software from becoming too complicated.

[0008] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0009] A semiconductor device according to one embodiment includes a decode circuit that identifies the processor that is the source of a write, a write permission setting storage circuit that stores a write permission setting indicating a processor that is allowed to write to each bit of a destination register, a mask / merge circuit that generates a value to be written back to the destination register based on the write permission setting and the source processor, and a write back circuit that writes the write back value back to the destination register.

[0010] A write method according to one embodiment includes a step of determining a processor from which the write is originating, a step of generating a value to be written back to the destination register based on a write permission setting indicating a processor that can write to each bit of a destination register and the source processor, and a step of writing back the value to be written back to the destination register. Effect of the Invention

[0011] According to the embodiment, it is possible to reduce the access time of the CPU to the register while preventing the software from becoming complicated. [Brief description of the drawings]

[0012] [Figure 1] 1 is a schematic circuit diagram showing a configuration of a semiconductor device according to a first embodiment. [Diagram 2] FIG. 2 is a schematic circuit diagram showing a configuration of a decoding circuit according to the first embodiment. [Diagram 3] FIG. 2 is a schematic circuit diagram showing a write permission setting circuit according to the first embodiment. [Figure 4] FIG. 2 is a schematic circuit diagram showing a configuration of a mask / merge circuit according to the first embodiment. [Diagram 5] 4 is a time chart showing the operation of the decoding circuit according to the first embodiment. [Figure 6] 4 is a time chart showing the operation of the mask / merge circuit according to the first embodiment. [Figure 7] 4 is a time chart showing the operation of the write-back circuit according to the first embodiment. [Figure 8] FIG. 11 is a diagram for explaining the configuration of a semiconductor device according to a second embodiment. [Figure 9] FIG. 11 is a schematic circuit diagram showing the configuration of a write-back circuit according to a second embodiment. [Figure 10] 13 is a time chart illustrating the operation of the write-back circuit according to the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] In order to clarify the explanation, the following description and drawings are omitted and simplified as appropriate. In addition, each element shown in the drawings as a functional block performing various processes can be configured in hardware with a CPU, memory, and other circuits, and in software with a program loaded into memory. Therefore, it is understood by those skilled in the art that these functional blocks can be realized in various forms by hardware, software running on hardware, or a combination thereof, and are not limited to any one of them. In addition, in each drawing, the same elements are given the same reference numerals, and duplicate explanations are omitted as necessary.

[0014] Moreover, the above-mentioned program includes a set of instructions (or software code) for making the computer perform one or more functions described in the embodiment when the program is loaded into the computer. The program may be stored in a non-transitory computer-readable medium or a tangible storage medium. By way of example and not limitation, the computer-readable medium or the tangible storage medium includes Random Access Memory (RAM), Read Only Memory (ROM), flash memory, Solid State Drive (SSD) or other memory technology, CD-ROM, Digital Versatile Disc (DVD), Blu-ray (registered trademark) disk or other optical disk storage, magnetic cassette, magnetic tape, magnetic disk storage or other magnetic storage device. The program may be transmitted on a transitory computer-readable medium or a communication medium. By way of example and not limitation, the transitory computer-readable medium or the communication medium includes electrical, optical, acoustic, or other forms of propagating signals.

[0015] EMBODIMENT 1 FIG. 1 is a schematic circuit diagram showing a configuration of a semiconductor device 100 according to a first embodiment. PWDATA[31:0], bus slave selection signals PSEL0-7, and PADDR[31:0] are input to the semiconductor device 100 from a write source processor 200 via an APB (Advanced Peripheral Bus) bus interface IF. PWDATA[31:0] is also called write data. PADDR[31:0] is also called a bus address. The bus slave selection signals PSEL0-PSEL7 correspond to ID0-7 of the write source processor. The number of IDs may be 2 or more and 6 or less, or may be 8 or more. The semiconductor device 100 writes data to a write destination register 310 of a write destination module 300 via the APB bus interface IF.

[0016] The semiconductor device 100 includes a decode circuit 110, a write permission setting storage circuit 120, a mask / merge circuit 130, and a write back circuit 140.

[0017] Bus slave selection signals PSEL0 to 7 and PADDR[31:0] are input to the decode circuit 110. The bus slave selection signal PSEL indicates the write source processor 200. PADDR[31:0] indicates the address of the write destination register 310. The decode circuit 110 identifies the write source processor 200.

[0018] The decode circuit 110 stores information (also called MASK_CON) regarding whether or not each bit of the write destination register 310 is masked. For example, if a bit is not masked, all processors may be permitted to write data to that bit. If a bit is masked, only a specific processor may be permitted to write data to that bit.

[0019] The decode circuit 110 generates a decode ID (also called a decode signal) based on MASK_CON and the bus slave selection signals PSEL0 to PSEL7, and outputs the decode ID to the mask / merge circuit .

[0020] Moreover, the decode circuit 110 outputs PSEL_OUT based on PSEL0 to PSEL7 to the write-back circuit 140. A more detailed configuration of the decode circuit 110 will be described later.

[0021] The write permission setting storage circuit 120 stores write permission settings indicating processors that can write to each bit of the write destination register 310. The write permission setting storage circuit 120 may include, for example, three flip-flops corresponding to each bit. This allows IDs 0 to 7 of the processor 200 to be represented. The write permission setting of each bit is also referred to as SFR_ID[2:0]. The detailed configuration of the write permission setting storage circuit 120 will be described later.

[0022] The mask / merge circuit 130 generates a value to be written back to the write destination register 310 based on the write permission setting and the write source processor 200. Specifically, the mask / merge circuit 130 may generate a value to be written back to the write destination register 310 for each bit based on the write permission setting and the decode ID. The mask / merge circuit 130 includes, for example, a mask circuit 131, a mask circuit 132, an OR circuit 133, and a comparison circuit 134. The mask circuits 131 and 132 are configured, for example, by an AND circuit. The mask circuit 131 outputs write data (e.g., PWDATA

[31] ) to the OR circuit 133 according to an instruction from the comparison circuit 134. The mask circuit 132 outputs data written to a bit (e.g., bit31) of the write destination register 310 to the OR circuit 133 according to an instruction from the comparison circuit 134. The comparison circuit 134 operates the mask circuits 131 and 132 based on the decode ID and SFR_ID. The detailed configuration of the mask / merge circuit 130 will be described later.

[0023] The write-back circuit 140 writes back the write-back value for each bit input from the mask / merge circuit 130 to the write-destination register 310. The write-back circuit 140 may include a selector that selects PWDATA[31:0] and the write-back value according to PSEL_OUT. The write-back circuit 140 also outputs PWDATA[31:0], PSEL, and PADDR[31:0] to the write-destination module 300.

[0024] 2, the configuration of the decoding circuit 110 will be described in detail. The decoding circuit 110 includes a comparison circuit 111, a selector 112, a signal generation unit 113, and a selector 114.

[0025] The comparator circuit 111 compares PADDR[18:16] included in the address bus PADDR[19:0] with PSEL_ID[2:0] obtained by binarizing the bus slave selection signals PSEL0 to 7. PADDR[18:16] are bits that represent the processor 200 that is the write source. The comparator circuit 111 outputs the comparison result to the selector 112 and the selector 114.

[0026] MASK_CON[31:0], which indicates whether or not to perform mask processing for each bit of PADDR[15:0], is input to the selector 112. Note that in the following, there are cases where H is added to the end of a hexadecimal number, and B is added to the end of a binary number.

[0027] PADDR[15:0] is 0000 H Then, MASK_CON[31:0] is, for example, 01 01 B The value 1 indicates that the masking is enabled, and the value 0 indicates that writing is always possible. Also, when PADDR[15:0] is 0001, H then MASK_CON[31:0] is 00..11 B PADDR[15:0] is 1FFF H then MASK_CON[31:0] is 00..000 B If the signals compared by the comparator circuit 111 match, the selector 112 outputs MASK_CON[31:0] according to PADDR[15:0] to the signal generator 113.

[0028] The signal generating unit 113 generates the decode ID[3:0][31:0] by using MASK_CON[31:0] and PSEL_ID[2:0]. When each bit of MASK_CON[31:0] is 0, the signal generating unit 113 generates the decode ID[3:0][]=8 corresponding to that bit. H In addition, when each bit of MASK_CON[31:0] is 1, the signal generating unit 113 sets the decode ID[3:0][]={0 B +PSEL_ID[2:0]}. For example, PADDR is 0001 HWhen MASK_CON[31:0] is 00...11 B and PSEL_ID[2:0] is 1 H In this case, the decode ID[3:0][31:0] is 88···11 H It is.

[0029] It can also be said that the signal generating unit 113 replaces each bit of MASK_CON[31:0] with a predetermined bit (e.g., 8) when the bit is 0. It can also be said that the signal generating unit 113 replaces each bit of MASK_CON[31:0] with PSEL_ID when the bit is 1.

[0030] The selector 114 receives PSEL0 to 7 and a signal having an output fixed to 1. If the signals compared by the comparison circuit 111 do not match, the selector 114 outputs 1 as PSEL_OUT. If the signals compared by the comparison circuit 111 match, the selector 114 outputs PSEL_OUT according to PSEL0 to 7. For example, if PSEL_ID[2][1][0] is 001, the selector 114 outputs PSEL0. If PSEL_ID[2][1][0] is 010, the selector 114 outputs PSEL1. If PSEL_ID[2][1][0] is 111, the selector 114 outputs PSEL7.

[0031] Also, the decode circuit 110 converts the address into a digital value of {0000 H +PADDR[15:0]}.

[0032] The decode circuit 110 uses the comparator circuit 111 to compare PSEL_ID[2:0] with PADDR[18:16], thereby reducing the possibility of erroneous writing occurring.

[0033] 3, a detailed configuration of the write permission setting storage circuit 120 will be described. The write permission setting storage circuit 120 includes an APB bus decoder 121 and a storage unit 122.

[0034] PSEL, PADDR[31:0], PWDATA[31:0], and PWRITE are input to the APB bus decoder 121 via the APB bus interface IF. PWRITE is a signal indicating whether or not to perform writing. In addition, PRDATA[31:0] is output from the APB bus decoder 121 via the APB bus interface IF.

[0035] The storage unit 122 includes three flip-flops FF for each bit. The three flip-flops FF store a write permission setting (also called SFR_ID[2:0]) that indicates the ID of a processor that can write to that bit. The storage unit 122 outputs SFR_ID[2:0] for each of bit0 to bit31. The write permission setting is configured to be configurable via the APB bus decoder 121.

[0036] The configuration of the mask / merge circuit 130 will be described in detail with reference to Fig. 4. The mask / merge circuit 130 includes a mask / merge circuit 130_0 for bit 0, ..., a mask / merge circuit 130_30 for bit 30, and a mask / merge circuit 130_31 for bit 31. The mask / merge circuit 130_31 will be described in detail, and a detailed description of the mask / merge circuits 130_0 to 130_30 will be omitted.

[0037] The mask / merge circuit 130_31 includes an AND circuit 131, an AND circuit 132, an OR circuit 133, and a comparison circuit 134. The AND circuit 131 receives PWDATA

[31] and AB_OUT, which is the output of the comparison circuit 134. The AND circuit 132 receives the register value

[31] of the write destination register 310 and the negation of AB_OUT, which is the output of the comparison circuit 134. The OR circuit 133 generates the write-back register value

[31] of the write destination register 310 by ORing the output of the AND circuit 131 and the output of the AND circuit 132.

[0038] The comparison circuit 134 compares A=decoded ID[3:0]

[31] and B={0 B + SFR_ID[2:0]} and A=B or A=8 H If the condition is satisfied, the comparator circuit 134 outputs AB_OUT=1. If the above condition is not satisfied, specifically, if A≠B, the comparator circuit 134 outputs AB_OUT=0.

[0039] For example, when MASK_CON

[31] =0, decode ID[3:0]

[31] =8. H Therefore, AB_OUT=1, and PWDATA

[31] is written back. Even if MASK_CON

[31] =1, if PSEL_ID[2:0]

[31] and SFR_ID[2:0]

[31] match, AB_OUT=1, and PWDATA

[31] is written back. If the above condition is not met, AB_OUT=0, and the register value

[31] of the write destination register 310 is written back.

[0040] Similar processing is performed in the mask / merge circuits 130_0, . . . and the mask / merge circuit 130_30. As a result, the write-back register value [0], . . . , the write-back register value

[30] , and the write-back register value

[31] are output.

[0041] Next, the operation of the semiconductor device 100 will be described with reference to FIGS.

[0042] 5 is a time chart showing the operation of the decode circuit 110. The decode circuit 110 judges whether or not PADDR[19:16] extracted from PADDR[19:0] of the address accessed by the user matches PSEL_ID[2:0] representing PSEL0 to 7. For example, if PADDR[19:16] is 0001 B and PSEL_ID[2:0] is 1 HIf so, it may be determined that PADDR[19:16] and PSEL_ID[2:0] match. The decode circuit 110 then determines whether or not the access is intended by the user.

[0043] Furthermore, the decode circuit 110 selects information indicating whether or not masking is performed for each bit of the write destination register 310 based on PADDR[15:0] indicating the address of the write destination register 310, and outputs it as MASK_CON[31:0]. As indicated by the dotted arrow 21, the decode circuit 110 replaces 1 included in MASK_CON[31:0] with PSEL_ID[2:0], replaces 0 included in MASK_CON[31:0] with 8, and outputs it as decode ID[3:0][31:0]. As indicated by the dotted arrow 22, the decode circuit 110 outputs PSEL_OUT according to PSEL0 to 7. Furthermore, as indicated by the dotted arrow 23, the decode circuit 110 outputs 0000 B +PADDR[15:0] is output as PADDR_OUT[19:0].

[0044] 6 is a time chart showing the operation of the mask / merge circuit 130. The mask / merge circuit 130 determines for each bit whether the condition that the decode ID[3:0] is 8 or the decode ID[3:0] and the SFR_ID[2:0] are consistent is satisfied. The mask / merge circuit 130 writes the PWDATA of the bit for which the condition is satisfied into the write-back register value of that bit.

[0045] For example, the 1st to 4th bits from the left of the decode ID[3:0][31:0] are 8888. H Therefore, the PWDATA and the write-back register value match, as shown by the arrow 31. For the same reason, as shown by the arrow 32, B and write back register value 0011 B and match.

[0046] Also, the 9th to 12th bits from the left of the decode ID[3:0][31:0] are 1111H and the corresponding bits of SFR_ID[2:0][31:0] are also 1111 H Therefore, as shown by the dotted arrow 33, the PWDATA 0110 B and write back register value 0110 B Similarly, the second to fourth bits from the right of the decode ID[3:0][31:0] are 111. H The second to fourth bits from the right of SFR_ID[2:0][31:0] are also 111. H Therefore, as shown by the dotted arrow 34, the PWDATA of 100 B and write back the register value of 100 B and match.

[0047] The mask / merge circuit 130 writes the write destination register value of the bit for which the above condition is not satisfied into the write back register value of the bit. For example, the fifth to eighth bits from the left of the decode ID[3:0][31:0] are 1111. H and the corresponding bits of SFR_ID[2:0][31:0] are 2222 H Therefore, as shown by the dotted arrow 35, the write destination register value of 0000 B and write back the register value of 0000 B Similarly, the rightmost bit of the decode ID[3:0][31:0] is 0. H The rightmost bit of SFR_ID[2:0][31:0] is 1. H Therefore, as indicated by the dotted arrow 36, the write destination register value of 0 and the write back register value of 0 match.

[0048] 7 is a time chart showing the operation of the write-back circuit 140. The decode circuit 110 has already generated PADDR_OUT[15:0] from which bits related to the source processor 200 have been removed. The write-back circuit 140 generates PADDR[31:0] by combining PADDR_OUT[19:0] based on PADDR_OUT[15:0] with PADDR[31:20] as indicated by the dotted arrow 41, and outputs the PADDR[31:0] to the destination module 300. The write-back circuit 140 also outputs the write-back register value[31:0] to the destination module 300 as PWDATA[31:0] as indicated by the dotted arrow 42. The write-back circuit 140 also generates PSEL based on PSEL_OUT as indicated by the dotted arrow 43, and outputs the PSEL to the destination module 300.

[0049] The semiconductor device 100 according to the first embodiment can control writing to the write destination module 300 by multiple processors by identifying the write source processor 200 and using the write permission setting. In this case, there is no need for software-based exclusive control or register read for writing back.

[0050] The semiconductor device 100 can reduce the access time of the CPU while preventing the software from becoming complicated. Furthermore, even if the software is modified, the function of avoiding a chain reaction of failures can be continued.

[0051] EMBODIMENT 2 The second embodiment is a modified example of the first embodiment. The configuration of a semiconductor device 100a according to the second embodiment will be described with reference to FIG. 8. Comparing FIG. 1 with FIG. 8, PSEL (privilege) indicating that the write source processor 200 has been granted a privilege is output to the write back circuit 140. When the write source processor 200 has been granted a privilege, the semiconductor device 100a outputs PADDR[31:0] and PWDATA[31:0] to the write destination module 300 without passing through the mask / merge circuit 130.

[0052] The configuration of the write-back circuit 140 according to the second embodiment will be described in detail with reference to Fig. 9. The write-back circuit 140 includes selectors 141-143.

[0053] When PSEL(privilege) is active, the selector 141 selects PSEL(privilege) and outputs it as PSEL to the destination module 300. When PSEL(privilege) is active, the selector 142 selects PWDATA[31:0] and outputs it to the destination module 300. When PSEL(privilege) is active, the selector 143 selects PADDR[31:0] and outputs it to the destination module 300.

[0054] 10 is a time chart showing the operation of the write-back circuit 140 according to the second embodiment. When PSEL(privilege) is active, PWDATA[31:0] is output to the write-destination module 300 instead of the write-back register value[31:0], as shown by the dotted arrow 51. Also, PADDR[31:0] is output to the write-destination module 300, as shown by the dotted arrow 52. Then, PSEL(privilege) is output to the write-destination module 300, as shown by the dotted arrow 53.

[0055] The semiconductor device 100a according to the second embodiment can provide a privileged mode in which no masking process is performed to the write source CPU, and can systematically manage access rights to registers.

[0056] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0057] 100, 100a Semiconductor device 110 Decoding circuit 111 Comparison circuit 112 Selector 113 Signal Generator 114 Selector 120 Write permission setting storage circuit 121 APB bus decoder 122 Storage area 130, 130_0 to 130_31 Mask / Merge Circuit 131, 132 Mask circuit, AND circuit 133 OR Circuit 134 Comparison circuit 140, 140a Write-back circuit 141~143 Selector 200 processors 300 Destination module 310 Write destination register

Claims

1. A decode circuit for identifying a processor that has written the data; a write permission setting storage circuit for storing a write permission setting indicating a processor that can write to each bit of the write destination register; a mask / merge circuit that generates a value to be written back to the destination register based on the write permission setting and the source processor; a write-back circuit that writes the write-back value back to the write destination register; A semiconductor device comprising:

2. A bus address and a bus slave selection signal corresponding to the processor that is the write source are input to the decode circuit, the bus address includes a bit representing the processor from which the write originated; The decode circuit determines whether the bits included in the bus address and the bus slave selection signal are consistent. The semiconductor device according to claim 1 .

3. The decode circuit generates a decode signal by replacing each bit of the write destination register with a predetermined bit when masking of the bit is not effective, and by replacing the bit with a bit representing the write source processor when masking of the bit is effective. The semiconductor device according to claim 1 .

4. The mask / merge circuit generates the write-back value based on write data supplied from the write-source processor when a condition is met that the bit matches the predetermined bit or the bit representing the write-source processor matches the write permission setting, and generates the write-back value based on data written in the write-destination register when the condition is not met. The semiconductor device according to claim 3 .

5. If the processor that is the source of the write is given a privilege, the processor outputs the bus address and the write data without passing through the mask / merge circuit. The semiconductor device according to claim 1 .

6. determining the processor from which the write originated; generating a value to be written back to the write destination register based on a write permission setting indicating a processor that can write to each bit of the write destination register and the write source processor; writing the write-back value back to the destination register; Including writing methods.

7. If the processor that is the source of the write is given a privilege, the bus address and the write data are output without going through the step of generating the write-back value. The writing method according to claim 6.

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