Substrate having side surface protection layer and manufacturing method thereof

Abstract

To provide: a substrate having a side surface protection layer that can reduce defects in a manufacturing step or a use step, and that can be produced at an enhanced yield; and a manufacturing method thereof.SOLUTION: There is provided a manufacturing method of a substrate including a packaging substrate on which one or more electron elements are arranged. The substrate includes: a glass core 21 that includes a first surface and a second surface facing each other, and a side surface coupling the first surface and the second surface; an upper layer 26 laminated on the first surface or a lower layer 29 laminated under the second surface; and a side surface protection layer 70 covering a side surface of the glass core with a protection material. A defect such as breaking, cracking, or chipping is formed in an inward direction of the glass core from the side surface of the glass core, and the protection material fills the defect. The substrate of the present invention can: reduce packaging substrate failures due to defects such as SeWaRe that are prone to occur or manifest in the glass core in a manufacturing step or a use step; and enhance durability.SELECTED DRAWING: Figure 7B

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE Embodiments relate to a substrate having a side protection layer which can be produced with reduced defects and improved yield, and a method for manufacturing the same. FIELD Embodiments relate to a substrate having excellent usability as a packaging substrate, and a method for manufacturing the same. [Background technology]

[0002] In the manufacture of electronic components, the process of forming circuits on a semiconductor wafer is called the front-end process (FE), and the process of assembling the wafer so that it can be used in an actual product is called the back-end process (BE). This back-end process includes the packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of electronic products in recent years are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms, such as nano-level line widths below the micron level, more than 10 million cells, high-speed operation, and large amounts of heat dissipation, but the technology to perfectly package these has not been fully supported. As a result, the electrical performance of semiconductors is sometimes determined by the packaging technology and the resulting electrical connections rather than the performance of the semiconductor technology itself.

[0004] The packaging substrate is made of ceramic or resin. Ceramic substrates such as silicon substrates have high resistance or high dielectric constant, so it is not easy to mount high-performance, high-frequency semiconductor elements on them. Resin substrates can mount relatively high-performance, high-frequency semiconductor elements, but there is a limit to how much the wiring pitch can be reduced.

[0005] Recently, glass substrates can be used as substrates for high-end packaging. By forming through holes in the glass substrate and applying a conductive material to the through holes, the wiring length between the device and the motherboard can be shortened, and the packaging substrate can have excellent electrical characteristics.

[0006] Related prior art includes Korean Patent No. 10-1406139, "Side processing method for transparent substrate for display device and processing device using same," and Korean Patent No. 10-1765198, "Window glass manufacturing method using UV pattern." Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the embodiment is to provide a substrate having a side protection layer that can be produced with reduced defects and improved yield, and a manufacturing method thereof. [Means for solving the problem]

[0008] In order to achieve the above object, a substrate according to at least one embodiment includes a packaging substrate on which one or more electronic devices are disposed, the substrate including a glass core having first and second surfaces facing each other and a side surface connecting the first and second surfaces, an upper layer laminated on the first surface or a lower layer laminated under the second surface, and a side protective layer that covers the side surface of the glass core with a protective material, and a defect is formed from the side surface of the glass core toward the inside of the glass core.

[0009] The protective material fills the space in the glass core caused by the defect.

[0010] The protective material may have a Young's modulus at 24° C. of 0.1 GPa to 17 GPa.

[0011] The packaging substrate may include the upper layer and the lower layer.

[0012] The side protective layer can encase the side surfaces of the upper layer, the glass core, and the lower layer.

[0013] The protective material may include an elastic polymer resin.

[0014] The elastic polymer resin may have a curing temperature of 120° C. or higher.

[0015] The substrate may be a strip substrate in which a plurality of the individual packaging substrates are arranged with a dummy area therebetween; a quad substrate in which the dummy area is disposed between a plurality of the strip substrates; a panel substrate in which the dummy area is disposed between a plurality of the quad substrates; or the individual packaging substrate.

[0016] The side surface of the glass core may protrude beyond the side surface of the upper layer or the side surface of the lower layer.

[0017] The protective material may include an elastomeric polymer that includes silane functional groups.

[0018] To achieve the above object, a method for manufacturing a substrate according to one or more embodiments provides a method for manufacturing a substrate having a side protection layer.

[0019] The method for manufacturing the substrate includes step A of providing a glass core having a first surface and a second surface facing each other, and forming an upper layer on the first surface and a lower layer below the second surface to provide a substrate; and step B of providing a side protection layer on a side surface of the substrate, the glass core of the substrate having defects formed on its side surface, the side protection layer filling the defects with a protective material and enveloping the side surface of the glass core.

[0020] In the method for producing the substrate, step C can be performed one or more times during step A or between step A and step B.

[0021] The step C is a step of checking for the occurrence of defects on the substrate of the step A.

[0022] In the method for manufacturing a substrate, step D may be further performed after step A.

[0023] The substrate in step A is a substrate in which a plurality of the individual packaging substrates are arranged with dummy regions interposed therebetween, and step D is a singulation step in which the individual packaging substrates are separated to obtain the packaging substrate. Effect of the Invention

[0024] The substrate and manufacturing method thereof according to the embodiment may reduce defects in the packaging substrate, such as SeWaRe, that tend to occur (or develop) in the glass core during manufacturing or use, and may improve durability.

[0025] The substrate and manufacturing method thereof according to the embodied embodiments can improve the manufacturing yield of the substrate by repairing the defects without a separate process for relieving the stress of the glass core.

[0026] The substrate and manufacturing method thereof according to the embodied embodiments may minimize the occurrence of additional defects such as cracks, chipping, etc. at the edges and / or corners of the substrate that may occur when the substrate is placed on a tray, boat, etc. for processing. [Brief description of the drawings]

[0027] [Figure 1] 1 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to an embodiment; [Diagram 2] 13 is a conceptual diagram illustrating a cross-sectional structure of a packaging substrate according to another embodiment; FIG. [Diagram 3] 1A and 1B are schematic cross-sectional views illustrating a portion of a packaging substrate according to an embodiment. [Figure 4] 1 is a flowchart illustrating a process of forming a core distribution layer in a process of manufacturing a packaging substrate according to an embodiment. [Diagram 5] 1 is a flowchart illustrating a process of forming an insulating layer in a process of manufacturing a packaging substrate according to an embodiment. [Figure 6] 1 is a perspective view of a substrate having a side protection layer according to an embodiment; [Figure 7A] 7 is an exemplary conceptual diagram of a cross section of the substrate before a side protective layer is formed, as seen along line AA' in FIG. 6. [Figure 7B] 7 is an exemplary conceptual diagram of a cross section of the substrate after the side protection layer is formed, as seen along line AA' in FIG. 6. [Figure 8A] 7 is another exemplary conceptual diagram of a cross section of the substrate before the side protective layer is formed, as seen along AA' in FIG. 6. [Figure 8B] 7 is another exemplary conceptual diagram of a cross section of the substrate after the side protection layer is formed, as seen along the line AA' in FIG. 6. [Figure 9A] 7 is another exemplary conceptual diagram of a cross section of the substrate before the side protective layer is formed, as seen along AA' in FIG. 6. [Figure 9B] 7 is another exemplary conceptual diagram of a cross section of the substrate after the side protection layer is formed, as seen along the line AA' in FIG. 6. BEST MODE FOR CARRYING OUT THEINVENTION

[0028] The following detailed description is provided to facilitate a comprehensive understanding of the method, device and / or system described herein. However, various changes, modifications and equivalents of the method, device and / or system described herein will become apparent after the contents presented in this application are understood. For example, the order of operations described herein is merely exemplary and is not limited to the operations described herein. Except for steps that necessarily proceed in a certain order, the order of operations may be changed depending on the understanding of the contents presented in this application. In addition, the description of known features may be omitted to improve clarity and conciseness after the disclosure of this application is understood. However, the omission of such features and their descriptions is not intended to be an admission of common knowledge.

[0029] The features described herein may be embodied in different forms and are not to be construed as being limited to the examples described herein, but rather the embodiments described herein are provided to illustrate some of the many possible ways of implementing the methods, apparatus and / or systems described herein that will become apparent after reading the present disclosure.

[0030] As used herein, terms such as "first," "second," and "third" may be used to describe various members, components, regions, layers, or sections, but are not intended to limit these members, components, regions, layers, or sections to these words. Instead, such terms are used to distinguish one member, component, region, layer, or section from another member, component, region, layer, or section. Thus, a first member, component, region, layer, or section referred to in any embodiment described herein could also be a second member, component, region, layer, or section without departing from the teachings of the embodiment.

[0031] Throughout the specification, when an element such as a layer, region, or substrate is described as being "on," "connected to," or "bonded" to another element, it may be described as being directly "on," "connected," or "bonded" to the other element, or there may be one or more intervening elements between them. In contrast, when an element is described as being "directly on," "directly connected," or "directly bonded," there may not be any other intervening elements between them. Similarly, expressions such as "between" and "directly between," and "adjacent" and "directly adjacent" may be interpreted as previously described.

[0032] The terms used herein are merely for describing particular examples and are not used to limit the disclosure. As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise. As used herein, the term "and / or" includes any one or more combinations of the associated listed items. As used herein, the terms "comprises," "comprises," and "has" specify the presence of stated features, numbers, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and / or combinations thereof. As used herein, the use of the term "can" in connection with an example or embodiment (e.g., what the example or embodiment can include or embody) means that there is at least one example or embodiment in which such feature is included or embodied, but not all examples are limited thereto.

[0033] In this application, "B is located on A" means that B is in direct contact with A or that B is disposed on A with another layer or structure therebetween, and therefore should not be construed as B being in direct contact with A.

[0034] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. Terms, such as those defined in commonly used dictionaries, should be interpreted to have a meaning consistent with their meaning in the context of the prior art and the present invention, and should not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0035] In one or more of the above examples, the term "A and / or B" means "A, B, or A and B."

[0036] In one or more of the above examples, terms such as "first," "second," "A," or "B" are used to distinguish identical terms from one another.

[0037] In one or more of the above instances, the singular forms are to be construed as including the plural forms as well as the singular forms unless specifically stated otherwise.

[0038] FIG. 1 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 is a conceptual diagram illustrating the cross-sectional structure of a packaging substrate according to another embodiment, and FIGS. 3(a) and (b) are conceptual diagrams illustrating the cross-section of a portion of a packaging substrate according to an embodiment.

[0039] To achieve the above objective, the semiconductor device 100 of the embodiment includes a semiconductor element section 30 in which one or more semiconductor elements 32, 34, and 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to and connects the semiconductor elements 32, 34, and 36 to each other.

[0040] The packaging substrate 20 according to one embodiment includes a core layer 22, an upper layer 26 disposed on one surface of the core layer 22, and a cavity portion 28 in which a cavity element 40 can be disposed.

[0041] The semiconductor element section 30 means an element mounted on a semiconductor device, and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, the semiconductor element section 30 may be, for example, a computing element such as a CPU or a GPU (first element: 32, second element: 34), a storage element such as a memory chip (third element: 36), or the like, but any semiconductor element mounted on a semiconductor device can be used without any restrictions.

[0042] The motherboard 10 may be a motherboard such as a printed circuit board or a printed wiring board.

[0043] The packaging substrate 20 may optionally further include a lower layer (not shown) located below the core layer.

[0044] The core layer 22 may include a glass substrate 21 including a first region 221 having a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 that is thinner than the first thickness (half cavity) or has a thickness of 0 mm (full cavity), a plurality of core vias 23 penetrating the glass substrate 21 in the thickness direction, and a core distribution layer 24 located on the surface of the glass substrate 21 or the core vias 23 and electrically connecting a first surface 213 of the glass substrate 21 to a second surface 214 opposite the first surface via the core vias 23.

[0045] The second region 222 of the core layer 22 may serve as a cavity structure.

[0046] In the same area, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other, and the two surfaces are generally parallel to each other, so that the glass substrate 21 has a constant thickness throughout.

[0047] An internal space 281 formed by the difference in thickness between the first section 221 and the second section 222 serves to accommodate a part or the whole of the cavity element 40 .

[0048] The glass substrate 21 may include core vias 23 penetrating the first surface 213 and the second surface 214. The core vias 23 may be formed in both the first area 221 and the second area 222, and may be formed at a desired pitch and pattern.

[0049] Conventionally, packaging substrates for semiconductor devices have been applied in the form of a laminate of a silicon substrate and an organic substrate. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements being generated when applied to high-speed circuits, and there is a drawback in that the power loss is relatively large. In addition, in the case of an organic substrate, a large area is required to form an increasingly complex distribution pattern, which does not fit with the trend of manufacturing electronic devices that are becoming ultra-miniaturized. In order to form a complex distribution pattern within a set size, it is necessary to substantially fine the pattern, but there is a practical limit to the fine pattern due to the characteristics of materials such as polymers applied to organic substrates.

[0050] In the embodiment, to solve this problem, the glass substrate 21 is used as a support for the core layer 22. In addition, by using the glass substrate 21 and the core via 23 formed penetrating the glass substrate 21, the length of electrical flow is further shortened, providing a packaging substrate 20 that is more compact, has faster response, and has less loss characteristics.

[0051] The glass substrate 21 is preferably a glass substrate used in semiconductors. For example, a borosilicate glass substrate or an alkali-free glass substrate may be used, but is not limited thereto.

[0052] The core via 23 penetrates the glass substrate 21. The core via 23 may be formed by removing a predetermined region of the glass substrate 21, specifically, by etching a plate-shaped glass by a physical and / or chemical method.

[0053] Specifically, the formation of the core via 23 may be achieved by forming a defect (scratch) on the surface of the glass substrate using a method such as a laser, followed by chemical etching, laser etching, etc., but is not limited thereto.

[0054] Based on a unit area (1 cm×1 cm) of the glass substrate 21, the number of the core vias 23 may be 100 to 3,000, 100 to 2,500, or 225 to 1,024. When such pitch conditions are satisfied, the formation of an electrically conductive layer and the performance of the packaging substrate can be improved.

[0055] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first and second surfaces of the glass substrate through a through via, and a core insulating layer 223 that encases the core distribution pattern. The core layer 22 has an electrically conductive layer formed therein through a core via, and serves as an electrical path across the glass substrate 21, and connects the upper and lower parts of the glass substrate over a relatively short distance, thereby allowing for faster electrical signal transmission and low loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0056] The shape of the cavity portion 28 is not limited and may be substantially circular, triangular, rectangular, hexagonal, octagonal, cross-shaped, or the like.

[0057] The cavity element 40 may be generally cylindrical, rectangular, or polygonal in shape.

[0058] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the cavity element 40 and the core distribution layer 24, and an insulating layer that encases the cavity distribution pattern.

[0059] Meanwhile, the cavity portion according to another embodiment may be embodied in a form penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion may be formed by a process similar to the process of forming the core via 23, and the area and shape penetrating the glass substrate 21 may be different from those of the core via 23.

[0060] In this embodiment, an insulating layer may be formed in the cavity portion after the cavity element 40 is arranged in the cavity portion. That is, an insulating layer may be formed in the cavity portion through the process of forming the core insulating layer 223 described above.

[0061] The core distribution pattern 241 may be patterned so as to be electrically connectable with the cavity element 40 .

[0062] The cavity element 40 may include an active element such as a transistor, or a power transfer element, ie, a passive element, such as a multi-layer ceramic capacitor (MLCC).

[0063] When an element such as a transistor that converts electrical signals between the motherboard and the semiconductor element portion to an appropriate level is applied as the cavity element 40, a transistor or the like is applied to the passage of the packaging substrate 20, thereby providing a semiconductor device 100 that is more efficient and has a higher speed.

[0064] In addition, power transfer devices such as multilayer ceramic capacitors (MLCCs) play an important role in the performance of semiconductor devices. Power transfer devices, which are passive devices, are generally applied to semiconductor devices in numbers of at least 200, and the performance of the device is also affected by the characteristics of the electrical conductive layer around the device when transferring power. In one embodiment, a non-circular core via can be applied to such power transfer devices, where an electrical conductive layer with low resistance is required.

[0065] Meanwhile, passive elements such as capacitors may be individually inserted and applied as the cavity element 40, or an element group including a number of passive elements embedded between insulating layers (cavity element insulating layers) may be formed with electrodes exposed and then inserted into the cavity element. In the latter case, the workability of manufacturing the packaging substrate may be further improved, and it is more advantageous for insulating layers to be positioned sufficiently and reliably in spaces between complex elements.

[0066] The glass substrate 21 acts as an intermediate or mediating role connecting the semiconductor device part 30 and the motherboard 10 at the upper and lower parts, respectively, and the core vias 23 act as paths for transmitting these electrical signals, thereby ensuring smooth signal transmission. The core vias arranged in the first area 221 are referred to as first area core vias 231 to distinguish them from the core vias in the second area 222 described below.

[0067] A top layer 26 is positioned on the first surface 213 .

[0068] The upper layer 26 may include an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25, and the top surface of the upper layer 26 may be protected by a cover layer 60 having an opening formed therein to which a connection electrode of a semiconductor element portion can directly abut.

[0069] The upper distribution layer 25 may include an upper insulating layer 253 located on the first surface, and an upper distribution pattern 251, which is an electrically conductive layer having a predetermined pattern and at least a portion of which is electrically connected to the core distribution layer 24, embedded in the upper insulating layer 253. The upper distribution layers 25 arranged one above the other may be connected to each other through blind vias 252.

[0070] The upper insulating layer 253 may be any material that can be used as an insulating layer for a semiconductor device or a packaging substrate, such as, but not limited to, an epoxy resin containing a filler.

[0071] The insulator layer may be formed by forming a coating layer and curing it, or may be formed by laminating an insulator film in an uncured or semi-cured state onto the core layer 22 and curing it. In this case, if a reduced pressure lamination method is used, the insulator can be filled into the inner space of the core via 23, allowing for efficient process.

[0072] According to one embodiment, even if multiple insulating layers are applied by stacking, it may be difficult to substantially separate the insulating layers, and the multiple insulating layers are collectively referred to as the upper insulating layer. Also, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case the boundary between them is not substantially separated. Alternatively, according to another embodiment, the boundary between the insulating layers may be created by setting different pressures and temperatures for curing the multiple insulating layers.

[0073] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a predetermined shape, and may be formed, for example, by a build-up layer method. In particular, an insulating layer may be formed, an unnecessary portion of the insulating layer may be removed, and an electrically conductive layer may be formed by a method such as copper plating. Then, an unnecessary portion of the electrically conductive layer may be selectively removed, and an insulating layer may be formed again on the electrically conductive layer. The method of removing the unnecessary portion of the formed insulating layer and forming an electrically conductive layer on the insulating layer by a method such as plating may be repeated. Through this, an upper distribution pattern 251 having an electrically conductive layer formed in a vertical or horizontal direction in a desired pattern may be formed.

[0074] The upper distribution pattern 251 is located between the core layer 22 and the semiconductor device part 30, and is formed to include a fine pattern in at least a part thereof so that electrical signals can be smoothly transmitted to the semiconductor device part 30 and the intended complex pattern can be fully accommodated. In this case, the fine pattern may have a width and interval each of less than 4 μm, 3.5 μm or less, 3 μm or less, 2.5 μm or less, or 1 to 2.3 μm (the same applies to the following explanation of the fine pattern).

[0075] The upper connection layer 27 includes an upper connection pattern 272 located on the upper insulating layer 253 and at least a portion of which is electrically connected to the upper distribution pattern 251, and an upper connection electrode 271 electrically connecting the semiconductor element portion 30 and the upper connection pattern 272.

[0076] The upper surface connection pattern 272 may be located on one surface of the upper insulating layer 253, or may be embedded with at least a portion thereof exposed on the upper insulating layer. For example, when the upper surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer may be formed by plating or the like, and the upper surface connection pattern embedded with a portion thereof exposed on the upper insulating layer may be formed by forming a copper plating layer, etc., and then removing a portion of the insulating layer or the electrically conductive layer by a method such as surface polishing or surface etching.

[0077] The upper connection pattern 272 may include a fine pattern at least in a portion thereof, like the above-mentioned upper distribution pattern 251. The upper connection pattern 272 including such a fine pattern can electrically connect more elements in a small area, facilitate the connection of electrical signals between elements or with the outside, and enable more integrated packaging.

[0078] The upper connection electrodes 271 may be directly connected to the semiconductor device part 30 via terminals or the like, or may be connected via device connection parts 51 such as solder balls.

[0079] The cavity portion 28 is located above and / or below the second region 222 and may include a cavity distribution layer 282 electrically connected to the core distribution pattern 241 and an internal space 281 in which the cavity element 40 is located. The cavity distribution layer 282 may be formed through a second region core via 232.

[0080] Specifically, the thickness of the glass substrate 21 in the second region 222 is thinner than that in the first region 221, and the cavity element 40 can be located in an internal space 281 formed by the difference in thickness. In addition, the core via 23 and the core distribution layer 24 formed in the glass substrate 21 serve as an electrical connection structure that connects the cavity element 40 to an external element.

[0081] Also, as described above, a cavity portion may be generated in the first area 221, i.e., penetrating the first surface 213 and the second surface 214 of the glass substrate 1, rather than the second area 222, and a cavity element 40 may be arranged in the cavity portion.

[0082] The packaging substrate 20 is also connected to the motherboard 10. A core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22 may be directly connected to a terminal of the motherboard 10, or the motherboard 10 and the packaging substrate 20 may be electrically connected to each other via a board connection part 52 such as a solder ball. In addition, the core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 via a lower layer (not shown) located under the core layer 22. The element connection part 51 and the board connection part 52 are collectively referred to as a connection part 50.

[0083] For example, the packaging substrate 20 located between the semiconductor device unit 30 and the motherboard 10 may not include any additional substrate other than the glass substrate 21 .

[0084] Conventionally, when connecting a device to a motherboard, an interposer and an organic substrate are laminated between them. This is understood to be applied in such a multi-layer form for at least two reasons. One is that there is a scale problem when directly bonding the fine pattern of the device to the motherboard, and the other is that there is a risk of damage to the wiring due to the difference in thermal expansion coefficient during the bonding process or the operation of the semiconductor device. In the embodiment, this problem is solved by applying a glass substrate with a thermal expansion coefficient similar to that of the semiconductor device, and forming a fine pattern with a fine scale sufficient for mounting the device on the first surface and the upper layer of the glass substrate.

[0085] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0086] 4 and 5 are flow charts illustrating a cross-sectional view of a manufacturing process of a packaging substrate according to an embodiment.

[0087] First, as shown in (a) of FIG. 4, a glass substrate 21a having flat first and second surfaces is prepared, and a defect (groove) 21b is formed on the glass surface at a predetermined position for forming a core via. The glass substrate may be a glass substrate used for substrates of electronic devices, for example, but is not limited to, an alkali-free glass substrate. As a commercially available product, a product manufactured by a manufacturer such as Corning, Schott, or AGC may be used. The defect (groove) may be formed by mechanical etching, laser irradiation, or other methods.

[0088] As shown in FIG. 4(b), the glass substrate 21a having the defect (groove) 21b undergoes an etching step to form a core via 23 through a physical or chemical etching process. In the etching process, the glass substrate forms a via in the defective portion, and the surface of the glass substrate 21a may also be etched at the same time. In order to prevent such etching of the glass surface, a masking film or the like may be applied. However, in consideration of the troublesome process of applying and removing the masking film, the glass substrate having the defect itself may be etched, and in this case, the thickness of the glass substrate having the core via may be somewhat thinner than the thickness of the initial glass substrate.

[0089] Thereafter, a core layer manufacturing step may be performed by forming an electrically conductive layer 21d on the glass substrate as shown in Fig. 4(c) and (d). The electrically conductive layer may be a metal layer typically including, but not limited to, copper metal.

[0090] The adhesion between the glass surface (including the glass substrate surface and the core via surface) and the copper metal surface may be poor due to their different properties. In the present embodiment, the adhesion between the glass surface and the metal may be improved by two methods, a dry method and a wet method.

[0091] The dry method is a method of applying sputtering, i.e., forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. The seed layer may be formed by sputtering different metals such as titanium, chromium, and nickel together with copper. In this case, the adhesion between the glass and the metal may be improved by the anchor effect caused by the interaction between the glass surface morphology and the metal particles.

[0092] The wet method is a method of performing a primer treatment, and is a method of forming a primer layer 21c by pretreating with a compound having a functional group such as an amine. Depending on the intended degree of adhesion, a primer treatment can be performed with a compound or particles having an amine functional group after pretreating with a silane coupling agent. As mentioned above, the support substrate of the embodiment needs to have high performance to be able to form a fine pattern, and this should be maintained even after the primer treatment. Therefore, when such a primer includes nanoparticles, it is preferable that nanoparticles having an average diameter of 150 nm or less are applied, and for example, it is preferable that nanoparticles are applied as particles having an amine group. The primer layer may be formed by applying an adhesion improver manufactured, for example, by MEC's ​​CZ series.

[0093] The seed layer / primer layer 21c may selectively form an electrically conductive layer or a metal layer with or without removing portions that do not require the formation of an electrically conductive layer. In addition, the seed layer / primer layer 21c may be selectively treated with portions that require or do not require the formation of an electrically conductive layer in an activated or inactivated state for metal plating, and the subsequent steps may be performed. For example, the activation or inactivation treatment may be a light irradiation treatment using a laser of a certain wavelength, a chemical treatment, or the like. The formation of the metal layer may be performed using a copper plating method or the like that is applied to the manufacture of semiconductor devices, but is not limited thereto.

[0094] As shown in (e) of Figure 4, a portion of the core distribution layer may be removed if unnecessary, or the seed layer may be partially removed or passivated, and then metal plating may be performed to form an electrically conductive layer in a predetermined pattern, thereby forming an etched layer 21e of the core distribution layer.

[0095] FIG. 5 illustrates a manufacturing step of forming an insulating layer and an upper distribution pattern according to one embodiment.

[0096] As shown in (a) of FIG. 5, the core via may undergo an insulating layer formation step of filling the vacant space with an insulating layer after the formation of the core distribution layer, which is the electrically conductive layer. The insulating layer may be manufactured in the form of a film. For example, a method of vacuum laminating an insulating layer in the form of a film may be applied. When vacuum lamination is performed in this manner, the insulating layer is sufficiently filled into the vacant space inside the core via, so that a core insulating layer without the formation of voids can be formed.

[0097] 5(b)-(e) illustrate the top layer fabrication steps.

[0098] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition forming the insulating layer 23a or laminating an insulating film, and the method of laminating an insulating film is preferable for simplicity. The lamination of the insulating film may be performed by laminating and curing the insulating film. In this case, if a reduced pressure lamination method is applied, the insulating resin may be sufficiently embedded even in layers in which no electrically conductive layer is formed inside the core via. The upper insulating layer is also directly abutted against the glass substrate at least in part, so that a material having sufficient adhesion is applied. Specifically, the glass substrate and the upper insulating layer preferably have a characteristic that satisfies an adhesion test value of 4B or more according to ASTM D3359.

[0099] The upper distribution pattern may be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form an etched layer 23d of the electrically conductive layer. In the case of electrically conductive layers formed adjacent to each other with an insulating layer in between, the blind vias 23b may be formed in the insulating layer and then a plating process may be performed. The blind vias may be formed by dry etching such as laser etching or plasma etching, or wet etching using a masking layer and an etchant.

[0100] Thereafter, a top connection layer and a cover layer may be formed, not shown.

[0101] The top connection pattern and the top connection electrodes may also be formed by a process similar to that for forming the upper distribution layer. Specifically, they may be formed by forming an etching layer of the insulating layer on the insulating layer 23e, forming an electrically conductive layer thereon, and then forming an etching layer of the electrically conductive layer. However, a method of selectively forming only the electrically conductive layer without applying the etching method may be applied. The cover layer may be formed by forming openings (not shown) at positions corresponding to the top connection electrodes to expose the top connection electrodes and allow them to be directly connected to element connection parts or element terminals.

[0102] After the upper layer is formed, a process of forming a lower connection layer and a cover layer to form a lower layer can be performed. In a similar manner to the above-mentioned upper connection layer and cover layer formation steps, a lower distribution layer and / or a lower connection layer, and optionally a cover layer (not shown) can be formed.

[0103] In this embodiment, a glass core is used as a support for the core layer. The glass core is a sheet glass, unlike the existing prepreg in which glass fibers are impregnated with a polymer. Although the glass core has the above-mentioned various advantages, it also has the disadvantage that defects such as breakage, cracks, and chipping may occur.

[0104] The cause of defects in glass cores is thought to be a combination of various factors. Stress or fine defects remaining in the glass core itself during the manufacturing process may crack due to impact, resulting in defects. Stress may also occur due to the influence of different materials formed in contact with both sides of the packaging substrate during the manufacturing process of the packaging substrate and / or repeated temperature changes. Such influences may lead to the occurrence of defects. Defects may also occur due to impacts applied during movement or processing. Defects that occur at the corners or edges of the glass core in a direction roughly perpendicular to the thickness direction are called sewerage. Sewerage progresses during the manufacturing process and can become large, deep and wide.

[0105] The embodiment proposes forming a protective layer to prevent fine defects or small cracks from developing into larger defects. In addition, in the manufacturing process of the packaging substrate, a process of relaxing the stress of the substrate may be additionally performed in order to prevent the occurrence of cracks, but this may reduce the manufacturing efficiency of the packaging substrate. The embodiment proposes an invention that applies a side protective layer that induces the occurrence of defects such as cracks, cracks, and chipping and fills the portions without additionally performing a process of relaxing the stress.

[0106] Fig. 6 is a perspective view of a substrate having a side protection layer according to an embodiment. Figs. 7A, 8A, and 9A are exemplary conceptual diagrams of a cross section of the substrate before forming a side protection layer as seen along line A-A' in Fig. 6, and Figs. 7B, 8B, and 9B are exemplary conceptual diagrams of a cross section of the substrate after forming a side protection layer as seen along line A-A' in Fig. 6. An embodiment will be described in detail below with reference to Figs. 6 to 9B.

[0107] In one or more embodiments, a substrate including a packaging substrate 20 on which one or more electronic elements are disposed is provided. The substrate includes a glass core 21 including a first surface 213 and a second surface 214 facing each other and a side surface 216 connecting the first surface and the second surface; an upper layer 26 laminated on the first surface or a lower layer 29 laminated under the second surface; and a side surface protection layer 70 that encases the side surface of the glass core with a protective material.

[0108] The description of the glass core, the core portion, the upper layer, the lower layer, etc., is the same as that described above. In addition, the formation of a cavity, etc., may also be applied to the embodiment.

[0109] Defect C is formed from side surface 216 of the glass core toward the inside of the glass core, and the protective material fills the space in the glass core caused by the defect.

[0110] Although it is preferable that defects in the glass core are not formed, they may be formed in the manufacturing process of the packaging substrate with a relatively high probability. The side protection layer 70 may be formed at the stage where defects are found. For example, the side protection layer 70 may be selectively formed one or more times on the substrate i) before forming the upper layer 26 and / or the lower layer 29 on the glass core, ii) during the process of forming the upper layer and / or the lower layer on the glass core, iii) after forming the upper layer and / or the lower layer on the glass core, or iv) after singulation into one or more individual packaging substrates.

[0111] The side protection layer 70 envelops the side surface 216 of the glass core and simultaneously fills the defect C. The side protection layer includes a protective material.

[0112] The protective material may include an elastic material.

[0113] The elastomeric material may include an elastomeric polymer that includes silane functional groups.

[0114] The elastic material may specifically be a silicone elastomer.

[0115] The elastic material may have a Young's modulus of 0.1 GPa or more, 1 GPa or more, or 2 GPa or more at 24° C. The Young's modulus may be 17 GPa or less, 15 GPa or less, 12 GPa or less, or 10 GPa or less.

[0116] The protective material may have a viscosity of 1,000 cP or more, 2,000 cP or more, or 3,000 cP or more in a solution state at 25° C. before curing. The viscosity may be 50,000 cP or less, 30,000 cP or less, 20,000 cP or less, or 10,000 cP or less. When a protective material having such a viscosity range is used, increasing the temperature to inject the protective material so that it is well embedded even in minute defects, and then lowering the temperature helps to maintain the injected state stably.

[0117] The elastic material may be cured at a curing temperature of 120°C or more. The curing may be performed by inducing a chemical reaction between the base resin and the curing agent. During the curing process, the degree of chemical bonding within the elastic material may be increased, and the mechanical strength of the protective material may be imparted and adjusted. The curing temperature may be 120°C or more, 125°C or more, or 130°C or more. The curing temperature may be 180°C or less, 175°C or less, or 160°C or less.

[0118] The curing temperature may be maintained for a curing time. The curing time may be 3 minutes or more, 5 minutes or more, or 7 minutes or more. The curing time may be 40 minutes or less, 35 minutes or less, or 30 minutes or less. When curing is performed for such a curing time, a protective material having stable mechanical properties can be obtained.

[0119] The protective material may contain 70% or more by weight of silicone elastomer. The protective material may contain 80% or more by weight of silicone elastomer. The protective material may contain 90% or more by weight of silicone elastomer. The protective material may contain 100% or less by weight of silicone elastomer.

[0120] The side protection layer 70 may be a silicone elastomer layer.

[0121] The silicone elastomer may be a cross-linked product of a silicone resin base material and a curing agent.

[0122] The base agent may include an alkene group at one or more ends. The base agent may have the structure of Formula 1 below.

[0123] [ka]

[0124] In the above Chemical Formula 1, n is an integer of 20-60.

[0125] The curing agent may have the structure of Formula 2 below.

[0126] [ka]

[0127] In the above Chemical Formula 2, x and y are each independently an integer of 2 to 10.

[0128] During the curing process, the alkene group contained in the base resin can form a crosslink with the curing agent, thereby improving the crosslink density in the blend resin and imparting a controlled rigidity to the protective material.

[0129] When forming the protective material, 3 parts by weight or more, 5 parts by weight or more, or 8 parts by weight or more of the curing agent may be applied relative to 100 parts by weight of the base material. When forming the protective material, 20 parts by weight or less, or 15 parts by weight or less of the curing agent may be applied relative to 100 parts by weight of the base material. When forming the protective material in such a range, it can be useful to more easily fill spaces caused by defects and to impart appropriate elasticity, strength, etc. to the side protective layer.

[0130] The side protection layer may be formed by applying a pre-cured composition of the protection material to the side of the substrate having defects such as cracks or chipping, and curing and fixing the composition. The application may be performed by, but is not limited to, dipping, slit coating, dry film coating, dispensing, or the like.

[0131] The tensile strength of the side protective layer 70 may be 1 MPa to 20 MPa. The tensile strength may be 2 MPa or more. The tensile strength may be 4 MPa or more. The tensile strength may be 15 MPa or less. The tensile strength may be 10 MPa or less. In such a case, even if the glass core 21 has a structure that is vulnerable to impact, the substrate can have stable durability. The tensile strength can be measured using a Universal Testing Machine (UTM).

[0132] The thermal expansion coefficient of the side protective layer 70 is 100 ppm / °C to 800 ppm / °C. The thermal expansion coefficient may be 150 ppm / °C or more. The thermal expansion coefficient may be 200 ppm / °C or more. The thermal expansion coefficient may be 250 ppm / °C or more. The thermal expansion coefficient may be 300 ppm / °C or more. The thermal expansion coefficient may be 700 ppm / °C or less. The thermal expansion coefficient may be 600 ppm / °C or less. The thermal expansion coefficient may be 500 ppm / °C or less. The thermal expansion coefficient may be 400 ppm / °C or less. In this case, the substrate can have stable durability and electrical reliability even in repeated heat treatment. The thermal expansion coefficient can be measured by a Thermal Mechanical Analyzer (TMA) using a thermomechanical analysis method. For example, the thermal expansion coefficient can be measured using a TMA of the Q400 model manufactured by TA Instruments.

[0133] The dielectric constant of the side protective layer 70 at a frequency of 100 Hz may be 4 or less. The dielectric constant may be 3.5 or less. The dielectric constant may be 3 or less. The dielectric constant may be 2.8 or less. The dielectric constant may be 1.5 or more.

[0134] The dielectric constant of the side protective layer 70 at a frequency of 100 kHz may be 4 or less. The dielectric constant may be 3.5 or less. The dielectric constant may be 3 or less. The dielectric constant may be 2.8 or less. The dielectric constant may be 1.5 or more.

[0135] In this case, signals can be efficiently transmitted through the electrically conductive layer pattern formed on the side surface protective layer 70. The dielectric constant of the side surface protective layer 70 is measured by a dielectric constant meter at room temperature.

[0136] The side protection layer may be formed when defects such as cracks and chipping occur in the glass core. Therefore, when it is confirmed that defects such as cracks and chipping occur in the glass core itself, the side protection layer may be formed on the glass core. In this case, the side protection layer may be formed exclusively on the side of the glass core, not on the side of the upper layer or the side of the lower layer.

[0137] If defects such as cracks, chipping, etc. occur in the glass core during the formation of the upper layer and / or lower layer, the side protection layer may be formed. In this case, a side protection layer may be formed to cover a part or the entire side of the upper layer and / or lower layer.

[0138] The side protective layer may further encase at least a portion of the upper layer or the lower layer with the protective material.

[0139] When observing the cross section of the substrate where the defect occurred, it can be seen that there is a laminated structure of glass-protective material-glass, which prevents the defect from expanding and allows the production of packaging substrate products even if glass damage such as defects occurs, thereby improving the efficiency of the manufacturing process.

[0140] In one or more embodiments, the substrate may be a strip substrate in which a number of individual packaging substrates are arranged with dummy areas interposed therebetween.

[0141] In one or more embodiments, the substrate may be a quad substrate in which multiple strip substrates are arranged with dummy regions interposed therebetween.

[0142] In one or more embodiments, the substrate may be a panel substrate in which a plurality of quad substrates are arranged with dummy regions interposed therebetween.

[0143] In the case of a substrate that is a strip substrate, a quad substrate, or a panel substrate, defects that occur in dummy regions at the edges of the substrate are filled with a protective material, and a side protective layer is formed to prevent additional defects from being generated in the substrate, cracks due to external impact, etc. When the strip substrate is separated into individual packaging substrates, the side protective layer may be removed.

[0144] In one or more embodiments, the substrate may be an individual packaging substrate. In this case, defects may occur on the side of the individual packaging substrate during the singulation process of the individual packaging substrate, which may cause additional cracks during subsequent processes such as moving and mounting devices. Therefore, a side protection layer may be formed on the individual packaging substrate after the singulation process, thereby improving the storage stability, such as impact resistance, of the individual packaging substrate.

[0145] In one or more embodiments, the entire side of the substrate, including the side of the upper layer and / or the lower layer and the side of the glass core, may be substantially perpendicular to the first and second sides (see FIGS. 7A and 7B). If the side is substantially perpendicular, defects such as breaks and cracks may occur at corners, etc., so a side protection layer may be formed to protect the substrate as shown in FIG. 7B.

[0146] In one or more embodiments, the substrate may have a side surface of the upper layer and / or the lower layer disposed inside the side surface of the glass core (see FIGS. 8A and 8B). In this case, a side surface protection layer may be formed to protect the substrate, and the side surface protection layer may be formed in a shape that covers both the step portion located between the upper layer and the first surface and the step portion located between the lower layer and the second surface as shown in FIG. 8B, thereby protecting the substrate.

[0147] In one or more embodiments, the substrate may have a glass core with a protruding central portion on the side. Specifically, the glass core may have a protruding central portion on the side, upper and lower edges may be chamfered, and the side of the upper layer and / or the lower layer may be disposed inside the side of the glass core (see FIGS. 9A and 9B). In this case, the side protection layer may be tapered toward the first and second sides from the glass core with the side of the upper layer and / or the lower layer as the center. In this case, the side protection layer may be formed in a form that envelops the tapered side of the upper layer, the side of the glass core with the protruding central portion, and the tapered side of the lower layer as shown in FIG. 9B, to protect the substrate.

[0148] A manufacturing method for a substrate according to another embodiment is a manufacturing method for a substrate having a side protection layer, and includes step A of providing a glass core having a first surface and a second surface facing each other, and forming an upper layer on the first surface and a lower layer below the second surface to provide a substrate; and step B of providing a side protection layer on a side of the substrate.

[0149] The glass core of the substrate has defects formed on its sides, and the side protection layer fills the defects with a protective material and encases the sides of the glass core. The specific structure, shape, physical properties, etc. are the same as those described above, so detailed description will be omitted.

[0150] The method for providing the upper layer and / or the lower layer is the same as that described above, and therefore a detailed description thereof will be omitted.

[0151] The method of forming the side protection layer may be a method of preparing a pre-hardened protective material (composition) in the form of a liquid or dry film, applying the pre-hardened protective material, and hardening the applied material. The thickness of the side protection layer is sufficient to enclose the side of the glass core, and the side protection layer that encloses the side of the glass core while filling the space of the defect can substantially suppress the spread of damage to the glass core and protect the glass core from additional impacts.

[0152] In the method for producing the substrate, step C can be performed one or more times during step A or between step A and step B.

[0153] The step C is a step of checking for the occurrence of defects on the substrate of the step A.

[0154] Step C may be repeated during the formation of the applied glass core, upper layer, and / or lower layer, illustratively after forming one or more insulating layers containing a polymer.

[0155] In the method for manufacturing the substrate, step D may be further performed after step A.

[0156] The substrate in step A is a substrate in which a plurality of individual packaging substrates are arranged with dummy regions interposed therebetween, and step D is a singulation step in which the individual packaging substrates are separated to obtain a packaging substrate.

[0157] As the singulation method, a known method may be applied.

[0158] The singulation method can, for example, involve removing an upper layer and / or a lower layer along a cutting line, forming a groove in a portion of the glass core, and then impacting the substrate to obtain an individual packaging substrate with the dummy area removed along the cutting line.

[0159] The cut surface from which the dummy region is removed may be substantially linear, and may have a cross section in the shape of Fig. 7A or Fig. 8A. In addition, the glass core in the cross section of Fig. 8B may have a chamfered or ground shape through a grinding operation or the like, and may have a cross section in the shape of Fig. 9A. The occurrence of defects in the cross section may be confirmed, and a side protection layer may also be formed on the side of the singulated individual packaging substrate.

[0160] The substrate of the embodiment can reduce defects of the packaging substrate caused by defects such as SeWaRe that tend to occur (or appear) in the glass core, and can improve durability. In addition, the substrate manufacturing yield can be improved by repairing the defects that occur without a separate process for relieving stress in the glass core. In addition, the substrate can minimize the occurrence of additional defects such as cracks and chipping at the edges and / or corners of the substrate that may occur when the substrate is placed on a tray or boat for processing.

[0161] Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the appended claims also fall within the scope of the present invention. [Explanation of symbols]

[0162] 100 Semiconductor device 10 Motherboard 30 Semiconductor Device Section 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging Substrate 21, 21a Glass substrate, glass core 22 Core Layer 223 Core insulation layer 213 Page 1 214 2nd page 216 Side 23 Corebia 24 Core Distribution Layer 241 Core Distribution Pattern 26 Upper layer 25 Upper distribution layer 251 Upper distribution pattern 253 Upper insulating layer 27 Top connection layer 271 Top connection electrode 272 Top connection pattern 28 Cavity 29 Lower Layer 70 Side protection layer C Defect

Claims

1. A substrate including a packaging substrate on which one or more electronic devices are disposed, a glass core including a first surface and a second surface opposed to each other and a side surface connecting the first surface and the second surface; an upper layer laminated on the first surface or a lower layer laminated under the second surface; and a side protection layer that wraps the side of the glass core with a protective material; The defect is formed from a side surface of the glass core toward an inside of the glass core, The protective material fills spaces within the glass core caused by the defects.

2. The substrate of claim 1 , wherein the protective material has a Young's modulus of 0.1 GPa to 17 GPa at 24° C.

3. the packaging substrate includes the upper layer and the lower layer, The substrate of claim 1 , wherein the side protection layer envelops a side surface of the upper layer, a side surface of the glass core, and a side surface of the lower layer.

4. The protective material includes an elastic polymer resin; The substrate of claim 1 , wherein the elastic polymer resin has a curing temperature of 120° C. or higher.

5. The substrate is a strip substrate in which a plurality of the individual packaging substrates are arranged with dummy regions interposed therebetween; a quad substrate in which the dummy area is disposed between a plurality of the strip substrates; a panel substrate in which the dummy area is disposed between a plurality of the quad substrates; or The substrate of claim 1 which is the individual packaging substrate.

6. The substrate according to claim 1 , wherein a side surface of the glass core protrudes beyond a side surface of the upper layer or a side surface of the lower layer.

7. The substrate of claim 1 , wherein the protective material comprises an elastomeric polymer containing silane functional groups.

8. A method for manufacturing a substrate having a side protection layer, comprising the steps of: Step A provides a substrate by providing a glass core having a first surface and a second surface opposed to each other, and forming an upper layer on the first surface and a lower layer below the second surface; and step B of providing a side protection layer on a side surface of the substrate, the glass core of the substrate has a defect formed on a side surface; The side surface protection layer fills the defects with a protective material and encases the side surfaces of the glass core.

9. The method for manufacturing the substrate includes performing step C one or more times during step A or between step A and step B, 9. The method for manufacturing a substrate according to claim 8, wherein said step C is a step of checking for the occurrence of defects in the substrate in said step A.

10. The method for manufacturing the substrate further includes a step D after the step A, The substrate in step A is a substrate in which a plurality of individual packaging substrates are arranged with dummy regions interposed therebetween; The method for manufacturing a substrate according to claim 8 , wherein step D is a singulation step of separating the individual packaging substrates to obtain the packaging substrate.

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