Wiring structure

Abstract

To suppress a conduction defect of three-dimensional wiring connected to a thin-film transistor in an upper surface side of a board from a lower surface side.SOLUTION: A wiring structure 1 includes: a first wiring layer 41 disposed on an upper surface of a board 10; an insulation layer 45 that is disposed on an upper surface of the first wiring layer 41 and becomes a gate insulation film 64 of a thin-film transistor 60; a second wiring layer 42 disposed on an upper surface of the insulation layer 45; a back wire 47 disposed on a lower surface of the board 10; and three-dimensional wires 31, 32 that are disposed in a thickness direction of the insulation layer 45 and the board 10 and connect each of the first wiring layer 41 and the second wiring layer 42 to the back wire 47. A gate electrode 61 of the thin-film transistor 60 is provided in one of the first wiring layer 41 and the second wiring layer 42; a source electrode 62 and a drain electrode 63 of the thin-film transistor 60 are provided in the other; and a three-dimensional wire in a side of the insulation layer 45 and a three-dimensional wire in a side of the board 10 are relayed by a relay electrode 35 provided in the first wiring layer 41 in the three-dimensional wire 32 for connecting the second wiring layer 42 to the back wire 47.SELECTED DRAWING: Figure 4B

Description

Technical Field

[0001] The present invention relates to a wiring structure of a circuit including a thin film transistor.

Background Art

[0002] A tiling display is a display device capable of realizing various sizes, shapes, and aspect ratios by arranging a plurality of panel units (tiling). In the case of a general panel unit, it is necessary to form signal wirings and the like at its peripheral portion, and it is difficult to narrow the region (frame, bezel) where the image of the peripheral portion is not displayed. Therefore, when the panel units are arranged and tiled, the bezel at the joint between the panel units becomes conspicuous.

[0003] In a panel unit, for example, when a light-emitting diode (LED) is used as a light-emitting element, a thin film transistor (TFT) serving as a switching element is formed on the display surface side (upper surface side) of the substrate. In recent years, as an element technology for bezel-less panel units, a TFT (three-dimensional wiring TFT, Non-Patent Document 1) and a TFT backplane that can be driven by three-dimensional wiring through a through-hole from the back surface side of the film substrate have been developed (Non-Patent Document 2). If signal wirings and the like can be taken out to the back surface side of the panel unit, it becomes unnecessary to arrange signal wirings and the like at the peripheral portion, and bezel-less (inconspicuous) tiling becomes possible.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

[0005] For example, when the TFT of the pixel of the panel unit is of the bottom gate type, as illustrated in FIG. 11, the wiring layer 941 of the gate electrode disposed on the upper surface of the substrate 910 can be taken out to the back surface side (lower surface side) of the substrate 910 by the three-dimensional wiring 931 penetrating the substrate 910 in its thickness direction and connected to the back surface wiring 947. On the other hand, the wiring layer 942 of the source electrode and the drain electrode disposed on the upper surface of the insulating layer 945 will be taken out to the lower surface side by the three-dimensional wiring 932 penetrating the insulating layer 945 and the substrate 910. The through holes for arranging these three-dimensional wirings 931 and 932 can be formed from the lower surface side of the substrate 910.

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, when forming through holes by dry etching from the lower surface side of the substrate, it is difficult to form through holes in the insulating layer 945 compared to the through holes in the substrate 910. Therefore, there has been a problem that the three-dimensional wiring 932 penetrating the insulating layer 945 is likely to have a conduction failure at a portion 938 close to the wiring layer 942 on the upper surface of the insulating layer 945. The present invention has been made in view of the above circumstances, and an object thereof is to provide a wiring structure that suppresses conduction failure of three-dimensional wiring connected from the lower surface side to a thin film transistor on the upper surface side of a substrate.

Means for Solving the Problems

[0007] The wiring structure according to the embodiment is a wiring structure that connects a thin film transistor disposed on the upper surface side of a substrate from the lower surface side, and includes a first wiring layer disposed on the upper surface of the substrate, an insulating layer disposed on the upper surface of the first wiring layer and serving as a gate insulating film of the thin film transistor, a second wiring layer disposed on the upper surface of the insulating layer, a back surface wiring disposed on the lower surface of the substrate, and a three-dimensional wiring disposed in the thickness direction of the insulating layer and the substrate and connecting each of the first wiring layer and the second wiring layer to the back surface wiring. A gate electrode of the thin film transistor is provided on one of the first wiring layer and the second wiring layer, and a source electrode and a drain electrode of the thin film transistor are provided on the other. In the three-dimensional wiring that connects the second wiring layer to the back surface wiring, the three-dimensional wiring on the insulating layer side and the three-dimensional wiring on the substrate side are relayed by a relay electrode provided on the first wiring layer.

[0008] Also, the pixel wiring structure according to the embodiment is a pixel wiring structure including the wiring structure according to the embodiment, and a scanning line, a data line, a power supply line, and a ground line in the pixel are respectively provided on the first wiring layer or the second wiring layer. At least one of the scanning line, the data line, the power supply line, and the ground line is connected to the back surface wiring by the three-dimensional wiring relayed by the relay electrode.

Advantages of the Invention

[0009] According to the present invention, it is possible to suppress conduction failure of the three-dimensional wiring that connects the thin film transistor on the upper surface side of the substrate from the lower surface side.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 4A

Figure 4B

Figure 5

Figure 6A

Figure 6B

Figure 6C

Figure 6D

Figure 6E

Figure 6F

Figure 6G

Figure 6H

Figure 6I

Figure 6J

Figure 6K

Figure 6L

Figure 7A

Figure 7B

Figure 7C

Figure 8

Figure 9A

Figure 9B

Figure 10

Figure 11

BEST MODE FOR CARRYING OUT THE INVENTION

[0011] [Wiring Structure] The wiring structure 1 according to the embodiment will be described with reference to FIGS. 1 to 4B. The wiring structure 1 is, for example, a wiring structure in a display device or the like that displays an image. As an example of the display device, there is a tiling display 200 as illustrated in FIG. 1. The tiling display 200 is a display device in which a plurality of panel units 100 are arranged side by side. The panel unit is a display device in which light-emitting elements and the like are arranged in a matrix direction with a thin film transistor (TFT) formed on a substrate as a switching element. Here, twelve rectangular panel units 100 are arranged side by side in a plan view. There are no particular restrictions on the shape of the panel unit or the number of panel units arranged. Note that the upper surface in FIG. 1 is the image display surface.

[0012] As illustrated in FIG. 2, pixels 50 are arranged in a matrix in the panel unit 100. The pixel 50 is a section of a display device corresponding to a pixel as the minimum unit of an image. Further, scanning lines SL and the like are arranged so as to pass through each pixel. Here, the scanning lines SL and the like and the TFTs which are switching elements are arranged on the upper surface side of the substrate.

[0013] In the panel unit 100, signal wirings and the like for connecting the TFTs, the scanning lines SL, and the like to the outside are further required. If such signal wirings and the like can be arranged on the lower surface side of the substrate, the width of the bezel 120 can be narrowed. Therefore, an element circuit in which the TFTs are arranged on the upper surface side of the substrate will be described as an example. The element circuit 2A illustrated in FIG. 3A has a bottom gate type TFT 60 on the upper surface side of the substrate, and the wirings of the first wiring layer 41 and the second wiring layer 42 extend in the vertical direction in the figure. Then, the three-dimensional wirings 31 and 32 for connecting the first wiring layer 41 and the second wiring layer 42 to the lower surface side of the substrate are arranged at positions separated from the TFT 60 in a plan view. Note that FIG. 3A omits the protective layer 18 to be described later, and the first wiring layer 41, the second wiring layer 42, and the semiconductor layer 65 layer on which patterns are formed are shown with different line types. The same applies to FIGS. 4A, 7A, and 9A.

[0014] The wiring structure 1 is a wiring structure for connecting a thin film transistor 60 arranged on the upper surface side of the substrate 10 from the lower surface side, and includes a first wiring layer 41, an insulating layer 45, a second wiring layer 42, a back surface wiring 47, and three-dimensional wirings 31 and 32. The three-dimensional wiring 32 for connecting the second wiring layer 42 to the back surface wiring 47 through a relay electrode 35 provided in the first wiring layer 41 is relayed. Hereinafter, each component of the wiring structure 1 will be described.

[0015] (Substrate) As illustrated in FIGS. 3B and 3C, the substrate 10 is a member that serves as a base for the element circuit 2A. The substrate 10 has a base material 12, an underlayer 14, and a planarization layer 16. Further, the substrate 10 has a lower through-hole 24 in which a three-dimensional wiring 31 or a lower three-dimensional wiring 32B described later is disposed. The lower through-hole 24 is a through-hole that penetrates the substrate 10, that is, the underlayer 14, the base material 12, and the planarization layer 16 in the thickness direction thereof. In the display device, one substrate serves as a common base for a large number of pixels, and the size and shape of the substrate can be the size and shape of the display device. The base material 12 is an insulating film-like or plate-like member. Various materials employed in printed wiring boards or the like can be used for the base material 12. Here, an insulating plastic is thinly formed in a film shape to form a flexible film substrate capable of being bent and deformed. The material of the film substrate can be various plastics such as polyimide (PI), polyethylene terephthalate (PET), etc., according to the application. Here, polyimide with excellent heat resistance is used. The thickness of the base material 12 can be, for example, from 5 μm to 20 μm, and here it is 8 μm.

[0016] The underlayer 14 is a silicon nitride layer that covers the surface of the base material 12 on the side where the TFT 60 is disposed. By providing the underlayer 14, the adhesion between the substrate and the member disposed on the upper surface of the substrate can be improved. Note that the surface on which the underlayer 14 is provided is the upper surface of the base material 12. That is, the upper surface of the substrate 10 becomes the underlayer 14, and the TFT 60 is disposed on the upper surface side of the substrate 10. The underlayer 14 can be, for example, a silicon nitride film. The thickness of the underlayer 14 can be, for example, from 30 nm to 100 nm, and here it is 50 nm. The planarization layer 16 is a layer that covers the surface of the base material 12 on the side opposite to the side where the TFT 60 is disposed. The planarization layer 16 can be an insulating coating-film-formable organic film or a fluororesin film. For example, ZEOCOAT (registered trademark) manufactured by Nippon Zeon Co., Ltd. can be cited as the material of such an organic film, and CYTOP (registered trademark) manufactured by AGC Inc. can be cited as the material of the fluororesin film. The planarization layer 16 can improve the flatness of the lower surface of the substrate 10.

[0017] (Thin film transistor) The thin film transistor (TFT) 60 is an element responsible for switching the circuit and controlling the current. The structure as a TFT is not particularly limited. As illustrated in FIG. 3B, here, it is a bottom gate type in which the gate electrode 61 is disposed on the substrate 10 side, and is a top contact type TFT in which the source electrode 62 and the drain electrode 63 are located on the upper surface of the semiconductor layer (active layer) 65. The TFT 60 has a gate electrode 61, a semiconductor layer 65, a gate insulating film 64, a source electrode 62, and a drain electrode 63. The TFT 60 has the gate electrode 61 disposed in contact with the underlying layer 14 via an insulating layer 45 serving as the gate insulating film 64 below the semiconductor layer 65. Various materials can be used for the semiconductor layer 65, such as amorphous silicon or an organic semiconductor. Here, it is In-Sn-Ga-O (ITZO) of an oxide semiconductor. The material of the semiconductor layer 65 may be, for example, In-Ga-Zn-O (IGZO) or In-Ga-Zn-Sn-O (IGZTO). The semiconductor layer 65 is disposed on the upper surface of the insulating layer 45 serving as the gate insulating film 64.

[0018] (First wiring layer and second wiring layer) The first wiring layer 41 and the second wiring layer 42 are layers having conductor patterns in the plane direction of the substrate 10. The first wiring layer 41 is the wiring layer closer to the substrate 10 among the two wiring layers on the upper surface side of the substrate 10. The first wiring layer 41 is disposed on the upper surface 10A of the substrate 10. Also, the first wiring layer 41 has a relay electrode 35 described later. The second wiring layer 42 is the wiring layer farther from the substrate 10 among the two wiring layers on the upper surface side of the substrate 10. The second wiring layer 42 is disposed on the upper surface of the insulating layer 45.

[0019] Electrodes of the TFT are provided in the first wiring layer 41 and the second wiring layer 42 together with the wiring. One of the first wiring layer 41 and the second wiring layer 42 is provided with the gate electrode 61 of the thin film transistor 60, and the other is provided with the source electrode 62 and the drain electrode 63 of the thin film transistor 60. Here, the TFT 60 is of the bottom gate type, the gate electrode 61 is provided on the first wiring layer 41, and the source electrode 62 and the drain electrode 63 are provided on the second wiring layer 42. The gate electrode 61 is the region of the first wiring layer 41 facing the semiconductor layer 65. The source electrode 62 and the drain electrode 63 are the regions of the second wiring layer 42 on the upper surface of the semiconductor layer 65.

[0020] The materials of the first wiring layer 41 and the second wiring layer 42 are, for example, molybdenum, aluminum, gold, nickel, copper, etc., and a metal laminated film formed by laminating these can be used. The first wiring layer 41 and the second wiring layer 42 are preferably formed of a laminated film of a metal containing molybdenum. For example, the first wiring layer 41 can be a wiring layer that achieves both conductivity and process resistance by adopting a laminated structure in which a layer of aluminum with high electrical conductivity is sandwiched between layers of molybdenum with high process resistance. The thickness of each of the first wiring layer 41 and the second wiring layer 42 can be set to be from 50 nm to 500 nm, and here it is set to 200 nm.

[0021] (Insulating layer) The insulating layer 45 is a layer that insulates the first wiring layer 41 and the second wiring layer 42. Also, the insulating layer 45 serves as the gate insulating film 64 of the TFT between the semiconductor layer 65 and the gate electrode 61. That is, the insulating layer 45 is disposed on the upper surface of the first wiring layer 41 and serves as the gate insulating film 64 of the thin film transistor 60. Further, the insulating layer 45 has an upper through hole 22 in which the upper three-dimensional wiring 32A described later is disposed. The upper through hole 22 is a through hole that penetrates the insulating layer 45 in its thickness direction. The insulating layer 45 is arranged to cover the entire upper surface of the substrate 10, and the lower surface of the insulating layer 45 is in contact with the upper surface 10A of the first wiring layer 41 and the substrate 10. The thickness of the insulating layer 45 can be, for example, from 100 nm to 300 nm, and here it is 200 nm. The material of the insulating layer 45 can be, for example, silicon oxide, silicon nitride, or a laminated film thereof, and here it is silicon oxide.

[0022] (Backside wiring) The backside wiring 47 is a wiring arranged on the surface of the substrate 10 opposite to the surface on which the TFTs of the substrate 10 are arranged. The backside wiring 47 can distribute, for example, signals from the outside, etc. at the position of the lower surface of the substrate 10 from which the first wiring layer 41 and the second wiring layer 42 are led out. The backside wiring 47 is arranged on the lower surface 10B of the substrate 10. The backside wiring 47 is arranged on the lower surface of the planarization layer 16 when the planarization layer 16 is provided, and on the lower surface of the base material 12 when the planarization layer 16 is not provided. The backside wiring 47 may have a backside electrode for connecting the backside wiring 47 to the outside. The material of the backside wiring 47 can be the same as that of the first wiring layer 41 or the second wiring layer 42. The thickness of the backside wiring 47 can be, for example, from 100 nm to 500 nm, and here it is 300 nm. Also, a coating layer for covering and protecting the backside wiring 47 may be provided.

[0023] (Three-dimensional wiring) As illustrated in FIG. 3C, the three-dimensional wirings 31, 32 are arranged in the thickness direction of the insulating layer 45 and the substrate 10, and are wirings for connecting each of the first wiring layer 41 and the second wiring layer 42 to the backside wiring 47. The three-dimensional wiring 31 for connecting the first wiring layer 41 to the backside wiring 47 connects the lower surface of the first wiring layer 41 and the upper surface of the backside wiring 47. In the three-dimensional wiring 32 that connects the second wiring layer 42 to the back surface wiring 47, the three-dimensional wiring on the insulating layer 45 side and the three-dimensional wiring on the substrate 10 side are relayed by the relay electrode 35 provided in the first wiring layer 41. The three-dimensional wiring 32 has an upper three-dimensional wiring 32A above the first wiring layer 41, that is, on the insulating layer 45 side, and a lower three-dimensional wiring 32B below the first wiring layer 41, that is, on the substrate 10 side. The upper three-dimensional wiring 32A and the lower three-dimensional wiring 32B are relayed by the relay electrode 35 provided in the first wiring layer 41 and are electrically connected.

[0024] The upper surface of the relay electrode 35 is connected to the upper three-dimensional wiring 32A, and the lower surface of the relay electrode 35 is connected to the lower three-dimensional wiring 32B. The relay electrode 35 is separated from other patterns and isolated in the first wiring layer 41. That is, the relay electrode 35 is not connected to anything other than the upper three-dimensional wiring 32A and the lower three-dimensional wiring 32B to be relayed, and is only connected to the three-dimensional wiring 32. The relay electrode 35 is arranged in a size and shape that includes the lower three-dimensional wiring 32B on the lower surface of the relay electrode 35 and the upper three-dimensional wiring 32A on the upper surface of the relay electrode 35, and is arranged at a position that includes these.

[0025] Here, the upper three-dimensional wiring 32A is continuous from the second wiring layer 42 to the upper surface of the relay electrode 35 and is connected to the upper surface of the relay electrode 35. The material of the upper three-dimensional wiring 32A is the same as that of the second wiring layer 42. Also, the lower three-dimensional wiring 32B is continuous from the back surface wiring 47 to the lower surface of the relay electrode 35 and is connected to the lower surface of the relay electrode 35. The material of the lower three-dimensional wiring 32B is the same as that of the back surface wiring 47. The material of the relay electrode 35 is the same as that of the first wiring layer 41. The relay electrode 35 is preferably formed of a laminated film of a metal containing molybdenum, like the first wiring layer 41.

[0026] In the three-dimensional wiring 32 that connects the second wiring layer 42 to the back surface wiring 47, it is preferable that the three-dimensional wirings 32 on the insulating layer 45 side and the substrate 10 side of the relay electrode 35, that is, the upper three-dimensional wiring 32A and the lower three-dimensional wiring 32B, are arranged at overlapping positions in a plan view. The overlapping position in the plan view means a position where the center of the lower three-dimensional wiring 32B on the lower surface of the relay electrode 35 is included in the range of the upper three-dimensional wiring 32A on the upper surface of the relay electrode 35 in the plan view. Here, the central axes of the upper three-dimensional wiring 32A and the lower three-dimensional wiring 32B are arranged on the same straight line. By arranging the upper three-dimensional wiring 32A and the lower three-dimensional wiring 32B at overlapping positions in the plan view, it is possible to suppress an increase in the area of the three-dimensional wiring 32 due to the provision of the relay electrode 35.

[0027] The three-dimensional wirings 31 and 32 are arranged in through-holes. The upper three-dimensional wiring 32A is arranged in an upper through-hole 22 that penetrates the insulating layer 45. The three-dimensional wiring 31 and the lower three-dimensional wiring 32B are arranged in a lower through-hole 24 that penetrates the substrate 10. The relay electrode 35 has a size and shape that includes the openings on the relay electrode 35 side of the upper through-hole 22 and the lower through-hole 24. By setting the position such that the center of the opening on the relay electrode 35 side of the lower through-hole 24 is included in the opening on the relay electrode 35 side of the upper through-hole 22 in the plan view, the upper three-dimensional wiring 32A and the lower three-dimensional wiring 32B of the three-dimensional wiring 32 can be arranged at overlapping positions in the plan view. Here, the central axes of the upper through-hole 22 and the lower through-hole 24 are arranged on the same straight line.

[0028] (Protective layer) The protective layer 18 is a layer that protects the members on the upper surface side of the substrate 10 from the outside air and the like. The protective layer 18 is arranged to cover the entire upper surface of the insulating layer 45 and is in contact with the upper surfaces of the semiconductor layer 65, the second wiring layer 42, and the insulating layer 45. The material of the protective layer 18 can be the same as that of the planarization layer 16.

[0029] The wiring structure 1 having the above configuration has TFTs arranged on the upper surface side of the substrate, and is composed of two layers, the first wiring layer 41 and the second wiring layer 42, which are responsible for wiring to the TFTs and form the electrodes of the TFTs. Conventionally, in the three-dimensional wiring that connects the second wiring layer to the back surface wiring, it has been difficult to form a through hole that is continuous from the lower surface of the substrate to the second wiring layer in the insulating layer, and conduction failure has easily occurred. Further, when the diameter of the through hole is increased to ensure conduction, there has been a problem that the area of the circuit increases. The wiring structure 1 can form the through holes separately on the insulating layer 45 side and the substrate 10 side by providing the relay electrode 35 in the first wiring layer 41, and can suppress conduction failure of the three-dimensional wiring 32 without increasing the area of the circuit. When forming a through hole passing through the insulating layer 45 from the lower surface side of the substrate 10 by, for example, dry etching, the diameter tends to become smaller as it is farther from the lower surface of the substrate 10. The wiring structure 1 can secure the diameter of the upper three-dimensional wiring 32A by providing the relay electrode 35 and suppress an increase in the electrical resistance of the three-dimensional wiring 32. Further, by connecting the relay electrode 35 only to the three-dimensional wiring 32, the influence on the electrical characteristics can be suppressed.

[0030] The wiring structure 1 is arranged at a position where the three-dimensional wirings on the insulating layer side and the substrate side of the relay electrode 35 overlap in plan view. Thereby, the relay electrode 35 can be provided without significantly changing the arrangement of the circuit pattern. The wiring structure 1 can provide the relay electrode 35 with the same material as the first wiring layer 41 as a part of the pattern of the first wiring layer 41. Thereby, an increase in the number of steps in the manufacturing process can be suppressed. Further, since the relay electrode 35 is formed of a laminated film of a metal containing molybdenum, improvement in conductivity and process resistance can be achieved.

[0031] Note that the three-dimensional wirings 31 and 32 may be arranged at positions overlapping the TFT 60 in plan view. The element circuit 2B illustrated in FIG. 4A is different from the element circuit 2A in that the three-dimensional wirings 31 and 32 are arranged so as to overlap the TFT 60 in plan view, and the other points are common. In the element circuit 2B, the relay electrode 35 is arranged at a position close to the source electrode 62 and the drain electrode 63 in a plan view. Then, as illustrated in FIG. 4B, the three-dimensional wiring 31 that connects the first wiring layer 41 to the back surface wiring 47 is connected to the lower surface of the gate electrode 61. The element circuit 2B can be arranged so that the three-dimensional wiring overlaps the TFT60 in a plan view, thereby improving the integration degree.

[0032] In the element circuits 2A and 2B and the element circuit 3 to be described later, the source and drain of the TFT may be interchanged with each other. Also, although the three three-dimensional wirings 31 and 32 are arranged on a single straight line, the three-dimensional wirings 31 and 32 do not have to be on a straight line, and the mutual positional relationship between the three-dimensional wirings 31 and 32 is not particularly limited. The three-dimensional wirings 31 and 32 do not have to be provided in sets of three, and the number of the three-dimensional wirings 31 and 32 is not particularly limited. For example, one three-dimensional wiring 32 may be provided alone.

[0033] The planarization layer 16 of the substrate 10 can be omitted according to the application or the like. When the planarization layer 16 is not provided, the lower surface of the substrate 10 becomes the lower surface of the base material 12, and the back surface wiring 47 is arranged on the lower surface of the base material 12. Also, in the three-dimensional wiring 32 that connects the second wiring layer 42 to the back surface wiring 47, the three-dimensional wirings on the insulating layer 45 side and the substrate 10 side of the relay electrode 35 do not have to be arranged at overlapping positions in a plan view. The upper three-dimensional wiring 32A may be arranged inside the outer edge of the relay electrode 35 on the upper surface of the relay electrode 35, and the lower three-dimensional wiring 32B may be arranged inside the outer edge of the relay electrode 35 on the lower surface of the relay electrode 35.

[0034] [Manufacturing Method of Wiring Structure] Next, the manufacturing method S1 of the wiring structure 1 will be described with reference to FIGS. 5 to 6L. As illustrated in FIG. 5, the manufacturing method of the wiring structure 1 includes a base material forming step S10, a first wiring layer forming step S21, an insulating layer forming step S22, a semiconductor layer forming step S23, an upper through hole forming step S24, a second wiring layer forming step S25, a protective layer forming step S26, a first glass substrate removing step S30, a planarization layer forming step S41, a lower through hole forming step S42, a back surface wiring forming step S43, and a second glass substrate removing step S50. Hereinafter, each step of the manufacturing method S1 will be described.

[0035] (Base material forming step) The base material forming step S10 is a step of forming the base material 12 and the underlayer 14. Here, as illustrated in FIG. 6A, the base material 12 and the underlayer 14 are formed on the first glass substrate 91. The base material 12 can be formed by applying a material having fluidity on a flat support member such as a glass plate and curing it. Here, the base material 12 is a film substrate with a thickness of 8 μm, and a polyimide (PI) material having fluidity is applied on the first glass substrate 91 and cured to form it. Then, a silicon nitride film is formed as the underlayer 14 on the cured PI by sputtering to a thickness of 50 nm.

[0036] (First wiring layer forming step) The first wiring layer forming step S21 is a step of forming the first wiring layer 41. As illustrated in FIG. 6B, a metal laminated film composed of molybdenum and aluminum is formed on the upper surface of the underlayer 14, which is the upper surface 10A of the substrate 10, by sputtering to a thickness of 200 nm. Then, by photolithography, it is processed into the gate electrode 61 of the TFT, the relay electrode 35 of the three-dimensional wiring 32, and the patterns of the other first wiring layer 41. The relay electrode 35 is formed to be larger than the openings on the relay electrode 35 side of the upper through hole 22 and the lower through hole 24. For example, when the upper through hole 22 is cylindrical, the relay electrode 35 can be formed in a rectangular shape with the length of the short side being 1.5 to 3 times the diameter of the upper through hole 22. Note that the shape of the relay electrode 35 is not particularly limited.

[0037] (Insulating layer forming step) The insulating layer formation step S22 is a step of forming the insulating layer 45. As illustrated in FIG. 6C, the insulating layer 45 is formed on the upper surface of the first wiring layer 41 by sputtering so as to cover the entire upper surface of the underlying layer 14. Here, the insulating layer 45 is a silicon oxide film with a thickness of 200 nm.

[0038] (Semiconductor layer formation step) The semiconductor layer formation step S23 is a step of forming the semiconductor layer 65 of the TFT. As illustrated in FIG. 6D, a layer of In-Sn-Ga-O (ITZO) with a thickness of 30 nm is formed on the upper surface of the insulating layer 45 by sputtering. Then, patterning is performed by photolithography so that the semiconductor layer 65 is disposed at the position where the TFT is formed. Here, each semiconductor layer 65 is patterned into a rectangular shape. Thereafter, heat treatment is performed in the atmosphere at 300 °C for 1 hour using a hot plate.

[0039] (Upper through-hole formation step) The upper through-hole formation step S24 is a step of forming an upper through-hole 22 that penetrates the insulating layer 45 in its thickness direction. The upper through-hole 22 is formed at the position where the three-dimensional wiring 32 is provided. As illustrated in FIG. 6E, the upper through-hole 22 is formed in such a size and position that the opening on the side of the relay electrode 35 is included in the upper surface of the relay electrode 35. Thereby, a bottomed hole having the upper surface of the relay electrode 35 as the bottom surface is formed by the upper through-hole 22 and the upper surface of the relay electrode 35. The shape of the upper through-hole 22 is not particularly limited, but for example, it can be formed in a cylindrical shape with a diameter of 5 μm to 10 μm. The upper through-hole 22 can be formed from the upper surface side of the insulating layer 45, for example, by dry etching.

[0040] (Second wiring layer formation step) The second wiring layer formation step S25 is a step of forming the second wiring layer 42 and the upper three-dimensional wiring 32A. First, a metal laminated film composed of, for example, molybdenum, nickel, and gold is formed on the upper surface of the insulating layer 45 to a thickness of 200 nm by sputtering. As illustrated in FIG. 6F, the upper three-dimensional wiring 32A is formed in the upper through hole 22 by this sputtering. Then, by photolithography, it is processed into the source electrode 62 and drain electrode 63 of the TFT, and the patterns of other second wiring layers 42. By the second wiring layer forming step S25, the second wiring layer 42 is formed and is electrically connected to the relay electrode 35.

[0041] (Protective layer forming step) The protective layer forming step S26 is a step of forming the protective layer 18. As illustrated in FIG. 6G, the protective layer 18 covers the second wiring layer 42 and the semiconductor layer 65 and is formed over the entire upper surface of the insulating layer 45. Here, a material of an insulating organic film that can be formed by coating is applied to the upper surfaces of the second wiring layer 42, the semiconductor layer 65, and the insulating layer 45 and is cured to form it. Then, heat treatment is performed at 150° C. for 1 hour in the atmosphere.

[0042] (First glass substrate removing step) The first glass substrate removing step S30 is a step of attaching the second glass substrate 92 and removing the first glass substrate 91. First, as illustrated in FIG. 6H, an adhesive layer 93 is provided on the upper surface of the protective layer 18, and the second glass substrate 92 serving as a support member is attached. The adhesive layer 93 has, for example, a heat-peelable adhesive layer on the protective layer 18 side. Then, the first glass substrate 91 is peeled off by laser lift-off.

[0043] (Planarization layer forming step) The planarization layer forming step S41 is a step of forming the planarization layer 16. As illustrated in FIG. 6I, the planarization layer 16 is formed on the lower surface of the base material 12 from which the first glass substrate 91 has been removed. Here, a material of an insulating organic film that can be formed by coating is used. Then, heat treatment is performed at 150° C. for 1 hour in the atmosphere. The substrate 10 is formed by the planarization layer forming step S41. When the planarization layer 16 is not provided, the substrate 10 is composed of the base material 12 and the underlayer 14, and the planarization layer forming step S41 can be omitted.

[0044] (Lower through hole forming step) The lower through-hole forming step S42 is a step of forming a lower through-hole 24 that penetrates the substrate 10 in its thickness direction. As illustrated in FIG. 6J, the lower through-hole 24 is formed at a position where the three-dimensional wirings 31 and 32 are provided. Here, a gate electrode 61 is formed at the position where the three-dimensional wiring 31 is provided, and the lower through-hole 24 is formed to have a size and position such that the opening on the gate electrode 61 side is included in the lower surface of the gate electrode 61. A relay electrode 35 is formed at the position where the three-dimensional wiring 32 is provided, and the lower through-hole 24 is formed to have a size and position such that the opening on the relay electrode 35 side is included in the lower surface of the relay electrode 35. As a result, a bottomed hole having the lower surface of the first wiring layer 41 as the bottom surface is formed by the lower through-hole 24 and the lower surface of the first wiring layer 41, and a bottomed hole having the lower surface of the relay electrode 35 as the bottom surface is formed by the lower through-hole 24 and the lower surface of the relay electrode 35.

[0045] The shape of the lower through-hole 24 is not particularly limited, but for example, it can be formed such that the opening on the lower surface 10B side of the substrate 10 has a circular shape with a diameter of 5 μm to 20 μm. The lower through-hole 24 can be formed from the lower surface 10B side of the substrate 10, for example, by dry etching.

[0046] (Back surface wiring forming step) The back surface wiring forming step S43 is a step of forming the back surface wiring 47, the three-dimensional wiring 31, and the lower three-dimensional wiring 32B. First, a metal laminated film composed of molybdenum and aluminum is formed on the lower surface 10B of the substrate 10 to a thickness of 300 nm by sputtering. As illustrated in FIG. 6K, the three-dimensional wiring 31 and the lower three-dimensional wiring 32B are formed in the lower through-hole 24 by this sputtering. Then, it is processed into the pattern of the back surface wiring 47 by photolithography. By the back surface wiring forming step S43, the back surface wiring 47 is formed and electrically connected to the first wiring layer 41 and the relay electrode 35.

[0047] (Second glass substrate removing step) The second glass substrate removing step S50 is a step of removing the second glass substrate 92 and the adhesive layer 93, as illustrated in FIG. 6L. Here, the second glass substrate 92 and the adhesive layer 93 are removed by heating the heat-peelable adhesive layer of the adhesive layer 93.

[0048] In the manufacturing method S1 including the above steps, a relay electrode 35 is provided on the first wiring layer 41 in the first wiring layer forming step S21. Then, a through hole from the insulating layer 45 side to the relay electrode 35 can be formed in the upper through hole forming step S24, and a through hole from the substrate 10 side to the relay electrode 35 can be formed in the lower through hole forming step S42. In this way, by separately forming the through holes with the insulating layer 45 and the substrate 10, it is possible to suppress the conduction failure of the three-dimensional wiring that easily occurs when forming the through hole of the insulating layer from the lower surface side of the substrate.

[0049] (Modification example) Next, the case where the TFT is a top gate type will be described with reference to FIGS. 7A to 7C. The element circuit 3 illustrated in FIG. 7A is different from the element circuit 2A in that the TFT is a top gate type thin film transistor 60T, and the others are common to the element circuit 2A. The TFT 60T illustrated in FIG. 7B is a top gate type, a source electrode 62T and a drain electrode 63T are provided on the first wiring layer 41, and a gate electrode 61T is provided on the second wiring layer 42 through the insulating layer 45 serving as a gate insulating film 64T. The semiconductor layer 65T is disposed on the upper surface of the substrate 10, that is, the upper surface of the underlying layer 14. Also, similar to the TFT 60 of the element circuit 2A, it is a top contact type in which the source electrode 62T and the drain electrode 63T are located on the upper surface of the semiconductor layer 65T.

[0050] As illustrated in FIG. 7C, in the element circuit 3, the three-dimensional wiring 31 connects the first wiring layer 41 where the source electrode 62T and the drain electrode 63T are provided to the back surface wiring 47. The three-dimensional wiring 32 connects the second wiring layer 42 where the gate electrode 61T is provided to the back surface wiring 47. And, similar to the element circuit 2A, in the three-dimensional wiring 32 that connects the second wiring layer 42 to the back surface wiring 47, the three-dimensional wiring on the insulating layer 45 side and the three-dimensional wiring on the substrate 10 side are relayed by a relay electrode 35 provided in the first wiring layer 41. Even when the TFT arranged on the upper surface side of the substrate is of the top gate type, the wiring structure 1 can be provided in the same manner as in the case of the bottom gate type. In the case of the top gate type TFT, since the semiconductor layer 65T is below the gate electrode 61T, the three-dimensional wiring 32 cannot be connected to the lower surface of the gate electrode 61T.

[0051] [Wiring structure of pixel] Next, the wiring structure of the pixel having the wiring structure 1 will be described with reference to FIGS. 2 and 8 to 10. As illustrated in FIG. 2, the pixels 50 are arranged in the matrix direction of the panel unit 100. Note that in the panel unit 100, some of the pixels 50 have the wiring structure 1. The pixel 50 having the wiring structure 1 may be described as the pixel 50A. In the panel unit 100, a scanning line SL, a data line DL, a power supply line PL, and a ground line GL are arranged so as to pass through each pixel. The scanning line SL is a wiring to which a signal for selecting a row of the pixel 50 is transmitted. The data line DL is a wiring to which a signal for setting the gradation of the pixel 50 is transmitted. The power supply line PL and the ground line GL are wirings for supplying power to the pixel 50. The panel unit 100 can control the gradation for each pixel by selecting the row of the pixel 50 with the scanning line SL and setting the voltage with the data line DL.

[0052] The panel unit 100 is a display device capable of displaying a color image. Here, the pixel 50 is composed of three sub-pixels that emit red, green, and blue (RGB) respectively, and three data lines DL are arranged for one pixel 50. Thereby, the gradations of the three sub-pixels can be controlled individually. The circuit of sub-pixel 52 is illustrated in FIG. 8. Sub-pixel 52 has two TFTs, namely a switching Sw-TFT that switches by row selection and a driving Dr-TFT that sets the current value of the light-emitting element. And it has a holding capacitor C that holds the gate voltage of the Dr-TFT. S Sub-pixel 52 has one light-emitting element. Here, the light-emitting element is a light-emitting diode (LED).

[0053] In sub-pixel 52, the circuit illustrated in FIG. 8 is arranged on the upper surface side of the substrate. Sub-pixel 52 can take out the electrodes of each element and the wiring connected to each element to the lower surface side and connect them to the back surface wiring by providing the wiring structure 1. Note that sub-pixel 52 having the wiring structure 1 may be described as sub-pixel 52A. Depending on the position of the pixel in the panel unit's array, it may not be necessary to take out the wiring on the upper surface side of the substrate to the lower surface side, and three-dimensional wiring may not be required. Therefore, pixels without the wiring structure 1 can be arranged at positions where three-dimensional wiring is not required. Pixels without the wiring structure 1 are different from pixel 50A having the wiring structure 1 in that no three-dimensional wiring connecting each of the first wiring layer and the second wiring layer to the back surface wiring is provided, but are common with pixel 50A having the wiring structure 1 in other aspects including the arrangement of elements and scanning lines. Note that pixels without the wiring structure 1 are composed of sub-pixels without the wiring structure 1, and pixel 50A having the wiring structure 1 is composed of sub-pixel 52A having the wiring structure 1.

[0054] The wiring structure of the pixel according to the embodiment is a wiring structure of a pixel having the wiring structure 1, in which each of the scanning line SL, data line DL, power line PL, and ground line GL in pixel 50 is provided in the first wiring layer 41 or the second wiring layer 42. And at least one of the scanning line SL, data line DL, power line PL, and ground line GL is connected to the back surface wiring 47 by a three-dimensional wiring 32 relayed by a relay electrode 35. Hereinafter, each configuration of the pixel's wiring structure will be described. As illustrated in FIG. 9A, the pixel 50A is composed of three sub-pixels 52A arranged in the row direction in which the scanning line SL extends. The sub-pixel 52A is provided with one relay electrode 35 and has a wiring structure 1. For the pixel 50A, sub-pixels 52A that emit red on the left side, green in the middle, and blue on the right side in FIG. 9A, for example, can be arranged.

[0055] Note that both the Sw-TFT and the Dr-TFT are of the bottom gate type, with a gate electrode provided in the first wiring layer 41 and source and drain electrodes provided in the second wiring layer 42. Also, both the Sw-TFT and the Dr-TFT are of the top contact type. In the first wiring layer 41 or the second wiring layer 42, each of the scanning line SL, data line DL, power line PL, and ground line GL in the pixel 50 is provided. Here, the scanning line SL, power line PL, and ground line GL are provided in the first wiring layer 41, and the data line DL is provided in the second wiring layer 42. These scanning line SL, data line DL, power line PL, and ground line GL are arranged so as to pass through each sub-pixel.

[0056] The scanning line SL, data line DL, power line PL, and ground line GL can be drawn out to the lower surface of the substrate 10 by three-dimensional wiring and connected to the back surface wiring 47. At this time, at least one of the scanning line SL, data line DL, power line PL, and ground line GL is connected to the back surface wiring 47 by three-dimensional wiring 32 relayed by the relay electrode 35. Here, the data line DL is connected to the back surface wiring 47 by three-dimensional wiring 32 relayed by the relay electrode 35. The sub-pixel 52A has one relay electrode 35. Note that the scanning line SL, power line PL, and ground line GL provided in the first wiring layer 41 can be connected to the back surface wiring 47 without being relayed by the relay electrode 35. As illustrated in FIG. 9B, the three-dimensional wiring 32 that connects the second wiring layer 42 to the back surface wiring 47 is relayed by a relay electrode 35 provided in the first wiring layer 41, with an upper three-dimensional wiring 32A on the insulating layer 45 side and a lower three-dimensional wiring 32B on the substrate 10 side.

[0057] The sub-pixels 52 and 52A have connection electrodes 70 to which LEDs are connected on the upper surface side serving as the display surface. A protective layer 18 is not provided in the region on the upper surface of the connection electrode 70 where the LEDs are arranged, and the surface of the connection electrode 70 is exposed to the outside. The connection electrode 70 is provided in the second wiring layer 42. By forming the second wiring layer 42 as a metal laminated film laminated in the order of molybdenum, nickel, and gold from the insulating layer 45 side, the connection electrode 70 can have a surface suitable for connecting the LED. Note that the description of the protective layer 18 is omitted in FIG. 9A. The protective layer 18 is provided so as to cover the entire surfaces of the pixels 50 and 50A except for a part of the upper surface of the connection electrode 70.

[0058] On the lower surface of the substrate 10, as a back surface wiring 47, signal wirings and the like for connecting the scanning lines SL and the like drawn to the lower surface to the outside can be provided. As illustrated in FIG. 10, the back surface wiring 47 connected to the scanning line SL, the power line PL, and the ground line GL, which are wirings in the row direction, is provided so as to spread in the column direction. Conversely, the back surface wiring 47 connected to the data line DL, which is a wiring in the column direction, is provided so as to spread in the row direction. Note that FIG. 10 illustrates the region where the back surface wiring 47 is arranged.

[0059] By providing the wiring structure 1, the wiring structure of the pixel having the above-described configuration can suppress a conduction failure of the three-dimensional wiring that connects the second wiring layer to the back surface wiring. In addition, signals and the like for operating the pixel are input from the outside of the display device such as the panel unit. With the wiring structure 1, signal wirings and the like for connecting the TFT, the scanning line, and the like to the outside of the panel unit can be arranged on the lower surface side of the substrate. As a result, signal wirings and the like are not required around the region where the pixels are arranged, and the bezel-less design of the panel unit can be achieved. In the panel unit having the wiring structure of the pixel, for example, the width of the bezel can be set to 10 μm or less. Note that the TFT in the wiring structure of the pixel can also be a top gate type.

[0060] The manufacturing method of the wiring structure of the pixel can be performed in the same manner as the manufacturing method S1 of the wiring structure 1. However, in the base material forming step S10, the base material 12 is formed to a size for arranging pixels in a matrix direction. One substrate 10 serves as a common base for the pixels arranged in the matrix direction. Also, in the first wiring layer forming step S21, the pattern formation of the first wiring layer 41 is performed to form the gate electrodes of the Sw-TFT and Dr-TFT, one electrode of the holding capacitor C S , the scanning line SL, the ground line GL, the power supply line PL, and the relay electrode 35. In the second wiring layer forming step S25, the pattern formation of the second wiring layer 42 is performed to form the source electrodes and drain electrodes of the Sw-TFT and Dr-TFT respectively, and the other electrode of the holding capacitor C S , the data line DL, and the connection electrode 70 to which the LED is connected. Then, in the protective layer forming step S26, after forming the protective layer 18, for example, by dry etching, a part of the protective layer 18 can be removed to expose a part of the upper surface of the connection electrode 70.

[0061] Pixels 50 and 50A having the above-described pixel wiring structure were arranged so that the resolution was 133 ppi and manufactured by the above-described manufacturing method. As a result of the evaluation, it was confirmed that the three-dimensional wiring connecting the data line to the back surface wiring could be relayed by the relay electrode provided in the first wiring layer and that it could operate well without conduction failure.

[0062] In the wiring structure 1, if the relay electrode 35 is provided such that the upper three-dimensional wiring 32A is connected to the upper surface of the relay electrode 35 and the lower three-dimensional wiring 32B is connected to the lower surface of the relay electrode 35, even if the upper three-dimensional wiring 32A and the lower three-dimensional wiring 32B are arranged spaced apart in a plan view, the effects of the present invention can be achieved.

Explanation of Reference Numerals

[0063] 1 Wiring structure 2A Element circuit (bottom gate type) 3 Element circuit (top gate type) 10 Substrate 12 Base material 14 Underlayer 16 Planarization layer 18 Protective layer 22 Upper through-hole 24 Lower through-hole 31 Three-dimensional wiring (first wiring layer) 32 Three-dimensional wiring (second wiring layer) 32A Upper three-dimensional wiring 32B Lower three-dimensional wiring 35 Relay electrode 41 First wiring layer 42 Second wiring layer 45 Insulating layer 47 Backside wiring 50 Pixel 52 Sub-pixel 60 Thin film transistor (TFT) 61 Gate electrode 62 Source electrode 63 Drain electrode 64 Gate insulating film 65 Semiconductor layer 70 Connection electrode 100 Panel unit 120 Bezel

Claims

1. A wiring structure that connects a thin film transistor disposed on an upper surface side of a substrate from a lower surface side, a first wiring layer disposed on an upper surface of the substrate; an insulating layer disposed on an upper surface of the first wiring layer and serving as a gate insulating film of the thin film transistor; a second wiring layer disposed on an upper surface of the insulating layer; a back surface wiring disposed on a lower surface of the substrate; a three-dimensional wiring arranged in a thickness direction of the insulating layer and the substrate, the three-dimensional wiring connecting each of the first wiring layer and the second wiring layer to the back surface wiring, a gate electrode of the thin film transistor is provided on one of the first wiring layer and the second wiring layer, and a source electrode and a drain electrode of the thin film transistor are provided on the other of the first wiring layer and the second wiring layer; A wiring structure in which, in a three-dimensional wiring that connects the second wiring layer to the back surface wiring, the three-dimensional wiring on the insulating layer side and the three-dimensional wiring on the substrate side are relayed by a relay electrode provided on the first wiring layer.

2. The wiring structure according to claim 1 , wherein the relay electrode is connected only to the three-dimensional wiring.

3. The wiring structure according to claim 2 , wherein the three-dimensional wiring on the insulating layer side and the substrate side of the relay electrode are arranged in overlapping positions in a plan view.

4. The wiring structure according to claim 1 , wherein the material of the relay electrode is the same as the material of the first wiring layer.

5. 2. The wiring structure according to claim 1, wherein the relay electrode is formed of a laminated film of a metal containing molybdenum.

6. A pixel wiring structure comprising the wiring structure according to any one of claims 1 to 5, a scanning line, a data line, a power supply line, and a ground line for the pixel are provided in the first wiring layer or the second wiring layer, At least one of the scanning line, the data line, the power supply line, and the ground line is connected to the rear surface wiring by the three-dimensional wiring relayed by the relay electrode.

Images