Light-emitting device, photoelectric conversion device, and electronic apparatus

Abstract

To reduce the load capacity of a signal line.SOLUTION: A light-emitting device has a first pixel circuit and a second pixel circuit, a signal line for supplying pixel signals to the first pixel circuit and the second pixel circuit, and a first transistor connected with the signal line. Each of the first pixel circuit and the second pixel circuit includes a light-emitting element, a second transistor arranged on a route through which current for causing the light-emitting element to emit light flows, and a third transistor connected with a control terminal of the second transistor. The third transistors of the first pixel circuit and the second pixel circuit are connected with the signal line via the first transistor.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a light-emitting device, a photoelectric conversion device, and an electronic device.

Background Art

[0002] Development of an active matrix display device in which a driving transistor for controlling a current flowing through a light-emitting element is arranged in a pixel circuit has been carried out. In the display device described in Patent Document 1, each of a plurality of pixel circuits constituting a pixel column is connected to one signal line.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] As the number of transistors connected to a signal line increases, the load capacitance of the signal line also increases. When the load capacitance of the signal line is large, the settling time of the potential of the signal line becomes long, and it becomes difficult to write a signal into the pixel circuit accurately and at high speed. Some aspects of the present invention aim to reduce the load capacitance of the signal line.

Means for Solving the Problems

[0005] According to one embodiment, there is provided a light-emitting device including a first pixel circuit and a second pixel circuit, a signal line for supplying a pixel signal to the first pixel circuit and the second pixel circuit, and a first transistor connected to the signal line. Each of the first pixel circuit and the second pixel circuit includes a light-emitting element, a second transistor disposed on a path through which a current for causing the light-emitting element to emit light flows, and a third transistor connected to a control terminal of the second transistor. The third transistor of each of the first pixel circuit and the second pixel circuit is connected to the signal line via the first transistor.

Effect of the Invention

[0006] According to the above embodiment, the load capacitance of the signal line can be reduced.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

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Figure 8

Figure 9

Figure 10

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Figure 12

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Figure 15

Embodiments for Carrying Out the Invention

[0008] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0009] <First Embodiment> With reference to FIG. 1, a configuration example of a light-emitting device 100 according to the first embodiment will be described. As will be described later, the light-emitting device 100 may be used in a display device. For example, the light-emitting device 100 may be used in a flat panel type (which may also be called a flat panel type) display device.

[0010] The light-emitting device 100 may include a plurality of pixel circuits 101, a vertical scanning circuit 103, a signal output circuit 104, and a control circuit 105. The plurality of pixel circuits 101 are arranged in a two-dimensional array (i.e., so as to form a plurality of pixel rows and a plurality of pixel columns) in the pixel array unit 102. A pixel row may be a row formed by a plurality of pixels arranged in the row direction (horizontal direction) in FIG. 1. A pixel column may be a column formed by a plurality of pixels arranged in the column direction (vertical direction) in FIG. 1. The plurality of pixel circuits 101 may be arranged in a one-dimensional array. In the example of FIG. 1, the plurality of pixel circuits 101 are arranged in 2m rows and n columns (m and n are integers of 1 or more). For one pixel column, the pixel circuit 101 arranged at the i-th position from the side closer to the signal output circuit 104 is represented as pixel circuit 101_i (i is an integer of 1 or more and 2m or less). The pixel circuit 101 may simply be called a pixel. In FIG. 1, for the sake of simplicity of explanation, the case where the number of pixel rows included in the pixel array unit 102 is even will be described. Instead of this, the number of pixel rows included in the pixel array unit 102 may be odd.

[0011] The plurality of pixel circuits 101 included in each pixel column constitute pixel blocks 108 in groups of a plurality. In FIG. 1, an example in which each pixel block 108 is constituted by two adjacent pixel circuits 101 arranged in the column direction (i.e., the direction in which the signal line 107 extends) will be described. For one pixel column, the pixel block 108 arranged at the i-th position from the side closer to the signal output circuit 104 is represented as pixel block 108_i (i is an integer of 1 or more and m or less). Each pixel block 108 may be constituted by three or more pixel circuits 101. The plurality of pixel circuits 101 included in the same pixel block 108 may be continuous or may not be continuous. For example, a pixel block 108 may be constituted by the pixel circuit 101 in the first row and the pixel circuit 101 in the third row, and the pixel circuit 101 in the second row may not be included in this pixel block 108. Furthermore, one pixel block 108 may include a plurality of pixel circuits 101 included in different pixel columns.

[0012] The number of pixel circuits 101 included in the pixel block 108 may be the same or different through the pixel array section 102. For example, the number of pixel circuits 101 included in the pixel block 108 may be different for each region of the pixel array section 102. Also, the pixel array section 102 may include pixel circuits 101 that do not constitute the pixel block 108. For example, the pixel block 108 may be arranged only in a part of the region of the pixel array section 102.

[0013] In the pixel array section 102, m scanning lines 106_1 to 106_m extending in the row direction are arranged respectively. In the following description, the plurality of scanning lines 106_1 to 106_m are collectively referred to as the scanning line 106. The description of the scanning line 106 may apply to any one of the one or more scanning lines 106_1 to 106_m. The scanning line 106 may represent any one of the one or more scanning lines 106_1 to 106_m or a specific one determined by the context. The same applies to other components collectively referred to below. One scanning line 106 may be divided into a plurality of scanning lines as will be described later. Each scanning line 106 connects each of the plurality of pixel blocks 108 included in the corresponding row and the vertical scanning circuit 103. The vertical scanning circuit 103 supplies a scanning signal to each pixel block 108 through the scanning line 106, thereby switching each of the plurality of transistors included in each pixel block 108 between on (i.e., conductive state) and off (i.e., non-conductive state). The operation of the vertical scanning circuit 103 is controlled by the control circuit 105.

[0014] In the pixel array section 102, n signal lines 107_1 to 107_n each extending in the column direction are arranged. In the following description, the plurality of signal lines 107_1 to 107_n are collectively referred to as the signal line 107. Each signal line 107 connects each of the plurality of pixel blocks 108 included in the corresponding column to the signal output circuit 104. The signal output circuit 104 supplies a pixel signal to each pixel circuit 101 included in each pixel block 108 through the signal line 107. The pixel signal can take a signal potential Vsig corresponding to the luminance information. The pixel signal may be called an image signal when an image is displayed by the light emitting device 100, or may be called a video signal when a video is displayed by the light emitting device 100. The operation of the signal output circuit 104 is controlled by the control circuit 105.

[0015] Referring to FIG. 2, a configuration example of the pixel block 108 will be described. The pixel block 108 is composed of two pixel circuits 101a and 101b adjacent to each other in the column direction and a block transistor 210. The pixel circuit 101a and the pixel circuit 101b may have the same configuration or different configurations. Both of the two pixel circuits 101a and 101b may correspond to the pixel circuit 101 in FIG. 1. For example, the pixel circuit 101a may correspond to the pixel circuit 101 included in the odd-numbered pixel rows, or the pixel circuit 101b may correspond to the pixel circuit 101 included in the even-numbered pixel rows. The following description of the pixel circuit 101 applies to both of the two pixel circuits 101a and 101b.

[0016] The scanning line 106 arranged for the pixel block 108 is divided into two writing scanning lines 209a and 209b and one block scanning line 211. The writing scanning line 209a is arranged for each odd-numbered pixel row. The writing scanning line 209b is arranged for each even-numbered pixel row. The block scanning line 211 is arranged for each row of the pixel block 108. The vertical scanning circuit 103 may also be divided corresponding to the two writing scanning lines 209a and 209b and one block scanning line 211.

[0017] The pixel circuit 101 may include a light-emitting element 201, a driving transistor 202, a writing transistor 203, and a capacitive element 204. The light-emitting element 201 may be a current-driven electro-optical element whose emission luminance changes according to the amount of current flowing through the light-emitting element 201. The light-emitting element 201 may be, for example, a light-emitting diode (LED) or an organic electroluminescence (EL) element. The light-emitting element 201 may have an anode and a cathode. The cathode of the light-emitting element 201 is connected to the power supply line 206. The power supply line 206 is commonly arranged for a plurality of pixel circuits 101. A power supply potential VSS is supplied to the power supply line 206. In the example of FIG. 2, all the transistors included in the pixel circuit 101 are P-type transistors. Instead of this, some or all of the transistors included in the pixel circuit 101 may be N-type transistors.

[0018] The driving transistor 202 is a transistor for adjusting the amount of current flowing through the light-emitting element 201. The current flowing through the light-emitting element 201 may also be called a driving current. Since the light-emitting element 201 emits light when a driving current flows through it, the driving current is a current for causing the light-emitting element 201 to emit light. The driving transistor 202 is arranged on the path through which the driving current flows (in the example of FIG. 2, on the path from the power supply line 205 through the driving transistor 202 and the light-emitting element 201 to the power supply line 206). In the example of FIG. 2, one of the two main terminals of the driving transistor 202 (for example, the drain) is connected to the anode of the light-emitting element 201. The other of the two main terminals of the driving transistor 202 (for example, the source) is connected to the power supply line 205. The power supply line 205 is commonly arranged for a plurality of pixel circuits 101. A power supply potential VDD is supplied to the power supply line 205. The power supply potential VDD supplied to the power supply line 205 may be higher than the potential VSS supplied to the power supply line 206.

[0019] The write transistor 203 is a transistor for switching whether to write the pixel signal supplied from the signal output circuit 104 to the pixel circuit 101 through the signal line 107 to the gate of the drive transistor 202. The gate of the drive transistor 202 functions as a control terminal of the drive transistor 202. The same applies to the gates of other transistors in this specification. The write transistor 203 is arranged on the path connecting the signal line 107 and the gate of the drive transistor 202. The gate of the write transistor 203 of the pixel circuit 101a is connected to the write scan line 209a. The gate of the write transistor 203 of the pixel circuit 101b is connected to the write scan line 209b. One of the two main terminals of the write transistor 203 (for example, the source) is connected to the signal line 107 via the block transistor 210. The other of the two main terminals of the write transistor 203 (for example, the drain) is connected to the gate of the drive transistor 202.

[0020] The capacitor element 204 is a capacitor element for holding the gate-source voltage of the drive transistor 202. The capacitor element 204 connects the gate of the drive transistor 202 and the source of the drive transistor 202.

[0021] As described above, in the circuit configuration of FIG. 2, the gate of the drive transistor 202, one of the main terminals of the write transistor 203 (for example, the drain), and one of the electrodes of the capacitor element 204 are connected to the same node 207. One of the main terminals of the drive transistor 202 (for example, the source), one of the electrodes of the capacitor element 204, and the power supply line 205 are connected to the same node 208.

[0022] One of the two main terminals of the block transistor 210 (e.g., source) is connected to the signal line 107. The other of the two main terminals of the block transistor 210 (e.g., drain) is connected to one main electrode (e.g., source) of the writing transistor 203 in the pixel circuit 101a. Further, the other of the two main terminals of the block transistor 210 (e.g., drain) is also connected to one main electrode (e.g., source) of the writing transistor 203 in the pixel circuit 101b. The gate of the block transistor 210 is connected to the block scanning line 211.

[0023] When the block transistor 210 is on and the writing transistor 203 in the pixel circuit 101a is on, the pixel signal supplied through the signal line 107 is written into the capacitive element 204 in the pixel circuit 101a. On the other hand, even when the block transistor 210 is on, if the writing transistor 203 in the pixel circuit 101a is off, the pixel signal supplied through the signal line 107 is not written into the capacitive element 204 in the pixel circuit 101a. The same applies to the writing of the pixel signal into the capacitive element 204 in the pixel circuit 101b.

[0024] There is parasitic capacitance with respect to the back gate or the like at the main terminal (e.g., source) of the transistor connected to the signal line 107. In the light-emitting device 100 described in FIGS. 1 and 2, the number of transistors (specifically, its source) connected to one signal line 107 is half the number of pixel rows (e.g., 2m), that is, m (the number of block transistors 210). As a result, the load capacitance of the signal line 107 is reduced as compared with the case where the writing transistor 203 (specifically, its source) of each pixel circuit 101 is directly connected to the signal line 107. Therefore, the settling time of the potential of the signal line 107 is shortened, and the signal can be accurately and quickly written into the pixel circuit 101.

[0025] The capacitance of the block transistor 210 may be smaller than the capacitance of each write transistor 203 of the pixel circuit 101a and the pixel circuit 101b. Thereby, the load capacitance of the signal line 107 can be further reduced. The thickness of the gate insulating film of the block transistor 210 may be larger than the thickness of the gate insulating film of each write transistor 203 of the pixel circuit 101a and the pixel circuit 101b. The area of the substrate surface occupied by the block transistor 210 may be smaller than the area of the substrate surface occupied by each write transistor 203 of the pixel circuit 101a and the pixel circuit 101b. The area of the substrate surface occupied by the transistor may be the total area in a plan view with respect to the substrate surface of two impurity regions that function as the source and the gate of the transistor, respectively, and the region where the channel is formed.

[0026] Referring to FIG. 3, an operation example of the light-emitting device 100 will be described. This operation can be executed by the control circuit 105 controlling the vertical scanning circuit 103 to change the potential of the scanning line 106 and controlling the signal output circuit 104 to change the potential of the signal line 107. The timing diagram of FIG. 3 shows the potential changes of the signal line 107, the plurality of writing scanning lines 209_1 to 209_4, and the plurality of block scanning lines 211_1 to 211_2. The writing scanning line 209_i (i is an integer of 1 or more) is arranged for the i-th pixel row from the side closer to the signal output circuit 104. The block scanning line 211_i (i is an integer of 1 or more) is arranged for the row of the i-th pixel block 108_i from the side closer to the signal output circuit 104. The block transistors 210 included in the pixel block 108_i are connected to the writing transistors 203 of the pixel circuit 101_2i - 1 included in the (2i - 1)-th pixel row and the writing transistors 203 of the pixel circuit 101_2i included in the 2i-th pixel row. For example, the block transistors 210 included in the pixel block 108_1 are connected to the writing transistors 203 of the pixel circuit 101_1 included in the first pixel row and the writing transistors 203 of the pixel circuit 101_2 included in the second pixel row. In the following description, the operation of a specific one pixel column included in the pixel array unit 102 will be described. The same operation is performed for the other pixel columns included in the pixel array unit 102.

[0027] Since all the transistors included in the pixel block 108 shown in FIG. 2 are P-type transistors, these transistors turn on when a low-level signal is supplied to the gate and turn off when a high-level signal is supplied to the gate. Some or all of the transistors included in the pixel block 108 shown in FIG. 2 may be N-type transistors.

[0028] In the example of FIG. 3, one frame period ends at time t1, and the next frame period starts from time t1. The frame period may be a period during which the control circuit 105 controls the light emission states of the light emitting elements 201 of all the pixel circuits 101 included in the pixel array unit 102 so as to represent one frame. One frame period includes a plurality of horizontal periods. The horizontal period may be a period during which the control circuit 105 controls the light emission states of the light emitting elements 201 of all the pixel circuits 101 included in one pixel row so as to represent one row of one frame. The time from the start of the frame period (for example, t1) until the potential is switched may be a preset value.

[0029] Immediately before time t1, high-level signals are supplied to both the plurality of write scan lines 209 and the plurality of block scan lines 211. Therefore, both the write transistors 203 included in each pixel circuit 101 and the block transistors 210 included in each pixel block 108 are off.

[0030] At time t1, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_1. The signal potential Vsig_1 has a value corresponding to the luminance of the light to be emitted by the light emitting element 201 of the pixel circuit 101_1. The potential of the signal line 107 settles to the signal potential Vsig_1 according to the time constant corresponding to the load of the signal line 107.

[0031] At time t2, the vertical scan circuit 103 switches the potential of the write scan line 209_1 and the potential of the block scan line 211_1 from high level to low level, respectively. As a result, the write transistor 203 of the pixel circuit 101_1 and the block transistor 210 included in the pixel block 108_1 are turned on. Thereby, the signal potential Vsig_1 is written into the capacitive element 204 of the pixel circuit 101_1, and the light emitting element 201 of this pixel circuit 101_1 emits light with a luminance corresponding to the signal potential Vsig_1. Since the write transistor 203 of the pixel circuit 101_2 is off, the signal potential Vsig_1 is not written into the capacitive element 204 of the pixel circuit 101_2.

[0032] At time t3, the vertical scanning circuit 103 switches the potential of each of the write scanning line 209_1 and the block scanning line 211_1 from a low level to a high level. As a result, the write transistor 203 of the pixel circuit 101_1 and the block transistor 210 included in the pixel block 108_1 are turned off. Even after this, the capacitive element 204 of the pixel circuit 101_1 continues to hold the signal potential Vsig_1.

[0033] At time t4, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_2. The signal potential Vsig_2 has a value corresponding to the luminance of the light to be emitted by the light emitting element 201 of the pixel circuit 101_2. The potential of the signal line 107 settles to the signal potential Vsig_2 according to a time constant corresponding to the load of the signal line 107.

[0034] At time t5, the vertical scanning circuit 103 switches the potential of each of the write scanning line 209_2 and the block scanning line 211_1 from a high level to a low level. As a result, the write transistor 203 of the pixel circuit 101_2 and the block transistor 210 included in the pixel block 108_1 are turned on. Thereby, the signal potential Vsig_2 is written into the capacitive element 204 of the pixel circuit 101_2, and the light emitting element 201 of the pixel circuit 101_2 emits light with a luminance corresponding to the signal potential Vsig_2. Since the write transistor 203 of the pixel circuit 101_1 is off, the signal potential Vsig_2 is not written into the capacitive element 204 of the pixel circuit 101_1.

[0035] At time t6, the vertical scanning circuit 103 switches the potential of each of the write scanning line 209_2 and the block scanning line 211_1 from a low level to a high level. As a result, the write transistor 203 of the pixel circuit 101_2 and the block transistor 210 included in the pixel block 108_1 are turned off. Even after this, the capacitive element 204 of the pixel circuit 101_2 continues to hold the signal potential Vsig_2.

[0036] By the control circuit 105 performing the same operation on the block scanning line 211_2 from time t7 to time t10 as from time t1 to time t4, the signal potential Vsig_3 is written into the capacitive element 204 of the pixel circuit 101_3. By the control circuit 105 performing the same operation on the block scanning line 211_2 from time t11 to time t13 as from time t4 to time t7, the signal potential Vsig_4 is written into the capacitive element 204 of the pixel circuit 101_4. Similarly, from the fifth pixel row to the last pixel row, the signal potential is written into the capacitive element 204 of the pixel circuit 101. When the processing is completed up to the last pixel row, one frame period ends.

[0037] In the operation of FIG. 3, the pixel rows included in the pixel array unit 102 are scanned one by one. Instead of this, the pixel rows included in the pixel array unit 102 may be scanned in plural rows at a time. Further, like interlace driving, different combinations of pixel rows may be scanned for each frame.

[0038] In the operation of FIG. 3, the write transistor 203 and the block transistor 210 are switched on simultaneously and switched off simultaneously. The operation by the vertical scanning circuit 103 is not limited to this. For example, the vertical scanning circuit 103 can write a pixel signal to the gate of the driving transistor 202 of the pixel circuit 101a by overlapping the period during which the block transistor 210 is on and the period during which the write transistor 203 of the pixel circuit 101a is on. As described above, the vertical scanning circuit 103 maintains the write transistor 203 of the pixel circuit 101b in the off state while both the block transistor 210 and the write transistor 203 of the pixel circuit 101a are on. Thereby, it is possible to suppress the pixel signal written into the pixel circuit 101a from being written into the pixel circuit 101b. The writing of the pixel signal to the gate of the driving transistor 202 of the pixel circuit 101b may be the same as the writing of the pixel signal to the gate of the driving transistor 202 of the pixel circuit 101a described above.

[0039] The vertical scanning circuit 103 may switch off the writing transistor 203 of the pixel circuit 101a after switching off the writing transistor 203 of the pixel circuit 101a from the state where both the block transistor 210 and the writing transistor 203 of the pixel circuit 101a are on, and then switch off the block transistor 210. In other words, the vertical scanning circuit 103 may switch off the writing transistor 203 of the pixel circuit 101a while maintaining the block transistor 210 on from the state where both the block transistor 210 and the writing transistor 203 of the pixel circuit 101a are on. Thereby, it is possible to suppress the deterioration of the signal accuracy due to the influence of the feed-through when turning off the writing transistor 203 and the feed-through when turning off the block transistor 210. The timing for switching off the writing transistor 203 of the pixel circuit 101b may be the same as the timing for switching off the writing transistor 203 of the pixel circuit 101a described above.

[0040] Referring to FIG. 4, another operation example of the light-emitting device 100 will be described. The operation of FIG. 4 may be the same as the operation of FIG. 3 in other respects, except that the switching timing of the signals supplied to the plurality of block scanning lines 211_1 to 211_2 is different from the operation of FIG. 3.

[0041] The vertical scanning circuit 103 switches the potential of the block scanning line 211_1 from a high level to a low level at time t1 and from a high level to a low level at time t7. Thereby, the block transistor 210 included in the pixel block 108_1 is turned on from time t1 to time t7. Therefore, at time t2, when the vertical scanning circuit 103 switches the potential of the writing scanning line 209_1 from a high level to a low level, the signal potential Vsig_1 is written into the capacitive element 204 of the pixel circuit 101_1. Thereafter, at time t5, when the vertical scanning circuit 103 switches the potential of the writing scanning line 209_2 from a high level to a low level, the signal potential Vsig_2 is written into the capacitive element 204 of the pixel circuit 101_2.

[0042] By the control circuit 105 performing the same operation on the block scanning line 211_2 from time t7 to t10 as that from time t1 to t4, the signal potential Vsig_3 is written into the capacitive element 204 of the pixel circuit 101_3. By the control circuit 105 performing the same operation on the block scanning line 211_2 from time t11 to t13 as that from time t4 to t7, the signal potential Vsig_4 is written into the capacitive element 204 of the pixel circuit 101_4. Similarly, from the fifth pixel row to the last pixel row, the signal potential is written into the capacitive element 204 of the pixel circuit 101. When the processing is completed up to the last pixel row, one frame period ends.

[0043] <Second Embodiment> Referring to FIG. 5, a configuration example of the light-emitting device 100 according to the second embodiment will be described. The light-emitting device 100 of the second embodiment is different from the light-emitting device 100 of the first embodiment in that the pixel circuit 101 further includes a light-emission control transistor 501 and a capacitive element 502, and the scanning line 106 further includes a light-emission scanning line 503a and a light-emission scanning line 503b. Other points may be the same.

[0044] The light-emission control transistor 501 is a transistor for switching whether or not to cause the light-emitting element 201 to emit light. In the example of FIG. 5, the light-emission control transistor 501 is a P-type transistor. Alternatively, the light-emission control transistor 501 may be an N-type transistor. The light-emission control transistor 501 is arranged on the path through which the drive current flows. In the example of FIG. 5, the light-emission control transistor 501 is arranged on the path connecting the source of the drive transistor 202 and the power supply line 205. Specifically, one of the two main terminals of the light-emission control transistor 501 (for example, the drain) is connected to the source of the drive transistor 202. The other of the two main terminals of the light-emission control transistor 501 (for example, the source) is connected to the power supply line 205. The gate of the light-emission control transistor 501 of the pixel circuit 101a is connected to the light-emission scanning line 503a. The gate of the light-emission control transistor 501 of the pixel circuit 101b is connected to the light-emission scanning line 503b.

[0045] The capacitance element 502 connects the source of the light emission control transistor 501 and the drain of the light emission control transistor 501. The light emission scanning line 503a is arranged for each odd-numbered pixel row. The light emission scanning line 503b is arranged for each even-numbered pixel row.

[0046] Referring to FIG. 6, an operation example of the light emitting device 100 according to the second embodiment will be described. This operation can be executed by the control circuit 105 controlling the vertical scanning circuit 103 to change the potential of the scanning line 106 and controlling the signal output circuit 104 to change the potential of the signal line 107. The timing diagram of FIG. 6 further shows changes in the potentials of a plurality of light emission scanning lines 503_1 to 503_4 in addition to the timing diagram of FIG. 3. The light emission scanning line 503_i (i is an integer of 1 or more) is arranged for the i-th pixel row from the side closer to the signal output circuit 104. In the following description, the operation of a specific one pixel column included in the pixel array unit 102 will be described. The same operation is performed for other pixel columns included in the pixel array unit 102.

[0047] Immediately before time t1, high-level signals are supplied to both the plurality of writing scanning lines 209 and the plurality of block scanning lines 211. Therefore, both the writing transistors 203 included in each pixel circuit 101 and the block transistors 210 included in each pixel block 108 are off. Immediately before time t1, low-level signals are supplied to all of the plurality of light emission scanning lines 503. Therefore, all the light emission control transistors 501 included in each pixel circuit 101 are on.

[0048] At time t1, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the reference potential Vref. The reference potential Vref may be a value that does not depend on the luminance signal. The potential of the signal line 107 settles to the signal potential Vref according to a time constant corresponding to the load of the signal line 107. Also, at time t1, the vertical scanning circuit 103 switches the potential of the light emission scanning line 503_1 from low level to high level. As a result, the light emission control transistor 501 of the pixel circuit 101_1 turns off.

[0049] At time t2, the vertical scanning circuit 103 switches the potential of the write scanning line 209_1 and the potential of the block scanning line 211_1 from high level to low level respectively. As a result, the write transistor 203 of the pixel circuit 101_1 and the block transistor 210 included in the pixel block 108_1 are turned on. Thereby, the potential of the gate of the driving transistor 202 of the pixel circuit 101_1 becomes the reference potential Vref. However, since the light emission control transistor 501 of the pixel circuit 101_1 is off, no driving current flows.

[0050] Between time t3 and time t4, the vertical scanning circuit 103 temporarily turns on the light emission control transistor 501 of the pixel circuit 101_1. Thereby, since the source of the driving transistor 202 of the pixel circuit 101_1 is connected to the power supply line 205, a driving current flows. When the light emission control transistor 501 turns off, the potential of the source of the driving transistor 202 decreases with the passage of time. This decrease ends when the gate-source voltage of the driving transistor 202 reaches about the threshold voltage of the driving transistor 202. Thereby, the threshold voltage of the driving transistor 202 is held in the capacitive element 204.

[0051] By the control circuit 105 performing the same operation as from time t1 to time t4 in FIG. 3 from time t4 to time t7, the signal potential Vsig_1 is written into the capacitive element 204 of the pixel circuit 101_1. From time t4 to time t7, the light emission control transistor 501 of the pixel circuit 101_1 is maintained off. Therefore, the light emitting element 201 of the pixel circuit 101_1 does not emit light.

[0052] At time t7, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the reference potential Vref. The potential of the signal line 107 stabilizes to the signal potential Vref according to the time constant corresponding to the load of the signal line 107. Also, at time t1, the vertical scanning circuit 103 switches the potential of the light emission scanning line 503_1 from a high level to a low level. As a result, the light emission control transistor 501 of the pixel circuit 101_1 turns on. Thereby, the light emitting element 201 of the pixel circuit 101_1 emits light with a luminance corresponding to the signal potential Vsig_1. Further, at time t7, the vertical scanning circuit 103 switches the potential of the light emission scanning line 503_2 from a low level to a high level. As a result, the light emission control transistor 501 of the pixel circuit 101_2 turns off.

[0053] At time t8, the vertical scanning circuit 103 switches the potential of the writing scanning line 209_2 and the potential of the block scanning line 211_1 from a high level to a low level, respectively. As a result, the writing transistor 203 of the pixel circuit 101_2 and the block transistor 210 included in the pixel block 108_1 turn on. Thereby, the potential of the gate of the driving transistor 202 of the pixel circuit 101_2 becomes the reference potential Vref. However, since the light emission control transistor 501 of the pixel circuit 101_2 is off, no driving current flows.

[0054] Between time t8 and time t9, the vertical scanning circuit 103 temporarily turns on the light emission control transistor 501 of the pixel circuit 101_2. Thereby, since the source of the driving transistor 202 of the pixel circuit 101_2 is connected to the power supply line 205, a driving current flows. When the light emission control transistor 501 turns off, the potential of the source of the driving transistor 202 decreases with the passage of time. This decrease ends when the gate-source voltage of the driving transistor 202 becomes about the threshold voltage of the driving transistor 202. Thereby, the threshold voltage of the driving transistor 202 is held in the capacitive element 204.

[0055] By the control circuit 105 performing the same operation from time t10 to time t13 as that from time t4 to time t7 in FIG. 3, the signal potential Vsig_2 is written into the capacitive element 204 of the pixel circuit 101_2. From time t10 to time t13, the emission control transistor 501 of the pixel circuit 101_2 is maintained in the off state. Therefore, the light-emitting element 201 of the pixel circuit 101_2 does not emit light.

[0056] By the control circuit 105 performing the same operation on the block scanning line 211_2 from time t13 to time t19 as that from time t1 to time t7, the signal potential Vsig_3 is written into the capacitive element 204 of the pixel circuit 101. By the control circuit 105 performing the same operation on the block scanning line 211_2 from time t19 to time t25 as that from time t10 to time t16, the signal potential Vsig_4 is written into the capacitive element 204 of the pixel circuit 101_4. Similarly, from the fifth pixel row to the last pixel row, the signal potential is written into the capacitive element 204 of the pixel circuit 101. When the processing is completed up to the last pixel row, one frame period is completed.

[0057] According to the operation of FIG. 6, the drive current flowing through the light-emitting element 201 of the pixel circuit 101_1 after time t7 becomes a value with reduced dependence on the threshold voltage of the drive transistor 202 while being based on the capacitance ratio between the capacitive element 204 and the capacitive element 502 and the signal potential Vsig_1. As a result, the variation in the luminance of the light-emitting element 201 due to the variation in the threshold voltage between the drive transistors 202 of the plurality of pixel circuits 101 is reduced. Therefore, the quality of the image displayed by the light-emitting device 100 is further improved.

[0058] Also in the second embodiment, similar to the first embodiment, the load capacitance of the signal line 107 is reduced. Also in the second embodiment, similar to the modified example described with reference to FIG. 4 in the first embodiment, the block transistor 210 in the pixel block 108 may be maintained in the on state during the period when the writing transistors 203 of the plurality of pixel circuits 101 in the pixel block 108 are being scanned.

[0059] <Embodiment 3> Referring to FIGS. 7 and 8, a configuration example of the light-emitting device 100 according to the third embodiment will be described. The light-emitting device 100 of the third embodiment is different from the light-emitting device 100 of the first embodiment in that the pixel array unit 102 is divided into a low-resolution region 701 and a high-resolution region 702, and the driving methods of these regions are different from each other. Other points may be the same. The differences between the first embodiment and the third embodiment may also be applied to the second embodiment.

[0060] Referring to FIG. 7, a configuration example of the light-emitting device 100 according to the third embodiment will be described. The hardware configuration of the light-emitting device 100 according to the third embodiment is the same as that of the light-emitting device 100 according to the first embodiment, but the operation of the vertical scanning circuit 103 is different. In the high-resolution region 702, the emission luminance is controlled for each pixel circuit 101, and in the low-resolution region 701, the emission luminance is controlled for each pixel block 108. Specifically, in order to display one image, in the high-resolution region 702, one pixel circuit 101 emits light according to one pixel signal, and in the low-resolution region 701, two pixel circuits 101 included in one pixel block 108 emit light according to one pixel signal. As a result, in the high-resolution region 702, an image is displayed with a higher resolution than in the low-resolution region 701.

[0061] In the example of FIG. 7, the low-resolution region 701 is divided into two parts so as to sandwich the high-resolution region 702. The layouts of the low-resolution region 701 and the high-resolution region 702 are not limited to the example of FIG. 7. The high-resolution region 702 may be divided into two or more parts, or the low-resolution region 701 may include only one part. Also, the number of pixel blocks 108 included in each of the low-resolution region 701 and the high-resolution region 702 is not limited to the example of FIG. 7. In the example of FIG. 7, the pixel array unit 102 is divided in the column direction, and the boundary between the low-resolution region 701 and the high-resolution region 702 extends in the row direction. Instead of or in addition to this, the pixel array unit 102 may be divided in the row direction, and the boundary between the low-resolution region 701 and the high-resolution region 702 may extend in the column direction. In this case, separate scanning lines 106 may be arranged for each of the low-resolution region 701 and the high-resolution region 702.

[0062] Referring to FIG. 8, an operation example of the light-emitting device 100 will be described. The timing diagram of FIG. 8 shows the potential changes of the signal line 107, the plurality of writing scanning lines 209_1 to 209_6, and the plurality of block scanning lines 211_1 to 211_3. The writing scanning lines 209_1 to 209_4 supply scanning signals to the pixel circuits 101 included in the low-resolution region 701. The writing scanning lines 209_5 to 209_6 supply scanning signals to the pixel circuits 101 included in the high-resolution region 702. The block scanning lines 211_1 to 211_2 supply scanning signals to the pixel blocks 108 included in the low-resolution region 701. The block scanning line 211_3 supplies a scanning signal to the pixel block 108 included in the high-resolution region 702. In the following description, the operation of a specific one pixel column included in the pixel array unit 102 will be described. The same operation is performed for the other pixel columns included in the pixel array unit 102.

[0063] Immediately before time t1, high-level signals are supplied to none of the plurality of writing scanning lines 209 and the plurality of block scanning lines 211. Therefore, the writing transistors 203 included in each pixel circuit 101 and the block transistors 210 included in each pixel block 108 are all off.

[0064] Since the first pixel row is included in the low-resolution region 701, from time 1, the vertical scanning circuit 103 performs an operation for scanning the low-resolution region 701. In the operation for scanning the low-resolution region 701, light emission is controlled for each pixel block 108. Hereinafter, the operation for scanning the low-resolution region 701 will be specifically described.

[0065] At time t1, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_1. The signal potential Vsig_1 has a value corresponding to the luminance of the light that the light-emitting elements 201 of the pixel circuit 101_1 and the light-emitting elements 201 of the pixel circuit 101_2 included in the second pixel row should emit. The potential of the signal line 107 settles to the signal potential Vsig_1 according to the time constant corresponding to the load of the signal line 107.

[0066] At time t2, the vertical scanning circuit 103 switches the potential of the write scanning line 209_1, the potential of the write scanning line 209_2, and the potential of the block scanning line 211_1 from high level to low level, respectively. As a result, the write transistor 203 of the pixel circuit 101_1, the write transistor 203 of the pixel circuit 101_2 included in the second pixel row, and the block transistor 210 included in the pixel block 108_1 are turned on. Thereby, the signal potential Vsig_1 is written into each of the capacitive elements 204 of the pixel circuit 101_1 and the capacitive elements 204 of the pixel circuit 101_2, and the light-emitting elements 201 of the pixel circuit 101_1 and the light-emitting elements 201 of the pixel circuit 101_2 emit light with a luminance corresponding to the signal potential Vsig_1.

[0067] At time t3, the vertical scanning circuit 103 switches the potentials of the write scanning line 209_1, the write scanning line 209_2, and the block scanning line 211_1 from low level to high level respectively. As a result, the write transistors 203 of the pixel circuit 101_1, the write transistors 203 of the pixel circuit 101_2, and the block transistors 210 included in the pixel block 108 are turned off. Even after this, the capacitive elements 204 of the pixel circuit 101_1 and the capacitive elements 204 of the pixel circuit 101_2 continue to hold the signal potential Vsig_1.

[0068] At time t4, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_2. The signal potential Vsig_2 has a value corresponding to the luminance of the light that the light emitting elements 201 of the pixel circuit 101_3 included in the third pixel row and the light emitting elements 201 of the pixel circuit 101_4 included in the fourth pixel row should emit. The potential of the signal line 107 settles to the signal potential Vsig_2 according to the time constant corresponding to the load of the signal line 107.

[0069] The operations at times t5 to t6 are the same as the operations at times t2 to t3. By the operations at times t5 to t6, the light emitting elements 201 of the pixel circuit 101_3 and the light emitting elements 201 of the pixel circuit 101_4 emit light with a luminance corresponding to the signal potential Vsig_2.

[0070] Since the third pixel row is included in the high - resolution region 702, from time t7, the vertical scanning circuit 103 performs operations for scanning the high - resolution region 702. By the operations for scanning the high - resolution region 702, similar to the first embodiment, the light emissions of the two pixel circuits 101 included in each pixel block 108 are controlled individually. Then, the vertical scanning circuit 103 executes the corresponding scanning method until the last pixel row according to whether the pixel block 108 is included in either the low - resolution region 701 or the high - resolution region 702. When the processing is completed up to the last pixel row, one frame period ends.

[0071] As described above, in the third embodiment, the vertical scanning circuit 103 writes the signal potential Vsig to the control terminals of the driving transistors 202 of the pixel circuits 101a and 101b, respectively, by overlapping the period during which the writing transistor 203 of the pixel circuit 101a is on, the period during which the writing transistor 203 of the pixel circuit 101b is on, and the period during which the block transistor 210 is on, for the pixel block 108 included in the low-resolution region 701. Also in the third embodiment, similar to the first embodiment, the load capacitance of the signal line 107 is reduced.

[0072] The control circuit 105 may dynamically change the layout of the low-resolution region 701 and the high-resolution region 702 in the pixel array unit 102 (hereinafter referred to as the resolution layout). The control circuit 105 may set the resolution layout according to a prior setting, may set the resolution layout according to an instruction from the user, or may set the resolution layout according to the nature of the displayed image. The control circuit 105 may change the resolution layout for each frame. For example, in a certain frame, the pixel blocks 108_1 to 108_j and the pixel blocks 108_k+1 to 108_m are included in the low-resolution region 701, and the pixel blocks 108_j+1 to 108_k are included in the high-resolution region 702. In another frame, the pixel blocks 108_1 to 108_j+2 and the pixel blocks 108_k+3 to 108_m are included in the low-resolution region 701, and the pixel blocks 108_j+3 to 108_k+2 are included in the high-resolution region 702.

[0073] The block transistor 210 may be omitted in a part of the plurality of pixel blocks 108, and the signal line 107 and the writing transistor 203 may be directly connected. For example, the block transistor 210 included in the low-resolution region 701 may be omitted, and the block transistor 210 may be included in the high-resolution region 702. Also, the block transistor 210 included in the high-resolution region 702 may be omitted, and the block transistor 210 may be included in the low-resolution region 701.

[0074] The period during which the block transistor 210 is on in the low-resolution region 701 is not limited to the example of FIG. 8. For example, the block transistor 210 of the pixel block 108_1 may be maintained on during a period overlapping with the period from time t2 to t3 (for example, the period from time t1 to t4). Also, in the low-resolution region 701, the writing transistor 203 may always be maintained on, and the pixel circuit 101 for writing the signal potential Vsig may be selected by switching the on / off state of the block transistor 210. The period during which the block transistor 210 is on in the high-resolution region 702 is not limited to the example of FIG. 8. For example, the block transistor 210 may be maintained on as in the modification of the first embodiment.

[0075] <Fourth Embodiment> Referring to FIGS. 9 and 10, a configuration example of the light-emitting device 100 according to the fourth embodiment will be described. The light-emitting device 100 of the fourth embodiment is different from the light-emitting device 100 of the third embodiment in that it includes a pixel block 900 of FIG. 9 instead of the pixel block 108 in the low-resolution region 701. Other points may be the same. The modifications described in the third embodiment are also applicable to the fourth embodiment.

[0076] Referring to FIG. 9, a configuration example of the pixel block 900 will be described. The pixel block 900 is composed of two pixel circuits 901a and 901b adjacent to each other in the column direction and a block transistor 210. The pixel circuit 901a and the pixel circuit 901b may have the same configuration or different configurations. The pixel circuits 901a and 901b are collectively referred to as the pixel circuit 901. The following description of the pixel circuit 901 applies to both of the two pixel circuits 901a and 901b.

[0077] The pixel circuit 901 is different from the pixel circuit 101 in that it does not include the writing transistor 203. Therefore, the control terminal of the driving transistor 202 is connected to the block transistor 210 without passing through other transistors. That is, the control terminal of the driving transistor 202 of the pixel circuit 901a, the control terminal of the driving transistor 202 of the pixel circuit 901b, and one main terminal (for example, the drain) of the block transistor 210 are connected to the same node. The light-emitting device 100 does not include the writing scan lines for the pixel circuits 901a and 901b.

[0078] Referring to FIG. 10, an operation example of the light-emitting device 100 will be described. The timing diagram of FIG. 10 shows the potential changes of the signal line 107, the plurality of writing scan lines 209_1 to 209_2, and the plurality of block scan lines 211_1 to 211_3. The writing scan lines 209_1 to 209_2 supply a scan signal to the pixel circuits 101 included in the high-resolution region 702. The block scan lines 211_1 to 211_2 supply a scan signal to the pixel blocks 108 included in the low-resolution region 701. The block scan line 211_3 supplies a scan signal to the pixel blocks 108 included in the high-resolution region 702. In the following description, the operation of a specific one pixel column included in the pixel array unit 102 will be described. The same operation is performed for the other pixel columns included in the pixel array unit 102.

[0079] Immediately before time t1, a high-level signal is supplied to none of the plurality of writing scan lines 209 and the plurality of block scan lines 211. Therefore, the writing transistor 203 included in each pixel circuit 101 and the block transistor 210 included in each pixel block 108 are all off.

[0080] Since the first pixel row is included in the low-resolution region 701, from time 1, the vertical scan circuit 103 performs an operation for scanning the low-resolution region 701. In the operation for scanning the low-resolution region 701, light emission is controlled for each pixel block 108. Hereinafter, the operation for scanning the low-resolution region 701 will be specifically described.

[0081] At time t1, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_1. The signal potential Vsig_1 has a value corresponding to the luminance of the light to be emitted by the light emitting elements 201 of the pixel circuit 101_1 and the light emitting elements 201 of the pixel circuits 101_2 included in the second pixel row. The potential of the signal line 107 settles to the signal potential Vsig_1 according to the time constant corresponding to the load of the signal line 107.

[0082] At time t2, the vertical scanning circuit 103 switches the potential of the block scanning line 211_1 from the high level to the low level. As a result, the block transistors 210 included in the pixel block 108_1 are turned on. Thereby, the signal potential Vsig_1 is written into each of the capacitive elements 204 of the pixel circuit 101_1 and the capacitive elements 204 of the pixel circuit 101_2, and the light emitting elements 201 of the pixel circuit 101_1 and the light emitting elements 201 of the pixel circuit 101_2 emit light with a luminance corresponding to the signal potential Vsig_1.

[0083] At time t3, the vertical scanning circuit 103 switches the potential of the block scanning line 211_1 from the low level to the high level. As a result, the block transistors 210 included in the pixel block 108_1 are turned off. Thereafter, the capacitive elements 204 of the pixel circuit 101_1 and the capacitive elements 204 of the pixel circuit 101_2 continue to hold the signal potential Vsig_1.

[0084] At time t4, the signal output circuit 104 switches the value of the pixel signal supplied to the signal line 107 to the signal potential Vsig_2. The signal potential Vsig_2 has a value corresponding to the luminance of the light to be emitted by the light emitting elements 201 of the pixel circuits 101_3 included in the third pixel row and the light emitting elements 201 of the pixel circuits 101_4 included in the fourth pixel row. The potential of the signal line 107 settles to the signal potential Vsig_2 according to the time constant corresponding to the load of the signal line 107.

[0085] The operations at times t5 to t6 are the same as the operations at times t2 to t3. By the operations at times t5 to t6, the light-emitting elements 201 of the pixel circuit 101_3 and the light-emitting elements 201 of the pixel circuit 101_4 emit light with a luminance corresponding to the signal potential Vsig_2.

[0086] Since the third pixel row is included in the high-resolution region 702, from time 7, the vertical scanning circuit 103 performs operations for scanning the high-resolution region 702. By the operations for scanning the high-resolution region 702, similar to the first embodiment, the light emission of the two pixel circuits 101 included in each pixel block 108 is individually controlled. Thereafter, the vertical scanning circuit 103 executes the corresponding scanning method until the last pixel row according to whether the pixel block 108 is included in either the low-resolution region 701 or the high-resolution region 702. When the processing is completed up to the last pixel row, one frame period ends.

[0087] As described above, in the fourth embodiment, for the pixel block 108 included in the low-resolution region 701, the vertical scanning circuit 103 writes the signal potential Vsig to each of the control terminals of the drive transistor 202 of the pixel circuit 101a and the drive transistor 202 of the pixel circuit 101b by turning on the block transistor 210. Also in the fourth embodiment, similar to the first embodiment, the load capacitance of the signal line 107 is reduced.

[0088] The control circuit 105 may dynamically change the resolution layout. Specifically, the control circuit 105 may set whether to include the portion having the pixel block 900 in the pixel array unit 102 in the low-resolution region 701 or the high-resolution region 702.

[0089] <Other Embodiments> FIG. 11 is a schematic diagram showing an example of a display device according to the present embodiment. The display device 1100 may include a touch panel 1103, a display panel 1105, a frame 1106, a circuit board 1107, and a battery 1108 between an upper cover 1101 and a lower cover 1109. The touch panel 1103 and the display panel 1105 are connected to flexible printed circuits FPC 1102 and 1104. A transistor is printed on the circuit board 1107. The battery 1108 may not be provided if the display device is not a portable device, or may be provided at another position even if it is a portable device.

[0090] The display device according to the present embodiment may include a color filter having red, green, and blue. The red, green, and blue may be arranged in a delta array in the color filter.

[0091] The display device according to the present embodiment may be used as a display unit of a portable terminal. In that case, it may have both a display function and an operation function. Examples of the portable terminal include mobile phones such as smartphones, tablets, and head-mounted displays.

[0092] The display device according to the present embodiment may be used as a display unit of an imaging device including an optical unit having a plurality of lenses and an imaging element that receives light that has passed through the optical unit. The imaging device may include a display unit that displays information acquired by the imaging element. Further, the display unit may be a display unit exposed to the outside of the imaging device or a display unit disposed in a viewfinder. The imaging device may be a digital camera or a digital video camera.

[0093] FIG. 12(a) is a schematic diagram showing an example of the imaging device according to the present embodiment. The imaging device 1200 may include a viewfinder 1201, a rear display 1202, an operation unit 1203, and a housing 1204. The viewfinder 1201 may include the display device according to the present embodiment. In that case, the display device may display not only the image to be captured but also environmental information, imaging instructions, and the like. The environmental information may include the intensity of external light, the direction of external light, the speed at which the subject moves, the possibility that the subject is blocked by an obstacle, and the like.

[0094] Since the timing suitable for imaging is only a short period of time, it is better to display information earlier. Therefore, it is preferable to use the display device using the organic light-emitting element of the present invention. This is because the organic light-emitting element has a high response speed. The display device using the organic light-emitting element can be more preferably used than these devices, such as a liquid crystal display device, for which a display speed is required.

[0095] The imaging device 1200 has an optical unit (not shown). The optical unit has a plurality of lenses and forms an image on an image sensor housed in the housing 1204. The plurality of lenses can adjust the focus by adjusting their relative positions. This operation can also be performed automatically. The imaging device may be called a photoelectric conversion device. The photoelectric conversion device may include, as imaging methods, a method of detecting the difference from a previous image instead of sequentially imaging, a method of cutting out from an image that is always recorded, and the like.

[0096] FIG. 12(b) is a schematic diagram showing an example of an electronic device according to the present embodiment. The electronic device 1250 includes a display unit 1251, an operation unit 1252, and a housing 1253. The housing 1253 may include a circuit, a printed circuit board having the circuit, a battery, and a communication unit. The operation unit 1252 may be a button or a reaction unit of a touch panel method. The operation unit may be a biometric recognition unit that recognizes a fingerprint and performs unlocking or the like. An electronic device having a communication unit can also be called a communication device. The electronic device may further have a camera function by including a lens and an imaging device. An image captured by the camera function is displayed on the display unit. Examples of the electronic device include a smartphone and a notebook personal computer.

[0097] FIG. 13 is a schematic diagram showing an example of a display device according to the present embodiment. FIG. 13(a) shows a display device such as a TV monitor or a PC monitor. The display device 1300 has a frame 1301 and a display unit 1302. The light-emitting device according to the present embodiment may be used for the display unit 1302.

[0098] It has a frame 1301 and a base 1303 that supports the display unit 1302. The base 1303 is not limited to the form of FIG. 13(a). The lower side of the frame 1301 may also serve as the base.

[0099] Further, the frame 1301 and the display unit 1302 may be bent. The radius of curvature may be 5000 mm or more and 6000 mm or less.

[0100] FIG. 13(b) is a schematic diagram showing another example of the display device according to the present embodiment. The display device 1350 in FIG. 13(b) is configured to be foldable and is a so-called foldable display device. The display device 1350 includes a first display unit 1351, a second display unit 1352, a housing 1353, and a bending point 1354. The first display unit 1351 and the second display unit 1352 may include a light-emitting device according to the present embodiment. The first display unit 1351 and the second display unit 1352 may be a single seamless display device. The first display unit 1351 and the second display unit 1352 can be separated at the bending point. The first display unit 1351 and the second display unit 1352 may display different images, or may display a single image together with the first and second display units.

[0101] FIG. 14(a) is a schematic diagram showing an example of the lighting device according to the present embodiment. The lighting device 1400 may include a housing 1401, a light source 1402, a circuit board 1403, an optical film 1404, and a light diffusing portion 1405. The light source may include an organic light-emitting element according to the present embodiment. The optical filter may be a filter that improves the color rendering property of the light source. The light diffusing portion can effectively diffuse the light of the light source, such as lighting up, and deliver the light to a wide range. The optical filter and the light diffusing portion may be provided on the light-emitting side of the lighting. If necessary, a cover may be provided on the outermost side.

[0102] The lighting device is, for example, a device for lighting an interior. The lighting device may emit any color from white, warm white, or other colors from blue to red. It may have a dimming circuit for dimming them. The lighting device may include the organic light-emitting element of the present invention and a power supply circuit connected thereto. The power supply circuit is a circuit that converts an AC voltage into a DC voltage. Also, white means a color temperature of 4200K and warm white means a color temperature of 5000K. The lighting device may have a color filter.

[0103] In addition, the lighting device according to the present embodiment may have a heat radiating portion. The heat radiating portion releases the heat inside the device to the outside of the device, and examples thereof include a metal having a high specific heat and liquid silicon.

[0104] Figure 14(b) is a schematic diagram of an automobile which is an example of the mobile body according to the present embodiment. The automobile has a tail lamp which is an example of a lighting device. The automobile 1450 may have a tail lamp 1451 and may be configured to turn on the tail lamp when a braking operation or the like is performed.

[0105] The tail lamp 1451 may have an organic light-emitting element according to the present embodiment. The tail lamp may have a protective member for protecting the organic EL element. The protective member has a certain degree of strength and may be made of any material as long as it is transparent, but is preferably made of polycarbonate or the like. A phthalic acid derivative, an acrylonitrile derivative or the like may be mixed with the polycarbonate.

[0106] The automobile 1450 may have a vehicle body 1453 and a window 1452 attached thereto. The window may be a transparent display as long as it is not a window for checking the front and rear of the automobile. The transparent display may have an organic light-emitting element according to the present embodiment. In this case, constituent materials such as electrodes of the organic light-emitting element are made of transparent members.

[0107] The mobile body according to the present embodiment has a drive unit such as an engine and a motor, and a moving unit such as wheels, a propeller, and tires. For example, the mobile body may be an automobile, a ship, an aircraft, a drone, a bicycle, a railway vehicle, or the like. The mobile body may have a body and a lighting device provided on the body. The lighting device may emit light to notify the position of the body. The lighting device has an organic light-emitting element according to the present embodiment.

[0108] With reference to Figure 15, application examples of the display device of each of the above embodiments will be described. The display device can be applied to a system that can be worn as a wearable device such as smart glasses, an HMD, or smart contacts. The imaging display device used in such an application example has an imaging device capable of photoelectrically converting visible light and a display device capable of emitting visible light.

[0109] FIG. 15(a) illustrates glasses 1500 (smart glasses) according to one application example. An imaging device 1502 such as a CMOS sensor or a SPAD is provided on the front surface side of the lens 1501 of the glasses 1500. Also, a display device of each of the above-described embodiments is provided on the back surface side of the lens 1501.

[0110] The glasses 1500 further include a control device 1503. The control device 1503 functions as a power supply that supplies power to the imaging device 1502 and the display device according to each embodiment. Also, the control device 1503 controls the operations of the imaging device 1502 and the display device. An optical system for condensing light onto the imaging device 1502 is formed in the lens 1501.

[0111] FIG. 15(b) illustrates glasses 1550 (smart glasses) according to one application example. The glasses 1550 have a control device 1552. An imaging device corresponding to the imaging device 1502 and a display device are mounted on the control device 1552. An optical system for projecting the light emitted from the display device in the control device 1552 is formed in the lens 1551, and an image is projected onto the lens 1551. The control device 1552 functions as a power supply that supplies power to the imaging device and the display device, and controls the operations of the imaging device and the display device. The control device may have a gaze detection unit that detects the wearer's gaze. Infrared light may be used for gaze detection. The infrared light emitting unit emits infrared light to the eyeball of the user who is gazing at the display image. An imaging unit having a light receiving element detects the reflected light of the emitted infrared light from the eyeball, and thus an imaging image of the eyeball is obtained. By having a reduction unit that reduces the light from the infrared light emitting unit to the display unit in a plan view, a reduction in image quality is reduced.

[0112] The user's gaze with respect to the display image is detected from the imaging image of the eyeball obtained by imaging infrared light. Any known method can be applied to gaze detection using the imaging image of the eyeball. As an example, a gaze detection method based on a Purkinje image by reflection of irradiation light on the cornea can be used.

[0113] More specifically, a gaze detection process based on the pupil corneal reflex method is performed. Using the pupil corneal reflex method, a gaze vector representing the orientation (rotation angle) of the eyeball is calculated based on the image of the pupil and the Purkinje image included in the captured image of the eyeball, thereby detecting the user's gaze.

[0114] The display device according to an embodiment of the present invention may include an imaging device having a light receiving element, and may control the display image of the display device based on the user's gaze information from the imaging device.

[0115] Specifically, the display device determines a first display area that the user is gazing at and a second display area other than the first display area based on the gaze information. The first display area and the second display area may be determined by the control device of the display device, or may be received from an external control device that has determined them. In the display area of the display device, the display resolution of the first display area may be controlled to be higher than that of the second display area. That is, the resolution of the second display area may be made lower than that of the first display area.

[0116] Also, the display area has a first display area and a second display area different from the first display area, and based on the gaze information, an area with a higher priority is determined from the first display area and the second display area. The first display area and the second display area may be determined by the control device of the display device, or may be received from an external control device that has determined them. The resolution of the area with a higher priority may be controlled to be higher than that of the area other than the area with a higher priority. That is, the resolution of the area with a relatively lower priority may be made lower.

[0117] Note that AI may be used to determine the first display area or the area with a higher priority. AI may be a model configured to estimate the angle of the gaze and the distance to the target at the tip of the gaze from the image of the eyeball, using the image of the eyeball and the direction in which the eyeball in the image is actually looking as teacher data. The AI program may be possessed by the display device, the imaging device, or an external device. When an external device has it, it is transmitted to the display device via communication.

[0118] When performing display control based on visual recognition, it can be preferably applied to smart glasses further having an imaging device that images the outside. The smart glasses can display the imaged external information in real time.

[0119] <Summary of Embodiment> [Item 1] A light-emitting device, a first pixel circuit and a second pixel circuit, signal lines for supplying pixel signals to the first pixel circuit and the second pixel circuit, a first transistor connected to the signal line, and each of the first pixel circuit and the second pixel circuit includes a light-emitting element, a second transistor disposed on a path through which a current for causing the light-emitting element to emit light flows, and a third transistor connected to a control terminal of the second transistor, wherein each of the third transistors of the first pixel circuit and the second pixel circuit is connected to the signal line via the first transistor. A light-emitting device. [Item 2] The light-emitting device according to Item 1, wherein the first pixel circuit and the second pixel circuit are arranged side by side in a direction in which the signal line extends. [Item 3] The light-emitting device according to Item 1 or 2, further comprising a scanning circuit that switches each of the first transistor, the first pixel circuit, and the second pixel circuit between on and off. [Item 4] The scanning circuit writes the pixel signal to the control terminal of the second transistor of the first pixel circuit by overlapping a period during which the first transistor is on and a period during which the third transistor of the first pixel circuit is on, By overlapping a period during which the first transistor is on and a period during which the third transistor of the second pixel circuit is on, writing the pixel signal to the control terminal of the second transistor of the second pixel circuit, the light-emitting device according to item 3. [Item 5] The scanning circuit While both the first transistor and the third transistor of the first pixel circuit are on, maintaining the third transistor of the second pixel circuit in an off state, While both the first transistor and the third transistor of the second pixel circuit are on, maintaining the third transistor of the first pixel circuit in an off state, the light-emitting device according to item 3 or 4. [Item 6] The scanning circuit From a state where both the first transistor and the third transistor of the first pixel circuit are on, while maintaining the first transistor on, switching the third transistor of the first pixel circuit to off, From a state where both the first transistor and the third transistor of the second pixel circuit are on, while maintaining the first transistor on, switching the third transistor of the second pixel circuit to off, the light-emitting device according to any one of items 3 to 5. [Item 7] The light-emitting device A third pixel circuit and a fourth pixel circuit to which a pixel signal is supplied from the signal line, A fourth transistor connected to the signal line, further comprising: Each of the third pixel circuit and the fourth pixel circuit A second light-emitting element, A fifth transistor disposed on a path through which a current for causing the second light-emitting element to emit light flows, A sixth transistor connected to a control terminal of the fifth transistor, including: Each of the sixth transistors of the third pixel circuit and the fourth pixel circuit is connected to the signal line via the fourth transistor. The scanning circuit writes the pixel signal to each of the control terminals of the fifth transistor of the third pixel circuit and the fifth transistor of the fourth pixel circuit by overlapping a period during which the fourth transistor is on, a period during which the sixth transistor of the third pixel circuit is on, and a period during which the sixth transistor of the fourth pixel circuit is on. The light-emitting device according to any one of items 3 to 6. [Item 8] The light-emitting device A fifth pixel circuit and a sixth pixel circuit to which a pixel signal is supplied from the signal line; And a seventh transistor connected to the signal line. Each of the fifth pixel circuit and the sixth pixel circuit A third light-emitting element; And an eighth transistor disposed on a path through which a current for causing the third light-emitting element to emit light flows. The control terminals of the eighth transistors of each of the fifth pixel circuit and the sixth pixel circuit are connected to the seventh transistor without passing through other transistors. The scanning circuit writes the pixel signal to each of the control terminals of the eighth transistor of the fifth pixel circuit and the eighth transistor of the sixth pixel circuit by turning on the seventh transistor. The light-emitting device according to any one of items 3 to 6. [Item 9] The capacitance of the first transistor is smaller than the capacitance of the third transistor of each of the first pixel circuit and the second pixel circuit. The light-emitting device according to any one of items 1 to 8. [Item 10] The thickness of the gate insulating film of the first transistor is greater than the thickness of the gate insulating films of the third transistors of the first pixel circuit and the second pixel circuit, respectively. The light-emitting device according to any one of Items 1 to 9. [Item 11] The area of the substrate surface occupied by the first transistor is smaller than the area of the substrate surface occupied by the third transistors of the first pixel circuit and the second pixel circuit, respectively. The light-emitting device according to any one of Items 1 to 10. [Item 12] An optical unit having a plurality of lenses, an imaging element that receives light that has passed through the optical unit, and a display unit that displays an image captured by the imaging element. The display unit has the light-emitting device according to any one of Items 1 to 11. The photoelectric conversion device. [Item 13] A display unit having the light-emitting device according to any one of Items 1 to 11, a housing in which the display unit is provided, and a communication unit provided in the housing and communicating with the outside. The electronic device.

[0120] The invention is not limited to the above embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Therefore, claims are attached to disclose the scope of the invention.

Description of Reference Numerals

[0121] 100 Light-emitting device, 101 Pixel circuit, 210 Block transistor

Claims

1. A light emitting device, comprising: A first pixel circuit and a second pixel circuit; a signal line for supplying a pixel signal to the first pixel circuit and the second pixel circuit; a first transistor connected to the signal line; Each of the first pixel circuit and the second pixel circuit includes A light-emitting element; a second transistor disposed on a path through which a current flows for causing the light emitting element to emit light; a third transistor connected to a control terminal of the second transistor; the third transistor of each of the first pixel circuit and the second pixel circuit is connected to the signal line via the first transistor.

2. The light emitting device according to claim 1 , wherein the first pixel circuit and the second pixel circuit are arranged side by side in a direction in which the signal lines extend.

3. The light emitting device according to claim 1 , further comprising a scanning circuit that switches the first transistor, each transistor of the first pixel circuit, and each transistor of the second pixel circuit between on and off.

4. The scanning circuit includes: writing the pixel signal to the control terminal of the second transistor of the first pixel circuit by overlapping a period during which the first transistor is on and a period during which the third transistor of the first pixel circuit is on; 4. The light emitting device according to claim 3, wherein the pixel signal is written to the control terminal of the second transistor of the second pixel circuit by overlapping a period in which the first transistor is on and a period in which the third transistor of the second pixel circuit is on.

5. The scanning circuit includes: maintaining the third transistor of the second pixel circuit off while both the first transistor and the third transistor of the first pixel circuit are on; 4. The light emitting device of claim 3, wherein the third transistor of the first pixel circuit is maintained off while both the first transistor and the third transistor of the second pixel circuit are on.

6. The scanning circuit includes: switching off the third transistor of the first pixel circuit from a state in which both the first transistor and the third transistor of the first pixel circuit are on, while maintaining the first transistor on; 4. The light emitting device according to claim 3, wherein, from a state in which both the first transistor and the third transistor of the second pixel circuit are on, the third transistor of the second pixel circuit is switched off while the first transistor is maintained on.

7. The light emitting device comprises: a third pixel circuit and a fourth pixel circuit to which pixel signals are supplied from the signal line; a fourth transistor connected to the signal line; Each of the third pixel circuit and the fourth pixel circuit A second light emitting element; a fifth transistor disposed on a path through which a current flows for causing the second light emitting element to emit light; a sixth transistor connected to a control terminal of the fifth transistor; the sixth transistor of each of the third pixel circuit and the fourth pixel circuit is connected to the signal line via the fourth transistor; 4. The light-emitting device according to claim 3, wherein the scanning circuit writes the pixel signal to each of the control terminal of the fifth transistor of the third pixel circuit and the control terminal of the fifth transistor of the fourth pixel circuit by overlapping a period in which the fourth transistor is on, a period in which the sixth transistor of the third pixel circuit is on, and a period in which the sixth transistor of the fourth pixel circuit is on.

8. The light emitting device comprises: a fifth pixel circuit and a sixth pixel circuit to which pixel signals are supplied from the signal line; a seventh transistor connected to the signal line; Each of the fifth pixel circuit and the sixth pixel circuit A third light-emitting element; and an eighth transistor disposed on a path through which a current flows for causing the third light emitting element to emit light; a control terminal of the eighth transistor in each of the fifth pixel circuit and the sixth pixel circuit is connected to the seventh transistor without passing through another transistor; 4. The light emitting device according to claim 3, wherein the scanning circuit writes the pixel signal to each of the control terminals of the eighth transistor of the fifth pixel circuit and the control terminal of the eighth transistor of the sixth pixel circuit by turning on the seventh transistor.

9. The light emitting device according to claim 1 , wherein a capacitance of the first transistor is smaller than a capacitance of the third transistor of each of the first pixel circuit and the second pixel circuit.

10. The light emitting device according to claim 1 , wherein a thickness of a gate insulating film of the first transistor is greater than a thickness of a gate insulating film of the third transistor of each of the first pixel circuit and the second pixel circuit.

11. The light emitting device according to claim 1 , wherein an area of ​​the substrate surface occupied by the first transistor is smaller than an area of ​​the substrate surface occupied by the third transistor of each of the first pixel circuit and the second pixel circuit.

12. an optical unit having a plurality of lenses, an image sensor that receives light that has passed through the optical unit, and a display unit that displays an image captured by the image sensor; A photoelectric conversion device, the display portion comprising the light-emitting device according to claim 1 .

13. 12. An electronic device comprising: a display portion having the light-emitting device according to claim 1; a housing in which the display portion is provided; and a communication portion provided in the housing and configured to communicate with an external device.

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