Circuit design support device

Abstract

To allow a designer to intuitively and visually check the influence on performance of a part of a circuit due to partially changing the design of the circuit, and the influence on environmental performance, thereby improving efficiency of circuit design support.SOLUTION: A circuit design support device includes a control unit including a calculation device, a memory, a storage, an input device, and a display device. The storage stores overall circuit information. The input device inputs circuit information to be changed in the overall circuit information to the control unit including the calculation device. The control unit including the calculation device calculates influence on performance of the circuit information to be changed and on performance of another circuit in the overall circuit information, and calculates influence on environmental performance due to the circuit information to be changed, and displays, on the display device, the calculated influence on the performance of the circuit information and influence on the performance of the another circuit in the overall circuit information, and the influence on the environmental performance due to the circuit information to be changed.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to a circuit design support device that supports a designer in designing a circuit. [Background technology]

[0002] In circuit design, there is known a circuit design support device that supports a designer in circuit design. As an example, Patent Document 1 discloses a circuit design support device and a circuit design support program that clearly indicates the function formed by a set of components that constitute a circuit, and makes it easier to understand a circuit diagram. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2012-99007 A Summary of the Invention [Problem to be solved by the invention]

[0004] The circuit design support device disclosed in Patent Document 1 is sufficiently effective in designing a specific circuit. However, in an electrical product in which the circuit is used, for example, even if one component is configured in a certain circuit, there may be a larger circuit realized by combining that component with other components. Furthermore, in some cases, a larger circuit may be configured by combining multiple large circuits. In an electrical product configured with such large-scale circuits, for example, even if a certain circuit is optimized, it may end up having a negative effect on the whole in relation to other circuits. Therefore, there has been a demand for the establishment and practical application of a method for circuit design support that not only focuses on individual circuits but also looks at the surroundings.

[0005] Furthermore, in recent years, there has been a growing demand to consider environmental performance when designing circuits. For example, even if a design results in improved circuit performance, a degradation of environmental performance, such as power consumption, may not be acceptable. Therefore, it is necessary to design circuits that take both performance and environmental performance into consideration.

[0006] The present invention has been made in light of the above circumstances, and aims to provide a circuit design support device that is capable of evaluating and presenting the impact of a change on other circuits when designing or modifying a circuit.Furthermore, the present invention provides a circuit design support device that is capable of presenting environmental performance along with the performance of the circuit, thereby enabling a circuit design that achieves a high balance between circuit performance and environmental friendliness. [Means for solving the problem]

[0007] One example of a means for solving the above problem is a circuit design support device having a CPU, memory, storage, input device, and display device, in which overall circuit information is stored in the storage, and circuit information to be changed from the overall circuit information is input to the CPU from the input means, and the CPU calculates the performance of the circuit information to be changed and the impact of the circuit information to be changed on the performance of other circuits in the overall circuit information, and calculates the impact of the circuit information to be changed on LCA performance (Life Cycle Assessment performance), and displays on the display means the calculated performance of the circuit information, the impact of the circuit information to be changed on the performance of other circuits in the overall circuit information, and the impact of the circuit information to be changed on environmental performance.

[0008] Further means and advantages of the present invention will become apparent throughout the entire specification below. Effect of the Invention

[0009] According to the circuit design support device of the present invention, a circuit designer can easily see the effect of a change in the circuit design on the performance of the circuit, the effect on the performance of other circuits, and the effect on the environmental performance on the display means. This makes it possible to proceed with the circuit design while checking the current state of the circuit, which makes it possible to efficiently design circuits that achieve both high performance and environmental friendliness.

[0010] Further means and advantages of the present invention will become apparent throughout the entire specification below. [Brief description of the drawings]

[0011] [Figure 1] 1 is a diagram illustrating an example of the configuration of a circuit design assistance device according to an embodiment of the present invention. [Diagram 2] 1 is a diagram illustrating an example of the configuration of a circuit design assistance device according to an embodiment of the present invention. [Diagram 3] FIG. 2 is a diagram showing an example of a processing concept of the circuit design assistance device of the present invention; [Figure 4] FIG. 2 is a diagram showing a graph topology in one embodiment of the present invention. [Figure 5A] FIG. 2 is a diagram showing an example of a target substrate in an embodiment of the present invention. [Figure 5B] FIG. 2 illustrates an example of a node in one embodiment of the present invention. [Figure 5C] FIG. 4 is a diagram illustrating an example of a data structure according to an embodiment of the present invention. [Figure 6A] FIG. 2 is a diagram illustrating an example of a target unit according to an embodiment of the present invention. [Figure 6B] FIG. 2 is a diagram illustrating an example of a target unit according to an embodiment of the present invention. [Figure 6C] FIG. 13 is a diagram showing an example of simultaneous display of nodes and a data structure in an embodiment of the present invention. [Figure 6D] FIG. 2 illustrates an example of a node in one embodiment of the present invention. [Figure 6E] FIG. 4 is a diagram illustrating an example of a data structure according to an embodiment of the present invention. [Figure 7A] FIG. 2 is a diagram illustrating an example of a target device in an embodiment of the present invention. [Figure 7B] FIG. 2 is a diagram illustrating an example of a target device in an embodiment of the present invention. [Figure 7C]FIG. 13 is a diagram showing an example of simultaneous display of nodes and a data structure in an embodiment of the present invention. [Figure 7D] FIG. 2 illustrates an example of a node in one embodiment of the present invention. [Figure 7E] FIG. 4 is a diagram illustrating an example of a data structure according to an embodiment of the present invention. [Figure 8A] FIG. 2 is a diagram showing an example of a display screen of the circuit design assistance device according to the embodiment of the present invention. [Figure 8B] FIG. 2 is a diagram showing an example of a display screen of the circuit design assistance device according to the embodiment of the present invention. [Figure 9] FIG. 2 is a flow chart according to an embodiment of the present invention. [Figure 10] FIG. 2 is a flow chart according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0012] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. EXAMPLES

[0013] 1 is a diagram showing an example of the configuration of a circuit design support device in this embodiment. Reference numeral 1 denotes the entire circuit design support device, and reference numeral 2 denotes a control unit, which may be, for example, the main body of a server, a PC, or a workstation. Reference numeral 8 denotes an input device, and reference numeral 9 denotes a display device. The control unit 2 has a CPU 3 that performs arithmetic processing, a storage 4, and a memory 5 that cooperates with these.

[0014] Based on circuit design change information 90 input from input device 8, the CPU calculates the circuit performance and environmental performance for the design change information. At this time, data is exchanged 91 in both directions between a calculation device, for example, CPU 3 and storage 4, and a database accumulated in storage 4 is referenced, or information is written to the database on storage 4. Similarly, data is exchanged 92 in both directions between CPU 3 and memory 5.

[0015] In this case, the environmental performance may be LCA performance. It may also be a part of the environmental performance such as power consumption. Alternatively, it is not excluded from the scope of the present application to perform the same processing as described in the present specification by focusing on evaluation items other than the environmental performance.

[0016] Fig. 2 shows an example in which a communication network 6 is interposed between the CPU 3 and storage 4 in Fig. 1. This is a diagram for explaining that, due to the recent development of cloud environments, it is possible to configure the control unit 2 or the circuit design support device 1 even in cases where the CPU and storage are located in spatially distant locations. Therefore, the circuit design support device 1 of the present application encompasses examples in which the hardware is distributed as shown in Fig. 2. For this reason, the term and concept of the circuit design support device 1 in the present application also includes the case of a circuit design support system.

[0017] FIG. 3 is a diagram for explaining the circuit design assistance device 1 of the present application, focusing particularly on the flow of data processing, arithmetic processing, or circuit design assistance.

[0018] 3, a user IF (interface) 7 having both the input device 8 and the display device 9 of FIG. 1 is provided.

[0019] Reference numeral 11 in the figure denotes a portion focusing on program processing performed by the CPU 3 in the control unit 2. Similarly, reference numeral 12 in FIG.

[0020] The processing programs executed by the CPU 3 include a circuit design program 51, a circuit model generation program 52, a performance / environment / influence range analysis program 53, a circuit analysis program 54, an LCA calculation program 55, and the like.

[0021] The DBs (databases) on the storage 4 include a netlist / component DB 56, an environment information DB 57, an analysis model DB 58, a circuit model DB 59, and the like.

[0022] First, a user or designer inputs design information 61 together with circuit design instructions via the user IF 7 into the circuit design program 51. At this time, the circuit design includes cases where a part of an existing circuit is changed. The circuit design program 51 is not limited to a unique program, and an existing circuit design tool may be used. Alternatively, this program may be executed in cooperation with an external PC, server, workstation, etc.

[0023] The circuit design program 51 generates a netlist and a parts list from a circuit diagram input by the user. The generated information is transmitted from the CPU 3 to the storage 4 at 71 and stored in the netlist / parts DB 56 on the storage 4.

[0024] Next, the operation of the circuit model generation program 52 will be described. The circuit model generation program 52 obtains at 72 a netlist and a parts list from the netlist / parts DB 56 for a specified or all circuits to be mounted on the target product. Similarly, it obtains at 73 environmental information from the environmental information DB 57. Similarly, it obtains at 74 an analysis model from the analysis model DB 58. Also, it receives the target product specification and input / output information from the user or designer via the user IF 7.

[0025] The circuit model generation program 52 generates a circuit model data structure based on this data or information. The generated circuit model data structure is stored in the circuit model DB 59 at 75.

[0026] The performance / environment / impact range analysis program 53 receives the target part and analysis items specified by the user IF 7, and receives design information or redesign information from the user or designer. Then, the netlist of the target circuit is generated from the circuit model stored in the circuit model DB 59.

[0027] Thereafter, the performance / environment / impact range analysis program 53 sends the netlist, analysis model, and information on the specified performance items as 81 to the circuit analysis program 54. It also sends the list of environmental information and the specification of LCA items as 84 to the LCA calculation program 55.

[0028] The circuit analysis program 54 outputs the analysis results of the specified circuit performance from the input netlist and analysis model to the performance / environment / impact range analysis program 53 at 82. It also passes information 83 about the power in the circuit in the analysis to the LCA calculation program 55.

[0029] The LCA calculation program 55 calculates designated LCA items from the input environmental information and the results of the power analysis of the circuit analysis program 54, and outputs the results as 85 to the performance / environment / impact range analysis program 53.

[0030] The performance / environment / impact range analysis program 53 generates a netlist of the target circuit from the circuit model based on the items specified by the user. It also extracts environmental information of the parts used in the target circuit, and outputs the results of the specified items, the impact range, and changed characteristic information based on the results of the circuit analysis program 54 and the LCA calculation program 55. It outputs the results to the user IF as 86 and presents them to the user or designer via the display device 9.

[0031] The netlist / component DB 56 stores netlists and component lists for some or all of the designed circuits. The environmental information DB 57 stores environmental information for the components and materials of the developed product. The analysis model DB 58 stores analysis models of the circuit components of the developed product. The circuit model DB 59 stores a circuit model data structure having circuit network information and environmental information for the entire generated product.

[0032] Such a circuit design support device 1 can reduce the burden on designers in circuit design and can speed up and improve the accuracy of design work. In particular, when used in consideration of LCA performance, it is possible to improve LCA for the entire product by implementing improved design while checking the performance analysis results and LCA calculation results, and it is possible to achieve both product performance and environmental load reduction at a higher level.

[0033] FIG. 4 is a diagram showing a graph topology structure, which is another central feature of the circuit design support device of the present invention.

[0034] Conventionally, there are two main graph topology structures used in circuit analysis: one is a graph topology structure for circuit network analysis, and the other is a graph topology structure for automatic layout.

[0035] The former is a graph topology structure that focuses on wiring, expressing each wiring as a node with a circle, connecting the circles with connection lines that are edges, and expressing each connection line by applying real components such as resistors, power supplies, capacitors, and coils. This is a graph topology structure that is mainly used for collections of two-terminal components, and is a graph topology structure intended for analyzing circuit networks using determinants. The latter is a graph topology structure intended for automatic layout, expressing and listing real components, that is, parts, as nodes with circles on the left side, and listing wiring as nodes with circles on the right side, connecting them with connection lines that are edges in accordance with the circuit, and assigning terminal information to the connection lines.

[0036] In contrast to these conventional graph topology structures, the present invention has a major feature in that it devisees and adopts a new graph topology structure, which makes it possible to efficiently perform circuit analysis and performance evaluation, especially in the case of analysis of a large-scale circuit that spans multiple layers, and contributes greatly to a significant reduction in the scale of calculations and an increase in speed, particularly in circuit design support devices.

[0037] The graph topology structure used in the present invention will be described with reference to Fig. 4. Nodes assigned to each component are provided as part nodes 31, as shown at 31 on the left side of Fig. 4. Then, nodes assigned to each wire are provided as wiring nodes 33, as shown at 33 on the right side of Fig. 4. The graph topology structure of the present invention is characterized in that nodes assigned in advance to each terminal are used as terminal nodes 32 between the part nodes 31 and the wiring nodes 33.

[0038] This makes it possible to smoothly link and pass on circuit information from lower layers to the intermediate layer and then to the upper layer in the circuit design of large-scale circuits. Therefore, in a circuit design support device, the representation and analysis of the entire circuit network of the device using the graph topology structure used in the present invention is itself considered to be novel and inventive.

[0039] Each node of the parts node 31, that is, each part, is associated with information on a Sim model (simulation model) and environmental information as part information 36.

[0040] Each node of the wiring nodes 33, that is, each wiring, is associated with information on the type of the wiring as wiring information 37. For example, input / output, input, output, and so on.

[0041] The relationship between part nodes 31 and terminal nodes 32, i.e., the relationship between each part and each terminal, is represented by a connecting line as a part-terminal edge 34. The relationship between terminal nodes 32 and wiring nodes 33, i.e., the relationship between each terminal and each wire, is represented by a connecting line as a terminal-wiring edge 35.

[0042] The concept or usage of Fig. 4 will be explained in more detail with reference to Figs. 5A to 5C. The diagrams explain the circuit diagram and graph topology structure of a part of the device, here referred to as substrate A, with Fig. 5A being the circuit diagram and Fig. 5C being a diagram expressing the circuit diagram of Fig. 5A in a graph topology structure. Fig. 5B is an explanatory diagram in which the connection lines between nodes are erased so that the locations of the terminal nodes can be confirmed in the graph topology structure of Fig. 5C.

[0043] First, Fig. 5A will be described. Fig. 5A is a circuit model for, for example, substrate A. Reference numeral 101 denotes an overall circuit diagram of substrate A, and is an example of a circuit including AMP1 as an amplifier 111, R1 as a resistor 112, R2 as a resistor 113, and AMP2 as an amplifier 114.

[0044] It should be noted that this circuit itself is merely for the purpose of explaining the invention, and no invention is claimed in relation to this circuit itself.

[0045] Figure 5B is a diagram showing the circuit of Figure 5A expressed in a graph topology structure similar to that of Figure 4. Note that the connection lines between the nodes are not shown in Figure 5B. This is for the purpose of explanation, and the connection lines will be described in Figure 5C.

[0046] First, a description will be given with reference to Fig. 5B. In the part node 122 on the left side of the figure, nodes corresponding to the parts AMP1, AMP2, R1, and R2 in Fig. 5A are set. 111 corresponds to AMP1, 114 to AMP2, 112 to R1, and 113 to R2.

[0047] Each part in the parts node is linked to the circuit model and environmental information of each part as 121.

[0048] Nodes corresponding to the wiring in Fig. 5A are set in the wiring node 124 on the right side of the figure. Each node in the wiring node 124 is associated with wiring information 125, such as input / output, input, output, and Non.

[0049] The wiring nodes 124 are basically set according to the actual input and output. In FIG. 5B, the top four nodes in the wiring nodes 124 are directly involved in input and output. Therefore, they refer to wiring and at the same time, they refer to input and output. On the other hand, the bottom two nodes N1 and N2 are set as nodes for the wiring itself. Therefore, they are not linked to information on direct input and output with the outside, and therefore, in the wiring information 125, information as "Non" is linked. In this way, by setting wiring nodes as necessary for the wiring itself that is not linked to the outside, it becomes possible to appropriately describe the entire circuit in the graph topology structure of the present invention.

[0050] A terminal node 123, which can be used in the present application to achieve greater effect, is set between the part node 122 and the wiring node 124. This is set in correspondence with a terminal in an actual circuit.

[0051] Next, explanation will be given using Fig. 5C. 102 shows the whole of board A in a graph topology structure. In Fig. 5C, the functions and assignments of the terminals at terminal node 123, such as V+, V-, Out, 1, 2, etc., are omitted. This is for the purpose of explanation, simplifying the lines to make the drawing easier to read, and in reality, it is desirable to simultaneously display these descriptions and the connection line information in Fig. 5C.

[0052] The relationship between part nodes 122 and terminal nodes 123, i.e., the relationship between each part and each terminal, is represented by a connecting line as part-terminal edge 126. The relationship between terminal nodes 123 and wiring nodes 124, i.e., the relationship between each terminal and each wire, is represented by a connecting line as terminal-wiring edge 127.

[0053] As described above, the representation using the graph topology structure enables circuit modeling with higher accuracy, and is particularly suitable for representing large-scale circuits or for large-scale calculations.

[0054] As described above, the graph topology structure is particularly suitable for expressing large-scale circuits or large-scale calculations, and this will be explained with reference to FIGS. 6A to 6E.

[0055] FIG. 6A is a circuit model for unit A, for example. If board A in FIG. 5A is a lower layer, then unit A in FIG. 6A can be said to be a middle layer that includes board A as a part of it. 131 is the overall circuit diagram of unit A, 141 is board P, 142 is cable P1, 143 is cable P2, 144 is board A, 145 is cable S1, and 146 is board B. Although board A, board B, and board P are described in the figure, the same applies if they are circuit group A, circuit group B, and circuit group P. Board A in FIG. 6A is the part corresponding to 101 in FIG. 5A, as shown as 101 in FIG. 6B.

[0056] Figure 6C is a graph topology representation of the circuit of Figure 6A, and also shows an example display screen.

[0057] In this figure, the representation is like that of Fig. 5B + Fig. 5C, and both the functions and assignments of the terminals in the terminal nodes, and the part-terminal edges and the terminal-wiring edges are displayed at the same time. An example of the screen display of the circuit design support device according to the present invention will be described later in Fig. 8A, and it is desirable that the graph topology structure displayed and presented to the designer at that time contains a lot of information as shown in Fig. 6C. This is because the display device 9 is capable of displaying in color, and the types of information can be distinguished by color coding. For example, node information is black, assignment information is green, and edge information is blue.

[0058] 132 shows the whole of unit A in a graph topology structure. In part node 151, nodes 141 corresponding to board P, 142 corresponding to cable P1, 143 corresponding to cable P2, 144 corresponding to board A, 145 corresponding to cable S1, and 146 corresponding to board B are set. In wiring node 153, a large number of inputs / outputs and wiring are set as nodes, as shown in FIG. 6C. In terminal node 152, similar to the case for board A, they are set corresponding to actual terminals and inputs / outputs. The connection relationships between parts and terminals are displayed as part-terminal edges 154, and the connection relationships between terminals and wiring are displayed as terminal-wiring edges 155.

[0059] As shown in Fig. 6C, in the graph topology display of unit A, substrate A in Fig. 5A can be incorporated as part of the configuration requirements as 101. Similarly, lower layer information can be seamlessly incorporated for substrate P, substrate B, or other configuration members. This is a major strength of the present invention, which uses a graph topology structure to represent and analyze circuits, and by continuing to incorporate and analyze lower layers and then incorporate and analyze the results into higher layers, it becomes possible to seamlessly analyze large-scale circuits or complex design items.

[0060] FIG. 6D is a diagram in which the lines of part / terminal edge 154 and terminal / wiring edge 155 are deleted from FIG. 6C, and only the nodes are shown.

[0061] FIG. 6E is a diagram in which the characters of the assignment details of the terminal nodes are deleted from FIG. 6C, and the connection relationship between the part-terminal edge 154 and the terminal-wiring edge 155 is extracted and shown.

[0062] Next, the case of proceeding to the analysis of a higher layer will be described with reference to Fig. 7A. Fig. 7A is the top layer, and is a circuit diagram of the entire circuit to be designed, or the entire product. Here, let us assume that it is a product. 161 is the circuit diagram of the entire product, 171 is the power supply unit, 172 is the control unit, 173 is unit A, and 174 is unit B.

[0063] As shown as 131 in FIG. 7B, unit A in FIG. 6A is incorporated as part of the lower layer constituting 161 as 173 in FIG. 7A.

[0064] Figure 7C is a diagram of the circuit of Figure 7A expressed in a graph topology structure. Although the layers are different, it corresponds to the expression in Figure 6C. It is also an example of a display screen.

[0065] 162 shows the entire product in a graph topology structure. In part node 181, nodes 181 corresponding to the power supply unit, 172 corresponding to the control unit, 173 corresponding to unit A, and 174 corresponding to unit B are set. In wiring node 183, a large number of inputs / outputs and wiring are set as nodes, as shown in FIG. 7C. In terminal node 182, similar to the case for board A, they are set corresponding to actual terminals and inputs / outputs. The connection relationships between parts and terminals are displayed as part / terminal edges 184, and the connection relationships between terminals and wiring are displayed as terminal / wiring edges 185.

[0066] As shown in Fig. 7C, in the display of the graph topology structure 162 of the entire product, unit A in Fig. 6A can be incorporated as part of the configuration requirements as 131. Similarly, the power supply unit, control unit, or other configuration units can seamlessly incorporate information of lower layers. This is a major strength of the present invention, which uses a graph topology structure to represent and analyze circuits, and by continuing to incorporate and analyze lower layers and the results into higher layers, it becomes possible to seamlessly analyze large-scale circuits or complex design items.

[0067] FIG. 7D is a diagram in which the lines of part / terminal edge 184 and terminal / wiring edge 185 are deleted from FIG. 7C, and only the nodes are shown.

[0068] FIG. 7E is a diagram in which the characters of the assignment details of the terminal nodes are deleted from FIG. 7C, and the connection relationship between the part-terminal edge 184 and the terminal-wiring edge 185 is extracted and shown.

[0069] As described above in detail using each diagram in Figures 5 to 7, by using a circuit representation using a graph topology structure and performing circuit analysis using it, it is possible to seamlessly analyze the overall design and performance from lower-level circuits to higher-level circuits and products, especially for large-scale circuits. This makes it possible to seamlessly and efficiently analyze the effects of design changes or performance changes in a lower-level circuit or part of it on the performance and characteristics of nearby components and circuits, higher layers, or the entire product.

[0070] The circuit design support device using the graph topology structure of the present application can realize seamless and efficient design and analysis of the entire product, thereby improving the efficiency of circuit design and reducing the time required for design. In addition, since it is possible to set more items than before as evaluation items, when applied to a circuit design support device that performs LCA calculation as shown in Figure 3, it is possible to realize efficient performance evaluation and environmental evaluation in a short time. Furthermore, since it is possible to evaluate the performance and environmental impact of changes to some circuits or components on other components or the entire product, it is possible to provide a circuit design support device that is effective when designing circuits that address environmental issues. EXAMPLES

[0071] This embodiment is an example of a display screen on the display device 9 in the circuit design assistance device 1 that performs circuit analysis using the graph topology structure in the first embodiment.

[0072] Fig. 8A shows an example of a display screen of the circuit design assistance device 1. Reference numeral 400 denotes the display screen, 101 denotes the display area for circuit 101 of board A in Fig. 5A, 131 denotes the display area for circuit 131 of unit A in Fig. 6A, and 161 denotes the display area for circuit 161 of the product in Fig. 7A. Layer 1, layer 2, and layer 3 are displayed from the left, from bottom to top. This enables the designer to easily confirm on the screen where the part to be changed in the design corresponds in the overall product circuit.

[0073] Reference numeral 102 is a display area for the graph topology of board A shown in Figure 5B or 5C, or a superimposed display thereof, and is a display relating to layer 1 corresponding to the circuit of board A in 101. Reference numeral 132 is a display area for the graph topology of unit A shown in Figure 6C, etc., and is a display relating to layer 2 corresponding to the circuit of unit A in 131. Reference numeral 162 is a display area for the graph topology of the product shown in Figure 7C, etc., and is a display relating to layer 3 corresponding to the circuit of the product in 161.

[0074] In this way, by displaying the circuit screen and the graph topology display corresponding to the circuit side-by-side on the display screen 400, the designer can easily verify and confirm the graph topology information set for the circuit. This makes it possible to grasp model construction errors at an early stage and correct them as necessary. This makes it possible to prevent deviations between the performance and characteristics of the actual circuit and the calculated performance and characteristics caused by model construction errors.

[0075] Reference numeral 402 denotes a display field for the analysis results for the circuit of layer 1, 403 denotes a display field for the analysis results for the circuit of layer 2, and 404 denotes a display field for the analysis results for the circuit of layer 3. The contents to be displayed can be set in advance by the designer in the circuit design support device 1. In the circuit design support device 1 which calculates LCA performance in addition to performance and power consumption, for example as shown in Fig. 3, the analysis results of LCA performance can also be displayed in this area.

[0076] This display allows performance, power consumption, and LCA performance to be checked side-by-side across layers, making it easy to see the impact of a design change on other locations or on the whole, as well as bottlenecks in the design.

[0077] The graph topology structures of 102, 132, and 162 also include cases where they are not intended to be displayed on a screen. This is because confirmation by the designer can be omitted in cases where the circuit design assistance device 1 is sufficiently reliable, or where there is no risk of the graph topology structure being affected by only standard design changes. For this reason, in the circuit design assistance device 1 of this embodiment, it is set so that the graph topology structure display can be switched ON and OFF as 410. This is realized by the designer selecting a desired item by operating the mouse from the user IF, or by clicking on the screen, etc.

[0078] Reference numeral 411 denotes a setting item for switching the display accuracy of the analysis results. It is possible to switch between detailed display and overall display. Fig. 8A shows an example in which detailed display is selected in the detailed tab, but if it is determined that there is almost no impact on lower layers or if one wishes to know only the analysis results and impact on the final overall product, the overall tab may be used to display only the overall analysis results and evaluation results by integrating the display areas 401, 402, and 403.

[0079] Reference numeral 412 denotes a tab area for selecting a step of the design support. In the target data selection tab 413, the circuit to be changed and the contents of the change are displayed, or in the case of a newly designed circuit, the screen is switched to an information input screen for the circuit. Reference numeral 414 denotes an input tab for the redesign target. This is used when an existing circuit library is called up, a part of it is specified on the screen, and change information for it is input. Reference numeral 415 denotes a tab for performing analysis processing after the designer has completed inputting data. By clicking this tab, the circuit design support device 1 performs a performance analysis and a characteristic analysis of the circuit, and displays the results on the display screen 400. An example is the display areas 402, 403, and 404 of the analysis results shown in FIG. 8A. Reference numeral 416 denotes a tab for presenting solutions. By clicking this tab, the circuit design support device considers solutions to bottlenecks in performance or unachieved items in environmental characteristics, and displays them on the screen. Reference numeral 417 denotes a tab for implementing design changes. If the analysis in the circuit design support device 1 determines that the specified performance is met, the designer can click this tab to make the design conditions on the circuit design support device the final conditions, and they will be reflected in the design database, etc.

[0080] FIG. 8B shows an example in which the graph topology structure display 410 is turned off on the display screen of FIG. 8A, and the analysis solution presentation 416 is clicked.

[0081] In this example, 102, 132, and 162 that display the graph topology structure disappear, and instead the display areas of analysis results 402, 403, and 404 move to the top, with solutions displayed below them. 422, 423, and 424 all display solutions, but when there are multiple solutions, 422 is the recommended solution with first priority, 423 is the first example of alternative solution 1, and 424 is the second example of alternative solution. In this way, by allowing the circuit design support device to present and display multiple solutions, the designer can determine and adopt the most optimal solution.

[0082] When presenting this solution, it may be examined and presented by a circuit design support device. Alternatively, it may be examined and presented in conjunction with an external program or processing device. This is because, with the rapid improvement in the decision-making ability and speed of deep learning through machine learning and AI in recent years, it may not be optimal to complete everything within a single device.

[0083] In the present invention, all circuit design support devices capable of displaying circuit information in a graph topology structure or capable of displaying a graph topology structure on a screen are included in the scope of the present invention. In addition, the scope of the present invention naturally includes circuit design support devices capable of displaying a graph topology structure on a screen only in exceptional circumstances, such as in a special mode, for example, a verification mode or an evaluation mode. EXAMPLES

[0084] In this embodiment, a detailed example of a processing procedure in the circuit design assistance device 1 of the present application will be described with reference to a flowchart. In particular, an example of a process for generating a circuit model data structure will be described with reference to FIG.

[0085] Processing starts in 201. In 202, a target product is selected. In 203, it is determined whether a circuit model of the target product already exists, and if YES, i.e., if it already exists, the process jumps to end 218 in 230. If NO, i.e., if it does not exist, the process proceeds to 204. In 204, a netlist and a parts list of one circuit of the target product are read from the netlist / parts DB. In 205, parts, terminals, and wiring information are extracted from all netlists, and the parts are classified into part node groups, terminal node groups, and wiring node groups. In 206, edges are generated for each node of the part group and each node of the terminal group based on the netlist. In 207, edges are generated for each node of the terminal group and each node of the wiring group based on the netlist. In 208, analysis models and environment information corresponding to all nodes in the part group are read from the DB, and are saved in the nodes as auxiliary information. In 209, input / output information is specified and saved in the nodes of the wiring group that are the input / output / input / output of the circuit. In 210, the part / terminal / wiring node group and edge information are saved in the circuit model DB as a circuit model. From 210, the flow continues to 211 at 231. At 211, it is determined whether the processing of all circuits of the target product is completed. If NO, that is, not completed, at 232, the process returns to 204, where the net list and parts list of the next circuit are read, and the process is resumed. If YES, at 212, the circuit model generated in the previous process is read from the circuit model DB. At 213, the wiring node in which the input / output information is saved is defined as a terminal node group, and the circuit model itself is defined as one part node, and reference information of the circuit model is saved as attached information. At 214, edges are generated between the nodes of the part and the terminal. At 215, wiring nodes and edges are generated between all terminals having connection information of this layer among the input / output information attached to the terminal. At 216, the part / terminal / wiring node group and edge information are saved in the circuit model DB as a circuit model one level above. At 218, it is determined whether the processing of all layers of the input / output information is completed. If NO, at 234, the process returns to 211. If YES, the process ends at 218.

[0086] The processing contents in the above flowchart can be more specifically explained as follows. This flow starts when the user specifies a target product. If a circuit model for the target product specified by the user has not yet been generated, this flow generates a circuit model data structure. First, the netlist and parts list of all circuits to be mounted on the target product are read from the netlist / parts DB, a circuit model data structure is generated, and an analysis model, environmental information, and input / output information are attached to each node.

[0087] Next, a circuit model to be used in the next higher layer is generated based on the input / output information, and the generation process is repeated until all layers included in the input / output information have been connected. Here, as an example of the configuration of the input / output information, layer 1 is connected to wiring X of board A, layer 2 is connected to wiring Y of unit D, ..., layer N is connected to wiring Z on the front of the equipment, and so on. As an example, the entire circuit model data structure is generated by repeating the process.

[0088] Next, an example of the performance / environment / impact range analysis flow will be described with reference to FIG.

[0089] Processing begins in 301. In 302, the target part and analysis items are specified. In 303, a circuit model of the product having the target part is read from the circuit model DB. In 304, a circuit model of only the target part is extracted, and a netlist for circuit analysis is generated. In 305, the circuit is analyzed and all input / output characteristics are saved as characteristic information before redesign. In 306, the redesign information is reflected in the circuit model, and a netlist for circuit analysis is generated. In 307, the circuit is analyzed and all input / output characteristics are saved as characteristic information after redesign. In 308, characteristic information before and after redesign is compared, and all wiring nodes that are different and have input / output information attached are extracted. In 309, the destination node name, wiring name, and characteristic information are saved based on the input / output information of the extracted wiring node. In 310, the results of the analysis items specified from the characteristic information after redesign, the destination node name, wiring name, and characteristic information are output to a user IF. In 311, the environmental information attached to all part nodes of the circuit model before redesign of the target part and the power information of the characteristic information before redesign are input into an LCA calculation program, and the results are saved as the LCA results before redesign. In 312, the environmental information attached to all part nodes of the circuit model after redesign of the target part and the power information of the characteristic information after redesign are input into an LCA calculation program, and the results are saved as the LCA results before redesign. In 313, the results of the analysis items specified from the LCA results before and after redesign are output to the user IF. The processing ends in 314.

[0090] The processing contents in the above flowchart can be more specifically explained as follows.

[0091] This flow starts when the user specifies the target area and analysis items.

[0092] The product's circuit model is read from the database based on the target part information specified by the user, and the circuit model of the target part is extracted from the product's circuit model. An analysis netlist is generated from the circuit model and circuit analysis is performed. Here, the analysis results before and after redesign are compared, and the wiring destinations and characteristic information of any differing wiring, as well as the specified analysis items, are output to the user interface. LCA is calculated based on the power information and environmental information from the circuit analysis results. The LCA also outputs the specified items both before and after redesign to the user interface. The user checks the results of the specified analysis items and the scope of the impact, and if necessary, sets the affected parts as the target parts and the characteristic information as the analysis items and executes this flow again.

[0093] The present invention has been described above using a number of embodiments. Here, one example of the invention disclosed in the present specification can be described in another way as follows, for example.

[0094] <Part 1> A circuit design support device having a control unit having an arithmetic unit, a memory, a storage, an input device, and a display device, in which overall circuit information is stored in the storage, and circuit information to be changed from the overall circuit information is input from the input device to a control unit having the arithmetic unit, and the control unit having the arithmetic unit calculates the performance of the circuit information to be changed and the impact on the performance of other circuits in the overall circuit information, as well as the impact of the changed circuit information on environmental performance, and displays the calculated performance of the circuit information, the impact on the performance of the other circuits in the overall circuit information, and the impact of the changed circuit information on environmental performance on the display device.

[0095] <Part 2> In the circuit design support device described in <Item 1>, the environmental performance is LCA performance.

[0096] <Part 3> In the circuit design support device described in <Item 1>, a control unit having the arithmetic device calculates the impact of the changed circuit information on the performance of other circuits in the entire circuit information and the impact on environmental performance by calculating the circuit information through modeling using graph topology.

[0097] <Part 4> In the circuit design support device described in <Item 3>, the modeling by the graph topology includes part nodes, wiring nodes, and terminal nodes located between the part nodes and the wiring nodes.

[0098] <Part 5> In the circuit design support device described in <No. 4>, the modeling by the graph topology includes part-terminal edges connecting the part nodes and the terminal nodes, and terminal-wiring edges connecting the terminal nodes and the wiring nodes.

[0099] <Part 6> A circuit design support device having a control unit having an arithmetic unit, a memory, a storage, an input device, and a display device, wherein the control unit having the arithmetic unit calculates, based on information from a database stored in the storage, performance information of the circuit that is the subject of the design change and the impact on the performance of other circuits to which the circuit that is the subject of the design change is connected, and calculates the impact of the design change on environmental performance, for circuit information that is the subject of the design change input from the input device, and the control unit having the arithmetic unit displays on the display device the performance of the circuit that is the subject of the design change, the impact on the performance of other circuits to which the circuit that is the subject of the design change is connected, and the impact of the design change on environmental performance.

[0100] <Part 7> In the circuit design support device according to <Item 6>, the environmental performance is at least one of power consumption and LCA performance.

[0101] <Part 8> In the circuit design support device described in <Item 6>, the control unit having the arithmetic device is a circuit design support device capable of displaying the circuit information as a graph topology on the display device.

[0102] <Number 9> In the circuit design support device described in <No. 8>, the graph topology includes part nodes, wiring nodes, and terminal nodes located between the part nodes and the wiring nodes.

[0103] <Part 10> In the circuit design support device described in <No. 9>, the graph topology includes part-terminal edges connecting the part nodes and the terminal nodes, and terminal-wiring edges connecting the terminal nodes and the wiring nodes.

[0104] <Part 11> In a circuit design support device having a control unit with a calculation unit, a memory, a storage, an input device, and a display device, the storage has databases of a net list of a circuit, a parts list, environmental information, an analysis model, and a circuit model, and the circuit model is a graph data structure in which a node group is generated from a first set of parts, a second set of terminals, and a third set of wiring from the net list, and edges are generated consisting of connection information between the parts and the terminals and connection information between the terminals and the wiring, and each node of the part node group, which is the first set, has a label that links the analysis model of the circuit performance corresponding to each part and environmental load information, and each node of the wiring node group, which is the third set, has input / output terminal information indicating whether the node is an input, output, or input / output of a product hierarchy, or something else, and among the wiring node group, a circuit design support device which converts a wiring node associated with any of the inputs and outputs into a terminal node in a higher layer, sets the wiring node as the terminal node of the higher layer, redefines the circuit model itself as a single parts node, generates edges between the parts nodes and the wiring nodes, generates wiring nodes in the higher layer from wiring information of the hierarchy one level higher contained in input / output information, and generates edges between the wiring nodes of the above-mentioned layer and the terminal nodes of the higher layer to generate a higher-level circuit model, generates the higher-level circuit model at all hierarchical levels to generate a circuit model of the entire product, determines other circuit parts that will be affected by the change of a circuit to be changed that has been input from the input device to a control unit having the arithmetic unit, and displays performance and environmental indexes of the circuit to be changed and the other circuit parts that will be affected by the change on the display device.

[0105] In addition, the term "circuit design support device" in this application also includes a circuit design support system.

[0106] Furthermore, various modifications and display modifications based on the ideas disclosed in the specification and drawings of the present application are naturally included within the scope of the disclosure of this application, as the fundamental ideas thereof are disclosed in the specification and drawings of the present application. [Explanation of symbols]

[0107] 1:Circuit design support equipment 2: Control unit 3: CPU 4: Storage 5: Memory 6: Communication Network 7: User IF 8: Input device 9:Display device 31, 122, 151, 181: Part nodes 32, 123, 152, 182: Terminal nodes 33, 124, 153, 183: Wiring nodes 34, 126, 154, 184: Parts / Terminal Edges 35, 127, 155, 185: Terminals and wiring edges 36, 121: Parts information 37, 125: Wiring information 51: Circuit design program 52: Circuit model generation program 53: Performance, environment and impact analysis program 54: Circuit analysis program 55: LCA calculation program 56: Netlist and component DB 57:Environmental information DB 58: Analysis model DB 59: Circuit model DB 61: Design information 72: Netlist and parts list 73:Environmental information 74:Analysis model 81: Information on netlists, analysis models, and specified performance items 82:Analysis results 83: Information about power in circuits 84: List of environmental information and specification of LCA items 85:Analysis results 101: Overall circuit diagram of board A 102: Graph topology structure of the entire substrate A 131: Overall circuit diagram of unit A 132: Graph topology structure of the entire unit A 161: Overall circuit diagram of the device 162: Graph topology structure of the entire product 400:Display screen 402, 403, 404: Analysis result display area

Claims

1. A circuit design support device having a control unit having a calculation device, a memory, a storage, an input device, and a display device, The storage stores the entire circuit information, The input device inputs circuit information to be changed from among the entire circuit information to a control unit having the arithmetic unit, The control unit having the arithmetic unit includes: Calculating the performance of the circuit information to be changed and the impact on the performance of other circuits in the entire circuit information, and calculating the impact of the circuit information to be changed on environmental performance; The circuit design support device displays on the display device the calculated performance of the circuit information, the effect on the performance of other circuits in the overall circuit information, and the effect on environmental performance of the changed circuit information.

2. 2. The circuit design support device according to claim 1, wherein the environmental performance is LCA performance.

3. 2. The circuit design support device according to claim 1, wherein a control unit having the arithmetic unit calculates the impact of the changed circuit information on the performance of other circuits in the entire circuit information and on environmental performance by calculating the circuit information through modeling using graph topology.

4. 4. The circuit design support device according to claim 3, wherein the modeling by the graph topology includes part nodes, wiring nodes, and terminal nodes located between the part nodes and the wiring nodes.

5. 5. The circuit design support device according to claim 4, wherein the modeling by the graph topology includes part / terminal edges connecting the part nodes and the terminal nodes, and terminal / wiring edges connecting the terminal nodes and the wiring nodes.

6. A circuit design support device having a control unit having a calculation device, a memory, a storage, an input device, and a display device, a control unit having the arithmetic unit, for circuit information that is the subject of a design change input from the input device, based on information from the database stored in the storage, calculates performance information of the circuit that is the subject of the design change and the impact on performance of other circuits to which the circuit that is the subject of the design change is connected, and calculates the impact of the design change on environmental performance; A control unit having the arithmetic device displays on the display device the performance of the circuit that is the subject of the design change, the impact on the performance of other circuits to which the circuit that is the subject of the design change is connected, and the impact of the design change on environmental performance.

7. 7. The circuit design support device according to claim 6, wherein the environmental performance is at least one of power consumption and LCA performance.

8. 7. The circuit design support device according to claim 6, wherein a control unit having said arithmetic unit is capable of displaying said circuit information on said display unit as a graph topology.

9. 9. The circuit design support device according to claim 8, wherein said graph topology includes part nodes, wiring nodes, and terminal nodes located between said part nodes and wiring nodes.

10. 10. The circuit design support device according to claim 9, wherein the graph topology includes part / terminal edges connecting the part nodes and the terminal nodes, and terminal / wiring edges connecting the terminal nodes and the wiring nodes.

11. A circuit design support device having a control unit having a calculation device, a memory, a storage, an input device, and a display device, The storage includes databases for a circuit netlist, a parts list, environmental information, an analysis model, and a circuit model, The circuit model is a graph data structure in which a node group is generated from the netlist, which is a first set of parts, a second set of terminals, and a third set of wiring, and edges are generated that are made up of connection information between the parts and the terminals and connection information between the terminals and the wiring, each node of the part node group, which is the first set, has a label that links an analytical model of the circuit performance corresponding to each part and environmental load information, and each node of the wiring node group, which is the third set, has input / output terminal information indicating whether the node is an input, output, or input / output of the product hierarchy, or something other than that, converting a wiring node associated with any one of the input, output, or input / output among the group of wiring nodes into a terminal node in an upper layer, setting the wiring node as a terminal node of the upper layer, redefining the circuit model itself as one parts node, generating edges between the parts node and the wiring nodes, generating wiring nodes of the upper layer from connection information of the next higher layer included in input / output information, and generating edges between the wiring nodes of the above layer and the terminal nodes of the upper layer, thereby generating an upper layer circuit model; The generation of the upper hierarchical circuit model is carried out at all hierarchical levels to generate a circuit model of the entire product; A circuit design support device that determines other circuit parts that will be affected by the change to a circuit to be changed that has been input from the input device to a control unit having the arithmetic unit, and displays on the display device the performance and environmental indexes of the circuit to be changed and the other circuit parts that will be affected by the change.

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