Integrated structure having diffusion barrier layer and electronic element including the same

Abstract

To provide an integrated structure having a diffusion barrier layer for reducing interface defects at a metal-semiconductor interface.SOLUTION: An integrated structure includes a silicon or SOI (silicon-on-insulator) substrate, a conductive layer separated from the substrate and containing a metal or a metal compound, and a diffusion barrier layer provided between the substrate and the conductive layer. The substrate and the diffusion barrier layer are in direct contact with each other to form a van der Waals bond. The diffusion barrier layer may block movement of materials (atoms) between the substrate and the conductive layer to block diffusion of metal atoms in a substrate lattice, and may control injection of holes from the conductive layer toward the substrate, thereby controlling metal-semiconductor interface defects in order to overcome limitations of ultra-miniaturization and a highly integrated semiconductor.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an integrated structure including a diffusion barrier layer, and more particularly, to an integrated structure including a diffusion barrier layer for reducing interface defects at a metal-semiconductor interface.

Background Art

[0002] For the implementation of artificial intelligence and Internet of Things (IoT) integration technologies, the development of low-power-drivable and intelligent semiconductor synaptic devices is being actively promoted worldwide. In particular, for the realization of immersive non-face-to-face industries and the advancement of national security networks in the post-corona era, an autonomous control device that autonomously collects information, learns and makes decisions, and executes them is necessary. In addition, artificial intelligence technology, which is widely used in the fourth industrial revolution, including big data analysis and autonomous driving vehicles, requires an NPU (Neural Processing Unit) as an artificial intelligence semiconductor optimized for the operation of deep learning algorithms. Since most of the existing computing semiconductors centered on CPUs (Central Processing Units) are expected to be switched to NPUs, which are artificial intelligence semiconductors, the importance of developing high-level semiconductors with driving performance capable of processing large-capacity information at high speed and low power has been further enhanced.

[0003] The metal-semiconductor interface can directly affect electron injection and current output, and is one of the factors determining the performance of semiconductor devices. In particular, a technology for reducing defects at the metal-semiconductor interface formed by diffusion and intermixing of substances (atoms) between a metal material used as an electrode or the like and a semiconductor channel is essential. Furthermore, different from the past, as current semiconductor process technology approaches the sub-nano (sub-1nm) level, quasi-ideal interface design at the ultra-fine scale is very important for overcoming the limitations of future ultra-fine and highly integrated semiconductors.

Summary of the Invention

[0004] The present invention has been devised to solve the above-mentioned problems, and provides an integrated structure capable of controlling defects at a metal-semiconductor interface and an electronic device including the same in order to overcome the limitations of ultra-miniaturization and highly integrated semiconductors. [Means for solving the problem]

[0005] In order to achieve the above technical objective, an integrated structure according to a preferred embodiment of the present invention can include a silicon or SOI (Silicon-on-insulator) substrate, a conductive layer spaced apart from the substrate and containing a metal or a metal compound, and a diffusion barrier layer provided between the substrate and the conductive layer.

[0006] The substrate and the diffusion barrier layer can be in direct contact and form van der Waals bonds.

[0007] The diffusion barrier layer may include a p-type semiconducting material.

[0008] The diffusion barrier layer may be a monolayer.

[0009] The diffusion barrier layer may have a thickness of 0.1 to 10 Å.

[0010] The diffusion barrier layer may include a transition metal dichalcogenide material.

[0011] The transition metal dichalcogenide material has the general formula MX 2 wherein M is a transition metal element and includes Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Ru, Co, Pd, Pt, Cu, Ga, In, Sn, Ge, Pb, or a combination of two or more selected from among these, and X is a chalcogen element and may include S, Se, Te, or a combination of two or more selected from among these.

[0012] The transition metal dichalcogenide material is MoS 2 , MoSe 2 , MoTe 2 , W.S. 2 , WSe 2 , W.T.e. 2 , ZrS 2 , ZrSe 2 , HfS 2 , HfSe 2 , NbSe 2 ,ReSe 2 , PdTe 2 Or, it may include a combination of two or more selected from these.

[0013] The crystal structure of the transition metal dichalcogenide material may be a hexagonal structure in a planar direction.

[0014] The metals may include Ti, Ni, Cr / Au, Ag, and combinations of two or more selected therefrom.

[0015] The present invention is characterized in that the movement of substances (atoms) in the conductive layer and the substrate is blocked.

[0016] The injection of electrons from the substrate to the conductive layer is blocked.

[0017] The present invention is characterized in that holes are injected from the conductive layer to the substrate.

[0018] The present invention may also be an electronic device including any one of the integrated structures described above. Effect of the Invention

[0019] According to the present invention, an integrated structure according to a preferred embodiment of the present invention includes a silicon or SOI (Silicon-on-insulator) substrate, a conductive layer containing a metal or a metal compound spaced apart from the substrate, and a diffusion barrier layer provided therebetween. The substrate and the diffusion barrier layer can be in direct contact with each other to form a van der Waals bond. The diffusion barrier layer can block the movement of material (atoms) between the substrate and the conductive layer to block the diffusion of metal atoms into the substrate lattice, and can control hole injection from the conductive layer toward the substrate, thereby controlling metal-semiconductor interface defects to overcome the limitations of ultra-miniaturized and highly integrated semiconductors.

[0020] The effects of the present invention are not limited to those described above, and include other effects that are not explicitly mentioned, although they can be clearly understood by those skilled in the art from the general description of the specification. [Brief description of the drawings]

[0021]

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Figure 5

[0022] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Advantages and features of the present invention, as well as methods for achieving the same, will become apparent from the following detailed embodiments together with the accompanying drawings. The present invention is not limited to the following embodiments, and may be embodied in various different forms, and the present embodiments are provided only to fully disclose the present invention and to fully inform those skilled in the art of the present invention of the scope of the invention, and the present invention is only defined by the scope of the claims. The same reference numerals are used to refer to the same components throughout the specification. Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used in the sense commonly understood by those having ordinary skill in the art to which the present invention belongs. In addition, terms defined in commonly used dictionaries are not interpreted ideally or excessively unless otherwise clearly defined. The terms used herein are intended to describe the embodiments and are not intended to limit the present invention. In the present specification, the singular form includes the plural form unless otherwise specified in the text. As used herein, components, steps, operations and / or elements referred to as "comprises" and / or "comprising" do not exclude the presence or addition of one or more other components, steps, operations and / or elements.

[0023] Integrated structure having a diffusion barrier layer FIG. 1 is a schematic diagram illustrating a cross-section of an integrated structure 100 including a diffusion barrier layer 20 according to one embodiment of the present invention.

[0024] 1, an integrated structure 100 may include a silicon or SOI (Silicon-on-insulator) substrate 10, a conductive layer 30 containing a metal or metal compound spaced therefrom, and a diffusion barrier layer 20 provided therebetween. The diffusion barrier layer 20 is a thin film and may function to block the movement of substances (atoms, electrons, holes, etc.) between the substrate 10 and the conductive layer 30, for example, the movement of metal atoms from the conductive layer 30 to the substrate 10.

[0025] The substrate 10 may be a semiconductor material, such as silicon or a silicon-on-insulator (SOI) substrate, and more specifically, may be a p-type semiconductor material, such as p-type silicon. The substrate 10 may further be a material doped with a dopant, but is not limited thereto.

[0026] The conductive layer 30 may include a metal or a metal compound. The metal or metal compound may include metal elements such as Ti, Ni, Cr / Au, Ag, and combinations of two or more selected from these, and may be any type of metal that includes a type of metal element suitable for application to electronic devices such as a metal electrode and metal interconnection.

[0027] The substrate 10 and the diffusion barrier layer 20 may be in direct contact with each other to form a van der Waals bond due to van der Waals force (vdW). Specifically, the bond between the silicon lattice on the surface of the substrate 10 and the diffusion barrier layer 20 may be formed by a bond due to van der Waals force. The atoms of each layer may be crossed with each other and not mixed or penetrated, but each interface may be physically clearly separated, that is, a van der Waals gap may be formed between the substrate 10 and the diffusion barrier layer 20. In particular, in the manufacturing process of the diffusion barrier layer 20, a transfer process, more specifically, a wet transfer process may be applied to minimize physical damage to the surface and form a diffusion barrier layer 20 of a uniform thickness. By providing the diffusion barrier layer 20 formed by van der Waals bonding on the surface of the substrate 10, highly reactive dangling bonds on the surface of the substrate 10 can be removed and the inherent physical properties of the substrate 10 can be preserved, which can be advantageously applied to the realization of highly integrated devices.

[0028] The diffusion barrier layer 20 and the conductive layer 30 may also form a direct contact, but the interface between the two may ideally be one in which a van der Wals (vdW) bond can be formed, but in practice may include an intermixing region in the diffusion barrier layer 20 due to diffusion of metal atoms of the conductive layer 30 without the van der Wals (vdW) bond being formed.

[0029] The diffusion barrier layer 20 can control the movement / diffusion of materials (atoms) in the substrate 10 and the conductive layer 30, thereby controlling the injection of electrons. In the conventional metal-semiconductor interface forming direct contact, metal atoms may diffuse or penetrate into silicon crystals by a conventional deposition method for forming a metal electrode, resulting in the formation of defects due to intermixing of different elements. However, the integrated structure according to the present invention can block the diffusion of metal atoms from the conductive layer 30 into the lattice of the substrate 10 (e.g., in the direction of metal → Si) by providing the diffusion barrier layer 20. Therefore, the diffusion of metal atoms into the silicon substrate crystal to form intermixing bonds and the formation of silicide, which is a compound of silicon and metal, can be suppressed, thereby reducing the density of interface defects, and the injection of electrons in the reverse direction (e.g., in the direction of Si → metal) from the substrate 10 to the conductive layer 30 can be blocked. As a result, the contact resistance at the interface between the substrate 10 and the conductive layer 30 is reduced, the trap density is reduced, and the Schottky barrier height is reduced. Therefore, the leakage current of the electronic device is reduced through the diffusion barrier layer 20, the rectification characteristics are maximized, and a quasi-ideal interface is formed, thereby improving the electrical characteristics.

[0030] In addition, the hole injection from the conductive layer 30 to the substrate 10 can be controlled through the diffusion barrier layer 20. Specifically, the efficiency of hole injection from the metal of the conductive layer 30 to the substrate 10 (for example, metal → Si direction) can be improved through the diffusion barrier layer 20, and the ON / OFF ratio, which is the driving performance of the device, can be improved by more than 100 times. This is because the application of the diffusion barrier layer 20 suppresses the formation of a metal induced gap state due to the penetration of metal atoms into the silicon (Si) lattice, and the Fermi level can be freely controlled by voltage driving without the Fermi level pinning phenomenon at the metal / semiconductor interface. As a result, it can be explained that the efficiency of hole injection can be improved by fundamentally removing factors that hinder hole injection due to such causes.

[0031] In particular, the diffusion barrier layer 20 may be formed as a monolayer to enhance the efficiency of hole injection. If one or more layers are repeatedly stacked to form a multilayer of two or more layers, it is undesirable since the efficiency of hole injection may decrease. The thickness of the single-layer diffusion barrier layer 20 for enhancing the efficiency of hole injection may be shallow on the nano to sub-nano scale or less, and may be extremely thin at 1 nm or less, and may have a thin thickness and maintain excellent characteristics. The thickness of the diffusion barrier layer 20 may be 0.1 to 10 Å, specifically 0.3 to 9 Å, and more specifically 0.5 to 8 Å. In one embodiment, the thickness of the diffusion barrier layer 20 may be 7 Å, but is not limited thereto. Such a diffusion barrier layer 20 may be advantageously applied to the realization of a highly integrated device having a fine line width.

[0032] The diffusion barrier layer 20 is about 10 -2 Ω cm or less, specifically about 10 -4 ~10 -2The diffusion barrier layer 20 may have a low resistivity value of Ω·cm. Since the diffusion barrier layer 20 has a low resistivity, it may have excellent electrical conductivity at a level similar to that of a metal or semimetal. However, if the diffusion barrier layer 20 is extremely thin, for example, 1 nm or less, it may have a resistivity value at a semiconductor level.

[0033] The diffusion barrier layer 20 may be a semiconductor material and may include a transition metal dichalcogenide (TMD) material. The transition metal dichalcogenide material has various advantages, such as having a two-dimensional crystal structure, excellent diffusion prevention properties, and being able to be formed with a very thin thickness. The transition metal dichalcogenide (TMD) may be a material having n-type or p-type semiconductor properties without doping, and in particular, the transition metal dichalcogenide (TMD) may be a material having p-type semiconductor properties. In order to enhance the doping properties, an atom substitution process in a chalcogen atomic layer may be further performed.

[0034] The transition metal dichalcogenide (TMD) layer having p-type semiconductor properties is in contact with the p-type silicon substrate 10, and is converted to silicon dioxide (SiO 2 ), and during the deposition process of the conductive layer 30, the metal atoms of the conductive layer 30 can be prevented from diffusing directly into the silicon lattice and from forming silicide, so that the problem of inhomogeneity of the silicon substrate can be basically prevented. This prevents the formation of a metal induced gap state in the silicon band structure, and as a result, the Fermi level pinning phenomenon can be suppressed.

[0035] The transition metal dichalcogenide material has the general formula MX2 where M is a transition metal element, for example, Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Ru, Co, Pd, Pt, Cu, Ga, In, Sn, Ge, Pb, or a combination of two or more selected therefrom, and X is a chalcogen element, for example, S, Se, Te, or a combination of two or more selected therefrom. Specifically, the transition metal dichalcogenide material is MoS 2 , MoSe 2 , MoTe 2 , W.S. 2 , WSe 2 , W.T.e. 2 , ZrS 2 , ZrSe 2 , HfS 2 , HfSe 2 , NbSe 2 ,ReSe 2 , PdTe 2 Or a combination of two or more selected from these. More specifically, the transition metal dichalcogenide material may be MoS 2 , MoSe 2 , W.S. 2 , WSe 2 or a combination of two or more selected therefrom, and in one embodiment, WSe 2 These may include, but are not limited to:

[0036] The crystal structure of the transition metal dichalcogenide material has a hexagonal structure in the planar direction based on a covalent bond between the transition metal M and the chalcogen element X. The crystal structure may be changed by a further phase change step or doping step.

[0037] In addition, when the diffusion barrier layer 20 is made of the transition metal dichalcogenide material, there are no dangling bonds extending outside the layer, so that the inherent physical properties of the substrate 10 can be preserved when formed on the substrate 10, making it advantageously applicable to the realization of highly integrated devices.

[0038] FIG. 2 shows the results of a transmission electron microscope (TEM) photograph of a cross section of a metal-semiconductor interface in an integrated structure according to one embodiment of the present invention, as well as the results of element mapping and EDS analysis of the cross section.

[0039] Referring to Figure 2, WSe 2 In an integrated structure in which a metal (Ni) electrode is in direct contact with a substrate without a diffusion barrier layer, it was found that metal atoms diffuse or penetrate into the silicon crystal, resulting in the simultaneous presence of metal element (Ni) and oxygen (O) elements in the interfacial layer with the substrate, forming an intermixing region due to the mixing of different elements.

[0040] FIG. 3 is a schematic diagram showing a cross-section of a metal-diffusion barrier layer-semiconductor interface for an integrated structure according to one embodiment of the present invention, showing a transmission electron microscope (TEM) image of the cross-section of the metal-diffusion barrier layer-semiconductor interface and an EDS elemental mapping result for the cross-section.

[0041] Referring to FIG. 3, WSe 2 Si / WSe with diffusion barrier layer 2 It can be seen that in the integrated structure in which the interface is constructed and the metal (Ag) is laminated, no intermixing region is formed because the metal atoms are unable to diffuse or penetrate into the silicon crystal.

[0042] Hereinafter, the present invention will be described in more detail using examples and comparative examples. However, the following examples and comparative examples are for illustrative purposes of the present invention, and the scope of the present invention is not limited thereto.

[0043] Production Example 1: WSe 2 Synthesis method of thin film Tungsten diselenide (WSe 2 ) is synthesized using chemical vapor deposition (CVD) equipment equipped with two heating zones. First, silicon dioxide (SiO 2 ) is used as the substrate, a quartz boat filled with 480 mg of selenium (Se, 99.5%, manufactured by Sigma-Aldrich) powder is placed in the left heating zone, and a quartz boat filled with a mixed powder of 40 mg of NaCl (99%, manufactured by Sigma-Aldrich) and 240 mg of tungsten oxide (WOx, 99.9%, manufactured by Sigma-Aldrich) is placed in the right heating zone. Then, with the distance between the two quartz boats set at 40 cm, the temperature of each heating zone is set to 870 °C for the left zone and 640 °C for the right zone, and WSe 2 is grown for 10 minutes. At this time, the flow rate of the Ar / H 2 gas as the carrier gas is 100 / 20 sccm, and the process pressure is optimized to 1 - 100 Torr in the synthesis stage.

[0044] Production Example 2: Si / WSe using wet transfer method 2 Interface formation A PMMA (Poly(methyl methacrylate)) polymer solution was coated on the WSe 2 thin film grown on the silicon dioxide (SiO 2 ) substrate produced by the method of Production Example 1. After PMMA coating, the produced PMMA / WSe 2 / SiO 2 was immersed in a 3 wt% KOH solution to obtain PMMA / WSe 2 layer and SiO 2The substrate was separated. Meanwhile, a patterned silicon (Si) substrate was produced by an exposure process. 2 The WSe layer was transferred onto a p-type silicon (Si) substrate that had been patterned by an exposure process, and the PMMA and photoresist (PR) were removed using acetone. 2 A thin film was prepared, which formed van der Waals (vdW) bonds on Si / WSe 2 The interface was prepared.

[0045] Example: Si / WSe bonded by van der Waals force (vdW) 2 Schottky diodes and transistors including the interface Si / WSe produced by the method of Production Example 2 2 We fabricated Schottky diodes and silicon (Si) channel transistors including the interface. Si / WSe 2 After performing an exposure process for patterning a metal electrode on the substrate including the interface, a metal electrode was deposited by an e-beam evaporator. At this time, the metals used for the metal electrode were Ti, Ni, Cr / Au and Ag. Then, a Schottky diode was fabricated by forming a metal electrode by a lift-off method in which the patterned photosensitive solution obtained in the exposure process was removed using acetone.

[0046] Meanwhile, a Si channel transistor was fabricated in a back-gating structure using a SOI (Silicon On Insulator) wafer. The Si / WSe 2 A WSe interface was formed, and a Ni electrode was deposited on it by electron beam evaporation. 2 The layers were then bonded together, where WSe 2Ideally, the WSe / Ni interface can be formed by van der Wals (vdW) bonding, but due to issues such as the actual process, the van der Wals (vdW) bonding cannot be formed and the WSe 2 The surface of the WSe layer is damaged. 2 The layer may include an intermixing region due to diffusion of Ni atoms into the layer. After patterning the channel by the exposure process, the surface of the SOI wafer is lightly oxidized by a dry oxidation method using plasma, and then a metal (Ni) electrode is formed by using a method similar to the lift-off method described above.

[0047] Comparative Example: Si / WSe 2 Manufacture of Schottky diodes and transistors without the interface Si / WSe produced by the method of Production Example 2 2 A Schottky diode and a silicon (Si) channel transistor were manufactured using the same method as in the example, except that no interface was included.

[0048] Test Example: Si / WSe bonded by van der Waals (vdW) 2 Measurement of Schottky diodes and transistors including the interface [Schottky barrier] WSe at the metal / semiconductor interface 2 To analyze the effect of reducing metal / semiconductor interface defects by the interface formation, electrical characteristics of Schottky diodes were analyzed. Specifically, the I-V rectification characteristics, Schottky barrier height (SBH), and interface trap density (D it ) to calculate WSe 2 The effect of inserting the interface layer was verified. The IV rectification characteristics were obtained by applying a voltage (V) of -2V to 2V and measuring the current (I). The current of a Schottky diode can generally be determined by the following formula 1.

[0049] [Number 1] I=I 0 [exp(qV / ηkT)-1]...(1)

[0050] In the above formula 1, q is the charge amount, V is the applied voltage, η is the ideality factor, k is the Boltzmann constant, and T is the temperature. 0 (Saturation current) is given by the following equation 2.

[0051] [Number 2] I 0 =AA * T 2 exp(-qφ0 / kT)...(2)

[0052] In the above formula 2, A is the diode area, A * is the Richardson constant, T is the temperature, q is the charge, k is the Boltzmann constant, and φ0 is the Schottky barrier height (SBH). 0 It can be seen that the variables that make up the Schottky barrier height are temperature (T) and Schottky barrier height (φ0). Using this, the saturation current was measured at seven temperature points at 10°C intervals from room temperature (RT, 25°C) to 75°C to calculate the Schottky barrier height. In fact, since the current flow of a Schottky diode is predominantly determined by the current flowing due to the low SBH, it can be corrected and calculated using a Barrier Height Inhomogeneities (BHI) model that corrects the Schottky barrier height.

[0053] [Charge trap density D it ] Charge traps are mainly generated by interface defects, so changes in interface defects can be indirectly inferred through changes in trap density. Furthermore, because interface traps capture and release charges, changes in trap density were quantitatively calculated by measuring CV (Capacitance-Voltage) and GV (Conductance-Voltage). CV and GV measurements were performed by fixing the frequency in 100kHz increments from 100kHz to 1MHz and applying AC voltages from -2V to 2V to obtain changes in capacitance and conductance. Trap density D it can be quantitatively expressed by the following Equation 3.

[0054] [Number 3] D it =(2.5 / Aq)(G / ω) peak ...(3)

[0055] In the above formula 3, A is the diode area, q is the charge, G is the conductance, and ω is each frequency.

[0056] FIG. 4 shows (a) and (c) energy diagrams and CV graphs of a metal-semiconductor interface, and (b) and (d) energy diagrams and CV graphs of a metal-diffusion barrier layer-semiconductor interface for an integrated structure according to one embodiment of the present invention.

[0057] 4(a) and 4(c), in the metal-semiconductor interface that forms a direct contact, metal atoms may diffuse or penetrate into the silicon crystal by a general deposition method for forming a metal electrode, resulting in the formation of intermixing defects of different elements. Due to such intermixing defects, the intrinsic physical properties of the silicon (Si) substrate are deformed, forming a metal-induced gap state (MIGS) in the silicon (Si) band gap, which may cause a problem of Fermi level pinning during electrostatic drive through the gate. As a result, the contact resistance of the metal-semiconductor interface increases, the output current decreases, and the drive voltage of a device having the same increases, which may increase the stress of the interface and lead to degradation of the device.

[0058] On the other hand, as shown in Fig. 4(b) and Fig. 4(d), a diffusion barrier layer (WSe 2 The effect of the insertion of ZnO is the reduction in Schottky barrier height and interface trap density D it The capacitance-voltage measurement results showed that WSe 2 Trap density after insertion D it It was confirmed that the defect density decreased by more than 10 times. In addition, the density was also decreased in various metals that can be used as electrodes, such as Ni, Ti, Au / Cr, and Ag, similar to the above results.

[0059] FIG. 5 is a schematic diagram of an electronic device (Si p-MOS) having an integrated structure according to an embodiment of the present invention, (a) an IV graph with and without a diffusion barrier layer, (b) an On / Off ratio, and (d) statistical results for maximum mobility, for an integrated structure according to an embodiment of the present invention.

[0060] As shown in Figure 5, WSe 2 It is a Si device with electrodes formed as a metal laminate structure, and when a drain voltage is applied, the metal / WSe 2 It can be seen that the hole charges injected through the electrode are transferred through a silicon channel to be driven.

[0061] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will recognize that the present invention may be embodied in other specific forms without departing from the technical spirit or gist of the present invention. Therefore, the above-described embodiments are illustrative in all respects and are not limiting. [Explanation of symbols]

[0062] 100 Integrated Structure 10 Substrate 20 Diffusion Barrier Layer 30 Conductive layer

Claims

1. a silicon or SOI (Silicon-on-insulator) substrate; a conductive layer spaced apart from the substrate and including a metal or a metal compound; a diffusion barrier layer disposed between the substrate and the conductive layer; Including, The substrate and the diffusion barrier layer are in direct contact and form a van der Waals bond. Accumulation structure.

2. The diffusion barrier layer comprises a p-type semiconducting material. The integrated structure of claim 1 .

3. The diffusion barrier layer is a monolayer. The integrated structure of claim 1 .

4. The thickness of the diffusion barrier layer is 0.1 to 10 Å. The integrated structure of claim 1 .

5. The diffusion barrier layer comprises a transition metal dichalcogenide material. The integrated structure of claim 1 .

6. The transition metal dichalcogenide material has the general formula MX ２ It is expressed as The M is a transition metal element, and includes Mo, W, Nb, V, Ta, Ti, Zr, Hf, Tc, Re, Ru, Co, Pd, Pt, Cu, Ga, In, Sn, Ge, Pb, or a combination of two or more selected from among these; The X is a chalcogen element, and includes S, Se, Te, or a combination of two or more selected therefrom. The integrated structure of claim 5 .

7. The transition metal dichalcogenide material is MoS ２ , MoSe ２ , MoTe ２ , W.S. ２ , WSe ２ , W.T.e ２ , ZrS ２ , ZrSe ２ , HfS ２ , HfSe ２ , NbSe ２ ,ReSe ２ , PdTe ２ or a combination of two or more selected from these. The integrated structure of claim 5 .

8. The crystal structure of the transition metal dichalcogenide material is a hexagonal structure in the planar direction. The integrated structure of claim 5 .

9. The metals include Ti, Ni, Cr / Au, Ag, and combinations of two or more selected therefrom. The integrated structure of claim 1 .

10. The movement of material (atoms) in the conductive layer and the substrate is blocked. The integrated structure of claim 1 .

11. Injection of electrons from the substrate into the conductive layer is blocked. The integrated structure of claim 1 .

12. Holes are injected from the conductive layer into the substrate. The integrated structure of claim 1 .

13. The integrated structure according to any one of claims 1 to 12 is included. An electronic device characterized by:

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