Semiconductor device drive device

Abstract

To provide a technology that enables a secondary side circuit to determine whether the ASC mode is being executed.SOLUTION: A semiconductor device drive device includes a primary circuit, a signal transmission circuit including an insulating element, and a secondary circuit that drives a semiconductor device on the basis of a plurality of transmission signals corresponding to a plurality of signals transmitted from the primary circuit via the signal transmission circuit. The secondary circuit includes an ASC mode determination circuit that determines whether a normal mode or an ASC mode is being executed on the basis of a transmission transition signal corresponding to a transition signal or a control transition signal among the plurality of transmission signals.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor element driving device. [Background technology]

[0002] Various techniques have been proposed for semiconductor element driving devices that drive semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) in inverter systems. For example, a technique has been proposed in which a primary circuit transmits a signal to a secondary circuit via an insulating element capable of transmitting the signal, and the secondary circuit drives the semiconductor element.

[0003] As an example, Patent Document 1 proposes a technique in which a primary side circuit transmits to a secondary side circuit a second control signal for driving a semiconductor element in an ASC (Active Short Circuit) mode with priority over a first control signal for driving a semiconductor element in a normal mode. In other words, the technique is proposed in which a primary side circuit to which the first control signal is input without receiving a second control signal transmits the first control signal to the secondary side circuit, and a primary side circuit to which the second control signal is input transmits the second control signal to the secondary side circuit regardless of the input of the first control signal. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2023 / 105943 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the technology of Patent Document 1, the secondary side circuit cannot determine whether the normal mode or the ASC mode is being executed, which causes a problem that the secondary side circuit cannot differentiate the operation of the ASC mode from the operation of the normal mode.

[0006] Therefore, the present disclosure has been made in consideration of the above-mentioned problems, and has an object to provide a technique that enables a secondary side circuit to determine whether or not the ASC mode is being executed. [Means for solving the problem]

[0007] A semiconductor element driving device according to the present disclosure includes a primary side circuit to which a plurality of signals including a first control signal for controlling driving of a semiconductor element in a normal mode, a second control signal for controlling driving of the semiconductor element in an ASC mode, and a transition signal for transitioning from the normal mode to the ASC mode, or including the first control signal and a control transition signal corresponding to the second control signal and the transition signal, a signal transmission circuit including an insulating element capable of transmitting a signal, and a secondary side circuit that drives the semiconductor element based on a plurality of transmission signals corresponding to the plurality of signals transmitted from the primary side circuit via the signal transmission circuit, and the secondary side circuit drives the semiconductor element based on the plurality of transmission signals. and a logic circuit that, when it is determined by the ASC mode determination circuit that the normal mode is being executed, drives the semiconductor element based on a first transmission control signal corresponding to the first control signal among the plurality of transmission signals, and drives the semiconductor element based on the second control signal among the plurality of transmission signals or a second transmission control signal corresponding to the control transition signal, when it is determined by the ASC mode determination circuit that the ASC mode is being executed. Effect of the Invention

[0008] According to the present disclosure, the secondary side circuit includes an ASC mode determination circuit that determines whether the normal mode or the ASC mode is being executed based on a transfer transition signal corresponding to a transition signal or a control transition signal among a plurality of transfer signals. With this configuration, the secondary side circuit can determine whether the ASC mode is being executed. [Brief description of the drawings]

[0009] [Figure 1] 1 is a circuit diagram showing a configuration of a semiconductor element driving device according to a first embodiment. [Diagram 2] 4 is a timing chart showing the operation of the semiconductor element driving device according to the first embodiment. [Diagram 3] 4 is a timing chart showing an operation of the ASC mode determination circuit according to the first embodiment. [Figure 4] FIG. 11 is a circuit diagram showing a configuration of a semiconductor element driving device according to a second embodiment. [Diagram 5] 10 is a timing chart showing the operation of the semiconductor element driving device according to the second embodiment. [Figure 6] FIG. 11 is a circuit diagram showing a configuration of a semiconductor element driving device according to a third embodiment. [Figure 7] 13 is a timing chart showing the operation of the semiconductor element driving device according to the third embodiment. [Figure 8] FIG. 13 is a circuit diagram showing a configuration of a semiconductor element driving device according to a fourth embodiment. [Figure 9] 13 is a timing chart showing the operation of the semiconductor element driving device according to the fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] Hereinafter, the embodiments will be described with reference to the accompanying drawings. The features described in each of the following embodiments are merely examples, and not all features are necessarily required. In the following description, the same or similar reference numerals are used to denote similar components in multiple embodiments, and different components will be mainly described.

[0011] <Embodiment 1> Fig. 1 is a circuit diagram showing the configuration of a semiconductor element driving device according to the present embodiment 1. The semiconductor element driving device in Fig. 1 includes a primary side circuit 1 to which a plurality of signals are input, a secondary side circuit 5 that drives a semiconductor element (not shown), and a signal transmission circuit 3 including an isolation element capable of transmitting a signal from the primary side circuit 1 to the secondary side circuit 5. In other words, the semiconductor element driving device in Fig. 1 is a gate driver IC with an internal isolation element.

[0012] The multiple signals input to the primary side circuit 1 are output from, for example, an ECU (Electronic Control Unit) and an MCU (Micro Controller Unit), etc. The multiple signals according to the first embodiment include a first control signal for controlling the drive of the semiconductor element in a normal mode, a second control signal for controlling the drive of the semiconductor element in an ASC (Active Short Circuit) mode, and a transition signal for transitioning from the normal mode to the ASC mode.

[0013] The primary side circuit 1 includes an IN terminal to which a first control signal is input, an ASC_IN terminal to which a second control signal is input, an ASC_EN terminal to which a transition signal is input, and modulation circuits 11, 12, 13, 14, and 15. The modulation circuits 11, 12, 13, 14, and 15 modulate a plurality of signals input to the primary side circuit 1 into modulated signals that can be transmitted by the signal transmission circuit 3.

[0014] The signal transmission circuit 3 includes an insulating element (isolator) capable of transmitting a signal through an insulating portion such as a space. In the following, the insulating elements will be described taking as an example a configuration in which the insulating elements are transformers magnetically coupled to each other as shown in Fig. 1, but are not limited to this. For example, the insulating elements may be capacitors capacitively coupled to each other, or photocouplers optically coupled to each other.

[0015] The secondary side circuit 5 includes demodulation circuits 51, 52, 53, 54, and 55, pulse restoration circuits 61 and 62, an ASC mode determination circuit 63, an abnormality detection and protection operation circuit 64 which is an abnormality detection circuit, a logic circuit 65, a drive circuit 66, an OUT terminal, and an ErrIN terminal. Note that the abnormality detection and protection operation circuit 64 and the ErrIN terminal are not necessarily provided.

[0016] The demodulation circuits 51 to 55 and the pulse restoration circuits 61 and 62 generate a plurality of transmission signals corresponding to the plurality of signals of the primary side circuit 1 based on the modulated signal transmitted from the primary side circuit 1 via the signal transmission circuit 3.

[0017] In the first embodiment, a first transmission control signal corresponding to a first control signal among the multiple transmission signals has substantially the same waveform as the first control signal. A second transmission control signal corresponding to a second control signal among the multiple transmission signals has substantially the same waveform as the second control signal. A transmission transition signal corresponding to a transition signal among the multiple transmission signals has a waveform different from that of the transition signal. As described below, the secondary side circuit 5 drives the semiconductor element based on multiple transmission signals including the first transmission control signal, the second transmission control signal, and the transmission transition signal.

[0018] The ASC mode determination circuit 63 determines whether the normal mode or the ASC mode is being executed based on the transmission transition signal corresponding to the transition signal of the ASC_EN terminal, and outputs a determination signal indicative of the determination result.

[0019] The abnormality detection and protection operation circuit 64 acquires a signal indicating the operating state of the semiconductor element via the ErrIN terminal. The abnormality detection and protection operation circuit 64 detects an abnormality of the semiconductor element based on the signal, and outputs an abnormality detection signal indicating the detection result of the abnormality of the semiconductor element. Note that the abnormality of the semiconductor element may include an abnormality of the semiconductor element driving device that is reflected in the operating state of the semiconductor element.

[0020] The logic circuit 65 receives a first transmission control signal corresponding to the first control signal of the IN terminal, a second transmission control signal corresponding to the second control signal of the ASC_IN terminal, a determination signal from the ASC mode determination circuit 63, and an abnormality detection signal from the abnormality detection and protection operation circuit 64. The logic circuit 65 outputs a drive signal for driving a semiconductor element (not shown) from a drive circuit 66 via an OUT terminal based on the first transmission control signal, the second transmission control signal, the determination result of the ASC mode determination circuit 63, and the detection result of the abnormality detection and protection operation circuit 64.

[0021] In the first embodiment, when the ASC mode determination circuit 63 determines that the normal mode is being executed (i.e., the ASC mode is not being executed), the logic circuit 65 drives the semiconductor element based on the first transmission control signal in principle. However, when the ASC mode determination circuit 63 determines that the normal mode is being executed and the abnormality detection and protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 performs an operation to protect the semiconductor element regardless of the first transmission control signal. The operation to protect the semiconductor element is, for example, an operation to shut down the semiconductor element.

[0022] On the other hand, when the ASC mode determination circuit 63 determines that the ASC mode is being executed, the logic circuit 65 drives the semiconductor element based on the second transmission control signal, not the first transmission control signal. When the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality detection and protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 drives the semiconductor element based on the second transmission control signal without performing an operation to protect the semiconductor element.

[0023] The semiconductor element (not shown) is driven by a drive signal output from the OUT terminal by the secondary side circuit 5. The semiconductor element is, for example, a semiconductor switching element of an inverter system that drives an inductive load such as a motor. The semiconductor element includes, for example, an insulated gate bipolar transistor (IGBT), a reverse conducting IGBT (RC-IGBT), and a metal oxide semiconductor field effect transistor (MOSFET). The material of the semiconductor element may include normal silicon (Si), or may include a wide band gap semiconductor such as silicon carbide (SIC), gallium nitride (GaN), or diamond. When the semiconductor element is made of a wide band gap semiconductor, stable operation under high temperature and high voltage and high switching speed are possible.

[0024] 2 is a timing chart showing the operation of the semiconductor element driving device according to the first embodiment. The normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected will be described below. Note that in the following explanation of each mode, overlapping contents will be omitted as appropriate.

[0025] <Normal mode> The modulation circuit 11 generates a modulated signal based on a rising edge of the first control signal input to the IN terminal, and the modulation circuit 12 generates a modulated signal based on a falling edge of the first control signal input to the IN terminal. That is, the modulation circuits 11 and 12 generate a modulated signal by performing edge trigger modulation on the first control signal. The modulated signals generated by the modulation circuits 11 and 12 are provided to the demodulation circuits 51 and 52, respectively, via the signal transmission circuit 3.

[0026] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the S terminal and the R terminal of the pulse restoration circuit 61, respectively. The pulse restoration circuit 61 generates a first transmission control signal having substantially the same waveform as the first control signal input to the primary side circuit 1 based on the edge trigger signals output from the demodulation circuits 51 and 52, and outputs the first transmission control signal from the Q terminal to the logic circuit 65. With this configuration, it is possible to transmit the first transmission control signal corresponding to the first control signal from the primary side circuit 1 to the secondary side circuit 5 while maintaining an insulating state between the primary side circuit 1 and the secondary side circuit 5 and without losing the square wave information of the first control signal.

[0027] The second control signal input to the ASC_IN terminal is also processed in the same manner as the first control signal. Specifically, the modulation circuit 13 generates a modulated signal based on the rising edge of the second control signal, and the modulation circuit 14 generates a modulated signal based on the falling edge of the second control signal. That is, the modulation circuits 13 and 14 generate a modulated signal by performing edge trigger modulation on the second control signal. The modulated signals generated by the modulation circuits 13 and 14 are provided to the demodulation circuits 53 and 54, respectively, via the signal transmission circuit 3.

[0028] The demodulation circuits 53 and 54 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 13 and 14 to the S terminal and the R terminal, respectively, of the pulse restoration circuit 62. The pulse restoration circuit 62 generates a second transmission control signal having substantially the same waveform as the second control signal input to the primary side circuit 1 based on the edge trigger signals output from the demodulation circuits 53 and 54, and outputs the second transmission control signal from the Q terminal to the logic circuit 65.

[0029] In the normal mode, a transition signal of the disable signal (Low) is input to the ASC_EN terminal. When the transition signal of the disable signal is input, the modulation circuit 15 outputs the disable signal, and the disable signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs a transmission transition signal of the disable signal to the ASC mode determination circuit 63. The ASC mode determination circuit 63 determines that the normal mode is being executed based on the transmission transition signal of the disable signal, and outputs a determination signal of the disable signal indicating the determination result to the logic circuit 65.

[0030] When the ASC mode determination circuit 63 determines that the normal mode is being executed, the logic circuit 65 rejects the second transmission control signal corresponding to the second control signal, and outputs a drive signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal.

[0031] <Normal mode when an abnormality is detected> If an abnormality occurs in a semiconductor element or the like during normal mode, a valid signal (High) is input to the ErrIN terminal of the secondary side circuit 5. When a valid signal is input to the ErrIN terminal, the abnormality detection and protection operation circuit 64 detects an abnormality in the semiconductor element and outputs an abnormality detection signal of an valid signal to the logic circuit 65.

[0032] When the ASC mode determination circuit 63 determines that the normal mode is being executed and the abnormality detection and protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 outputs a signal (Low) to the OUT terminal to shut down the semiconductor element regardless of the first transmission control signal.

[0033] <ASCモード> In the ASC mode, a transition signal of a valid signal is input to the ASC_EN terminal. When the transition signal is a valid signal, the modulation circuit 15 generates a modulated signal including a burst-like pulse by OOK (On-Off-Keying). The modulated signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs a transmission transition signal corresponding to the modulated signal to the ASC mode determination circuit 63. The transmission transition signal has substantially the same waveform as the modulation signal of the modulation circuit 15.

[0034] 3 is a timing chart showing the operation of the ASC mode determination circuit 63 according to the first embodiment. In the ASC mode determination circuit 63, a count reset trigger for resetting the count of the pulses of the transmission transition signal to 0 and a determination trigger for the ASC mode determination circuit 63 to make a determination are generated. A determination cycle is a period between the count reset trigger and the determination trigger.

[0035] The ASC mode determination circuit 63 determines that the ASC mode is being executed when the pulse of the transmission transition signal is counted a predetermined number of times (N≧2) within a determination cycle, which is a predetermined period. In this case, the ASC mode determination circuit 63 outputs a determination signal of an effective signal indicating the determination result that the ASC mode is being executed to the logic circuit 65. On the other hand, even if the transition signal of the ASC_EN terminal is an effective signal momentarily, if the number of times counted from the pulse of the transmission transition signal within the determination cycle does not reach N, the ASC mode determination circuit 63 does not determine that the ASC mode is being executed. In this case, the ASC mode determination circuit 63 outputs a determination signal of an ineffective signal indicating the determination result that the normal mode is being executed to the logic circuit 65. With this configuration, it is possible to suppress erroneous determination by the ASC mode determination circuit 63 due to noise.

[0036] When the ASC mode determination circuit 63 determines that the normal mode is being executed, the logic circuit 65 rejects the first transmission control signal corresponding to the first control signal, and outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal.

[0037] <ASC mode when an abnormality is detected> If an abnormality occurs in a semiconductor element or the like during the ASC mode, a valid signal is input to the ErrIN terminal of the secondary side circuit 5. When a valid signal is input to the ErrIN terminal, the abnormality detection and protection operation circuit 64 detects an abnormality in the semiconductor element and outputs an abnormality detection signal, which is an valid signal, to the logic circuit 65.

[0038] When the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality detection / protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 outputs a drive signal to the OUT terminal based on a second transmission control signal corresponding to the second control signal. With this configuration, in the ASC mode, operation in the ASC mode can be continued regardless of the detection result of the abnormality detection / protection operation circuit 64.

[0039] <Summary of the first embodiment> According to the semiconductor element driving device of the first embodiment, the ASC mode determination circuit 63 of the secondary side circuit 5 determines whether the normal mode or the ASC mode is being executed based on a transmission transition signal corresponding to the transition signal. With this configuration, the secondary side circuit 5 can differentiate the operation of the ASC mode when an abnormality is detected from the operation of the normal mode when an abnormality is detected based on the determination result of the ASC mode determination circuit 63.

[0040] <Embodiment 2> Fig. 4 is a circuit diagram showing the configuration of a semiconductor element driving device according to the second embodiment. The configuration of the primary side circuit 1 in Fig. 4 is similar to the configuration of the primary side circuit 1 in Fig. 1, except that a demodulation circuit 16, an FO output circuit 17 which is an output circuit, an input priority determination circuit 18, and an FO terminal which is a terminal are added, and the modulation circuits 13 and 14 are deleted. The configuration of the secondary side circuit 5 in Fig. 4 is similar to the configuration of the secondary side circuit 5 in Fig. 1, except that a modulation circuit 56 is added, and the demodulation circuits 53 and 54 and the pulse restoration circuit 62 are deleted.

[0041] The modulation circuit 56 of the secondary side circuit 5 generates a modulation signal including burst-like pulses based on the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64.

[0042] The demodulation circuit 16 of the primary side circuit 1 generates a burst signal including burst-shaped pulses based on the modulated signal transmitted from the secondary side circuit 5 via the signal transmission circuit 3. The FO output circuit 17 smoothes the burst signal generated by the demodulation circuit 16 and generates a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64. Note that in the second embodiment, the transmission result signal corresponds to a logical OR signal of the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64, but may correspond to either the determination signal or the abnormality detection signal.

[0043] The input priority determination circuit 18 selects a first control signal at the IN terminal and a second control signal at the ASC_IN terminal based on the transmission result signal of the FO output circuit 17 and the transition signal at the ASC_EN terminal, and outputs them to the signal transmission circuit 3 via the modulation circuits 11, 12. The FO terminal is a terminal for outputting a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 to the outside.

[0044] 5 is a timing chart showing the operation of the semiconductor element driving device according to the second embodiment. The normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected will be described below. Note that in the following description of each mode, overlapping contents will be omitted as appropriate.

[0045] <Normal mode> In the normal mode, a transition signal of an invalid signal is input to the ASC_EN terminal. When the transition signal is an invalid signal, the input priority determination circuit 18 determines that the normal mode is being executed regardless of the output signal of the FO output circuit 17. In this case, the input priority determination circuit 18 rejects the second control signal of the ASC_IN terminal and outputs the first control signal of the IN terminal to the modulation circuits 11 and 12.

[0046] The modulation circuits 11 and 12 perform edge trigger modulation on the first control signal to generate a modulated signal. The modulated signals generated by the modulation circuits 11 and 12 are provided to the demodulation circuits 51 and 52, respectively, via the signal transmission circuit 3.

[0047] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the S terminal and the R terminal of the pulse restoration circuit 61. The pulse restoration circuit 61 generates a first transmission control signal having substantially the same waveform as the first control signal input to the primary side circuit 1 based on the edge trigger signals output from the demodulation circuits 51 and 52, and outputs the first transmission control signal from the Q terminal to the logic circuit 65.

[0048] When the transition signal of the invalid signal is input, the modulation circuit 15 outputs an invalid signal, and the invalid signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs a transmission transition signal of the invalid signal to the ASC mode determination circuit 63. The ASC mode determination circuit 63 determines that the normal mode is being executed based on the transmission transition signal of the invalid signal, and outputs a determination signal of the invalid signal indicative of the determination result to the logic circuit 65.

[0049] When the ASC mode determination circuit 63 determines that the normal mode is being executed, the logic circuit 65 outputs a drive signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal of the IN terminal.

[0050] <Normal mode when an abnormality is detected> If an abnormality occurs in a semiconductor element or the like during normal mode, a valid signal is input to the ErrIN terminal of the secondary side circuit 5. When a valid signal is input to the ErrIN terminal, the abnormality detection and protection operation circuit 64 detects an abnormality in the semiconductor element and outputs an abnormality detection signal, which is an valid signal, to the logic circuit 65 and the modulation circuit 56.

[0051] When the ASC mode determination circuit 63 determines that the normal mode is being executed and the abnormality detection and protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 outputs a signal to the OUT terminal to shut down the semiconductor element regardless of the first transmission control signal.

[0052] When the abnormality detection signal of the abnormality detection and protection operation circuit 64 is a valid signal, the modulation circuit 56 generates a modulated signal including a burst-shaped pulse by OOK. The modulated signal is transmitted to the demodulation circuit 16 via the signal transmission circuit 3, and the demodulation circuit 16 outputs a burst signal corresponding to the modulated signal to the FO output circuit 17. The burst signal has substantially the same waveform as the modulated signal of the modulation circuit 56.

[0053] The FO output circuit 17 smoothes the burst signal of the demodulation circuit 16 and generates a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 .

[0054] The transmission result signal is output to the FO terminal, and an external device on the primary side circuit 1 side can check for an abnormality in the semiconductor element from the transmission result signal at the FO terminal. Furthermore, the transmission of the transmission result signal can be achieved by a pair of insulating elements (here, a pair of transformers).

[0055] The transmission result signal is also output to the input priority determination circuit 18. However, since the transition signal at the ASC_EN terminal is an invalid signal, the input priority determination circuit 18 determines that normal mode is being executed and outputs the first control signal at the IN terminal to the modulation circuits 11 and 12.

[0056] <ASCモード> In the ASC mode, a transition signal of a valid signal is input to the ASC_EN terminal. When the transition signal is a valid signal, the modulation circuit 15 generates a modulated signal including a burst-like pulse by OOK. The modulated signal is transmitted to the demodulation circuit 55 via the signal transmission circuit 3, and the demodulation circuit 55 outputs a transmission transition signal corresponding to the modulated signal to the ASC mode determination circuit 63. The transmission transition signal has substantially the same waveform as the modulated signal of the modulation circuit 15.

[0057] The ASC mode determination circuit 63 determines that the ASC mode is being executed when the pulses of the transmission transition signal are counted N times within a determination cycle. When the ASC mode determination circuit 63 determines that the ASC mode is being executed, it outputs a determination signal of a valid signal indicative of the determination result not only to the logic circuit 65 but also to the modulation circuit 56. On the other hand, when the ASC mode determination circuit 63 determines that the normal mode is being executed, it outputs a determination signal of an invalid signal indicative of the determination result not only to the logic circuit 65 but also to the modulation circuit 56.

[0058] The modulation circuit 56, the signal transmission circuit 3, the demodulation circuit 16, and the FO output circuit 17 perform the same operation as in the normal mode when an abnormality is detected. As a result, a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal and the input priority determination circuit 18. Since the determination signal of the ASC mode determination circuit 63 is a valid signal, the transmission result signal also becomes a valid signal.

[0059] When the transition signal at the ASC_EN terminal is a valid signal and the transmission result signal of the FO output circuit 17 is a valid signal, the input priority determination circuit 18 determines that the ASC mode has been accepted by the secondary side circuit 5. In this case, the input priority determination circuit 18 rejects the first control signal at the IN terminal and outputs the second control signal at the ASC_IN terminal to the modulation circuits 11 and 12.

[0060] The modulation circuits 11 and 12, the signal transmission circuit 3, the demodulation circuits 51 and 52, and the pulse restoration circuit 61 perform the same operation as in the normal mode for the second control signal. As a result, a second transmission control signal corresponding to the second control signal at the ASC_IN terminal is output to the logic circuit 65. When the ASC mode determination circuit 63 determines that the ASC mode is being executed, the logic circuit 65 outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal at the ASC_IN terminal.

[0061] <ASC mode when an abnormality is detected> If an abnormality occurs in a semiconductor element or the like during the ASC mode, a valid signal is input to the ErrIN terminal of the secondary side circuit 5. When a valid signal is input to the ErrIN terminal, the abnormality detection and protection operation circuit 64 detects an abnormality in the semiconductor element and outputs an abnormality detection signal, which is an effective signal, to the logic circuit 65 and the modulation circuit 56.

[0062] When the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality detection / protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 outputs a drive signal to the OUT terminal based on a second transmission control signal corresponding to the second control signal. With this configuration, in the ASC mode, operation in the ASC mode can be continued regardless of the detection result of the abnormality detection / protection operation circuit 64.

[0063] The modulation circuit 56, the signal transmission circuit 3, the demodulation circuit 16, and the FO output circuit 17 perform the same operation as in the normal mode when an abnormality is detected. As a result, a transmission result signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal and the input priority determination circuit 18. Since the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 are both valid signals, the transmission result signal also becomes a valid signal.

[0064] <Summary of the second embodiment> According to the second embodiment, the input priority determination circuit 18 of the primary side circuit 1 selectively outputs the first control signal of the IN terminal and the second control signal of the ASC_IN terminal to the signal transmission circuit 3 based on the transition signal of the ASC_EN terminal. With such a configuration, the number of modulation circuits and demodulation circuits can be reduced compared to the configuration of the first embodiment, and therefore the area and number of parts of the semiconductor element driving device can be reduced.

[0065] Furthermore, based on the transmission result signal of the FO output circuit 17 and the transition signal of the ASC_EN terminal, the input priority determination circuit 18 of the primary side circuit 1 selectively outputs the first control signal of the IN terminal and the second control signal of the ASC_IN terminal to the signal transmission circuit 3. With this configuration, the input priority determination circuit 18 can perform control to switch between the first control signal and the second control signal, taking into consideration the transmission result signal that reflects the determination result of the ASC mode determination circuit 63.

[0066] <Embodiment 3> Fig. 6 is a circuit diagram showing the configuration of a semiconductor element driving device according to the third embodiment. The configuration of the primary side circuit 1 in Fig. 6 is similar to the configuration of the primary side circuit 1 in Fig. 4, except that a transition signal of the ASC_EN terminal is input to the modulation circuits 11 and 12 and the modulation circuit 15 is deleted. The configuration of the secondary side circuit 5 in Fig. 6 is similar to the configuration of the secondary side circuit 5 in Fig. 4, except that an OR circuit 70 is added and the demodulation circuit 55 is deleted.

[0067] When the transition signal at the ASC_EN terminal is an invalid signal, the modulation circuits 11 and 12 of the primary side circuit 1 perform edge trigger modulation on the output signal of the input priority judgment circuit 18 in the same manner as the modulation circuits 11 and 12 of the second embodiment. On the other hand, when the transition signal at the ASC_EN terminal is a valid signal, the modulation circuits 11 and 12 perform OOK on the output signal of the input priority judgment circuit 18 to generate a modulated signal including burst-like pulses.

[0068] The OR circuit 70 of the secondary side circuit 5 outputs a logical OR signal of the output signals of the demodulation circuits 51 and 52 to the ASC mode determination circuit 63 .

[0069] 7 is a timing chart showing the operation of the semiconductor element driving device according to the third embodiment. The normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected will be described below. Note that in the following explanation of each mode, overlapping contents will be omitted as appropriate.

[0070] <Normal mode> In the third embodiment, a logical sum signal from the OR circuit 70 is input to the ASC mode determination circuit 63. However, since the interval between pulses of the logical sum signal in the normal mode is relatively long, the ASC mode determination circuit 63 determines that the normal mode is being executed without counting the pulses of the transmission transition signal N times within the determination cycle.

[0071] The normal mode according to the third embodiment from this point onwards is similar to the normal mode according to the second embodiment. That is, the input priority determination circuit 18 outputs a first control signal to the IN terminal, and the logic circuit 65 outputs a drive signal to the OUT terminal based on a first transmission control signal corresponding to the first control signal.

[0072] <Normal mode when an abnormality is detected> The normal mode when an abnormality is detected according to the third embodiment is the same as the normal mode when an abnormality is detected according to the second embodiment. That is, the abnormality detection and protection operation circuit 64 outputs an abnormality detection signal of an enable signal to the logic circuit 65, and the logic circuit 65 outputs a signal for shutting down the semiconductor element to the OUT terminal regardless of the first transmission control signal. Also, a transmission result signal of an enable signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0073] <ASCモード> In the ASC mode, a transition signal of the enable signal is input to the ASC_EN terminal. In this case, the modulation circuits 11 and 12 do not perform edge trigger modulation, but perform OOK on the output signal of the input priority determination circuit 18 to generate a modulated signal including a burst-like pulse according to the period of the output signal.

[0074] The modulated signal is transmitted to the demodulation circuits 51 and 52 via the signal transmission circuit 3, and the demodulation circuits 51 and 52 output signals corresponding to the modulated signal to the S terminal and the R terminal, respectively, of the pulse restoration circuit 61. The demodulation circuits 51 and 52 also output signals corresponding to the modulated signal to the OR circuit 70.

[0075] The OR circuit 70 outputs a logical sum signal of the output signals of the demodulation circuits 51, 52 as a transfer transition signal to the ASC mode determination circuit 63. The ASC mode determination circuit 63 counts the pulses of the transfer transition signal, which includes burst-like pulses like the transfer transition signal of the second embodiment, a predetermined number N times within a determination cycle, and therefore determines that the ASC mode is being executed.

[0076] The subsequent ASC mode according to the third embodiment is similar to the ASC mode according to the second embodiment. That is, the input priority determination circuit 18 outputs a second control signal to the ASC_IN terminal, and the logic circuit 65 outputs a drive signal to the OUT terminal based on a second transmission control signal corresponding to the second control signal. In addition, a transmission result signal of an effective signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0077] <ASC mode when an abnormality is detected> As described in the ASC mode, except for the difference in the process of generating the transmission transition signal from the second embodiment, the ASC mode at the time of abnormality detection according to the third embodiment is the same as the ASC mode at the time of abnormality detection according to the second embodiment. That is, the abnormality detection and protection operation circuit 64 outputs an abnormality detection signal of an enable signal to the logic circuit 65, and the logic circuit 65 outputs a drive signal to the OUT terminal based on a second transmission control signal corresponding to the second control signal. Also, a transmission result signal of an enable signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0078] <Summary of the Third Embodiment> According to the third embodiment, the number of modulation circuits and demodulation circuits can be reduced compared to the configuration of the second embodiment, so that the area and number of parts of the semiconductor element driving device can be reduced. Note that, as long as it does not affect the judgment of the ASC mode judgment circuit 63, the modulation circuits 11 and 12 may generate and output a modulated signal by OOK even in the normal mode. With such a configuration, the secondary side circuit 5 can confirm the start-up of the primary side power supply of the primary side circuit 1.

[0079] <Fourth embodiment> Fig. 8 is a circuit diagram showing the configuration of a semiconductor element driving device according to the fourth embodiment. The configuration of the primary side circuit 1 in Fig. 8 is similar to the configuration of the primary side circuit 1 in Fig. 6, except that the ASC_IN terminal, the ASC_EN terminal, and the input priority determination circuit 18 are deleted. The configuration of the secondary side circuit 5 in Fig. 8 is similar to the configuration of the secondary side circuit 5 in Fig. 6, except that a waveform shaping circuit 72 is added.

[0080] In the fourth embodiment, a plurality of signals are selectively input to the IN terminal of the primary side circuit 1. The plurality of signals include a first control signal and a control transition signal. The control transition signal corresponds to the second control signal and transition signal described above, and includes a burst-like pulse having a shorter pulse width than the first control signal.

[0081] The ASC mode determination circuit 63 determines whether the normal mode or the ASC mode is being executed based on a transmission transition signal corresponding to the control transition signal.

[0082] The modulation circuits 11 and 12, the demodulation circuits 51 and 52, and the pulse restoration circuit 61 generate a signal including a burst-shaped pulse corresponding to the control transition signal. In the fourth embodiment, the signal output from the pulse restoration circuit 61 has substantially the same waveform as that of the control transition signal. The waveform shaping circuit 72 generates a second transmission control signal, which is a square wave signal, based on the signal output from the pulse restoration circuit 61. When the ASC mode determination circuit 63 determines that the ASC mode is being executed, the logic circuit 65 drives the semiconductor element based on the second transmission control signal, which is a square wave signal generated by the waveform shaping circuit 72.

[0083] 9 is a timing chart showing the operation of the semiconductor element driving device according to the fourth embodiment. The normal mode, the normal mode when an abnormality is detected, the ASC mode, and the ASC mode when an abnormality is detected will be described below. Note that in the following explanation of each mode, overlapping contents will be omitted as appropriate.

[0084] <Normal mode> In the normal mode, the first control signal is input to the IN terminal. The modulation circuits 11 and 12 generate modulated signals by performing edge trigger modulation on the first control signal. The modulated signals generated by the modulation circuits 11 and 12 are provided to the demodulation circuits 51 and 52, respectively, via the signal transmission circuit 3.

[0085] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the S terminal and the R terminal of the pulse restoration circuit 61, respectively. The pulse restoration circuit 61 generates a first transmission control signal having substantially the same waveform as the first control signal input to the primary side circuit 1 based on the edge trigger signals output from the demodulation circuits 51 and 52, and outputs the first transmission control signal from the Q terminal to the waveform shaping circuit 72. Since the first transmission control signal has a frequency less than the threshold, the waveform shaping circuit 72 outputs the first transmission control signal to the logic circuit 65.

[0086] The ASC mode determination circuit 63 determines that the normal mode is being executed because the pulses of the transmission transition signal are not counted N times within the determination cycle. The ASC mode determination circuit 63 according to the fourth embodiment differs from the ASC mode determination circuits 63 according to the first to third embodiments in that the ASC mode determination circuit 63 sequentially determines, for each signal provided to the IN terminal, whether the signal is the first control signal in the normal mode or the control transition signal in the ASC mode.

[0087] As a result of the above operations, the logic circuit 65 outputs a drive signal to the OUT terminal based on the first transmission control signal corresponding to the first control signal.

[0088] <Normal mode when an abnormality is detected> The normal mode when an abnormality is detected according to the fourth embodiment is the same as the normal mode when an abnormality is detected according to the third embodiment. That is, the abnormality detection and protection operation circuit 64 outputs an abnormality detection signal of an enable signal to the logic circuit 65, and the logic circuit 65 outputs a signal for shutting down the semiconductor element to the OUT terminal regardless of the first transmission control signal. Also, a transmission result signal of an enable signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0089] <ASCモード> In the normal mode, a control transition signal is input to the IN terminal. The modulation circuits 11 and 12 perform edge trigger modulation on the control transition signal to generate a modulated signal including a burst-like pulse. The modulated signals generated by the modulation circuits 11 and 12 are provided to the demodulation circuits 51 and 52, respectively, via the signal transmission circuit 3.

[0090] The demodulation circuits 51 and 52 output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the S terminal and R terminal of the pulse restoration circuit 61. The demodulation circuits 51 and 52 also output edge trigger signals equivalent to the modulated signals generated by the modulation circuits 11 and 12 to the OR circuit 70.

[0091] The pulse restoration circuit 62 generates a signal having substantially the same waveform as the control transition signal input to the primary side circuit 1 based on the edge trigger signals output from the demodulation circuits 51, 52, and outputs the signal from the Q terminal to the waveform shaping circuit 72. Since the signal output from the pulse restoration circuit 62 has a frequency equal to or higher than a threshold, the waveform shaping circuit 72 generates a second transmission control signal, which is a square wave signal, based on the signal, and outputs the second transmission control signal to the logic circuit 65.

[0092] The OR circuit 70 outputs a logical sum signal of the edge trigger signals output from the demodulation circuits 51 and 52 to the ASC mode determination circuit 63. The ASC mode determination circuit 63 counts pulses of the logical sum signal including burst-like pulses like the transmission transition signal of the third embodiment a predetermined N times within a determination cycle, and therefore determines that the ASC mode is being executed.

[0093] The subsequent ASC mode according to the third embodiment is the same as the ASC mode according to the third embodiment. That is, the logic circuit 65 outputs a drive signal to the OUT terminal based on the second transmission control signal corresponding to the second control signal. Also, a transmission result signal of an effective signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0094] <ASC mode when an abnormality is detected> When the ASC mode determination circuit 63 determines that the ASC mode is being executed and the abnormality detection and protection operation circuit 64 detects an abnormality in the semiconductor element, the logic circuit 65 outputs a drive signal to the OUT terminal based on a second transmission control signal corresponding to the second control signal. Also, a transmission result signal of an effective signal corresponding to the determination signal of the ASC mode determination circuit 63 and the abnormality detection signal of the abnormality detection and protection operation circuit 64 is output to the FO terminal of the primary side circuit 1.

[0095] <Summary of the fourth embodiment> According to the semiconductor element driving device of the fourth embodiment, similarly to the first to third embodiments, the ASC mode determination circuit 63 of the secondary side circuit 5 determines whether the normal mode or the ASC mode is being executed based on a transmission transition signal corresponding to the transition signal. With this configuration, the secondary side circuit 5 can differentiate the operation of the ASC mode when an abnormality is detected from the operation of the normal mode when an abnormality is detected based on the determination result of the ASC mode determination circuit 63.

[0096] Furthermore, according to the fourth embodiment, the ASC_IN terminal, the ASC_EN terminal, and the input priority determination circuit 18 can be eliminated from the configuration of the third embodiment, so that a reduction in the area and number of components of the semiconductor element driving device can be expected.

[0097] It should be noted that the embodiments and modifications may be freely combined, and the embodiments and modifications may be modified or omitted as appropriate.

[0098] Various aspects of the present disclosure are summarized below as appendices.

[0099] (Appendix 1) a primary side circuit to which a plurality of signals are input, the primary side circuit including a first control signal for controlling the operation of a semiconductor element in a normal mode, a second control signal for controlling the operation of the semiconductor element in an ASC mode, and a transition signal for transitioning from the normal mode to the ASC mode, or the primary side circuit including the first control signal and a control transition signal corresponding to the second control signal and the transition signal; A signal transmission circuit including an insulating element capable of transmitting a signal; a secondary side circuit that drives the semiconductor device based on a plurality of transmission signals corresponding to the plurality of signals transmitted from the primary side circuit via the signal transmission circuit; Equipped with The secondary side circuit includes: an ASC mode determination circuit that determines whether the normal mode or the ASC mode is being executed based on a transmission transition signal corresponding to the transition signal or the control transition signal among the plurality of transmission signals; a logic circuit that drives the semiconductor element based on a first transmission control signal corresponding to the first control signal among the plurality of transmission signals when it is determined by the ASC mode determination circuit that the normal mode is being executed, and drives the semiconductor element based on a second transmission control signal corresponding to the second control signal or the control transition signal among the plurality of transmission signals when it is determined by the ASC mode determination circuit that the ASC mode is being executed; A semiconductor element driving device comprising:

[0100] (Appendix 2) 2. The semiconductor element driving device according to claim 1, the transmitted transition signal includes a burst of pulses; The semiconductor element driving device, wherein the ASC mode determination circuit determines that the ASC mode is being executed when the pulses of the transmission transition signal are counted a predetermined number of times within a predetermined period.

[0101] (Appendix 3) A semiconductor element driving device according to claim 1 or 2, The secondary side circuit includes: Further comprising an abnormality detection circuit for detecting an abnormality of the semiconductor element; The logic circuit includes: When the ASC mode determination circuit determines that the normal mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor device, an operation to protect the semiconductor device is performed regardless of the first transmission control signal; a semiconductor element driving device that drives the semiconductor element based on the second transmission control signal when the ASC mode determination circuit determines that the ASC mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor element.

[0102] (Appendix 4) A semiconductor element driving device according to any one of Supplementary Note 1 to Supplementary Note 3, The primary side circuit includes: a modulation circuit for generating a modulation signal based on rising and falling edges of the first control signal, The secondary side circuit includes: The semiconductor element driving device further includes a demodulation circuit that generates an edge trigger signal used to generate the first transmission control signal based on the modulated signal transmitted from the primary side circuit via the signal transmission circuit.

[0103] (Appendix 5) The semiconductor element driving device according to claim 4, The secondary side circuit includes: The semiconductor device driving device further includes a pulse restoration circuit that generates the first transfer control signal based on the edge trigger signal.

[0104] (Appendix 6) A semiconductor element driving device according to claim 1 or 2, The secondary side circuit includes: The semiconductor device further includes an abnormality detection circuit that outputs an abnormality detection signal indicating a detection result of an abnormality in the semiconductor device, The primary side circuit includes: a terminal for outputting, to an outside, a transmission result signal corresponding to the abnormality detection signal transmitted from the secondary side circuit via the signal transmission circuit.

[0105] (Appendix 7) A semiconductor element driving device according to claim 1 or 2, The secondary side circuit includes: an abnormality detection circuit that outputs an abnormality detection signal indicative of a detection result of an abnormality in the semiconductor element; a modulation circuit that generates a modulation signal including a burst-like pulse based on the abnormality detection signal; Further comprising: The primary side circuit includes: a demodulation circuit that generates a burst signal including burst-shaped pulses based on the modulated signal transmitted from the secondary side circuit via the signal transmission circuit; an output circuit that smoothes the burst signal and generates a transmission result signal corresponding to the abnormality detection signal; A semiconductor element driving device comprising:

[0106] (Appendix 8) A semiconductor element driving device according to any one of claims 1 to 7, the plurality of signals includes the first control signal, the second control signal, and the transition signal; The primary side circuit includes: an input priority determination circuit that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transition signal;

[0107] (Appendix 9) 9. The semiconductor element driving device according to claim 8, The secondary side circuit includes: Further comprising an abnormality detection circuit for detecting an abnormality of the semiconductor element; The input priority determination circuit includes: a semiconductor element driving device that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on a transmission result signal that corresponds to the judgment result of the ASC mode judgment circuit and the detection result of the abnormality detection circuit and is transmitted from the secondary side circuit via the signal transmission circuit, and based on the transition signal.

[0108] (Appendix 10) A semiconductor element driving device according to any one of claims 1 to 7, the plurality of signals includes the first control signal and the control transition signal; The secondary side circuit includes: The semiconductor element driving device further includes a waveform shaping circuit that generates the second transmission control signal, which is a square wave signal, based on a signal including a burst-like pulse corresponding to the control transition signal transmitted from the primary side circuit via the signal transmission circuit.

[0109] (Appendix 11) A semiconductor element driving device according to any one of claims 1 to 10, The semiconductor element driving device, wherein the isolation elements include transformers magnetically coupled to each other.

[0110] (Appendix 12) A semiconductor element driving device according to any one of claims 1 to 10, The semiconductor element driving device, wherein the isolation elements include capacitors capacitively coupled to each other.

[0111] (Appendix 13) A semiconductor element driving device according to any one of claims 1 to 10, The semiconductor element driving device, wherein the isolation elements include photocouplers optically coupled to each other. [Explanation of symbols]

[0112] 1 primary side circuit, 3 signal transmission circuit, 5 secondary side circuit, 11-15, 56 modulation circuit, 16, 51-55 demodulation circuit, 17 FO output circuit, 18 input priority determination circuit, 61, 62 pulse restoration circuit, 63 ASC mode determination circuit, 64 abnormality detection protection operation circuit, 65 logic circuit, 70 OR circuit, 72 waveform shaping circuit.

Claims

1. a primary side circuit to which a plurality of signals are input, the primary side circuit including a first control signal for controlling the operation of a semiconductor element in a normal mode, a second control signal for controlling the operation of the semiconductor element in an ASC mode, and a transition signal for transitioning from the normal mode to the ASC mode, or the primary side circuit including the first control signal and a control transition signal corresponding to the second control signal and the transition signal; A signal transmission circuit including an insulating element capable of transmitting a signal; a secondary side circuit that drives the semiconductor device based on a plurality of transmission signals corresponding to the plurality of signals transmitted from the primary side circuit via the signal transmission circuit; Equipped with The secondary side circuit includes: an ASC mode determination circuit that determines whether the normal mode or the ASC mode is being executed based on a transmission transition signal corresponding to the transition signal or the control transition signal among the plurality of transmission signals; a logic circuit that drives the semiconductor element based on a first transfer control signal corresponding to the first control signal among the plurality of transfer signals when the ASC mode determination circuit determines that the normal mode is being executed, and drives the semiconductor element based on a second transfer control signal corresponding to the second control signal or the control transition signal among the plurality of transfer signals when the ASC mode determination circuit determines that the ASC mode is being executed; A semiconductor element driving device comprising:

2. 2. The semiconductor element driving device according to claim 1, the transmitted transition signal includes a burst of pulses; The semiconductor element driving device, wherein the ASC mode determination circuit determines that the ASC mode is being executed when the pulses of the transmission transition signal are counted a predetermined number of times within a predetermined period.

3. 3. The semiconductor element driving device according to claim 1, The secondary side circuit includes: Further comprising an abnormality detection circuit for detecting an abnormality of the semiconductor element; The logic circuit includes: When the ASC mode determination circuit determines that the normal mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor device, an operation to protect the semiconductor device is performed regardless of the first transmission control signal. a semiconductor element driving device that drives the semiconductor element based on the second transmission control signal when the ASC mode determination circuit determines that the ASC mode is being executed and the abnormality detection circuit detects an abnormality in the semiconductor element.

4. 3. The semiconductor element driving device according to claim 1, The primary side circuit includes: a modulation circuit for generating a modulation signal based on rising and falling edges of the first control signal, The secondary side circuit includes: The semiconductor element driving device further includes a demodulation circuit that generates an edge trigger signal used to generate the first transmission control signal based on the modulated signal transmitted from the primary side circuit via the signal transmission circuit.

5. 5. The semiconductor element driving device according to claim 4, The secondary side circuit includes: The semiconductor device driving device further includes a pulse restoration circuit that generates the first transfer control signal based on the edge trigger signal.

6. 3. The semiconductor element driving device according to claim 1, The secondary side circuit includes: The semiconductor device further includes an abnormality detection circuit that outputs an abnormality detection signal indicating a detection result of an abnormality in the semiconductor device, The primary side circuit includes: a terminal for outputting, to an outside, a transmission result signal corresponding to the abnormality detection signal transmitted from the secondary side circuit via the signal transmission circuit.

7. 3. The semiconductor element driving device according to claim 1, The secondary side circuit includes: an abnormality detection circuit that outputs an abnormality detection signal indicative of a detection result of an abnormality in the semiconductor element; a modulation circuit that generates a modulation signal including a burst-like pulse based on the abnormality detection signal; Further comprising: The primary side circuit includes: a demodulation circuit that generates a burst signal including burst-shaped pulses based on the modulated signal transmitted from the secondary side circuit via the signal transmission circuit; an output circuit that smoothes the burst signal and generates a transmission result signal corresponding to the abnormality detection signal; A semiconductor element driving device comprising:

8. 3. The semiconductor element driving device according to claim 1, the plurality of signals includes the first control signal, the second control signal, and the transition signal; The primary side circuit includes: an input priority determination circuit that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on the transition signal;

9. 9. The semiconductor element driving device according to claim 8, The secondary side circuit includes: Further comprising an abnormality detection circuit for detecting an abnormality of the semiconductor element; The input priority determination circuit includes: a semiconductor element driving device that selectively outputs the first control signal and the second control signal to the signal transmission circuit based on a transmission result signal that corresponds to the judgment result of the ASC mode judgment circuit and the detection result of the abnormality detection circuit and is transmitted from the secondary side circuit via the signal transmission circuit, and the transition signal.

10. 3. The semiconductor element driving device according to claim 1, the plurality of signals includes the first control signal and the control transition signal; The secondary side circuit includes: The semiconductor element driving device further includes a waveform shaping circuit that generates the second transmission control signal, which is a square wave signal, based on a signal including a burst-like pulse corresponding to the control transition signal transmitted from the primary side circuit via the signal transmission circuit.

11. 3. The semiconductor element driving device according to claim 1, The semiconductor element driving device, wherein the isolation elements include transformers magnetically coupled to each other.

12. 3. The semiconductor element driving device according to claim 1, The semiconductor element driving device, wherein the isolation elements include capacitors capacitively coupled to each other.

13. 3. The semiconductor element driving device according to claim 1, The semiconductor element driving device, wherein the isolation elements include photocouplers optically coupled to each other.

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