Semiconductor integrated circuit and electronic apparatus

Abstract

To provide a semiconductor integrated circuit capable of lowering an operation limit voltage at which a reset signal can be output.SOLUTION: A semiconductor integrated circuit includes: a first detection circuit that operates using a first input voltage as a power supply voltage and asserts a first signal when a drop in the first input voltage is detected; a second detection circuit that operates using a second input voltage as a power supply voltage and asserts a second signal when a drop in the second input voltage is detected; and an output circuit that monitors the first signal and the second signal, and outputs a reset signal from the output terminal when the first signal or the second signal is asserted, wherein the first detection circuit makes the first signal undefined when the first input voltage drops to a first operation limit voltage or less, and the second detection circuit makes the second signal undefined when the second input voltage drops to a second operation limit voltage or less, and the first operation limit voltage is lower than the second operation limit voltage.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor integrated circuit and an electronic device. [Background technology]

[0002] 2. Description of the Related Art There is known a reset semiconductor integrated circuit that includes a voltage detection circuit and outputs a reset signal when a power supply voltage to be monitored falls below a predetermined level (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2022-129021 A Summary of the Invention [Problem to be solved by the invention]

[0004] When the power supply voltage of a semiconductor integrated circuit falls below its operating limit voltage, the reset signal output from the semiconductor integrated circuit may become unstable. In this case, the reset for the electronic circuit may malfunction before the power supply voltage of the electronic circuit receiving the reset signal falls below its operating limit voltage. For example, if the timing at which the reset for the electronic circuit malfunctions is too early with respect to the timing at which the power supply voltage of the electronic circuit falls below its operating limit voltage, the operating voltage range of the electronic circuit may be excessively limited.

[0005] The present disclosure provides a semiconductor integrated circuit capable of lowering the operating limit voltage at which a reset signal can be output, and an electronic device including the semiconductor integrated circuit. [Means for solving the problem]

[0006] The first aspect is a plurality of terminals including a first input terminal, a second input terminal, and an output terminal; a first detection circuit that operates using a first input voltage of the first input terminal as a power supply voltage and asserts a first signal when it detects a drop in the first input voltage; a second detection circuit that operates using a second input voltage of the second input terminal as a power supply voltage and asserts a second signal when it detects a drop in the second input voltage; an output circuit that monitors the first signal and the second signal, and outputs a reset signal from the output terminal when the first signal or the second signal is asserted; the first detection circuit asserts the first signal until the first input voltage drops from a first detection voltage to a first operating limit voltage, and makes the first signal indefinite when the first input voltage drops to or below the first operating limit voltage; the second detection circuit asserts the second signal until the second input voltage drops from a second detection voltage to a second operating limit voltage, and makes the second signal indefinite when the second input voltage drops to or below the second operating limit voltage; The first operating limit voltage is lower than the second operating limit voltage. It is a semiconductor integrated circuit.

[0007] A second aspect is the semiconductor integrated circuit of the first aspect, the first detection circuit includes a first transistor having a first threshold voltage, and the first transistor is an element that is turned off when a gate voltage of the first transistor becomes lower than the first threshold voltage when the first input voltage falls to or below the first operating limit voltage; the second detection circuit includes a second transistor having a second threshold voltage, and the second transistor is an element that is turned off when a gate voltage of the second transistor becomes lower than the second threshold voltage when the second input voltage falls to or below the second operating limit voltage; The first threshold voltage is lower than the second threshold voltage. It is a semiconductor integrated circuit.

[0008] A third aspect is the semiconductor integrated circuit of the second aspect, The first transistor has a lower breakdown voltage than the second transistor. It is a semiconductor integrated circuit.

[0009] A fourth aspect is a semiconductor integrated circuit according to any one of the first to third aspects, The output circuit includes: a logic circuit to which the first signal and the second signal are input; an output stage that outputs the reset signal in accordance with an output signal of the logic circuit; It is a semiconductor integrated circuit.

[0010] The fifth aspect is A semiconductor integrated circuit according to any one of the first to fourth aspects; a first power supply line connected to the first input terminal; a second power supply line connected to the second input terminal; an electronic circuit connected to the first power supply line and the output terminal; It is an electronic device.

[0011] A sixth aspect is the electronic device of the fifth aspect, a regulator that steps down the voltage of the second power supply line and outputs the stepped-down voltage to the first power supply line; It is an electronic device.

[0012] A seventh aspect is the electronic device of the sixth aspect, The second power supply line is connected to a battery power supply line of a vehicle. It is an electronic device. Effect of the Invention

[0013] According to the present disclosure, it is possible to lower the operating limit voltage at which a reset signal can be output. [Brief description of the drawings]

[0014] [Figure 1] 1 is a diagram illustrating an example of a configuration of an electronic device including a semiconductor integrated circuit according to a first embodiment. [Diagram 2] FIG. 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor integrated circuit according to a comparative example. [Diagram 3] 1 is a diagram showing an example of the relationship between a gate voltage VG and a drain current IDS. [Figure 4] FIG. 11 is a diagram for explaining the respective operating limit voltages of the comparative example and the example. [Diagram 5] 4 is a timing chart showing an example of the operation of the semiconductor integrated circuit according to the first embodiment. [Figure 6] FIG. 4 is a diagram illustrating an example of a configuration of a first detection circuit. [Figure 7] FIG. 4 is a diagram illustrating an example of a configuration of a second detection circuit. [Figure 8] FIG. 11 is a diagram illustrating an example of a configuration of an electronic device including a semiconductor integrated circuit according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0016] Fig. 1 is a diagram showing an example of the configuration of an electronic device including a semiconductor integrated circuit according to the first embodiment. An electronic device 201 shown in Fig. 1 includes a reset IC 101. The reset IC 101 is an example of the semiconductor integrated circuit according to the first embodiment. The reset IC (Integrated Circuit) is also called a voltage detector.

[0017] The electronic device 201 is a device for a vehicle, and is mounted on the vehicle for use. Specific examples of the electronic device 201 include a car navigation device, a drive recorder, an in-vehicle device for an ETC (Electronic Toll Collection system), a USB (Universal Serial Bus) connector, a camera, a radar, a communication device, an ECU (Electronic Control Unit), etc. However, the electronic device 201 is not limited to these.

[0018] The electronic device 201 is powered by an on-board power supply (not shown) connected to a battery power supply line 63 mounted on a vehicle. The electronic device 201 operates on DC power supplied from the on-board power supply (not shown) via the battery power supply line 63. The on-board power supply is, for example, a 12-volt battery. The battery power supply line 63 is, for example, a wire harness for the battery power supply.

[0019] The electronic device 201 includes a terminal BAT, a regulator 60, a first power supply line 67, a second power supply line 61, an electronic circuit 70, and a reset IC101.

[0020] The terminal BAT is a battery power terminal connected to a battery power line 63 of the vehicle. The battery power line 63 is connected to a second power line 61 of the electronic device 201 via the terminal BAT. DC power supplied from the battery power line 63 is input to the second power line 61 of the electronic device 201 via the terminal BAT. The DC power input from the terminal BAT is input to an input terminal of the regulator 60 and a second input terminal VS2 of the reset IC 101 via the second power line 61. The second power line 61 is, for example, a power supply pattern formed on a board built into the electronic device 201 and on which the reset IC 101 is mounted.

[0021] The regulator 60 is a power supply circuit that steps down the DC voltage of the second power supply line 61 to a constant power supply voltage Vdd and outputs it to the first power supply line 67. The regulator 60 steps down a DC voltage of, for example, 12 volts to generate a power supply voltage Vdd of 3.3 volts. A specific example of the regulator 60 is a linear regulator such as an LDO (Low Drop Out) regulator. The power supply voltage Vdd generated by the regulator 60 is supplied to a power supply terminal VDD of the reset IC 101 and a power supply terminal of the electronic circuit 70 via the first power supply line 67. The first power supply line 67 is, for example, a power supply pattern formed on a board built into the electronic device 201 and on which the reset IC 101 is mounted.

[0022] The electronic circuit 70 operates on a power supply voltage Vdd, and is activated by a reset signal S1 supplied from the reset IC 101. The activation of the electronic circuit 70 activates the electronic device 201. The electronic circuit 70 controls the operation of the electronic device 201. Specific examples of the electronic circuit 70 include a processor such as a central processing unit (CPU), a microcomputer, a system-on-chip (SoC), and a large-scale semiconductor integrated circuit (LSI).

[0023] The reset IC 101 has a function of monitoring the voltages of the first power supply line 67 and the second power supply line 61. The reset IC 101 monitors the voltages of the first power supply line 67 and the second power supply line 61, and outputs a reset signal S1 from an output terminal OUT to the electronic circuit 70 based on the monitoring results.

[0024] The reset IC 101 includes a first input terminal VS1 (power supply terminal VDD), a ground terminal GND, a second input terminal VS2, an output terminal OUT, a first detection circuit 10, a second detection circuit 20, and an output circuit 40. The reset IC 101 may include a release delay terminal CD.

[0025] The first input terminal VS1 (power supply terminal VDD) is connected to the first power supply line 67, and receives the power supply voltage Vdd of the first power supply line 67. The ground terminal GND is connected to a reference potential such as ground potential. The reset IC 101 operates based on the potential of the ground terminal GND, and is operated by the power supply voltage Vdd applied between the power supply terminal VDD and the ground terminal GND.

[0026] The second input terminal VS2 is connected to the second power supply line 61, and receives the power supply voltage of the second power supply line 61. The output terminal OUT is connected to the reset terminal of the electronic circuit 70, and outputs the reset signal S1 generated by the reset IC 101. The release delay terminal CD is connected to a capacitor 71 for generating a delay time for the reset signal S1.

[0027] The first detection circuit 10 is a voltage detection circuit connected to a first input terminal VS1, and operates using a first input voltage Vs1, which is the voltage of the first input terminal VS1, as a power supply voltage (operating voltage). The first input voltage Vs1 corresponds to a power supply voltage Vdd applied between a power supply terminal VDD and a ground terminal GND.

[0028] The first detection circuit 10 detects a voltage drop at the first input terminal VS1 (more specifically, an excessively low first input voltage Vs1). When the first detection circuit 10 detects a voltage drop at the first input terminal VS1 (a drop in the first input voltage Vs1), it asserts the first signal V1. For example, when the first detection circuit 10 detects a state in which the first input voltage Vs1 falls below a predetermined first detection voltage VTHD1, it asserts the first signal V1. On the other hand, when the first detection circuit 10 detects a state in which the first input voltage Vs1 exceeds a predetermined first release voltage VTHU1, it negates the first signal V1.

[0029] There is hysteresis between the first release voltage VTHU1 and the first detection voltage VTHD1. The first release voltage VTHU1 is a threshold value that is set to a voltage value higher than the first detection voltage VTHD1.

[0030] The second detection circuit 20 is a voltage detection circuit connected to the second input terminal VS2, and operates using the second input voltage Vs2, which is the voltage of the second input terminal VS2, as a power supply voltage (operating voltage). The second input voltage Vs2 corresponds to the power supply voltage applied between the second input terminal VS2 and the ground terminal GND.

[0031] The second detection circuit 20 detects a voltage drop at the second input terminal VS2 (more specifically, an excessively low second input voltage Vs2). When the second detection circuit 20 detects a voltage drop at the second input terminal VS2 (a drop in the second input voltage Vs2), it asserts the second signal V2. For example, when the second detection circuit 20 detects a state in which the second input voltage Vs2 falls below a predetermined second detection voltage VTHD2, it asserts the second signal V2. On the other hand, when the second detection circuit 20 detects a state in which the second input voltage Vs2 exceeds a predetermined second release voltage VTHU2, it negates the second signal V2.

[0032] There is hysteresis between the second release voltage VTHU2 and the second detection voltage VTHD2. The second release voltage VTHU2 is a threshold value that is set to a voltage value higher than the second detection voltage VTHD2.

[0033] The output circuit 40 monitors the first signal V1 and the second signal V2, and outputs a reset signal S1 from the output terminal OUT when the first signal V1 or the second signal V2 is asserted. In detail, the output circuit 40 outputs the reset signal S1 from the output terminal OUT when the first detection circuit 10 detects that the first input voltage Vs1 is lower than the first detection voltage VTHD1 or when the second detection circuit 20 detects that the second input voltage Vs2 is lower than the second detection voltage VTHD2.

[0034] The output circuit 40 monitors the first signal V1 and the second signal V2, and stops outputting the reset signal S1 from the output terminal OUT when the first signal V1 and the second signal V2 are negated. In detail, the output circuit 40 stops outputting the reset signal S1 from the output terminal OUT when the first detection circuit 10 detects that the first input voltage Vs1 is higher than the first release voltage VTHU1 and when the second detection circuit 20 detects that the second input voltage Vs2 is higher than the second release voltage VTHU2.

[0035] The output circuit 40 includes, for example, a logic circuit 41 to which a first signal V1 and a second signal V2 are input, and an output stage 42 that outputs a reset signal S1 in accordance with an output signal G1 of the logic circuit 41. The logic circuit 41 operates using a first input voltage Vs1, which corresponds to a power supply voltage Vdd applied between a power supply terminal VDD and a ground terminal GND, as a power supply voltage (operating voltage).

[0036] The logic circuit 41 has, for example, a NAND gate 45 to which the first signal V1 and the second signal V2 are input. The logic circuit 41 monitors the first signal V1 and the second signal V2 by the NAND gate 45, and when either the first signal V1 or the second signal V2 is asserted, outputs an output signal G1 to the output stage 42, which causes a low-level reset signal S1 to be output from the output terminal OUT. On the other hand, the logic circuit 41 monitors the first signal V1 and the second signal V2 by the NAND gate 45, and when both the first signal V1 and the second signal V2 are negated, stops the output of the output signal G1 to the output stage 42 and stops the output of the reset signal S1 from the output terminal OUT. As a result, the output of the reset signal S1 from the output terminal OUT is released, and a high-level signal is output from the output terminal OUT.

[0037] The output stage 42 has a transistor 43 that outputs the reset signal S1 in an open-drain output format, for example. The transistor 43 is, for example, a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) having a gate to which the output signal G1 is input, a source connected to a ground terminal GND, and a drain connected to an output terminal OUT. The output terminal OUT is pulled up and connected to a first power supply line 67 via an external resistor element 65. By externally connecting the resistor element 65 to the reset IC 101, the high-level output voltage value of the output terminal OUT (the high-level voltage value of the reset signal S1) can be arbitrarily set by the potential of the first power supply line 67.

[0038] In this way, the reset IC 101 monitors the voltage of the first power supply line 67 connected to the first input terminal VS1 by monitoring the first input voltage Vs1, and monitors the voltage of the second power supply line 61 connected to the second input terminal VS2 by monitoring the second input voltage Vs2. When the reset IC 101 detects that the first input voltage Vs1 has fallen below a predetermined first detection voltage VTHD1 or that the second input voltage Vs2 has fallen below a predetermined second detection voltage VTHD2, it outputs a signal of a level (for example, a low level) representing an abnormally low voltage state as a reset signal S1 from the output terminal OUT.

[0039] On the other hand, when the reset IC 101 detects that the first input voltage Vs1 is higher than the first release voltage VTHU1 and the second input voltage Vs2 is higher than the second release voltage VTHU2, it outputs a signal of a level indicating a normal voltage state (e.g., a high level) from the output terminal OUT (it cancels the output of the reset signal S1).

[0040] In this way, the reset IC 101 of the first embodiment has a voltage drop detection function for multiple channels (in this example, the first power supply line 67 and the second power supply line 61). Since the voltage drop detection function for multiple channels is stored in the single-chip reset IC 101, the component mounting area can be reduced compared to a configuration in which the voltage drop detection function for multiple channels is realized by multiple chips.

[0041] The first detection circuit 10 asserts the first signal V1 until the first input voltage Vs1 drops from the first detection voltage VTHD1 to the first operating limit voltage VL1, and makes the first signal V1 undefined when the first input voltage Vs1 drops below the first operating limit voltage VL1. The first operating limit voltage VL1 is the operating lower limit voltage at which the first detection circuit 10 can maintain the assertion of the first signal V1. On the other hand, the second detection circuit 20 asserts the second signal V2 until the second input voltage Vs2 drops from the second detection voltage VTHD2 to the second operating limit voltage VL2, and makes the second signal V2 undefined when the second input voltage Vs2 drops below the second operating limit voltage VL2. The second operating limit voltage VL2 is the operating lower limit voltage at which the second detection circuit 20 can maintain the assertion of the second signal V2.

[0042] In the reset IC 101 of the first embodiment, the first detection circuit 10 and the second detection circuit 20 are formed so that the first operating limit voltage VL1 is lower than the second operating limit voltage VL2. In this case, when the second input voltage Vs2 drops to the second operating limit voltage VL2 or lower, the second signal V2 becomes unstable. On the other hand, even if the first input voltage Vs1 drops to the same voltage as the second operating limit voltage VL2 at which the second signal V2 becomes unstable, the first signal V1 does not become unstable but is maintained in an asserted state. By maintaining the assertion of the first signal V1, the output circuit 40 can maintain the output of the reset signal S1. Therefore, the operating limit voltage at which the reset signal S1 can be output can be lowered to the first operating limit voltage VL1.

[0043] Since the operating limit voltage at which the reset signal S1 can be outputted can be lowered to the first operating limit voltage VL1, the possibility of the reset for the electronic circuit 70 malfunctioning before the power supply voltage of the electronic circuit 70 drops below the operating limit voltage of the electronic circuit 70 can be reduced. In this case, for example, it becomes easy to adjust the timing at which the reset for the electronic circuit 70 malfunctions so that it is not too early with respect to the timing at which the power supply voltage of the electronic circuit 70 drops below the operating limit voltage of the electronic circuit 70. This reduces the possibility that the operating voltage range of the electronic circuit 70 is excessively limited. In addition, since the voltage range at which the assertion of the reset signal S1 can be maintained can be expanded downward, the reset IC 101 can be suitably employed as a reset IC for the electronic circuit 70 with a relatively low operating limit voltage.

[0044] Next, in order to explain the functions and effects of the semiconductor integrated circuit of the first embodiment in more detail, a semiconductor integrated circuit of a comparative embodiment will be described.

[0045] Fig. 2 is a diagram showing an example of the configuration of an electronic device including a semiconductor integrated circuit of a comparative example. The electronic device 202 shown in Fig. 2 includes a reset IC 100. The reset IC 100 monitors the voltage of the second power supply line 61, and outputs a reset signal S1 from an output terminal OUT to an electronic circuit 70 based on the monitoring result. The reset IC 100 shown in Fig. 2 differs from the reset IC 101 shown in Fig. 1 in that it does not include a first detection circuit 10.

[0046] The second detection circuit 20 shown in Fig. 2 has the same configuration and function as the second detection circuit 20 shown in Fig. 1. The second detection circuit 20 is a voltage detection circuit connected to the second input terminal VS2, and operates using the second input voltage Vs2, which is the voltage of the second input terminal VS2, as a power supply voltage (operating voltage). The second detection circuit 20 asserts the second signal V2 until the second input voltage Vs2 drops from the second detection voltage VTHD2 to the second operating limit voltage VL2, and makes the second signal V2 indefinite when the second input voltage Vs2 drops below the second operating limit voltage VL2.

[0047] 2 monitors the second signal V2, and outputs a reset signal S1 from an output terminal OUT when the second signal V2 is asserted. The output circuit 40 includes a logic circuit 41 to which the second signal V2 is input, and an output stage 42 that outputs the reset signal S1 in accordance with an output signal G1 of the logic circuit 41. The logic circuit 41 operates using a second input voltage Vs2, which corresponds to a power supply voltage applied between the second input terminal VS2 and the ground terminal GND, as a power supply voltage (operating voltage).

[0048] The logic circuit 41 has, for example, a negation gate 46 to which the second signal V2 is input. The logic circuit 41 monitors the second signal V2 by the negation gate 46, and when the second signal V2 is asserted, outputs an output signal G1 to the output stage 42, which causes a low-level reset signal S1 to be output from the output terminal OUT. On the other hand, the logic circuit 41 monitors the second signal V2 by the negation gate 46, and when the second signal V2 is negated, stops the output of the output signal G1 to the output stage 42 and stops the output of the reset signal S1 from the output terminal OUT. This cancels the output of the reset signal S1 from the output terminal OUT, and a high-level signal is output from the output terminal OUT.

[0049] In the comparative embodiment shown in Fig. 2, the second detection circuit 20 makes the second signal V2 indefinite when the second input voltage Vs2 drops to or below the second operating limit voltage VL2. Therefore, the operating limit voltage at which the reset signal S1 can be output can only be reduced to the second operating limit voltage VL2. In contrast, in the first embodiment shown in Fig. 1, as described above, the operating limit voltage at which the reset signal S1 can be output can be reduced to the first operating limit voltage VL1, which is lower than the second operating limit voltage VL2.

[0050] The battery power supply line 63 and the second power supply line 61 may become overvoltage due to an incorrect connection of a 24-volt battery for trucks, etc. For this reason, in a comparative embodiment shown in FIG. 2, the second detection circuit 20 and the logic circuit 41 to which the high voltage of the second power supply line 61 may be applied, and the transistor 43 driven by the logic circuit 41 are formed to have a relatively high withstand voltage. For example, as shown in FIG. 3, they are formed using a high-withstand voltage NMOS transistor whose threshold voltage is higher than that of a standard-withstand voltage NMOS transistor. The NMOS transistor means an N-channel type MOSFET.

[0051] The threshold voltage of the high-voltage NMOS transistor is higher than that of the standard-voltage NMOS transistor. Therefore, when the gate voltage decreases with a decrease in the voltage of the second power supply line 61 (the second input voltage Vs2), the high-voltage NMOS transistor cannot maintain the on-state at a relatively high gate voltage value. As a result, as shown in the upper part of FIG. 4, when the second input voltage Vs2 is a relatively high voltage value, the reset signal S1 becomes unstable.

[0052] 1, the second detection circuit 20 to which the high voltage of the second power supply line 61 may be applied is formed to have a relatively high withstand voltage. On the other hand, the first detection circuit 10 and logic circuit 41 to which the low voltage of the first power supply line 67 is applied, and the transistor 43 driven by the logic circuit 41 are formed to have a relatively low withstand voltage. For example, as shown in FIG. 3, they are formed using standard withstand voltage NMOS transistors whose threshold voltage is lower than that of high withstand voltage NMOS transistors.

[0053] The threshold voltage of the standard voltage NMOS transistor is lower than the threshold voltage of the high voltage NMOS transistor. Therefore, even if the first input voltage Vs1 drops with a drop in the voltage of the second power supply line 61 (second input voltage Vs2) and the gate voltage drops with the drop in the first input voltage Vs1, the standard voltage NMOS transistor can maintain the on state up to a relatively low gate voltage value. As a result, as shown in the lower part of FIG. 4, the operating limit voltage at which the reset signal S1 can be output can be lowered compared to the upper part of FIG. 4.

[0054] Thus, in the first embodiment shown in FIG. 1, the first detection circuit 10 includes, for example, a first transistor T1 having a first threshold voltage Vth1. The first transistor T1 is, for example, the above-mentioned standard voltage NMOS transistor. The first transistor T1 is an element that is turned off when the gate voltage becomes lower than the first threshold voltage Vth1 when the first input voltage Vs1 drops to or below the first operating limit voltage VL1. On the other hand, the second detection circuit 20 includes, for example, a second transistor T2 having a second threshold voltage Vth2. The second transistor T2 is, for example, the above-mentioned high voltage NMOS transistor. The second transistor T2 is an element that is turned off when the gate voltage becomes lower than the second threshold voltage Vth2 when the second input voltage Vs2 drops to or below the second operating limit voltage VL2.

[0055] In the reset IC 101 of the first embodiment, the first detection circuit 10 and the second detection circuit 20 are formed so that the first threshold voltage Vth1 is lower than the second threshold voltage Vth2. For example, the first transistor T1 is formed to have a lower breakdown voltage than the second transistor T2, so that the first threshold voltage Vth1 is lower than the second threshold voltage Vth2. When the first threshold voltage Vth1 is lower than the second threshold voltage Vth2, even if the gate voltage of the first transistor T1 drops to the same voltage as the second threshold voltage Vth2 at which the second transistor T2 is turned off, the first transistor T1 is maintained in the on state without being turned off. By maintaining the on state of the first transistor T1, the assertion of the first signal V1 and the level of the output signal G1 are maintained, and the output circuit 40 can maintain the output of the reset signal S1. Therefore, the operating limit voltage at which the reset signal S1 can be output can be lowered to the first operating limit voltage VL1.

[0056] 5 is a timing chart showing an example of the operation of the semiconductor integrated circuit of the first embodiment. When the first input voltage Vs1 is equal to or lower than the first operating limit voltage VL1, the first signal V1 output from the first detection circuit 10 becomes indefinite (from time t1 to time t2). The first detection circuit 10 asserts the first signal V1 until the first input voltage Vs1 rises from the first operating limit voltage VL1 to the first release voltage VTHU1 (from time t2 to time t5). When the first input voltage Vs1 rises and becomes higher than the first release voltage VTHU1, the first detection circuit 10 switches the first signal V1 from assert to negate (time t5). In this example, the first signal V1 switches from a low level to a high level.

[0057] When the first input voltage Vs1 drops and becomes lower than the first detection voltage VTHD1, the first detection circuit 10 switches the first signal V1 from negated to asserted (time t9). In this example, the first signal V1 switches from high level to low level. The first detection circuit 10 asserts the first signal V1 until the first input voltage Vs1 drops from the first detection voltage VTHD1 to the first operating limit voltage VL1 (time t9 to time t11). When the first input voltage Vs1 is equal to or lower than the first operating limit voltage VL1, the first signal V1 output from the first detection circuit 10 becomes indefinite (after time t11).

[0058] On the other hand, when the second input voltage Vs2 is equal to or lower than the second operating limit voltage VL2, the second signal V2 output from the second detection circuit 20 becomes indefinite (time t1 to time t3). The second detection circuit 20 asserts the second signal V2 until the second input voltage Vs2 rises from the second operating limit voltage VL2 to the second release voltage VTHU2 (time t3 to time t4). When the second input voltage Vs2 rises and becomes higher than the second release voltage VTHU2, the second detection circuit 20 switches the second signal V2 from assert to negate (time t4). In this example, the second signal V2 switches from a low level to a high level.

[0059] When the second input voltage Vs2 drops and becomes lower than the second detection voltage VTHD2, the second detection circuit 20 switches the second signal V2 from negated to asserted (times t6 and t8). In this example, the second signal V2 switches from high level to low level. The second detection circuit 20 asserts the second signal V2 until the second input voltage Vs2 drops from the second detection voltage VTHD2 to the second operating limit voltage VL2 (times t8 to t10). When the second input voltage Vs2 is equal to or lower than the second operating limit voltage VL2, the second signal V2 output from the second detection circuit 20 becomes indefinite (after time t10).

[0060] As a result, when the first signal V1 or the second signal V2 is asserted, the reset IC 101 outputs a low-level reset signal S1 from the output terminal OUT. On the other hand, when the first signal V1 and the second signal V2 are negated, the reset IC 101 outputs a high-level reset signal S1 from the output terminal OUT. During the period from time t6 to time t7, the second signal V2 is asserted, but since the output terminal OUT is pulled up to the first power supply line 67 by the resistor element 65, the output of the high-level reset signal S1 is maintained. The reset IC 101 sets the reset signal S1 to indeterminate when the first input voltage Vs1 is equal to or lower than the first operating limit voltage VL1 which is lower than the second operating limit voltage VL2. Thereby, the operating limit voltage at which the reset signal S1 can be output can be lowered to the first operating limit voltage VL1.

[0061] FIG. 6 is a diagram showing a configuration example of the first detection circuit. The first detection circuit 10 monitors the first input voltage Vs1. When a voltage drop state of the first input voltage Vs1 is detected, the first detection circuit 10 asserts the first signal V1, and in this case, outputs a low-level first signal V1. On the other hand, when a voltage drop state of the first input voltage Vs1 is not detected, the first detection circuit 10 negates the first signal V1, and in this case, outputs a high-level first signal V1.

[0062] The first detection circuit 10 includes a resistive voltage dividing circuit 18 (resistors 11, 12, 13) and a first voltage detection circuit 1. The first voltage detection circuit 1 includes a diode 68, a comparator 17, a transistor 14, a reference voltage generation circuit 19 (constant current source 15 and reference voltage source 16), a transistor 51, a resistor 52, a Schmitt trigger 53, and a transistor 54.

[0063] The diode 68 has its anode connected to the ground terminal GND and its cathode connected to the first input terminal VS1. The diode 68 clamps the negative first input voltage Vs1 by the forward voltage of the diode 68, thereby protecting the first detection circuit 10 from the input of the negative first input voltage Vs1. The diode 68 is, for example, an electrostatic protection element.

[0064] The resistive voltage divider circuit 18 is a monitoring circuit that monitors the first input voltage Vs1. The resistive voltage divider circuit 18 is a series circuit of resistors 11, 12, and 13, and is connected between the ground terminal GND and the first input terminal VS1. The resistive voltage divider circuit 18 outputs a detection voltage Vs11 obtained by dividing the first input voltage Vs1 from the connection point between the resistors 11 and 12. In other words, the detection voltage Vs11 has a value corresponding to the first input voltage Vs1.

[0065] When the output voltage V11 of the comparator 17 is at a low level, the transistor 14 is off, and therefore the resistive voltage divider circuit 18 outputs a detection voltage Vs11 obtained by dividing the first input voltage Vs1 using the resistor 11 and the resistors 12 and 13. When the output voltage V11 of the comparator 17 is at a high level, the transistor 14 is on, and therefore the resistive voltage divider circuit 18 outputs a detection voltage Vs11 obtained by dividing the first input voltage Vs1 using the resistors 11 and 12. This allows the above-mentioned hysteresis (=first release voltage VTHU1-first detection voltage VTHD1) to be imparted to the comparison of magnitude between the detection voltage Vs11 generated by the resistive voltage divider circuit 18 and the reference voltage VREF generated by the reference voltage generation circuit 19.

[0066] The comparator 17 compares the detected voltage Vs11 with the reference voltage VREF and outputs an output voltage V11 according to the comparison result. The reference voltage VREF is a constant voltage value generated by stepping down the power supply voltage Vdd by the reference voltage generation circuit 19. The reference voltage VREF is input to the non-inverting input terminal of the comparator 17, and the detected voltage Vs11 is input to the inverting input terminal of the comparator 17. When the detected voltage Vs11 is lower than the reference voltage VREF, the comparator 17 outputs a high-level output voltage V11, and when the detected voltage Vs11 is higher than the reference voltage VREF, the comparator 17 outputs a low-level output voltage V11.

[0067] The reference voltage generating circuit 19 generates a constant reference voltage VREF lower than the power supply voltage Vdd, for example, by passing a constant current from a constant current source 15 to a reference voltage source 16. The constant current source 15 is, for example, a depletion type MOSFET whose drain is connected to the power supply voltage Vdd and whose gate and source are shorted. The reference voltage source 16 is, for example, a diode-connected depletion type MOSFET.

[0068] Therefore, when the output voltage V11 is at a high level, the first voltage detection circuit 1 determines that a voltage drop state of the first input voltage Vs1 has been detected, and turns on the transistor 51. When the transistor 51 is turned on, the logic signal V12 becomes a low level. The Schmitt trigger 53 causes the logic signal V13 to become a high level. The high level logic signal V13 turns on the transistor 54, and therefore the first signal V1 is output at a low level (the first signal V1 is asserted).

[0069] On the other hand, when the output voltage V11 is at a low level, the first voltage detection circuit 1 determines that the first input voltage Vs1 is normal and turns off the transistor 51. When the transistor 51 is turned off, the logic signal V12 becomes a high level. The Schmitt trigger 53 causes the logic signal V13 to become a low level. The low-level logic signal V13 turns off the transistor 54, so that a high-level first signal V1 is output by a pull-up resistor (not shown) (the first signal V1 is negated).

[0070] For example, some or all of the constant current source 15, the reference voltage source 16, the comparator 17, the transistors 14, 51, 54, and the Schmitt trigger 53 are formed using the first transistor T1.

[0071] 7 is a diagram showing an example of the configuration of the second detection circuit. The second detection circuit 20 monitors the second input voltage Vs2. When a voltage drop state of the second input voltage Vs2 is detected, the second detection circuit 20 asserts the second signal V2, and in this case, outputs a low-level second signal V2. On the other hand, when a voltage drop state of the second input voltage Vs2 is not detected, the second detection circuit 20 negates the second signal V2, and in this case, outputs a high-level second signal V2.

[0072] The second detection circuit 20 has a resistive voltage divider circuit 28 (resistors 21, 22, 23) and a second voltage detection circuit 2. The second voltage detection circuit 2 has a diode 69, a comparator 27, a transistor 24, a reference voltage generation circuit 29 (constant current source 25 and reference voltage source 26), inverter circuits 55 and 56, and a transistor 57.

[0073] The diode 69 has an anode connected to the ground terminal GND and a cathode connected to the second input terminal VS2. The diode 69 clamps the negative second input voltage Vs2 by the forward voltage of the diode 69, and therefore protects the second detection circuit 20 from the input of the negative second input voltage Vs2. The diode 69 is, for example, an electrostatic protection element.

[0074] The resistive voltage divider circuit 28 is a monitoring circuit that monitors the second input voltage Vs2. The resistive voltage divider circuit 18 is a series circuit of a resistor 21, a resistor 22, and a resistor 23, and is connected between the ground terminal GND and the second input terminal VS2. The resistive voltage divider circuit 28 outputs a detection voltage Vs21 obtained by dividing the second input voltage Vs2 from the connection point between the resistor 21 and the resistor 22. In other words, the detection voltage Vs21 has a value corresponding to the second input voltage Vs2.

[0075] When the output voltage V21 of the comparator 27 is at a low level, the transistor 24 is off, and therefore the resistive voltage divider circuit 28 outputs the detection voltage Vs21 obtained by dividing the second input voltage Vs2 by the resistor 21 and the resistors 22 and 23. When the output voltage V21 of the comparator 27 is at a high level, the transistor 24 is on, and therefore the resistive voltage divider circuit 28 outputs the detection voltage Vs21 obtained by dividing the second input voltage Vs2 by the resistors 21 and 22. This allows the above-mentioned hysteresis (=second release voltage VTHU2-second detection voltage VTHD2) to be imparted to the comparison of magnitude between the detection voltage Vs21 generated by the resistive voltage divider circuit 28 and the reference voltage VREF generated by the reference voltage generation circuit 29.

[0076] The comparator 27 compares the detected voltage Vs21 with the reference voltage VREF and outputs an output voltage V21 according to the comparison result. The reference voltage VREF is a constant voltage value generated by stepping down the power supply voltage Vdd by the reference voltage generation circuit 29. The reference voltage VREF is input to the non-inverting input terminal of the comparator 27, and the detected voltage Vs21 is input to the inverting input terminal of the comparator 27. When the detected voltage Vs21 is lower than the reference voltage VREF, the comparator 27 outputs a high-level output voltage V21, and when the detected voltage Vs21 is higher than the reference voltage VREF, the comparator 27 outputs a low-level output voltage V21.

[0077] The reference voltage generating circuit 29 generates a constant reference voltage VREF lower than the power supply voltage Vdd, for example, by passing a constant current from a constant current source 25 to a reference voltage source 26. The constant current source 25 is formed, for example, of a depletion type MOSFET whose drain is connected to the power supply voltage Vdd and whose gate and source are shorted. The reference voltage source 26 is formed, for example, of a diode-connected depletion type MOSFET.

[0078] Therefore, when the output voltage V21 is at a high level, the second voltage detection circuit 2 determines that a voltage drop state of the second input voltage Vs2 has been detected, and sets the logic signal V22 to a high level by the inversion circuits 55 and 56, which invert the logic between the input and output signals. The high-level logic signal V22 turns on the transistor 57, so that a low-level second signal V2 is output (the second signal V2 is asserted).

[0079] On the other hand, when the output voltage V21 is at a low level, the second voltage detection circuit 2 determines that the second input voltage Vs2 is in a normal voltage state and sets the logic signal V22 to a low level via the inversion circuits 55 and 56. The low-level logic signal V22 turns off the transistor 57, so that a high-level second signal V2 is output by a pull-up resistor (not shown) (the second signal V2 is negated).

[0080] For example, some or all of the constant current source 25, the reference voltage source 26, the comparator 27, the transistors 24 and 57, and the inverting circuits 55 and 56 are formed using the second transistor T2.

[0081] FIG. 8 is a diagram showing an example of the configuration of an electronic device including a semiconductor integrated circuit according to the second embodiment. In the second embodiment, the description of the configuration, operation, or effect similar to that of the first embodiment will be omitted by incorporating the above description. An electronic device 202 shown in FIG. 8 includes a reset IC 102. The reset IC 102 is an example of the semiconductor integrated circuit according to the second embodiment. The reset IC 102 of the second embodiment differs from the reset IC 101 of the first embodiment in that the output stage 42 is a CMOS (Complementary Metal Oxide Semiconductor) output type. The output stage 42 operates on a power supply voltage Vdd applied between a first input terminal VS1 (power supply terminal VDD) and a ground terminal GND.

[0082] The output stage 42 has transistors 43 and 47 that output the reset signal S1 in a CMOS output format. The output stage 42 has an inverter circuit in which the transistors 43 and 47 are complementarily combined. By making the output stage 42 a CMOS output format, the resistive element 65 (see FIG. 1) can be eliminated, and the current consumption that flows through the transistor 43 via the resistive element 65 when the transistor 43 is in an on state can be reduced.

[0083] As described above, the embodiment has been described, but the above embodiment is presented as an example, and the present invention is not limited to the above embodiment. The above embodiment can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the scope of the invention and its equivalents described in the claims.

[0084] For example, the semiconductor integrated circuit to which the contents of the present disclosure can be applied is not limited to a reset IC, but may be another semiconductor integrated circuit such as a power supply IC.

[0085] The battery power line may be an ignition power line that transmits an ignition signal, or an accessory power line that transmits an accessory signal.

[0086] The electronic device is not limited to a device for a vehicle, but may be another electronic device for a purpose other than a vehicle.

[0087] The reset signal S1 is not limited to being low active, but may be high active. The output format of the output circuit 40 may be changed as appropriate. [Explanation of symbols]

[0088] 1 First voltage detection circuit 2 Second voltage detection circuit 10 First detection circuit 18 Resistor divider circuit 20 Second detection circuit 28 Resistor voltage divider circuit 30 Third detection circuit 40 Output circuit 41 Logic Circuits 42 Output stage 60 Regulator 61 Second Power Line 63 Battery power line 67 First Power Line 70 Electronic circuits 71 Capacitor 100, 101, 102 Semiconductor integrated circuits 200,201,202 Electronic equipment

Claims

1. a plurality of terminals including a first input terminal, a second input terminal, and an output terminal; a first detection circuit that operates using a first input voltage at the first input terminal as a power supply voltage and asserts a first signal when it detects a drop in the first input voltage; a second detection circuit that operates using a second input voltage at the second input terminal as a power supply voltage and asserts a second signal when it detects a drop in the second input voltage; an output circuit that monitors the first signal and the second signal, and outputs a reset signal from the output terminal when the first signal or the second signal is asserted; the first detection circuit asserts the first signal until the first input voltage drops from a first detection voltage to a first operating limit voltage, and makes the first signal indefinite when the first input voltage drops to or below the first operating limit voltage; the second detection circuit asserts the second signal until the second input voltage drops from a second detection voltage to a second operating limit voltage, and makes the second signal indefinite when the second input voltage drops to or below the second operating limit voltage; The first operating limit voltage is lower than the second operating limit voltage. Semiconductor integrated circuit.

2. the first detection circuit includes a first transistor having a first threshold voltage, the first transistor being an element that is turned off when a gate voltage of the first transistor becomes lower than the first threshold voltage when the first input voltage falls to or below the first operating limit voltage; the second detection circuit includes a second transistor having a second threshold voltage, and the second transistor is an element that is turned off when a gate voltage of the second transistor becomes lower than the second threshold voltage when the second input voltage falls to or below the second operating limit voltage, The first threshold voltage is lower than the second threshold voltage.

2. The semiconductor integrated circuit according to claim 1.

3. The first transistor has a lower breakdown voltage than the second transistor.

3. The semiconductor integrated circuit according to claim 2.

4. The output circuit includes: a logic circuit to which the first signal and the second signal are input; an output stage that outputs the reset signal in accordance with an output signal of the logic circuit; 2. The semiconductor integrated circuit according to claim 1.

5. A semiconductor integrated circuit according to any one of claims 1 to 4; a first power supply line connected to the first input terminal; a second power supply line connected to the second input terminal; an electronic circuit connected to the first power supply line and the output terminal; electronic equipment.

6. a regulator that steps down the voltage of the second power supply line and outputs the stepped-down voltage to the first power supply line; 6. The electronic device according to claim 5.

7. The second power supply line is connected to a battery power supply line of a vehicle.

7. The electronic device according to claim 6.

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