Semiconductor device

Abstract

To provide a semiconductor device capable of securing a withstand voltage between a transformer made of a first coil and a third coil and a transformer made of a second coil and a fourth coil.SOLUTION: A semiconductor device includes: a semiconductor substrate; an insulating film; a first coil, a second coil, a third coil, and a fourth coil; and a first guard ring and a second guard ring. The first coil and the second coil are formed on the semiconductor substrate. The third coil faces the first coil through the insulating film. The fourth coil faces the second coil through the insulating film. The first guard ring is formed to surround the third coil in plan view. The second guard ring is formed to surround the fourth coil in plan view. The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in plan view.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present disclosure relates to a semiconductor device. [Background technology]

[0002] For example, International Publication No. WO 2014 / 097425 (Patent Document 1) describes a semiconductor device. The semiconductor device described in Patent Document 1 has a transformer composed of a pair of coils facing each other with an insulating layer interposed therebetween. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2014 / 097425 Summary of the Invention [Problem to be solved by the invention]

[0004] When the transformer of the semiconductor device described in Patent Document 1 is used as a high-side transformer and a low-side transformer to configure a power conversion device such as a DC-DC converter (direct current-direct current converter), the dielectric strength voltage between the high-side transformer and the low-side transformer is insufficient. Other problems and new features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0005] The semiconductor device of the present disclosure includes a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, and a first guard ring and a second guard ring. The first coil and the second coil are formed on the semiconductor substrate. The third coil faces the first coil via the insulating film. The fourth coil faces the second coil via the insulating film. The first guard ring is formed to surround the third coil in a planar view. The second guard ring is formed to surround the fourth coil in a planar view. The first guard ring and the second guard ring are adjacent to each other while being spaced apart from each other in a planar view. Effect of the Invention

[0006] According to the semiconductor device of the present disclosure, it is possible to ensure a dielectric strength voltage between the transformer constituted by the first coil and the third coil and the transformer constituted by the second coil and the fourth coil. [Brief description of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram of a semiconductor device DEV1. [Diagram 2] 4 is an explanatory diagram showing an example of signal transmission from a control circuit CC to a drive circuit. FIG. [Diagram 3] FIG. 2 is a first plan view of the semiconductor chip CHP2. [Figure 4] FIG. 2 is a second plan view of the semiconductor chip CHP2. [Diagram 5] FIG. 13 is a third plan view of the semiconductor chip CHP2. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] FIG. 13 is a plan view of a semiconductor chip CHP2 according to a first modified example. [Figure 9] FIG. 11 is a plan view of a semiconductor chip CHP2 according to a second modified example. [Figure 10] 1A to 1C are manufacturing process diagrams of the semiconductor chip CHP2. [Figure 11] FIG. 11 is a cross-sectional view illustrating an ion implantation step S2. [Figure 12] FIG. 11 is a cross-sectional view illustrating a first insulating film forming step S3. [Figure 13] FIG. 11 is a cross-sectional view illustrating a first via plug forming step S4. [Figure 14] FIG. 11 is a cross-sectional view illustrating a first wiring layer forming step S5. [Figure 15] FIG. 11 is a cross-sectional view illustrating a second insulating film forming step S6. [Figure 16] FIG. 11 is a cross-sectional view illustrating a second via plug forming step S7. [Figure 17] FIG. 11 is a cross-sectional view illustrating a second wiring layer forming step S8. [Figure 18] FIG. 11 is a cross-sectional view illustrating a third insulating film forming step S9. [Figure 19] 11 is a cross-sectional view illustrating a third via plug forming step S10. FIG. [Figure 20] 11 is a cross-sectional view illustrating a third wiring layer forming step S11. FIG. [Figure 21] 11 is a cross-sectional view illustrating a fourth wiring layer forming step S12. FIG. [Figure 22] FIG. 2 is a first plan view of a semiconductor chip CHP2 in the semiconductor device DEV2. [Figure 23] FIG. 2 is a second plan view of the semiconductor chip CHP2 in the semiconductor device DEV2. [Figure 24] FIG. 13 is a third plan view of the semiconductor chip CHP2 in the semiconductor device DEV2. [Diagram 25] 23 is a cross-sectional view taken along line XXV-XXV in FIG. 22. [Figure 26] FIG. 2 is a plan view of a semiconductor chip CHP2 in the semiconductor device DEV3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] The details of the embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are designated by the same reference numerals, and redundant description will not be repeated.

[0009] (First embodiment) A description will be given of a semiconductor device according to a first embodiment. The semiconductor device according to the first embodiment is referred to as a semiconductor device DEV1.

[0010] (Configuration of semiconductor device DEV1) The configuration of the semiconductor device DEV1 will be described below.

[0011] <Schematic configuration of semiconductor device DEV1> The schematic configuration of the semiconductor device DEV1 will be described below.

[0012] Fig. 1 is a block diagram of the semiconductor device DEV1. As shown in Fig. 1, the semiconductor device DEV1 has a semiconductor chip CHP1, a semiconductor chip CHP2, a semiconductor chip CHP3, and a semiconductor chip CHP4. The semiconductor device DEV1 constitutes a DC-DC converter. The semiconductor device DEV1 may constitute an OBC (On-Board Charger).

[0013] The semiconductor chip CHP1 has a control circuit CC, a transmitting circuit TX1, and a transmitting circuit TX2, and the semiconductor chip CHP3 has a receiving circuit RX1. The semiconductor chip CHP4 has a receiving circuit RX2. The transmitting circuits TX1 and TX2 are electrically connected to the control circuit CC. The receiving circuits RX1 and RX2 are electrically connected to a drive circuit (not shown).

[0014] The semiconductor chip CHP2 has a transformer TR1, a transformer TR2, and lead-out wiring PL1 and lead-out wiring PL2. The transformer TR1 and the transformer TR2 are a high-side transformer and a low-side transformer, respectively.

[0015] The transformer TR1 has a transmitting coil CL1 and a receiving coil CL3. The transmitting coil CL1 has a coil CL11 and a coil CL12, and the receiving coil CL3 has a coil CL31 and a coil CL32. The transmitting coil CL1 and the receiving coil CL3 are electrically connected to a transmitting circuit TX1 and a receiving circuit RX1, respectively.

[0016] More specifically, one end of the coil CL11 is electrically connected to the transmission circuit TX1, the other end of the coil CL11 is electrically connected to one end of the coil CL12, and the other end of the coil CL12 is electrically connected to the transmission circuit TX1. One end of the coil CL31 is electrically connected to the reception circuit RX1, the other end of the coil CL31 is electrically connected to one end of the coil CL32 via the lead-out wiring PL1, and the other end of the coil CL32 is electrically connected to the reception circuit RX1.

[0017] The transformer TR2 has a transmitting coil CL2 and a receiving coil CL4. The transmitting coil CL2 has a coil CL21 and a coil CL22, and the receiving coil CL4 has a coil CL41 and a coil CL42. The transmitting coil CL2 and the receiving coil CL4 are electrically connected to the transmitting circuit TX2 and the receiving circuit RX2, respectively.

[0018] More specifically, one end of the coil CL21 is electrically connected to the transmission circuit TX2, the other end of the coil CL21 is electrically connected to one end of the coil CL22, and the other end of the coil CL22 is electrically connected to the transmission circuit TX2. One end of the coil CL41 is electrically connected to the reception circuit RX2, the other end of the coil CL41 is electrically connected to one end of the coil CL42 via the lead-out wiring PL2, and the other end of the coil CL42 is electrically connected to the reception circuit RX2.

[0019] In the semiconductor device DEV1, a signal is transmitted from the control circuit CC to the drive circuit by the transmitter circuit TX1, the transformer TR1, and the receiver circuit RX1. In the semiconductor device DEV1, a signal is also transmitted from the control circuit CC to the drive circuit by the transmitter circuit TX2, the transformer TR2, and the receiver circuit RX2.

[0020] FIG. 2 is an explanatory diagram showing an example of signal transmission from the control circuit CC to the drive circuit. As shown in FIG. 2, the control circuit CC inputs a signal SG1 to the transmission circuit TX1. The signal SG1 is a square wave. The transmission circuit TX1 modulates the signal SG1 to a signal SG2 and sends the signal SG2 to the transmission coil CL1. When the signal SG2 flows to the transmission coil CL1, a signal SG3 corresponding to the signal SG2 flows to the reception coil CL3 due to induced electromotive force. The reception circuit RX1 amplifies the signal SG3 and demodulates it to a signal SG4 (square wave), and outputs it to the drive circuit. In this way, a signal is transmitted from the control circuit CC to the drive circuit. Signal transmission using the transmission circuit TX2, the transmission coil CL2, and the reception coil CL4 is also performed in the same manner. In this way, in the semiconductor device DEV1, signal transmission between the transmission circuit TX1 and the reception circuit RX1 and signal transmission between the transmission circuit TX2 and the reception circuit RX2 are performed by a pulse communication method.

[0021] <Detailed configuration of the semiconductor chip CHP2> Fig. 3 is a first plan view of the semiconductor chip CHP2. Fig. 4 is a second plan view of the semiconductor chip CHP2. Fig. 5 is a third plan view of the semiconductor chip CHP2. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5. As shown in Figs. 3 to 7, the semiconductor chip CHP2 has a semiconductor substrate SUB.

[0022] The semiconductor substrate SUB has a first surface FS and a second surface SS. The second surface SS is the surface opposite to the first surface FS. The first surface FS and the second surface SS are end surfaces in the thickness direction of the semiconductor substrate SUB. The constituent material of the semiconductor substrate SUB is, for example, single crystal silicon. The semiconductor substrate SUB has an impurity-implanted region IR. The impurity-implanted region IR is formed in the first surface FS. The conductivity type of the semiconductor substrate SUB is, for example, p-type. The dopant concentration in the impurity-implanted region IR is higher than the dopant concentration outside the impurity-implanted region IR.

[0023] The semiconductor chip CHP2 further has an insulating film IF1. The insulating film IF1 is disposed on the semiconductor substrate SUB. More specifically, the insulating film IF1 is disposed on the first surface FS. The insulating film IF1 is made of, for example, silicon oxide.

[0024] The semiconductor chip CHP2 further includes a wiring layer WL1. The wiring layer WL1 is disposed on the insulating film IF1. The wiring layer WL1 includes a wiring WL1a, a wiring WL1b, a wiring WL1c, and a wiring WL1d. The wiring WL1a, the wiring WL1b, the wiring WL1c, and the wiring WL1d extend along a first direction DR1 in a plan view. The wiring layer WL1 is made of, for example, a conductive material mainly composed of aluminum.

[0025] The wiring layer WL1 further has a wiring WL1e. Although not shown, the wiring WL1e overlaps with a guard ring GR3 described below in a plan view. The semiconductor chip CHP2 further has a via plug VP1. The via plug VP1 is embedded in a via hole formed in the insulating film IF1, and connects the wiring WL1e and the semiconductor substrate SUB (impurity implanted region IR). The constituent material of the via plug VP1 is, for example, a conductive material mainly composed of tungsten.

[0026] The semiconductor chip CHP2 further includes an insulating film IF2. The insulating film IF2 is disposed on the insulating film IF1 so as to cover the wiring layer WL1. The insulating film IF2 is made of, for example, silicon oxide.

[0027] The semiconductor chip CHP2 further includes a wiring layer WL2. The wiring layer WL2 is disposed on the insulating film IF2. The wiring layer WL2 includes a transmitting coil CL1 (coil CL11 and coil CL12), a transmitting coil CL2 (coil CL21 and coil CL22), and wiring WL2a, wiring WL2b, wiring WL2c, and wiring WL2d. The wiring layer WL2 is made of a conductive material mainly composed of aluminum, for example.

[0028] The coil CL11 and the coil CL12 are adjacent to each other in the first direction DR1. The coil CL11 and the coil CL12 are spirally wound in a plan view. More specifically, in the example shown in FIG. 4, the coil CL11 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and the coil CL12 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. The coil CL11 and the coil CL12 are electrically connected to each other in series. More specifically, the outermost end of the coil CL11 is connected to the outermost end of the coil CL12.

[0029] The coil CL21 and the coil CL22 are adjacent to each other in the first direction DR1. The coil CL21 and the coil CL22 are spirally wound in a plan view. More specifically, in the example shown in FIG. 4, the coil CL21 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and the coil CL22 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. The coil CL21 and the coil CL22 are electrically connected to each other in series. More specifically, the outermost end of the coil CL21 is connected to the outermost end of the coil CL22.

[0030] The transmitter coil CL1 and the transmitter coil CL2 are adjacent to each other while being spaced apart from each other in the first direction DR1. More specifically, the coil CL12 is adjacent to the coil CL21 in the first direction DR1.

[0031] The wiring WL2a, wiring WL2b, wiring WL2c, and wiring WL2d extend along a second direction DR2 in a plan view. The second direction DR2 is a direction perpendicular to the first direction DR1 in a plan view. One end of the wiring WL2a and one end of the wiring WL2b are adjacent to the coils CL11 and CL12, respectively. One end of the wiring WL2c and one end of the wiring WL2d are adjacent to the coils CL21 and CL22, respectively.

[0032] The wiring layer WL2 further has a wiring WL2e. In a plan view, the wiring WL2e surrounds the transmitting coil CL1 and the transmitting coil CL2, and overlaps with a guard ring GR3 described later. However, the wiring WL2e does not go completely around, and is separated at a part thereof. The semiconductor chip CHP2 further has a via plug VP2. The via plug VP2 is embedded in a via hole formed in the insulating film IF2, and connects the wiring WL1e and the wiring WL2e. The constituent material of the via plug VP2 is, for example, a conductive material mainly composed of tungsten.

[0033] The wiring WL1a is connected to the wiring WL2a and the coil CL11 by a via plug VP2. The wiring WL1b is connected to the wiring WL2b and the coil CL12 by a via plug VP2. The wiring WL1c is connected to the wiring WL2c and the coil CL21 by a via plug VP2. The wiring WL1d is connected to the wiring WL2d and the coil CL22 by a via plug VP2. The material of the via plug VP2 is, for example, a conductive material mainly composed of tungsten.

[0034] The semiconductor chip CHP2 further includes a plurality of insulating films IF3. The plurality of insulating films IF3 are stacked. The insulating film IF3 in the lowest layer is disposed on the insulating film IF2 so as to cover the wiring layer WL2. The insulating film IF3 is made of, for example, silicon oxide.

[0035] The semiconductor chip CHP2 further includes a wiring layer WL3. The wiring layer WL3 includes a receiving coil CL3 (coil CL31 and coil CL32), a receiving coil CL4 (coil CL41 and coil CL42), a drawing wiring PL1, a drawing wiring PL2, a guard ring GR1, a guard ring GR2, and a guard ring GR3. The wiring layer WL3 is made of a conductive material mainly composed of aluminum, for example.

[0036] The coil CL31 and the coil CL32 are adjacent to each other in the first direction DR1. The coil CL31 and the coil CL32 are spirally wound in a plan view. More specifically, in the example shown in FIG. 5, the coil CL31 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and the coil CL32 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. The coil CL31 and the coil CL32 are electrically connected in series to each other via the lead-out wiring PL1. More specifically, the outermost end of the coil CL31 is connected to the outermost end of the coil CL32.

[0037] The coils CL31 and CL32 face the coils CL11 and CL12, respectively, with insulating films (a plurality of insulating films IF3) interposed therebetween, whereby the coils CL31 and CL32 are magnetically coupled to the coils CL11 and CL12, respectively.

[0038] The coil CL41 and the coil CL42 are adjacent to each other in the first direction DR1. The coil CL41 and the coil CL42 are spirally wound in a plan view. More specifically, in the example shown in FIG. 5, the coil CL41 is wound counterclockwise from the innermost circumference to the outermost circumference in a plan view, and the coil CL42 is wound clockwise from the outermost circumference to the innermost circumference in a plan view. The coil CL41 and the coil CL42 are electrically connected in series to each other via the lead-out wiring PL2. More specifically, the outermost end of the coil CL41 is connected to the outermost end of the coil CL42.

[0039] The coils CL41 and CL42 face the coils CL21 and CL22, respectively, with insulating films (multiple insulating films IF3) interposed therebetween. As a result, the coils CL41 and CL42 are magnetically coupled to the coils CL21 and CL22, respectively. As described above, the coils CL12 and CL21 are spaced apart in the first direction DR1, and therefore the coils CL32 and CL41 are also spaced apart in the first direction DR1.

[0040] The guard ring GR1 surrounds the receiving coil CL3 in a planar view. The guard ring GR2 surrounds the receiving coil CL4 in a planar view. The guard ring GR2 is adjacent to the guard ring GR1 in the first direction DR1 while being spaced apart from the guard ring GR1. The guard ring GR3 surrounds the guard rings GR1 and GR2 in a planar view. A first potential is applied to the guard ring GR1. A second potential is applied to the guard ring GR2. A third potential is applied to the guard ring GR3. The first potential and the second potential are higher than the third potential. The first potential is higher than the second potential. The guard rings GR1, GR2, and GR3 are, for example, elliptical in a planar view.

[0041] The shortest distance between the guard rings GR1 and GR2 in a planar view is defined as distance DIS1. The shortest distance between the guard rings GR1 and GR3 in a planar view is defined as distance DIS2. The shortest distance between the guard rings GR2 and GR3 in a planar view is defined as distance DIS3. As described above, the guard rings GR1 and GR2 are spaced apart from each other, so distance DIS1 is greater than 0. It is preferable that distance DIS1 is equal to or smaller than distance DIS2 and distance DIS3. That is, it is preferable that the relationship 0<distance DIS1≦distance DIS2 and 0<distance DIS1≦distance DIS3 is satisfied among distances DIS1, DIS2, and DIS3. It is preferable that distance DIS1 is equal to or larger than 15 μm. It is preferable that distance DIS2 and distance DIS3 are equal to or larger than 150 μm.

[0042] The wiring layer WL3 further includes pads PD1, PD2, PD3, PD4, PD5, and PD6. The pads PD1 and PD2 are connected to the innermost ends of the coils CL31 and CL32, respectively. The pads PD3 and PD4 are connected to the innermost ends of the coils CL41 and CL42, respectively. The pads PD5 and PD6 are connected to the lead-out wiring PL1 and PL2, respectively. The pad PD5 is also connected to the guard ring GR1, and the pad PD6 is also connected to the guard ring GR2.

[0043] The wiring layer WL3 further includes a pad PD7, a pad PD8, a pad PD9, and a pad PD10. The pads PD7, PD8, PD9, and PD10 are disposed outside the guard ring GR3 in a plan view. The pads PD7 and PD8 overlap the other end of the wiring WL2a and the other end of the wiring WL2b, respectively, in a plan view. The pads PD9 and PD10 overlap the other end of the wiring WL2c and the other end of the wiring WL2c, respectively, in a plan view.

[0044] The semiconductor chip CHP2 further has a plurality of wiring layers WL4. Each of the plurality of wiring layers WL4 is disposed on one insulating film IF3 and is covered by another insulating film IF3 disposed on the one insulating film IF3. However, the lowermost wiring layer WL4 is disposed on the insulating film IF2 and is covered by the lowermost insulating film IF3. Each of the plurality of wiring layers WL4 has a wiring WL4a. Although not shown, the wiring WL4a overlaps with the guard ring GR3 in a plan view.

[0045] The semiconductor chip CHP2 further has a plurality of via plugs VP3. Each of the plurality of via plugs VP3 is embedded in a via hole formed in each of the plurality of insulating films IF3. The via plug VP3 connects two overlapping wirings WL4a with the insulating film IF3 interposed therebetween, connects the wiring WL4a in the uppermost layer to the guard ring GR3, and connects the wiring WL4a in the lowermost layer to the wiring WL2e.

[0046] Although not shown, the pads PD7, PD8, PD9, and PD10 are electrically connected to the other end of the wiring WL2a, the other end of the wiring WL2b, the other end of the wiring WL2c, and the other end of the wiring WL2d, respectively, by the via plug VP3 and a plurality of wiring layers WL4. Therefore, the pads PD7, PD8, PD9, and PD10 are electrically connected to the coils CL11, CL12, CL21, and CL22, respectively.

[0047] The semiconductor chip CHP2 further has a passivation film PF. The passivation film PF is disposed on the uppermost insulating film IF3 so as to cover the wiring layer WL3. From the openings of the passivation film PF, the pads PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, and PD10 are exposed. The material constituting the passivation film PF is, for example, silicon nitride. The pads PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, and PD10 are used as bonding pads for external connection.

[0048] <Modification of semiconductor chip CHP2> Modified examples of the semiconductor chip CHP2 will be described below.

[0049] FIG. 8 is a plan view of a semiconductor chip CHP2 according to a first modified example. As shown in FIG. 8, each of the guard rings GR1 and GR2 may have a straight line portion GRa. The straight line portion GRa extends along the second direction DR2 in a plan view. The second direction DR2 is a direction perpendicular to the first direction DR1 in a plan view. The straight line portion GRa of the guard ring GR1 and the straight line portion GRa of the guard ring GR2 face each other in the first direction DR1. In the first direction DR1, the length of the straight line portion GRa is preferably larger than the width of the receiving coil CL3 (coil CL31, coil CL32) and the width of the receiving coil CL4 (coil CL41, coil CL42). The length of the straight line portion GRa in the second direction DR2 may be, for example, 50 μm or more.

[0050] Each of the guard rings GR1 and GR2 may further include a straight portion GRb, a straight portion GRc, a corner portion GRd, a corner portion GRe, and an arc portion GRf. The straight portion GRb and the straight portion GRc extend along the first direction DR1 and face each other in the second direction DR2. One end of the straight portion GRb is connected to one end of the straight portion GRa by the corner portion GRd. One end of the straight portion GRc is connected to the other end of the straight portion GRa by the corner portion GRe. The corner portion GRd and the corner portion GRe extend in a curved shape having a predetermined curvature in a planar view. The arc portion GRf connects the other end of the straight portion GRb and the other end of the straight portion GRc. The arc portion GRf is arc-shaped in a planar view.

[0051] Fig. 9 is a plan view of a semiconductor chip CHP2 according to a second modification. As shown in Fig. 9, each of the guard rings GR1 and GR2 may not have the straight line portion GRb, the straight line portion GRc, the corner portion GRd, the corner portion GRe, and the arc portion GRf. In this case, the remaining portion of each of the guard rings GR1 and GR2 may extend while curving from one end of the straight line portion GRa to the other end. From another point of view, each of the remaining portions of the guard rings GR1 and GR2 may be wedge-shaped in a plan view.

[0052] <Manufacturing method of semiconductor chip CHP2> A method for manufacturing the semiconductor chip CHP2 will be described below.

[0053] Fig. 10 is a manufacturing process diagram of the semiconductor chip CHP2. As shown in Fig. 10, the manufacturing method of the semiconductor chip CHP2 includes a preparation step S1, an ion implantation step S2, a first insulating film forming step S3, a first via plug forming step S4, a first wiring layer forming step S5, and a second insulating film forming step S6. The manufacturing method of the semiconductor chip CHP2 further includes a second via plug forming step S7, a second wiring layer forming step S8, a third insulating film forming step S9, a third via plug forming step S10, a third wiring layer forming step S11, a fourth wiring layer forming step S12, and a passivation film forming step S13.

[0054] In the preparation step S1, a semiconductor substrate SUB is prepared. After the preparation step S1, an ion implantation step S2 is performed. Fig. 11 is a cross-sectional view illustrating the ion implantation step S2. As shown in Fig. 11, in the ion implantation step S2, an impurity implanted region IR is formed by ion implantation. After the ion implantation step S2, a first insulating film formation step S3 is performed.

[0055] Fig. 12 is a cross-sectional view illustrating the first insulating film forming step S3. As shown in Fig. 12, in the first insulating film forming step S3, an insulating film IF1 is formed on the semiconductor substrate SUB by, for example, a CVD (Chemical Vapor Deposition) method. After the first insulating film forming step S3, a first via plug forming step S4 is performed.

[0056] 13 is a cross-sectional view for explaining the first via plug forming step S4. As shown in FIG. 13, in the first via plug forming step S4, a via plug VP1 is embedded in the insulating film IF1. In the first via plug forming step S4, first, a via hole is formed in the insulating film IF1 by dry etching using a resist pattern formed by photolithography as a mask. Second, a constituent material of the via plug VP1 is embedded in the via hole by, for example, a CVD method. Third, the constituent material of the via plug VP1 protruding from the via hole is removed by, for example, a CMP (Chemical Mechanical Polishing) method. After the first via plug forming step S4, a first wiring layer forming step S5 is performed.

[0057] 14 is a cross-sectional view for explaining the first wiring layer forming step S5. As shown in FIG. 14, in the first wiring layer forming step S5, a wiring layer WL1 is formed on an insulating film IF1. In the first wiring layer forming step S5, first, a constituent material of the wiring layer WL1 is formed by, for example, a sputtering method. Second, the formed constituent material of the wiring layer WL1 is patterned by, for example, dry etching using a resist pattern formed by a photolithography method as a mask. After the first wiring layer forming step S5, a second insulating film forming step S6 is performed.

[0058] 15 is a cross-sectional view for explaining the second insulating film forming step S6. As shown in FIG. 15, in the second insulating film forming step S6, an insulating film IF2 is formed on the insulating film IF1 so as to cover the wiring layer WL1. In the second insulating film forming step S6, first, a constituent material of the insulating film IF2 is formed by, for example, a CVD method. Second, the constituent material of the formed insulating film IF2 is planarized by, for example, a CMP method. After the second insulating film forming step S6, a second via plug forming step S7 is performed.

[0059] 16 is a cross-sectional view for explaining the second via plug forming step S7. As shown in FIG. 16, in the second via plug forming step S7, a via plug VP2 is embedded in the insulating film IF2 by the same method as in the first via plug forming step S4. After the second via plug forming step S7, a second wiring layer forming step S8 is performed.

[0060] 17 is a cross-sectional view for explaining the second wiring layer forming step S8. As shown in FIG. 17, in the second wiring layer forming step S8, the wiring layer WL2 is formed on the insulating film IF2. In the second wiring layer forming step S8, first, the constituent material of the wiring layer WL2 is formed into a film by, for example, sputtering. Second, the formed constituent material of the wiring layer WL2 is patterned by, for example, dry etching using a resist pattern formed by photolithography as a mask. After the second wiring layer forming step S8, a third insulating film forming step S9 is performed.

[0061] 18 is a cross-sectional view illustrating the third insulating film forming step S9. As shown in FIG. 18, in the third insulating film forming step S9, an insulating film IF3 is formed on the insulating film IF2 so as to cover the wiring layer WL2. After the third insulating film forming step S9, a third via plug forming step S10 is performed.

[0062] 19 is a cross-sectional view illustrating the third via plug forming step S10. As shown in FIG. 19, in the third via plug forming step S10, a via plug VP3 is embedded in the insulating film IF3 by the same method as in the second via plug forming step S7. After the third via plug forming step S10, a third wiring layer forming step S11 is performed.

[0063] Fig. 20 is a cross-sectional view for explaining the third wiring layer forming step S11. As shown in Fig. 20, in the third wiring layer forming step S11, a wiring layer WL4 is formed by the same method as in the second wiring layer forming step S8. The third insulating film forming step S9, the third via plug forming step S10, and the third wiring layer forming step S11 are repeated until the insulating film IF3 in the uppermost layer is formed. After the insulating film IF3 in the uppermost layer is formed, the fourth wiring layer forming step S12 is performed.

[0064] Fig. 21 is a cross-sectional view illustrating the fourth wiring layer forming step S12. As shown in Fig. 21, in the fourth wiring layer forming step S12, a wiring layer WL3 is formed on the uppermost insulating film IF3 by the same method as in the second wiring layer forming step S8. After the fourth wiring layer forming step S12, a passivation film forming step S13 is performed.

[0065] In the passivation film forming process S13, a passivation film PF is formed on the insulating film IF3 in the uppermost layer so as to cover the wiring layer WL4. In the passivation film forming process S13, first, a constituent material of the passivation film PF is formed by, for example, a CVD method. Second, the constituent material of the passivation film PF is patterned by, for example, dry etching using a resist pattern formed by a photolithography method as a mask.

[0066] After the above steps are performed, the semiconductor chip CHP2 having the structure shown in FIG. 3 to FIG. 7 is formed by dividing the semiconductor chip into individual pieces by dicing or the like.

[0067] <Effects of semiconductor device DEV1> The effects of the semiconductor device DEV1 will be described below.

[0068] In the semiconductor device DEV1, the transformer TR1 and the transformer TR2 function as a high-side transformer and a low-side transformer, respectively, so that it is necessary to ensure a dielectric strength voltage between the transformer TR1 and the transformer TR2.

[0069] In the semiconductor chip CHP2, the receiving coil CL3 (coil CL31, coil CL32) is surrounded by the guard ring GR1 in a plan view, and the receiving coil CL4 (coil CL41, coil CL42) is surrounded by the guard ring GR2 in a plan view. Therefore, in the semiconductor chip CHP2, the potential difference between the receiving coil CL3 and the receiving coil CL4 and the surroundings (specifically, the potential difference between the guard ring GR3) is stabilized. In this way, the semiconductor device DEV1 having the semiconductor chip CHP2 can ensure the dielectric strength voltage between the transformer TR1 and the transformer TR2.

[0070] Between the receiving coil CL3 and the guard ring GR3 (between the guard ring GR1 and the guard ring GR2 and the guard ring GR3), the dielectric strength against AC is an issue, and the distances DIS2 and DIS3 are set to satisfy this dielectric strength. Between the receiving coil CL3 and the receiving coil CL4 (between the guard ring GR1 and the guard ring GR2), the dielectric strength against DC is an issue, and this dielectric strength can be ensured even if the distance DIS1 is smaller than the distance DIS2 and the distance DIS3. Therefore, by satisfying the relationship 0<distance DIS1≦distance DIS2 and the relationship 0<distance DIS1≦distance DIS3, it is possible to miniaturize the semiconductor chip CHP2 while ensuring the desired dielectric strength.

[0071] When the guard rings GR1 and GR2 each have a straight portion GRa, a singular point where electric field concentration occurs between the guard rings GR1 and GR2 is unlikely to occur. Therefore, in this case, even if the distance DIS1 is reduced, it is possible to increase the dielectric strength between the guard rings GR1 and GR2 (between the receiving coils CL3 and CL4), and thus it is possible to reduce the size of the semiconductor chip CHP2.

[0072] In the semiconductor device DEV1, the distance between the transmitting coil CL2 and the receiving coil CL4 is larger than that in the semiconductor device DEV2 described later. This means that the capacitance of the transmitting coil CL2, the receiving coil CL4, and the insulating film between the transmitting coil CL2 and the receiving coil CL4 is smaller. The smaller the capacitance, the more the common mode transient immunity (CMTI) is improved. Therefore, the semiconductor device DEV1 can improve the CMTI.

[0073] Second embodiment A semiconductor device according to a second embodiment will be described. The semiconductor device according to the second embodiment will be referred to as a semiconductor device DEV2. Here, differences from the semiconductor device DEV1 will be mainly described, and overlapping descriptions will not be repeated.

[0074] (Configuration of semiconductor device DEV2) The configuration of the semiconductor device DEV2 will be described below.

[0075] The semiconductor device DEV2 has a semiconductor chip CHP1, a semiconductor chip CHP2, a semiconductor chip CHP3, and a semiconductor chip CHP4. In this respect, the configuration of the semiconductor device DEV2 is common to the configuration of the semiconductor device DEV1.

[0076] FIG. 22 is a first plan view of the semiconductor chip CHP2 in the semiconductor device DEV2. FIG. 23 is a second plan view of the semiconductor chip CHP2 in the semiconductor device DEV2. FIG. 24 is a third plan view of the semiconductor chip CHP2 in the semiconductor device DEV2. FIG. 25 is a cross-sectional view taken along the line XXV-XXV in FIG. 22. As shown in FIGS. 22 to 25, in the semiconductor chip CHP2 of the semiconductor device DEV2, one wiring layer WL4 has a receiving coil CL4 (coil CL41, coil CL42), a guard ring GR2, a pad PD3, a pad PD4, and a pad PD6. In the semiconductor chip CHP2 of the semiconductor device DEV2, the other wiring layer WL4 has a wiring WL4a, a wiring WL4b, and a wiring WL4c. In the semiconductor chip CHP2 of the semiconductor device DEV2, the wiring layer WL3 further has a pad PD11, a pad PD12, and a pad PD13.

[0077] From another perspective, if the insulating film IF3 between the transmitting coil CL2 and the receiving coil CL4 is defined as the first insulating film, and the insulating films IF3 other than the first insulating film are collectively defined as the second insulating films, then only the first insulating film is interposed between the transmitting coil CL2 and the receiving coil CL4, while both the first insulating film and the second insulating film are interposed between the transmitting coil CL1 and the receiving coil CL3. Note that since the transformer TR2 is a low-side transformer, even if the thickness of the insulating film between the transmitting coil CL2 and the receiving coil CL4 is small, the insulation withstand voltage between the transmitting coil CL2 and the receiving coil CL4 can be ensured.

[0078] In the semiconductor chip CHP2 of the semiconductor device DEV2, the wiring WL4a is a guard ring GR4 that surrounds the guard ring GR2 in a plan view. If the shortest distance between the guard ring GR2 and the guard ring GR4 in a plan view is a distance DIS4, it is preferable that the relationship of distance DIS1≦distance DIS4 is satisfied. The wiring layer WL4 having the receiving coil CL4, the guard ring GR2, and the guard ring GR4 is, for example, the bottom wiring layer WL4.

[0079] The wiring layer WL4 having the wiring WL4b, the wiring WL4c, and the wiring WL4d is, for example, one layer above the wiring layer WL4 having the receiving coil CL4, the guard ring GR2, and the guard ring GR4. The wiring WL4b, the wiring WL4c, and the wiring WL4d extend along the second direction DR2 in a plan view. One end of the wiring WL4b and one end of the wiring WL4c overlap the pads PD3 and PD4 in a plan view. One end of the wiring WL4d overlaps the pad PD6 in a plan view. The other end of the wiring WL4b and the other end of the wiring WL4c overlap the pads PD11 and PD12 in a plan view. The other end of the wiring WL4d overlaps the pad PD13 in a plan view. The pads PD11, PD12, and PD13 are disposed outside the guard ring GR3 in a plan view.

[0080] The pads PD11, PD12, and PD13 are electrically connected to the pads PD3, PD4, and PD6, respectively, by the via plugs VP3 and a plurality of wiring layers WL4. That is, in the semiconductor chip CHP2 of the semiconductor device DEV2, the pads PD3, PD4, and PD6 are not used as bonding pads for external connection because they are not in the uppermost wiring layer, but are pulled up to the pads PD11, PD12, and PD13 in the uppermost wiring layer via the wiring layer (wiring WL4b, wiring WL4c, and wiring WL4d) one layer above. Then, the pads PD11, PD12, and PD13 are used as bonding pads. Note that the semiconductor chip CHP2 of the semiconductor device DEV2 does not need to have the guard ring GR2. In these respects, the configuration of the semiconductor device DEV2 is different from that of the semiconductor device DEV1.

[0081] <Effects of semiconductor device DEV2> The effects of the semiconductor device DEV2 will be described below.

[0082] In the semiconductor chip CHP2 of the semiconductor device DEV2, the receiving coil CL3 and the receiving coil CL4 are formed in different wiring layers. Therefore, in the semiconductor device DEV2, even if the distance DIS1 is small, the distance required to ensure the dielectric strength voltage between the receiving coil CL3 and the receiving coil CL4 can be secured, and the chip size (more specifically, the dimension in the first direction DR1) of the semiconductor chip CHP2 can be reduced.

[0083] Third embodiment A semiconductor device according to a third embodiment will be described. The semiconductor device according to the third embodiment will be referred to as a semiconductor device DEV3. Here, differences from the semiconductor device DEV2 will be mainly described, and overlapping descriptions will not be repeated.

[0084] (Configuration of semiconductor device DEV3) The configuration of the semiconductor device DEV3 will be described below.

[0085] The semiconductor device DEV3 has a semiconductor chip CHP1, a semiconductor chip CHP2, a semiconductor chip CHP3, and a semiconductor chip CHP4. In this respect, the configuration of the semiconductor device DEV3 is common to the configuration of the semiconductor device DEV2.

[0086] 26 is a plan view of the semiconductor chip CHP2 in the semiconductor device DEV3. As shown in FIG. 26, in the semiconductor chip CHP2 of the semiconductor device DEV3, the width of the coil CL41 and the width of the coil CL42 are smaller than the width of the coil CL31 and the coil CL32 in the first direction DR1. In the semiconductor chip CHP2 of the semiconductor device DEV3, the width of the coil CL41 and the width of the coil CL42 are smaller than the width of the coil CL31 and the coil CL32 in the second direction DR2 as well. Similarly, in the semiconductor chip CHP2 of the semiconductor device DEV3, the width of the coil CL21 and the width of the coil CL22 are smaller than the width of the coil CL11 and the coil CL12 in the first direction DR1, and the width of the coil CL21 and the width of the coil CL22 are smaller than the width of the coil CL11 and the coil CL12 in the second direction DR2 as well.

[0087] In the semiconductor chip CHP2 of the semiconductor device DEV3, the pads PD3 and PD4 are not used as bonding pads, and the dimensions of the pads PD3 and PD4 can be reduced. Therefore, in the semiconductor chip CHP2 of the semiconductor device DEV3, the dimensions of the coil CL41 (coil CL42) can be made smaller than those of the coil CL31 (coil CL32) while maintaining the number of turns. However, in the semiconductor chip CHP2 of the semiconductor device DEV3, the number of turns of the coil CL41 (coil CL42) may be made smaller than the number of turns of the coil CL31 (coil CL32) in the first direction DR1 and the second direction DR2. In these respects, the configuration of the semiconductor device DEV3 is different from that of the semiconductor device DEV2.

[0088] <Effects of semiconductor device DEV3> The effects of the semiconductor device DEV3 will be described below.

[0089] In the semiconductor chip CHP2 of the semiconductor device DEV2, the thickness of the insulating film interposed between the transmitting coil CL2 and the receiving coil CL4 is smaller than that of the semiconductor chip CHP2 of the semiconductor device DEV1, so that the capacitance due to the transmitting coil CL2, the receiving coil CL4 and the insulating film between them becomes large, which may result in a decrease in CMTI.

[0090] The thickness of the insulating film interposed between the transmitter coil CL2 and the receiver coil CL4 in the semiconductor chip CHP2 of the semiconductor device DEV3 is also the same as that in the semiconductor chip CHP2 of the semiconductor device DEV2. However, in the semiconductor chip CHP2 of the semiconductor device DEV3, the sizes of the transmitter coil CL2 and the receiver coil CL4 are smaller, and as a result, the capacitance of the transmitter coil CL2, the receiver coil CL4, and the insulating film therebetween is smaller. Therefore, according to the semiconductor device DEV3, it is possible to improve the CMTI in the transformer TR2 while reducing the size of the semiconductor chip CHP2.

[0091] (Additional Note) The embodiments of the present disclosure include the following features.

[0092] <Appendix 1> A semiconductor substrate; An insulating film; A first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil, and an eighth coil; A first guard ring and a second guard ring are provided. the first coil, the second coil, the third coil, and the fourth coil are formed on the semiconductor substrate, the first coil and the second coil are electrically connected in series with each other, the third coil and the fourth coil are electrically connected in series with each other, the fifth coil faces the first coil via the insulating film, the sixth coil faces the second coil via the insulating film, the seventh coil faces the third coil via the insulating film, the eighth coil faces the fourth coil via the insulating film, the fifth coil and the sixth coil are electrically connected in series with each other, the seventh coil and the eighth coil are electrically connected in series with each other, the first guard ring is formed to surround the fifth coil and the sixth coil in a plan view, the second guard ring is formed to surround the seventh coil and the eighth coil in a plan view, The semiconductor device, wherein the first guard ring and the second guard ring are adjacent to each other and spaced apart from each other in a plan view.

[0093] <Appendix 2> the first coil and the second coil are aligned in a first direction in a plan view, each of the first guard ring and the second guard ring has a first linear portion extending along a second direction perpendicular to the first direction; 2. The semiconductor device according to claim 1, wherein the first straight portion of the first guard ring is disposed to face the first straight portion of the second guard ring.

[0094] <Appendix 3> The first linear portion has a first end and a second end opposite to the first end, 3. The semiconductor device according to claim 2, wherein a remaining portion of each of the first guard ring and the second guard ring extends from the first end to the second end while being curved in a plan view.

[0095] <Appendix 4> The first linear portion has a first end and a second end opposite to the first end, each of the first guard ring and the second guard ring further includes a second straight portion, a third straight portion, a first corner portion, a second corner portion, and an arc portion; the second linear portion and the third linear portion extend along the first direction and face each other in the second direction, the second linear portion has a third end and a fourth end opposite the third end, the third linear portion has a fifth end and a sixth end that is an end opposite to the fifth end, the first corner portion connects the third end and the first end, the second corner portion connects the fifth end and the second end, The first corner portion and the second corner portion extend in a curved shape in a plan view, 3. The semiconductor device according to claim 2, wherein the arc portion connects the fourth end and the sixth end and extends in an arc shape in a plan view.

[0096] <Appendix 5> 3. The semiconductor device according to claim 2, wherein in the second direction, a length of the first straight portion is greater than or equal to a width of the third coil and a width of the fourth coil.

[0097] <Appendix 6> 6. The semiconductor device according to claim 5, wherein the length of the first straight portion in the second direction is 50 μm or more.

[0098] <Appendix 7> 2. The semiconductor device according to claim 1, wherein, in a cross-sectional view, the third coil, the fourth coil, the first guard ring, and the second guard ring are formed in the same layer.

[0099] <Appendix 8> Further comprising a third guard ring; 2. The semiconductor device according to claim 1, wherein the third guard ring is formed to surround the first guard ring and the second guard ring in a plan view.

[0100] <Appendix 9> The semiconductor device described in Appendix 8, wherein a first distance, which is the shortest distance between the first guard ring and the second guard ring in a planar view, is shorter than a second distance, which is the shortest distance between the first guard ring and the third guard ring in a planar view, and a third distance, which is the shortest distance between the second guard ring and the third guard ring in a planar view.

[0101] <Appendix 10> the first distance is 15 μm or more; 10. The semiconductor device according to claim 9, wherein the second distance and the third distance are 50 μm or more.

[0102] <Appendix 11> 9. The semiconductor device of claim 8, wherein a first voltage applied to the first guard ring and a second voltage applied to the second guard ring are higher than a third voltage applied to the third guard ring.

[0103] <Appendix 12> the first coil and the third coil are magnetically coupled to configure a high-side transformer, 2. The semiconductor device according to claim 1, wherein the second coil and the fourth coil are magnetically coupled to form a low-side transformer.

[0104] <Appendix 13> A semiconductor substrate; A first insulating film, a second insulating film, and a third insulating film; a first wiring layer, a second wiring layer and a third wiring layer; A first coil, a second coil, a third coil, a fourth coil, a fifth coil, a sixth coil, a seventh coil, and an eighth coil; A first guard ring and a second guard ring are provided. the first insulating film is formed on the semiconductor substrate, the first wiring layer is formed on the first insulating film, the second insulating film is formed on the first insulating film so as to cover the first wiring layer; the second wiring layer is disposed on the second insulating film, the third insulating film is formed on the second insulating film so as to cover the second wiring layer; the third wiring layer is formed on the third insulating film, the first coil, the second coil, the third coil, and the fourth coil are formed in the first wiring layer, the fifth coil and the sixth coil are formed in the third wiring layer, the seventh coil and the eighth coil are formed in the second wiring layer, the first coil and the second coil face the fifth coil and the sixth coil via the second insulating film and the third insulating film, respectively; the third coil and the fourth coil face the seventh coil and the eighth coil, respectively, via the second insulating film; the first guard ring is formed to surround the fifth coil and the sixth coil in a plan view, the second guard ring is formed to surround the seventh coil and the eighth coil in a plan view, The semiconductor device, wherein the first guard ring and the second guard ring are adjacent to each other and spaced apart from each other in a plan view.

[0105] <Appendix 14> A first semiconductor chip; A second semiconductor chip; A third semiconductor chip; and a fourth semiconductor chip; the first semiconductor chip has a first transmission circuit and a second transmission circuit; the second semiconductor chip has a first transformer for a high side and a second transformer for a low side, the third semiconductor chip has a first receiving circuit; the fourth semiconductor chip has a second receiving circuit; a signal transmitted by the first transmitting circuit is transmitted to the first receiving circuit via the first transformer in a pulse communication manner; a signal transmitted by the second transmitting circuit is transmitted to the second receiving circuit via the second transformer in a pulse communication manner; the third semiconductor chip has a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, a first guard ring, and a second guard ring; the first coil and the second coil are formed on the semiconductor substrate, the third coil faces the first coil via the insulating film, the fourth coil faces the second coil via the insulating film, the first coil and the third coil are magnetically coupled to configure the first transformer, the second coil and the fourth coil are magnetically coupled to configure the second transformer, the first guard ring is formed to surround the third coil in a plan view, the second guard ring is formed to surround the fourth coil in a plan view, The semiconductor device, wherein the first guard ring and the second guard ring are adjacent to each other and spaced apart from each other in a plan view.

[0106] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0107] CHP1, CHP2, CHP3, CHP4 semiconductor chip, CL1 transmitting coil, CL11, CL12 coil, CL2 transmitting coil, CL21, CL22 coil, CL3 receiving coil, CL31, CL32 coil, CL4 receiving coil, CL41, CL42 coil, DEV1, DEV2, DEV3 semiconductor device, DIS1, DIS2, DIS3, DIS4 distance, DR1 first direction, DR2 second direction, FS first surface, GR1, GR2 guard ring, GR3, GR4 guard ring, GRa, GRb, GRc straight portion, GRd corner portion, GRe corner portion, GRf circular arc portion, IF1 insulating film, IF2 insulating film, IF3 insulating film, IR impurity implanted region, PD1, PD2, PD3, PD4, PD5, PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13 Pad, PF passivation film, PL1, PL2 lead wiring, RX1, RX2 receiving circuit, S1 preparation process, S2 ion implantation process, S3 first insulating film formation process, S4 first via plug formation process, S5 first wiring layer formation process, S6 second insulating film formation process, S7 second via plug formation process, S8 second wiring layer formation process, S9 third insulating film formation process, S10 third via plug formation process, S11 third wiring layer formation process, S12 fourth wiring layer formation process, S13 passivation film formation process, SG1, SG2, SG3, SG4 signal, SS second surface, SUB semiconductor substrate, TR1, TR2 transformer, TX1, TX2 transmitting circuit, VP1, VP2, VP3 Via plugs, WL1a, WL1b, WL1c, WL1d, WL1e, WL2a, WL2b, WL2c, WL2d, WL2e, WL4a, WL4b, WL4c, WL4d wiring, WL1, WL2, WL3, WL4 wiring layers.

Claims

1. A semiconductor substrate; An insulating film; A first coil, a second coil, a third coil and a fourth coil; A first guard ring and a second guard ring are provided, the first coil and the second coil are formed on the semiconductor substrate, the third coil faces the first coil via the insulating film, the fourth coil faces the second coil via the insulating film, the first guard ring is formed to surround the third coil in a plan view, the second guard ring is formed to surround the fourth coil in a plan view, the first guard ring and the second guard ring are adjacent to but spaced apart from each other in a plan view.

2. the first coil and the second coil are aligned in a first direction in a plan view, each of the first guard ring and the second guard ring has a first linear portion extending along a second direction perpendicular to the first direction; The semiconductor device according to claim 1 , wherein the first linear portion of the first guard ring is disposed to face the first linear portion of the second guard ring.

3. The first linear portion has a first end and a second end opposite to the first end, The semiconductor device according to claim 2 , wherein the remaining portions of the first guard ring and the second guard ring extend from the first end to the second end while being curved in a plan view.

4. The first linear portion has a first end and a second end opposite to the first end, each of the first guard ring and the second guard ring further includes a second straight portion, a third straight portion, a first corner portion, a second corner portion, and an arc portion; the second linear portion and the third linear portion extend along the first direction and face each other in the second direction, the second linear portion has a third end and a fourth end opposite to the third end, The third linear portion has a fifth end and a sixth end that is an end opposite to the fifth end, the first corner portion connects the third end and the first end, the second corner portion connects the fifth end and the second end, The first corner portion and the second corner portion extend in a curved shape in a plan view, The semiconductor device according to claim 2 , wherein said arc portion connects said fourth end and said sixth end, and extends in an arc shape in a plan view.

5. The semiconductor device according to claim 2 , wherein a length of the first straight portion in the second direction is equal to or greater than a width of the third coil and a width of the fourth coil.

6. The semiconductor device according to claim 5 , wherein the length of the first straight portion in the second direction is 50 μm or more.

7. The semiconductor device according to claim 1 , wherein, in a cross-sectional view, the third coil, the fourth coil, the first guard ring, and the second guard ring are formed in the same layer.

8. Further comprising a third guard ring; The semiconductor device according to claim 1 , wherein the third guard ring is formed to surround the first guard ring and the second guard ring in a plan view.

9. 9. The semiconductor device of claim 8, wherein a first distance, which is the shortest distance between the first guard ring and the second guard ring in a planar view, is shorter than a second distance, which is the shortest distance between the first guard ring and the third guard ring in a planar view, and a third distance, which is the shortest distance between the second guard ring and the third guard ring in a planar view.

10. the first distance is 15 μm or more; The semiconductor device according to claim 9 , wherein the second distance and the third distance are equal to or greater than 50 μm.

11. 9. The semiconductor device according to claim 8, wherein a first voltage applied to the first guard ring and a second voltage applied to the second guard ring are higher than a third voltage applied to the third guard ring.

12. the first coil and the third coil are magnetically coupled to configure a high-side transformer, The semiconductor device according to claim 1 , wherein the second coil and the fourth coil are magnetically coupled to form a low-side transformer.

13. A semiconductor substrate; A first insulating film, a second insulating film, and a third insulating film; a first wiring layer, a second wiring layer and a third wiring layer; A first coil, a second coil, a third coil and a fourth coil; A first guard ring and a second guard ring are provided, the first insulating film is formed on the semiconductor substrate, the first wiring layer is formed on the first insulating film, the second insulating film is formed on the first insulating film so as to cover the first wiring layer; the second wiring layer is disposed on the second insulating film, the third insulating film is formed on the second insulating film so as to cover the second wiring layer; the third wiring layer is formed on the third insulating film, the first coil and the second coil are formed in the first wiring layer, the third coil is formed in the third wiring layer, the fourth coil is formed in the second wiring layer, the first coil and the third coil face each other via the second insulating film and the third insulating film, the second coil and the fourth coil face each other via the second insulating film, the first guard ring is formed to surround the third coil in a plan view, the second guard ring is formed to surround the fourth coil in a plan view, the first guard ring and the second guard ring are adjacent to but spaced apart from each other in a plan view.

14. the first guard ring is formed in the third wiring layer, The semiconductor device according to claim 13 , wherein the second guard ring is formed in the second wiring layer.

15. Further comprising a third guard ring; The semiconductor device according to claim 13 , wherein the third guard ring is formed to surround the first guard ring and the second guard ring in a plan view.

16. 16. The semiconductor device of claim 15, wherein a first distance, which is the shortest distance between the first guard ring and the second guard ring in a planar view, is shorter than a second distance, which is the shortest distance between the first guard ring and the third guard ring in a planar view, and a third distance, which is the shortest distance between the second guard ring and the third guard ring in a planar view.

17. the first distance is 15 μm or more; The semiconductor device according to claim 16 , wherein the second distance and the third distance are equal to or greater than 50 μm.

18. the first coil and the second coil are aligned in a first direction in a plan view, In the first direction, a width of the second coil and a width of the fourth coil are smaller than a width of the first coil and a width of the third coil; 14. The semiconductor device according to claim 13, wherein in a second direction perpendicular to the first direction, a width of the second coil and a width of the fourth coil are smaller than a width of the first coil and a width of the third coil.

19. The semiconductor device according to claim 13 , wherein the number of turns of the second coil and the number of turns of the fourth coil are smaller than the number of turns of the first coil and the number of turns of the third coil.

20. A first semiconductor chip; A second semiconductor chip; A third semiconductor chip; a fourth semiconductor chip; the first semiconductor chip has a first transmission circuit and a second transmission circuit; the second semiconductor chip has a first transformer for a high side and a second transformer for a low side, the third semiconductor chip has a first receiving circuit; the fourth semiconductor chip has a second receiving circuit; a signal transmitted by the first transmitting circuit is transmitted to the first receiving circuit via the first transformer; a signal transmitted by the second transmitting circuit is transmitted to the second receiving circuit via the second transformer; the third semiconductor chip has a semiconductor substrate, an insulating film, a first coil, a second coil, a third coil, a fourth coil, a first guard ring, and a second guard ring; the first coil and the second coil are formed on the semiconductor substrate, the third coil faces the first coil via the insulating film, the fourth coil faces the second coil via the insulating film, the first coil and the third coil are magnetically coupled to configure the first transformer, the second coil and the fourth coil are magnetically coupled to configure the second transformer, the first guard ring is formed to surround the third coil in a plan view, the second guard ring is formed to surround the fourth coil in a plan view, the first guard ring and the second guard ring are adjacent to but spaced apart from each other in a plan view.

Images