Semiconductor device

Abstract

To protect a plurality of semiconductor chips, mounted on a silicon interposer, from an electro-static discharge (ESD) current, without increasing a chip area.SOLUTION: A semiconductor device has: a substrate; and a plurality of semiconductor chips provided on the substrate. Each of the plurality of semiconductor chips has: a plurality of types of chip power source lines; and a circuit connected to the plurality of types of chip power source lines. A signal outputted from the circuit of one of the semiconductor chips is inputted into the circuit of another one of the semiconductor chips. The substrate has: a plurality of substrate power source lines connected to the plurality of chip power source lines of the plurality of semiconductor chips; and a plurality of substrate clamp circuits connected to the plurality of types of substrate power source lines.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device. [Background technology]

[0002] There is a known technology for mounting multiple semiconductor chips (dies) on a silicon interposer. There is a known technology for providing an I / O (Input / Output) circuit on a die that connects the die to the outside or to other dies. There is a known technology for suppressing damage to elements due to ESD (Electro-Static Discharge) current by placing a protection circuit (clamp circuit) between the power supply line and the ground line. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication No. 2021 / 0193647 [Patent Document 2] U.S. Patent No. 9,245,852 [Patent Document 3] U.S. Patent No. 8,040,645 [Patent Document 4] U.S. Pat. No. 1,139,8469 [Patent Document 5] JP 2013-065870 A [Patent Document 6] US Patent Application Publication No. 2021 / 0313375 [Patent Document 7] U.S. Patent No. 9,412,708 Summary of the Invention [Problem to be solved by the invention]

[0004] When multiple semiconductor chips supplied with different power supply voltages are mounted on a silicon interposer, the wiring provided on the silicon interposer and the multiple semiconductor chips may become a discharge path for ESD current. For example, when the input / output circuits of multiple semiconductor chips are connected with signal lines, if the power supply voltage changes due to the ESD current flowing through the power supply line of the semiconductor chip, an overvoltage may be applied to elements such as transistors provided in the input / output circuit. When a protection circuit is provided on each semiconductor chip to protect elements such as transistors of the semiconductor chip from ESD current, the chip area may increase.

[0005] The present invention has been made in consideration of the above-mentioned points, and has an object to protect multiple semiconductor chips mounted on a silicon interposer from ESD current while suppressing an increase in chip area. [Means for solving the problem]

[0006] In one aspect of the present invention, a semiconductor device includes a substrate, a first substrate power line provided on the substrate, a second substrate power line supplied with a voltage different from that of the first substrate power line, and a third substrate power line supplied with a voltage different from that of the first substrate power line, a first substrate clamp circuit provided on the substrate and arranged between the first substrate power line and the second substrate power line, a second substrate clamp circuit provided on the substrate and arranged between the first substrate power line and the third substrate power line, a first semiconductor chip and a second semiconductor chip provided on the substrate, and a first chip power line provided on the first semiconductor chip and electrically connected to the first substrate power line. a second chip power line provided on the first semiconductor chip and electrically connected to the second substrate power line; a first circuit provided on the first semiconductor chip and arranged between the first chip power line and the second chip power line; a third chip power line provided on the second semiconductor chip and electrically connected to the first substrate power line; a fourth chip power line provided on the second semiconductor chip and electrically connected to the third substrate power line; and a second circuit provided on the second semiconductor chip and arranged between the third chip power line and the fourth chip power line, wherein a signal output from the first circuit is input to the second circuit. Effect of the Invention

[0007] According to the disclosed technology, it is possible to protect multiple semiconductor chips mounted on a silicon interposer from ESD current while suppressing an increase in chip area. [Brief description of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram illustrating a problem of a semiconductor device in which a plurality of semiconductor chips are mounted on a silicon interposer. [Diagram 2] 1 is a block diagram showing an example of a semiconductor device according to a first embodiment. [Diagram 3] 3 is a cross-sectional view showing an outline of the connection between the silicon interposer and each chip in FIG. 2. [Figure 4] 3 is a circuit diagram showing an example of an internal circuit mounted on the semiconductor chip of FIG. 2. [Diagram 5] 3 is a circuit diagram illustrating an example of the clamp circuit of FIG. 2. [Figure 6] 3 is a transparent plan view showing an example of an arrangement of wiring and circuits formed on the silicon interposer and each chip in FIG. 2. [Figure 7] 3 is a cross-sectional view showing an outline of the structure of the silicon interposer shown in FIG. 2. [Figure 8] FIG. 13 is a block diagram showing an example of a semiconductor device according to a second embodiment. [Figure 9] 9 is a transparent plan view showing an example of an arrangement of wiring and circuits formed on the silicon interposer and each chip in FIG. 8. [Figure 10] FIG. 13 is a block diagram showing an example of a semiconductor device according to a third embodiment. [Figure 11] 11 is a transparent plan view showing an example of an arrangement of wiring and circuits formed on the silicon interposer and each chip in FIG. [Figure 12] FIG. 13 is a block diagram showing an example of a semiconductor device according to a fourth embodiment. [Figure 13] FIG. 13 is a block diagram showing an example of a semiconductor device according to a fifth embodiment. [Figure 14] FIG. 14 is an explanatory diagram illustrating an example of the ESD protection circuit of FIG. [Figure 15] FIG. 13 is an explanatory diagram showing another example of an ESD protection circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] Hereinafter, the embodiments will be described with reference to the drawings. In the following, a reference symbol indicating a signal is also used to indicate a signal line or a signal terminal. A reference symbol indicating a power supply voltage is also used to indicate a power supply line or a power supply terminal to which the power supply voltage is supplied.

[0010] Fig. 1 shows a block diagram for explaining the problem of a semiconductor device in which multiple semiconductor chips are mounted on a silicon interposer. The semiconductor device SEM0 shown in Fig. 1 has multiple semiconductor chips CP1, CP2, CP3 (chiplets) mounted on a silicon interposer INTP, and has a so-called 2.5-dimensional mounting form. Note that in Fig. 1, three semiconductor chips CP1, CP2, CP3 are mounted on the silicon interposer INTP, but for example, two or four or more semiconductor chips may be mounted on the silicon interposer INTP.

[0011] For example, each of the semiconductor chips CP1, CP2, and CP3 may have a function of processing signals or data and may operate in cooperation with one another. By implementing the functions implemented in the semiconductor device SEM0 using multiple chiplets, each chiplet can be manufactured using an appropriate semiconductor manufacturing process. Therefore, the increase in manufacturing costs of the semiconductor device SEM0 can be suppressed compared to the case where multiple chiplets are integrated into one chip.

[0012] The semiconductor chip CP1 has internal circuits CIR1A and CIR1B, a clamp circuit CLMP1, a power supply line VDD1c, and a ground line VSS1c. The internal circuits CIR1A and CIR1B are arranged between the ground line VSS1c and the power supply line VDD1c, and operate by receiving the power supply voltage VDD1c and the ground voltage VSS1c. The clamp circuit CLMP1 is arranged between the ground line VSS1c and the power supply line VDD1c, and protects the internal circuits CIR1A and CIR1B, which are protected circuits, from ESD.

[0013] The semiconductor chip CP2 has internal circuits CIR2A and CIR2B, a clamp circuit CLMP2, a power supply line VDD2c, and a ground line VSS2c. The internal circuits CIR2A and CIR2B are arranged between the ground line VSS2c and the power supply line VDD2c, and operate by receiving the power supply voltage VDD2c and the ground voltage VSS2c. The clamp circuit CLMP2 is arranged between the ground line VSS2c and the power supply line VDD2c, and protects the internal circuits CIR2A and CIR2B, which are protected circuits, from ESD.

[0014] The semiconductor chip CP3 has internal circuits CIR3A and CIR3B, a clamp circuit CLMP3, a power supply line VDD3c, and a ground line VSS3c. The internal circuits CIR3A and CIR3B are arranged between the ground line VSS3c and the power supply line VDD3c, and operate by receiving the power supply voltage VDD3c and the ground voltage VSS3c. The clamp circuit CLMP3 is arranged between the ground line VSS3c and the power supply line VDD3c, and protects the internal circuits CIR3A and CIR3B, which are protected circuits, from ESD.

[0015] An output signal line OUT1 connected to an internal circuit CIR1B of the semiconductor chip CP1 is electrically connected to a signal line SIG formed on a silicon interposer ITNP via a bump BMP such as a microbump. The signal line SIG is electrically connected to an input signal line IN2 connected to an internal circuit CIR2A of the semiconductor chip CP2 via a bump BMP. That is, an output signal OUT1 output from the internal circuit CIR1B is input to the internal circuit CIR2A.

[0016] Hereinafter, the semiconductor chips CP1-CP3 are also simply referred to as chips CP1-CP3. When the semiconductor chips CP1-CP3 are described without distinction, they are also referred to as chip CPx. When the internal circuits CIR1A and CIR1B are described without distinction, they are also referred to as internal circuits CIR1x. When the internal circuits CIR2A and CIR2B are described without distinction, they are also referred to as internal circuits CIR2x. When the internal circuits CIR3A and CIR3B are described without distinction, they are also referred to as internal circuits CIR3x. When the internal circuits CIR1A, CIR1B, CIR2A, CIR2B, CIR3A, and CIR3B are described without distinction, they are also referred to as internal circuits CIRx. When the clamp circuits CLMP1-CLMP3 are described without distinction, they are also referred to as clamp circuits CLMPx.

[0017] For example, the internal circuit CIRx is an input / output circuit. The clamp circuit CLMP1 suppresses damage to the internal circuit CIR1x due to an ESD current flowing into the chip CP1 in a process of mounting the chip CP1 on the silicon interposer ITNP. The clamp circuit CLMP2 suppresses damage to the internal circuit CIR2x due to an ESD current flowing into the chip CP2 in a process of mounting the chip CP2 on the silicon interposer ITNP. The clamp circuit CLMP3 suppresses damage to the internal circuit CIR3x due to an ESD current flowing into the chip CP3 in a process of mounting the chip CP3 on the silicon interposer ITNP.

[0018] The silicon interposer ITNP has a power supply line VDD1 electrically connected to the power supply line VDD1c of the chip CP1 via the bump BMP, a power supply line VDD2 electrically connected to the power supply line VDD2c of the chip CP2 via the bump BMP, and a power supply line VDD3 electrically connected to the power supply line VDD3c of the chip CP3 via the bump BMP. The silicon interposer ITNP and each chip CPx may be electrically connected to each other via a TSV (Through Silicon Via). The silicon interposer ITNP has a ground line VSS electrically connected in common to the ground line VSS1c of the chip CP1, the ground line VSS2c of the chip CP2, and the ground line VSS3c of the chip CP3 via the bump BMP.

[0019] The silicon interposer ITNP has an external ground terminal VSS and external power supply terminals VDD1, VDD2, and VDD3 exposed on the surface. The external ground terminal VSS is electrically connected to a ground line VSS of the silicon interposer ITNP. The external power supply terminal VDD1 is electrically connected to a power supply line VDD1 of the silicon interposer ITNP. The external power supply terminal VDD2 is electrically connected to a power supply line VDD2 of the silicon interposer ITNP. The external power supply terminal VDD3 is electrically connected to a power supply line VDD3 of the silicon interposer ITNP.

[0020] The clamp circuit CLMP1 protects the internal circuit CIR1x from ESD by forming a current path between the power supply line VDD1c and the ground line VSS1c when ESD occurs. The clamp circuit CLMP2 protects the internal circuit CIR2x from ESD by forming a current path between the power supply line VDD2c and the ground line VSS2c when ESD occurs. The clamp circuit CLMP3 protects the internal circuit CIR3x from ESD by forming a current path between the power supply line VDD3c and the ground line VSS3c when ESD occurs.

[0021] The ESD described below occurs when a human finger or the like comes into contact with an external terminal of the semiconductor device SEM0 during transportation after manufacturing of the semiconductor device SEM0 or during installation of the semiconductor device SEM0 in a system. That is, the model of ESD described below is the Human Body Model (HBM).

[0022] In the semiconductor device SEM0, when each chip CPx is manufactured using advanced technology, the transistors have a lower breakdown voltage, the wiring is thin, and the wiring resistance is high in many cases compared to chips manufactured using legacy technology. It is difficult for wiring with high resistance to sufficiently discharge ESD current. For this reason, it may be difficult for the chip CPx manufactured using advanced technology to meet the ESD protection specifications, for example, in automotive applications that require high reliability. If the clamp circuit CLMPx provided in each chip CPx is enlarged in order to strengthen the breakdown voltage of the transistors against ESD, this leads to an increase in the chip size.

[0023] For example, in the human body model, when a positive ESD voltage is applied from the external power supply terminal VDD1 with respect to the external power supply terminal VDD2 as the reference (ESD application), an ESD current flows through the paths indicated by the dashed arrow and the dashed arrow in Figure 1. The discharge path indicated by the dashed line includes the clamp circuits CLMP1 and CLMP2, and therefore the potential difference between the input side and output side of the current is likely to be larger than that of the discharge path indicated by the dashed line.

[0024] For example, when ESD is applied, the rise in the power supply voltage VDD2 (VDD2c) may lag behind the rise in the power supply voltage VDD1 (VDD1c), causing the high-level voltage of the output signal OUT1 from the internal circuit CIR1B to exceed the power supply voltage VDD2c. This may result in the transistor being destroyed if the potential difference between the gate and source (VDD2c) of the PMOS transistor in the internal circuit CIR2A that receives the input signal IN2 exceeds the withstand voltage of the transistor.

[0025] (First embodiment) FIG. 2 shows an example of a semiconductor device in the first embodiment. The same elements as those in FIG. 1 are given the same reference numerals, and detailed description is omitted. The semiconductor device SEM1 shown in FIG. 2, like the semiconductor device SEM0 in FIG. 1, has a plurality of semiconductor chips CP1, CP2, and CP3 (chiplets) mounted on a silicon interposer INTP, and has a so-called 2.5-dimensional mounting form. The silicon interposer INTP is an example of a substrate. The chip CP1 is an example of a first semiconductor chip, and the chip CP2 is an example of a second semiconductor chip.

[0026] The circuit configuration of the chips CP1, CP2, and CP3 is the same as that shown in Fig. 1. The values ​​of the power supply voltages VDD1, VDD2, and VDD3 may be the same as each other, or may be different from each other to the extent that voltage level conversion of signals transmitted between the chips CPx is not required. If measures are taken to prevent ESD current from flowing into each chip CPx in the process of mounting each chip CPx on the silicon interposer ITNP, each clamp circuit CLMPx does not need to be formed in each chip CPx.

[0027] The silicon interposer INTP has clamp circuits CLMP21, CLMP22, and CLMP23 added to the configuration of FIG. 1. The clamp circuit CLMP21 is disposed between the ground line VSS and the power supply line VDD1. The clamp circuit CLMP22 is disposed between the ground line VSS and the power supply line VDD2. The clamp circuit CLMP31 is disposed between the ground line VSS and the power supply line VDD3. Hereinafter, when the clamp circuits CLMP21, CLMP22, CLMP23, etc. provided in the silicon interposer INTP are described without distinction, they are also referred to as clamp circuits CLMP2x.

[0028] The ground line VSS is an example of a first substrate power line. The power lines VDD1 and VDD2 of the silicon interposer ITNP are examples of a second substrate power line and a third substrate power line, respectively. The clamp circuit CLMP21 is an example of a first substrate clamp circuit. The clamp circuit CLMP22 is an example of a second substrate clamp circuit.

[0029] The ground line VSS1c of the chip CP1 is an example of a first chip power line, the power line VDD1c of the chip CP1 is an example of a second chip power line, the ground line VSS2c of the chip CP2 is an example of a third chip power line, and the power line VDD2c of the chip CP2 is an example of a fourth chip power line.

[0030] The internal circuits CIR1A and CIR1B are an example of a first circuit that is a circuit to be protected from ESD. The internal circuits CIR2A and CIR2B are an example of a second circuit that is a circuit to be protected. The clamp circuit CLMP1 is an example of a first chip clamp circuit, and the clamp circuit CLMP2 is an example of a second chip clamp circuit. The size of the clamp circuit CLMPx of each chip CPx is smaller than the size of the clamp circuit CLMP2x of the interposer ITNP. The size of the clamp circuit CLMPx is described in FIG. 5.

[0031] In the semiconductor device SEM1, for example, in a human body model, when a positive ESD voltage is applied from the external power supply terminal VDD1 with respect to the external power supply terminal VDD2 as a reference (ESD application), an ESD current flows through the path indicated by the dashed arrow in Fig. 2. As shown in Fig. 2, by forming clamp circuits CLMP21-CLMP23 between each of the power supply lines VDD1-VDD3 and the ground line VSS in the silicon interposer ITNP, it is possible to prevent the ESD current from flowing into each chip CPx, and to prevent damage to elements in each chip CPx.

[0032] Fig. 3 shows, in a cross-sectional view, an outline of the connection between the silicon interposer INTP and each chip CPx in Fig. 2. The bumps BMP connected to each chip CPx are electrically connected to external terminals EXT via wiring in the silicon interposer ITNP, or are connected to other chips via the bumps BMP and wiring in the silicon interposer ITNP.

[0033] Fig. 4 shows an example of the internal circuits CIR1B and CIR2A mounted on the semiconductor chips CP1 and CP2 of Fig. 2. For example, the internal circuit CIR1B has an output buffer including two inverters IV1 connected in series, receives an input signal IN1 at the front-stage inverter IV1A, and outputs an output signal OUT1 from the rear-stage inverter IV1B.

[0034] For example, the internal circuit CIR2A has an input buffer including two inverters IV2 connected in series, receives an input signal IN2 at the front-stage inverter IV2A, and outputs an output signal OUT2 from the rear-stage inverter IV2B. Note that the chip CP1 may be equipped with circuits other than the output buffer, and the chip CP2 may be equipped with circuits other than the input buffer. Also, a signal may be transmitted from the output buffer formed on the chip CP2 to the input buffer formed on the chip CP1.

[0035] Fig. 5 shows an example of the clamp circuit CLMP21 of Fig. 2. Note that the clamp circuits CLMP22 and CLMP23 may use the same circuit as that shown in Fig. 5. The clamp circuit CLMP21 is formed using a PMOS transistor PM1 or an NMOS transistor NM1.

[0036] The clamp circuit CLMP21 in which the PMOS transistor PM1 is used includes a capacitor C1, a resistor R1, an inverter IV3, and a PMOS transistor PM1. The capacitor C1 and the resistor R1 are connected in series between a power supply line VDD1 and a ground line VSS via a node ND1, and function as an RC time constant circuit. The input of the inverter IV3 is connected to the node ND1, and the output is connected to the gate of the PMOS transistor PM1. The source and substrate of the PMOS transistor PM1 are connected to the power supply line VDD1, and the drain is connected to the ground line VSS.

[0037] In the clamp circuit CLMP21 using a PMOS transistor, during system operation of the semiconductor device SEM1, the input of the inverter IV3 is pulled down to a low level via the resistor R1, and the inverter IV3 outputs a high level. The PMOS transistor PM1 receives a high level at its gate and turns off. During an ESD event in which an ESD voltage is applied to the power supply line VDD1, the input of the inverter IV3 becomes a high level due to the coupling action of the capacitor C1, and outputs a low level. The PMOS transistor PM1 receives a high level at its source and a low level at its gate and turns on, passing an ESD current from the power supply line VDD1 to the ground line VSS.

[0038] The clamp circuit CLMP21, which uses an NMOS transistor, includes a resistor R1, a capacitor C1, an inverter IV3, and an NMOS transistor NM1. The resistor R1 and the capacitor C1 are connected in series between a power supply line VDD1 and a ground line VSS via a node ND1, and function as an RC time constant circuit. The inverter IV3 has an input connected to the node ND1 and an output connected to the gate of the NMOS transistor NM1. The NMOS transistor NM1 has a drain connected to the power supply line VDD1, and a source and a substrate connected to the ground line VSS.

[0039] In the clamp circuit CLMP21 using an NMOS transistor, during system operation of the semiconductor device SEM1, the input of the inverter IV3 is pulled up to a high level via a resistor R1, and outputs a low level. The NMOS transistor NM1 receives a low level at its gate and turns off. During an ESD event in which an ESD voltage is applied to the power supply line VDD1, the input of the inverter IV3 is regarded as a low level due to the RC time constant of the resistor R1 and the capacitor C1, and the inverter IV3 outputs a high level. The NMOS transistor NM1 receives a low level at its source and a high level at its gate, and turns on, passing an ESD current from the power supply line VDD1 to the ground line VSS.

[0040] The clamp circuit CLMPx formed in each chip CPx is a circuit similar to the clamp circuit CLMP2x of the silicon interposer ITNP, and includes a transistor that passes a current when an overvoltage occurs due to ESD, and an RC time constant circuit. The size of the transistor in the clamp circuit CLMPx of each chip CPx is smaller than the size of the transistor in each clamp circuit CLMP2x of the silicon interposer ITNP. For example, the size of the transistor may be indicated by the gate width. Also, the RC time constant of the RC time constant circuit of the clamp circuit CLMPx of each chip CPx may be smaller than the RC time constant of the RC time constant circuit of each clamp circuit CLMP2x of the silicon interposer ITNP.

[0041] Fig. 6 shows an example of the layout of wiring and circuits formed in the silicon interposer ITNP and each chip CPx in Fig. 2. The ground line VSS and power supply lines VDD1, VDD2, VDD3 of the silicon interposer ITNP are arranged to extend in the Y direction at intervals in the X direction. The power supply lines VDD1, VDD2, VDD3 and the ground line VSS are arranged alternately. In addition, in the silicon interposer ITNP, a ground line VSS that connects the ground lines VSS extending in the Y direction to each other is arranged to extend in the X direction.

[0042] The clamp circuit CLMP21 of the silicon interposer ITNP is disposed in an area where the power supply line VDD1 and the ground line VSS of the silicon interposer ITNP are disposed, and is electrically connected to the power supply line VDD1 and the ground line VSS through the via VIA1. The position at which the clamp circuit CLMP21 is disposed is not limited to the position shown in Fig. 6, and may be any position that overlaps with the power supply line VDD1 and the ground line VSS of the silicon interposer ITNP in a plan view.

[0043] The clamp circuit CLMP22 is disposed in an area where the power supply line VDD2 and the ground line VSS of the silicon interposer ITNP are disposed, and is electrically connected to the power supply line VDD2 and the ground line VSS through a via VIA1. The position at which the clamp circuit CLMP22 is disposed is not limited to the position shown in Fig. 6, and may be any position that overlaps with the power supply line VDD2 and the ground line VSS of the silicon interposer ITNP in a plan view.

[0044] The clamp circuit CLMP23 is disposed in an area where the power supply line VDD3 and the ground line VSS of the silicon interposer ITNP are disposed, and is electrically connected to the power supply line VDD3 and the ground line VSS through a via VIA1. The position at which the clamp circuit CLMP23 is disposed is not limited to the position shown in Fig. 6, and may be any position that overlaps with the power supply line VDD3 and the ground line VSS of the silicon interposer ITNP in a plan view.

[0045] The chip CP1 is disposed in an area where the power supply line VDD1 and the ground line VSS of the silicon interposer ITNP are disposed. The power supply line VDD1c and the ground line VSS1c of the chip CP1 are disposed extending in the X direction at intervals in the Y direction, and are electrically connected to the power supply line VDD1 and the ground line VSS of the silicon interposer ITNP through vias VIA2, respectively. The clamp circuit CLMP1 of the chip CP1 is electrically connected to the power supply line VDD1c and the ground line VSS of the chip CP1 through vias VIA3. The position at which the clamp circuit CLMP1 is disposed is not limited to the position shown in FIG. 6, and may be any position that overlaps with the power supply line VDD1c and the ground line VSS1c of the chip CP1 in a plan view.

[0046] The chip CP2 is disposed in an area where the power supply line VDD2 and the ground line VSS of the silicon interposer ITNP are disposed. The power supply line VDD2c and the ground line VSS of the chip CP2 are disposed extending in the X direction at intervals in the Y direction, and are electrically connected to the power supply line VDD2 and the ground line VSS of the silicon interposer ITNP through vias VIA2. The clamp circuit CLMP2 of the chip CP2 is electrically connected to the power supply line VDD2c and the ground line VSS of the chip CP2 through vias VIA3. The position at which the clamp circuit CLMP2 is disposed is not limited to the position shown in FIG. 6, and may be any position that overlaps with the power supply line VDD2c and the ground line VSS of the chip CP2 in a plan view.

[0047] The chip CP3 is disposed in an area where the power supply line VDD3 and the ground line VSS of the silicon interposer ITNP are disposed. The power supply line VDD3c and the ground line VSS of the chip CP3 are disposed extending in the X direction at intervals in the Y direction, and are electrically connected to the power supply line VDD3 and the ground line VSS of the silicon interposer ITNP through vias VIA2, respectively. The clamp circuit CLMP3 of the chip CP3 is electrically connected to the power supply line VDD3c and the ground line VSS of the chip CP3 through vias VIA3. The position at which the clamp circuit CLMP3 is disposed is not limited to the position shown in FIG. 6, and may be any position that overlaps with the power supply line VDD3c and the ground line VSS of the chip CP3 in a plan view.

[0048] The via VIA1 is provided to connect the wiring of the silicon interposer ITNP to each clamp circuit CLMP2x. The via VIA2 is provided to connect the wiring of the silicon interposer ITNP to the wiring of each chip CPx. The via VIA3 is provided to connect the wiring of each chip CPx to each clamp circuit CLMPx.

[0049] The clamp circuit CLMPx of each chip CPx is smaller in scale than the clamp circuit CLMP2x of the interposer ITNP. Note that in each clamp circuit CLMPx, CLMP2x, the number of vias connected to the power supply line and the ground line, and the number of power supply lines and ground lines to be connected are not limited to those shown in FIG.

[0050] Fig. 7 shows, in a cross-sectional view, an outline of the structure of the silicon interposer INTP of Fig. 2. The silicon interposer ITNP has a substrate SUB and a plurality of wiring layers WL formed on the substrate SUB. The substrate SUB has a diffusion region DIF formed by impurity injection, and a transistor structure is formed by the diffusion region DIF and a gate electrode GT formed on the diffusion region DIF via a gate insulating film.

[0051] The capacitor C1 (FIG. 5) of each clamp circuit CLMP2x of the interposer ITNP in FIG. 2 may be formed, for example, by a capacitive element using a gate capacitance included in a transistor structure formed on the substrate SUB. The resistor R1 (FIG. 5) of each clamp circuit CLMP2x may be formed, for example, by a resistive element using a diffusion region DIF included in a transistor structure formed on the substrate SUB. Alternatively, each of the capacitor C1 or resistor R1 of each clamp circuit CLMP2x may be formed by a capacitance (comb capacitance) or a wiring resistance due to wiring provided in the wiring layer WL. Furthermore, a diode or a thyristor may be formed using a transistor structure.

[0052] As described above, in the first embodiment, by forming clamp circuits CLMP21-CLMP23 between each power supply line VDD1-VDD3 and the ground line VSS in the silicon interposer ITNP, it is possible to prevent ESD current from flowing into the chips CP1-CP3, and to prevent damage to elements in the chips CP1-CP3.

[0053] The clamp circuits CLMP1-CLMP3 formed in the chips CP1-CP3, respectively, can suppress damage to the internal circuits CIR1x, CIR2x, CIR3x caused by ESD current flowing into the chips CP1-CP3 during the process of mounting the chips CP1-CP3 on the silicon interposer ITNP.

[0054] By mounting the clamp circuits CLMP1-CLMP3, which are smaller in scale than the clamp circuits CLMP21-CLMP23, on the chips CP1-CP3, respectively, it is possible to suppress an increase in the chip size of the chips CP1-CP3.

[0055] Second embodiment Fig. 8 shows an example of a semiconductor device in the second embodiment. The same elements as those in Fig. 2 are given the same reference numerals, and detailed description is omitted. The semiconductor device SEM2 shown in Fig. 8 has a plurality of semiconductor chips CP1, CP2, and CP3 (chiplets) mounted on a silicon interposer INTP, similar to the semiconductor device SEM1 in Fig. 2, and has a so-called 2.5-dimensional mounting form.

[0056] In the semiconductor device SEM2, the chip CP1 is electrically connected to a ground line VSS1 of the silicon interposer ITNP, and the chips CP2 and CP3 are electrically connected to a ground line VSS2 of the silicon interposer ITNP. Therefore, the semiconductor device SEM2 has external ground terminals VSS1 and VSS2. The silicon interposer ITNP has a ground line VSS1 electrically connected to the external ground terminal VSS1, a ground line VSS2 electrically connected to the external ground terminal VSS2, and a bidirectional diode BID1 arranged between the ground lines VSS1 and VSS2. The bidirectional diode BID1 may be formed using the transistor structure on the substrate SUB shown in FIG. 7.

[0057] The clamp circuit CLMP21 is disposed between the ground line VSS1 and the power supply line VDD1 of the silicon interposer ITNP. The clamp circuit CLMP22 is disposed between the ground line VSS2 and the power supply line VDD2 of the silicon interposer ITNP. The clamp circuit CLMP23 is disposed between the ground line VSS2 and the power supply line VDD3 of the silicon interposer ITNP.

[0058] The ground line VSS1c of the chip CP1 is electrically connected to the ground line VSS1 of the silicon interposer ITNP via the bump BMP. The ground line VSS2c of the chip CP2 and the ground line VSS3c of the chip CP3 are electrically connected to the ground line VSS2 of the silicon interposer ITNP via the bump BMP. Other elements of the semiconductor device SEM2 are similar to the elements of the semiconductor device SEM1 of FIG.

[0059] The ground lines VSS1 and VSS2 of the silicon interposer ITNP are examples of a fourth substrate power line and a fifth substrate power line, respectively. The power line VDD3 of the silicon interposer ITNP is an example of a sixth substrate power line. The clamp circuit CLMP23 is an example of a third substrate clamp circuit. The bidirectional diode BID1 is an example of a first bidirectional diode. The ground line VSS3c of the chip CP3 is an example of a fifth chip power line, and the power line VDD3c of the chip CP3 is an example of a sixth chip power line.

[0060] By forming the bidirectional diode BID1 in the silicon interposer ITNP, when a potential difference occurs between the ground lines VSS1 and VSS2, a current can flow between them. This allows, for example, an ESD current to flow between the ground lines VSS1 and VSS2 when ESD occurs, and the ESD current can be discharged.

[0061] For example, in the human body model, when a positive ESD voltage is applied from the external power supply terminal VDD1 with respect to the external power supply terminal VDD2 as the reference (ESD application), an ESD current flows through a path including the bidirectional diode BID1, as indicated by the dashed arrow in Figure 8. This makes it possible to prevent the ESD current from flowing into each chip CPx, and thus to prevent damage to elements in each chip CPx.

[0062] In addition, when the bidirectional diode BID1 is not formed in the silicon interposer ITNP, for example, a bidirectional diode is formed in one of the chips CP1-CP3 in order to suppress the ESD current from flowing to each of the chips CP1-CP3. For example, when a bidirectional diode is formed in the chip CP1, the ground line VSS2 of the silicon interposer ITNP is electrically connected to the ground line VSS1c of the chip CP1 via the bump BMP (or TSV).

[0063] This may cause the number of bumps BMP (or TSV) to exceed the limit. Also, the chip size of the chip CP1 on which the bidirectional diode BID1 is formed increases, which increases the chip cost. The chip cost also increases due to a decrease in yield caused by the increase in chip size. Also, when each chip CPx is manufactured using advanced technology, there may be cases where a suitable bidirectional diode that can be mounted on the chip CPx is not available.

[0064] Fig. 9 shows an example of the layout of wiring and circuits formed on the silicon interposer ITNP and each of the chips CP1-CP3 of Fig. 8. The same elements as those in Fig. 6 are given the same reference numerals and detailed description will be omitted.

[0065] 9 is similar to the circuit arrangement of FIG. 6, except that the bidirectional diode BID1 is formed in the silicon interposer ITNP. The bidirectional diode BID1 is arranged in an area where the ground lines VSS1 and VSS2 are arranged, and is electrically connected to the ground lines VSS1 and VSS2 through the via VIA1. The ground line VSS2 of the silicon interposer INTP is connected to the ground line VSS2c of the chip CP2 and the ground line VSS3c of the chip CP3. The position where the bidirectional diode BID1 is arranged is not limited to the position shown in FIG. 9, and may be any position that overlaps with the ground lines VSS1 and VSS2 of the silicon interposer ITNP in a plan view.

[0066] As described above, the second embodiment can also provide the same effects as the first embodiment. For example, in the silicon interposer ITNP, a clamp circuit CLMP21 is formed between the power supply line VDD1 and the ground line VSS1, and clamp circuits CLMP22 and CLMP23 are formed between the power supply lines VDD2 and VDD3 and the ground line VSS2, respectively. This makes it possible to prevent the ESD current from flowing into the chips CP1-CP3, and to prevent the destruction of elements in the chips CP1-CP3.

[0067] Furthermore, in the second embodiment, when the chips CP1-CP3 are connected to different ground lines VSS1 and VSS2, a bidirectional diode BID1 is formed in the silicon interposer ITNP to electrically connect the ground lines VSS1 and VSS2 to each other. This allows the ESD current to flow between the ground lines VSS1 and VSS2 of the silicon interposer ITNP when ESD occurs, and the ESD current can be discharged. As a result, the ESD current can be prevented from flowing into the chips CP1-CP3, and destruction of elements in the chips CP1-CP3 can be prevented.

[0068] Third embodiment Fig. 10 shows an example of a semiconductor device in the third embodiment. The same elements as those in Fig. 8 are given the same reference numerals, and detailed description is omitted. The semiconductor device SEM3 shown in Fig. 10 has a plurality of semiconductor chips CP1, CP2, and CP3 (chiplets) mounted on a silicon interposer INTP, similar to the semiconductor device SEM2 in Fig. 8, and has a so-called 2.5-dimensional mounting form.

[0069] In the semiconductor device SEM3, the chip CP1 is electrically connected to the ground line VSS1 of the silicon interposer ITNP, the chip CP2 is electrically connected to the ground line VSS2 of the silicon interposer ITNP, and the chip CP3 is electrically connected to the ground line VSS3 of the silicon interposer ITNP. Therefore, the semiconductor device SEM3 has external ground terminals VSS1, VSS2, and VSS3. The silicon interposer ITNP has a ground line VSS1 electrically connected to the external ground terminal VSS1, a ground line VSS2 electrically connected to the external ground terminal VSS2, and a ground line VSS3 electrically connected to the external ground terminal VSS3.

[0070] The silicon interposer ITNP also has a bidirectional diode BID1 arranged between the ground lines VSS1 and VSS2, a bidirectional diode BID2 arranged between the ground lines VSS2 and VSS3, and a bidirectional diode BID3 arranged between the ground lines VSS3 and VSS1. Each of the bidirectional diodes BID1-BID3 may be formed using the transistor structure on the substrate SUB shown in Fig. 7. A clamp circuit CLMP23 is arranged between the power supply line VDD3 and the ground line VSS3 of the silicon interposer ITNP.

[0071] The ground line VSS3c of the chip CP3 is electrically connected to the ground line VSS3 of the silicon interposer ITNP via the bump BMP. Other elements of the semiconductor device SEM3 are similar to the elements of the semiconductor device SEM2 in FIG.

[0072] As in Fig. 8, for example, in the human body model, when a positive ESD voltage is applied from the external power supply terminal VDD1 with respect to the external power supply terminal VDD2 as the reference (ESD application), an ESD current flows through a path including the bidirectional diode BID1 indicated by the dashed arrow in Fig. 10. This makes it possible to prevent the ESD current from flowing into each chip CP, and to prevent damage to elements in each chip CP.

[0073] Fig. 11 shows an example of the layout of wiring and circuits formed in the silicon interposer ITNP and each chip CP1-CP3 of Fig. 10. The same elements as those in Fig. 6 and Fig. 9 are given the same reference numerals and detailed description is omitted. Fig. 11 is the same as the circuit layout in Fig. 9, except that bidirectional diodes BID2 and BID3 are formed in the silicon interposer ITNP.

[0074] The bidirectional diode BID2 is disposed in an area where the ground lines VSS2 and VSS3 are disposed, and is electrically connected to the ground lines VSS2 and VSS3 through the via VIA1. The bidirectional diode BID3 is disposed in an area where the ground lines VSS3 and VSS1 are disposed, and is electrically connected to the ground lines VSS3 and VSS1 through the via VIA1. The position where the bidirectional diode BID2 is disposed is not limited to the position shown in FIG. 11, and may be any position that overlaps the ground lines VSS2 and VSS3 of the silicon interposer ITNP in a planar view. The position where the bidirectional diode BID3 is disposed is not limited to the position shown in FIG. 11, and may be any position that overlaps the ground lines VSS3 and VSS1 of the silicon interposer ITNP in a planar view.

[0075] As described above, the third embodiment can also provide the same effects as the first and second embodiments. For example, in the silicon interposer ITNP, clamp circuits CLMP21-CLMP23 are formed between the power supply lines VDD1-VDD3 and the ground lines VSS1-VSS3, respectively. This makes it possible to prevent the ESD current from flowing into the chips CP1-CP3, and to prevent the destruction of elements in the chips CP1-CP3.

[0076] When the chips CP1-CP3 are electrically connected to the ground lines VSS1-VSS3 of the silicon interposer ITNP, bidirectional diodes BID1-BID3 that electrically connect the ground lines VSS1-VSS3 to each other are formed in the silicon interposer ITNP. This allows the ESD current to flow between the ground lines VSS1-VSS3 of the silicon interposer ITNP when ESD occurs, and the ESD current can be discharged. As a result, the ESD current can be prevented from flowing into the chips CP1-CP3, and damage to elements in the chips CP1-CP3 can be prevented.

[0077] (Fourth embodiment) Fig. 12 shows an example of a semiconductor device in the fourth embodiment. The same elements as those in Fig. 10 are given the same reference numerals, and detailed description is omitted. The semiconductor device SEM4 shown in Fig. 12 has a plurality of semiconductor chips CP1, CP2, and CP3 (chiplets) mounted on a silicon interposer INTP, similar to the semiconductor device SEM3 in Fig. 10, and has a so-called 2.5-dimensional mounting form.

[0078] The interposer ITNP of the semiconductor device SEM4 has clamp circuits CLMP24 and CLMP25 arranged between the ground line VSS1 and the power supply lines VDD2 and VDD3, respectively. The interposer ITNP has clamp circuits CLMP26 and CLMP27 arranged between the ground line VSS2 and the power supply lines VDD1 and VDD3, respectively. The interposer ITNP has clamp circuits CLMP28 and CLMP29 arranged between the ground line VSS3 and the power supply lines VDD1 and VDD2, respectively. That is, the interposer ITNP has a crossed domain clamp circuit CLMP2x. Other elements of the semiconductor device SEM4 are similar to those of the semiconductor device SEM3 of FIG.

[0079] The ground line VSS1 of the silicon interposer INTP is an example of a fourth substrate power line, the ground line VSS2 of the silicon interposer INTP is an example of a seventh substrate power line, and the ground line VSS3 of the silicon interposer INTP is an example of an eighth substrate power line. The clamp circuit CLMP24 is an example of a fourth substrate clamp circuit, and the clamp circuit CLMP25 is an example of a fifth substrate clamp circuit. The clamp circuit CLMP26 is an example of a sixth substrate clamp circuit, and the clamp circuit CLMP27 is an example of a seventh substrate clamp circuit. The clamp circuit CLMP28 is an example of an eighth substrate clamp circuit, and the clamp circuit CLMP29 is an example of a ninth substrate clamp circuit.

[0080] As described above, the fourth embodiment can also provide the same effects as the first to third embodiments. For example, when ESD occurs, it is possible to prevent an ESD current from flowing through the chips CP1-CP3, and to prevent damage to elements in the chips CP1-CP3.

[0081] Fifth embodiment Fig. 13 shows an example of a semiconductor device in the fifth embodiment. The same elements as those in Fig. 2 are given the same reference numerals, and detailed description is omitted. The semiconductor device SEM5 shown in Fig. 13 has a plurality of semiconductor chips CP1, CP2, and CP3 (chiplets) mounted on a silicon interposer INTP, similar to the semiconductor device SEM1 in Fig. 2, and has a so-called 2.5-dimensional mounting form.

[0082] The interposer ITNP has a signal line SIG1 electrically connected to an external signal terminal SIG1 and an input terminal of an internal circuit CIR1A of the chip CP1, and a protection circuit ESD1 against electrostatic discharge arranged between the signal line SIG1 and a ground line VSS. The interposer ITNP has a signal line SIG2 electrically connected to an external signal terminal SIG2 and an input terminal of an internal circuit CIR2A of the chip CP2, and a protection circuit ESD2 against electrostatic discharge arranged between the signal line SIG2 and a ground line VSS. The interposer ITNP has a signal line SIG3 electrically connected to an external signal terminal SIG3 and an input terminal of an internal circuit CIR3A of the chip CP3, and a protection circuit ESD3 against electrostatic discharge arranged between the signal line SIG3 and a ground line VSS.

[0083] The external signal terminal SIG1 is an example of a first signal terminal, and the external signal terminal SIG2 is an example of a second signal terminal. The signal line SIG1 is an example of a first signal line, and the signal line SIG2 is an example of a second signal line. The internal circuit CIR1A is an example of a first circuit, and the input terminal of the internal circuit CIR1A is an example of a first input terminal. The internal circuit CIR2A is an example of a second circuit, and the input terminal of the internal circuit CIR2A is an example of a second input terminal. The protection circuit ESD1 is an example of a first protection circuit, and the protection circuit ESD2 is an example of a second protection circuit.

[0084] The internal circuit CIR1A of the chip CP1 receives the signal SIG1 supplied to the external signal terminal SIG1 via the signal line SIG1 of the silicon interposer ITNP, and outputs the signal to the internal circuit CIR1B. The internal circuit CIR2A of the chip CP2 receives the signal SIG2 supplied to the external signal terminal SIG2 via the signal line SIG2 of the silicon interposer ITNP, receives the input signal IN2 from the chip CP1, and outputs the signal to the internal circuit CIR2B. The internal circuit CIR3A of the chip CP3 receives the signal SIG3 supplied to the external signal terminal SIG3 via the signal line SIG3 of the silicon interposer ITNP, and outputs the signal to the internal circuit CIR3B.

[0085] The protection circuit ESD1 is disposed between the signal line SIG1 and the ground line VSS, and during an ESD event in which an ESD voltage is applied to the external signal terminal SIG1, an ESD current flows to the ground line VSS to protect the internal circuit CIR1A from destruction. The protection circuit ESD2 is disposed between the signal line SIG2 and the ground line VSS, and during an ESD event in which an ESD voltage is applied to the external signal terminal SIG2, an ESD current flows to the ground line VSS to protect the internal circuit CIR2A from destruction. The protection circuit ESD3 is disposed between the signal line SIG3 and the ground line VSS, and during an ESD event in which an ESD voltage is applied to the external signal terminal SIG3, an ESD current flows to the ground line VSS to protect the internal circuit CIR3A from destruction.

[0086] Figure 14 shows an example of the ESD protection circuit ESD1 of Figure 13. The ESD protection circuits ESD2 and ESD3 of Figure 13 are also similar to Figure 14. The upper side of Figure 14 shows the circuit configuration of the ESD protection circuit ESD1, and the lower side of Figure 14 shows an example of the cross-sectional structure of the NMOS transistor NM2 included in the ESD protection circuit ESD1.

[0087] The ESD protection circuit ESD1 has a resistor R2 and an NMOS transistor NM2 arranged in series between a signal line SIG1 and a ground line VSS. The gate, source, and substrate of the NMOS transistor NM2 are connected to the ground line VSS, and the drain of the NMOS transistor NM2 is electrically connected to the signal line SIG1 via the resistor R2.

[0088] As a result, the NMOS transistor NM2 functions as a diode D2 with its anode connected to the ground line VSS and its cathode connected to the signal line SIG1. As a result, a negative ESD current can flow from the ground line VSS to the signal line SIG1 via the diode D2. In addition, the NMOS transistor NM2 functions as a parasitic lateral NPN bipolar transistor LNPN consisting of its source, substrate, and drain. The base of the parasitic lateral NPN bipolar transistor LNPN is electrically connected to the ground line VSS via the resistor R3. As a result, a positive ESD current can flow from the signal line SIG1 to the ground line VSS via the parasitic lateral NPN bipolar transistor LNPN.

[0089] A fin field effect transistor (FinFET) may be arranged in place of the NMOS transistor NM2, which is a planar transistor. A thyristor element may be used in place of the NMOS transistor NM2. The resistor R2 may be omitted from each of the ESD protection circuits ESD1, ESD2, and ESD3. The gate GT of the NMOS transistor NM2 may be connected to a control circuit that controls the operation of the ESD protection circuit, instead of the ground line VSS.

[0090] Figure 15 shows another example of an ESD protection circuit. The ESD protection circuit ESD4 shown in Figure 15 is implemented as a fail-safe I / O buffer in a signal cell. The ESD protection circuit ESD4 is realized by an ESD protection diode formed in the signal cell and a parasitic bipolar transistor (parasitic diode) formed in the NMOS transistor NM3 of the output buffer OBUF. The output buffer OBUF has a PMOS transistor PM3 and an NMOS transistor NM3 connected in series between the I / O power supply line VDDIO and the ground line VSS via a node of the external signal terminal PAD.

[0091] The power cell has an ESD clamp circuit ESDCLMP arranged between the external power supply terminal VDDIO and the external ground terminal VSS. For example, when a positive ESD voltage is applied to the external signal terminal PAD with respect to the power supply terminal VDDIO, an ESD current flows from the external signal terminal PAD to the external power supply line VDDIO via the parasitic bipolar transistor, the ground line VSS, and the clamp circuit ESDCLMP, as shown by the thick solid arrow. Thus, the operation of the parasitic bipolar transistor is necessary for ESD countermeasures when a positive ESD voltage is applied to the fail-safe I / O buffer.

[0092] When a negative ESD voltage is applied to the external signal terminal PAD with respect to the power supply terminal VDDIO, an ESD current flows from the external power supply terminal VDDIO to the external signal terminal PAD via the clamp circuit ESDCLMP, the ground line VSS, and the ESD protection diode, as indicated by the thick dashed arrow.

[0093] The discharge path when a positive or negative ESD voltage is applied to the signal pad PAD with respect to the ground terminal VSS is also the same as the discharge path shown in Fig. 15. For example, in order to provide ESD protection between the external signal terminal PAD and the external ground terminal VSS, a thyristor element may be added to the signal cell in addition to the output buffer OBUF.

[0094] As described above, the fifth embodiment can also provide the same effects as the first embodiment. For example, the clamp circuits CLMP21-CLMP23 of the silicon interposer ITNP can prevent the ESD current from flowing to the chips CP1-CP3, and can prevent the elements in the chips CP1-CP3 from being destroyed.

[0095] Furthermore, in the fifth embodiment, by arranging the ESD protection circuits ESD1-ESD3 in the silicon interposer ITNP, it is possible to prevent the ESD current from flowing through the chips CP1-CP3 even when an ESD voltage is applied to an external signal terminal through which a signal is input or output to the chips CP1-CP3. As a result, it is possible to prevent the destruction of elements in the chips CP1-CP3.

[0096] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without departing from the spirit of the present invention, and can be appropriately determined according to the application form. [Explanation of symbols]

[0097] BID1, BID2, BID3 Bidirectional diodes BM Bump C1 Capacitor CIR1A, CIR1B internal circuit CIR2A, CIR2B internal circuit CIR3A, CIR3B internal circuit CLMP1, CLMP2, CLMP3 clamp circuits CLMP21, CLMP22, CLMP23 Clamp Circuits CLMP24, CLMP25, CLMP26 clamp circuits CLMP27, CLMP28, CLMP29 Clamp Circuits CP1, CP2, CP3 Semiconductor Chips D2 Diode DIF Diffusion Area ESD1, ESD2, ESD3, ESD4 ESD protection circuits ESDCLMP Clamp circuit EXT External terminal GT gate electrode IN2 input signal line INTP Silicon Interposer IV1, IV2, IV3 inverters LNPN Parasitic Lateral NPN Bipolar Transistor ND1 Node NM1, NM2, NM3 NMOS transistors OBUF Output Buffer OUT1, OUT2 output signal PAD External signal terminal PM1, PM3 PMOS transistors R1, R2, R3 resistance SEM0, SEM1, SEM2, SEM4, SEM5 Semiconductor device SIG, SIG1, SIG2, SIG3 signal line SUB board VDD1, VDD2, VDD3 power lines VDD1c, VDD2c, VDD3c power lines VDDIO External power supply pin VIA1, VIA2, BIA3 vias VSS external ground terminal, ground wire VSS1, VSS2, VSS3 ground wire VSS1c, VSS2c, VSS3c ground wire WL wiring layer

Claims

1. A substrate; a first substrate power line provided on the substrate, a second substrate power line to which a voltage different from that of the first substrate power line is supplied, and a third substrate power line to which a voltage different from that of the first substrate power line is supplied; a first substrate clamp circuit provided on the substrate and disposed between the first substrate power line and the second substrate power line; a second substrate clamp circuit provided on the substrate and disposed between the first substrate power line and the third substrate power line; a first semiconductor chip and a second semiconductor chip provided on the substrate; a first chip power supply line provided in the first semiconductor chip and electrically connected to the first substrate power supply line; a second chip power supply line provided in the first semiconductor chip and electrically connected to the second substrate power supply line; a first circuit provided in the first semiconductor chip and disposed between the first chip power line and the second chip power line; a third chip power supply line provided in the second semiconductor chip and electrically connected to the first substrate power supply line; a fourth chip power supply line provided in the second semiconductor chip and electrically connected to the third substrate power supply line; a second circuit provided in the second semiconductor chip and disposed between the third chip power line and the fourth chip power line; A semiconductor device in which a signal output from the first circuit is input to the second circuit.

2. a first chip clamp circuit provided in the first semiconductor chip and disposed between the first chip power line and the second chip power line; a second chip clamp circuit provided in the second semiconductor chip and disposed between the third chip power line and the fourth chip power line; The semiconductor device according to claim 1 .

3. the first substrate clamp circuit, the second substrate clamp circuit, the first tip clamp circuit, and the second tip clamp circuit each have an element that passes a current when an overvoltage occurs; The size of the elements of the first tip clamp circuit and the second tip clamp circuit is smaller than the size of the elements of the first substrate clamp circuit and the second substrate clamp circuit. The semiconductor device according to claim 2 .

4. the first substrate clamp circuit, the second substrate clamp circuit, the first tip clamp circuit and the second tip clamp circuit further include an RC time constant circuit including a resistor and a capacitor; The RC time constant of the first tip clamp circuit and the second tip clamp circuit is smaller than the RC time constant of the first substrate clamp circuit and the second substrate clamp circuit. The semiconductor device according to claim 3 .

5. a first bidirectional diode provided on the substrate; the first substrate power line includes a fourth substrate power line and a fifth substrate power line electrically connected via the first bidirectional diode; the first chip power line is electrically connected to the fourth substrate power line; The third chip power line is electrically connected to the fifth substrate power line. The semiconductor device according to claim 1 .

6. the first substrate clamp circuit is disposed between the fourth substrate power line and the second substrate power line; The second substrate clamp circuit is disposed between the fifth substrate power line and the third substrate power line. The semiconductor device according to claim 5 .

7. a sixth substrate power supply line provided on the substrate and supplied with a voltage different from that of the first substrate power supply line; a third semiconductor chip provided on the substrate; a fifth chip power supply line provided in the third semiconductor chip and electrically connected to the fifth substrate power supply line; a sixth chip power supply line provided in the third semiconductor chip and electrically connected to the sixth substrate power supply line; a third circuit provided in the third semiconductor chip and disposed between the fifth chip power line and the sixth chip power line; a third substrate clamp circuit provided on the substrate and disposed between the fifth substrate power supply line and the sixth substrate power supply line; The semiconductor device according to claim 5 .

8. a second bidirectional diode and a third bidirectional diode provided on the substrate; the fifth substrate power line includes a seventh substrate power line and an eighth substrate power line electrically connected via the second bidirectional diode, the fourth substrate power line is electrically connected to an eighth substrate power line via the third bidirectional diode; the third chip power line is electrically connected to the seventh substrate power line; The fifth chip power line is electrically connected to the eighth substrate power line. The semiconductor device according to claim 7.

9. a fourth substrate clamp circuit provided on the substrate and disposed between the fourth substrate power supply line and the third substrate power supply line; a fifth substrate clamp circuit provided on the substrate and disposed between the fourth substrate power supply line and the sixth substrate power supply line; a sixth substrate clamp circuit provided on the substrate and disposed between the seventh substrate power line and the second substrate power line; a seventh substrate clamp circuit provided on the substrate and disposed between the seventh substrate power supply line and the sixth substrate power supply line; an eighth substrate clamp circuit provided on the substrate and disposed between the eighth substrate power line and the second substrate power line; a ninth substrate clamp circuit provided on the substrate and disposed between the eighth substrate power line and the third substrate power line. The semiconductor device according to claim 8.

10. a first signal terminal and a second signal terminal provided on the substrate; a first signal line provided on the substrate and electrically connecting the first signal terminal and a first input terminal of the first circuit; a second signal line provided on the substrate and electrically connecting the second signal terminal and a second input terminal of the second circuit; a first protection circuit against electrostatic discharge disposed between the first signal line and the first substrate power line; a second protection circuit against electrostatic discharge disposed between the second signal line and the first substrate power line; The semiconductor device according to claim 1 .

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