Array substrate and display panel

Abstract

To protect a semiconductor film in a TFT while suppressing the decrease in an opening ratio.SOLUTION: An array substrate 21 includes a first TFT 27 including a first insulating film 31, a first semiconductor film 27D disposed in a layer thereon, a second insulating film 33 disposed in a layer thereon, a first gate electrode 27E disposed in a layer thereon, and a first source electrode 27B and a first drain electrode 27C connected to the first semiconductor film 27D through a first contact hole 36 penetrating a third insulating film 34 disposed in a layer thereon. The first TFT 27 includes an auxiliary film 32 that is disposed at a position overlapping with at least a lower surface of the first source electrode 27B and the first drain electrode 27C in the layer above or below the first semiconductor film 27D, and that is formed of a non-metal material.SELECTED DRAWING: Figure 5

Description

[Technical field]

[0001] The present technology relates to an array substrate and a display panel. [Background technology]

[0002] It is known that display panels such as liquid crystal panels and organic EL (electro-luminescence) panels use TFTs (thin film transistors) as switching elements. TFTs are formed by laminating various thin films on an array substrate (active matrix substrate, TFT substrate) that constitutes the display panel. Patent Document 1 discloses that two types of TFTs are formed on the same substrate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2020-202223 A

[0004] The TFT described in Patent Document 1 includes a first TFT having a channel made of a first polysilicon and a second polysilicon made by imparting electrical conductivity to the first polysilicon as a source and drain, and a second TFT having a channel made of an oxide semiconductor and a source and drain made of an oxide semiconductor by imparting electrical conductivity. In addition, a metal protective film is formed on the oxide semiconductor film of the second TFT at a portion connected to the drain electrode and the source electrode. The metal protective film is provided to protect the oxide semiconductor film from hydrofluoric acid when the through holes for the drain electrode and the source electrode are cleaned with hydrofluoric acid. This makes it possible to suppress deterioration of the oxide semiconductor film. Summary of the Invention [Problem to be solved by the invention]

[0005] When providing the above-mentioned metal protective film, it is necessary to form the metal protective film large, including a margin, in consideration of the variation in the planar pattern during manufacturing and the positional deviation between the planar patterns of each part. However, if the planar size of the metal protective film is increased, there is a concern that the aperture ratio will decrease because the metal material has a light-shielding property.

[0006] The technology described in this specification was completed based on the above-mentioned circumstances, and has an object to protect the semiconductor film of the TFT while suppressing the decrease in the aperture ratio. [Means for solving the problem]

[0007] (1) An array substrate related to the technology described in the present specification includes a first TFT having: a first insulating film arranged on an upper layer side of an insulating substrate, a first semiconductor film arranged on the first insulating film, a second insulating film arranged on the first semiconductor film, a first gate electrode arranged on the second insulating film and overlapping with the first semiconductor film, a third insulating film arranged on the first gate electrode, a first source electrode and a first drain electrode made of a metal layer arranged on the third insulating film and connected to the first semiconductor film through a first contact hole penetrating the third insulating film, and an auxiliary film made of a non-metallic material arranged in a position overlapping at least lower surfaces of the first source electrode and the first drain electrode in an upper layer or a lower layer of the first semiconductor film.

[0008] (2) In addition to the above (1), the array substrate may be configured such that the auxiliary film is disposed above the first semiconductor film and is made of a transparent conductive material.

[0009] (3) In addition to the above (1), the array substrate may be configured such that the auxiliary film is disposed below the first semiconductor film and is made of the same material as the first semiconductor film.

[0010] (4) In addition to any one of (1) to (3) above, the array substrate may further include a first light-shielding portion on the lower layer side of the first insulating film, the first light-shielding portion overlapping the first gate electrode but not overlapping the lower surfaces of the first source electrode and the first drain electrode.

[0011] (5) In addition to any one of (1) to (4) above, the array substrate may be such that the first TFT is a TFT of a double gate structure further having a second gate electrode arranged below the first insulating film.

[0012] (6) In addition to the above (5), the array substrate may further include a second TFT having a second semiconductor film, a gate insulating film arranged on an upper layer of the second semiconductor film, a third gate electrode arranged on the upper layer of the gate insulating film and made of the same material as the second gate electrode, the first insulating film arranged on the upper layer of the third gate electrode, the third insulating film arranged on the upper layer of the first insulating film, and a second source electrode and a second drain electrode connected to the second semiconductor film through a second contact hole penetrating the third insulating film, the first insulating film, and the gate insulating film from the upper layer of the third insulating film, wherein the first semiconductor film of the first TFT is made of an oxide semiconductor material, and the second semiconductor film of the second TFT is made of a polysilicon semiconductor material.

[0013] (7) A display panel related to the technology described in this specification includes an array substrate as described in any one of (1) to (6) above, an opposing substrate arranged opposite the array substrate with an internal space between them, and a liquid crystal layer sealed in the internal space. Effect of the Invention

[0014] According to the technique described in this specification, it is possible to protect the semiconductor film of the TFT while suppressing a decrease in the aperture ratio. [Brief description of the drawings]

[0015] [Figure 1] 1 is a schematic plan view of a liquid crystal panel according to a first embodiment; [Diagram 2] Cross-section of a liquid crystal panel [Diagram 3] A circuit diagram showing a pixel arrangement in a display area of ​​an array substrate. [Figure 4] 1 is a cross-sectional view of the first TFT and the second TFT of an array substrate; [Diagram 5] Enlarged cross-sectional view of the first TFT and its surroundings in Figure 4 [Figure 6A] 5A to 5C are diagrams showing a manufacturing process of the array substrate shown in FIG. [Figure 6B] FIG. 6B is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 6A; [Figure 6C] FIG. 6B is a diagram showing a manufacturing process of the array substrate; [Figure 6D] FIG. 6C is a diagram showing a manufacturing process of the array substrate; [Figure 6E] FIG. 6C is a diagram showing a manufacturing process of the array substrate, subsequent to FIG. 6D. [Figure 6F] FIG. 6C is a diagram showing a manufacturing process of the array substrate, subsequent to FIG. 6E. [Figure 7A] FIG. 1 is a diagram showing a manufacturing process of an array substrate according to Comparative Example 1. [Figure 7B] FIG. 7B is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 7A; [Figure 8] FIG. 11 is an enlarged cross-sectional view of a first TFT of an array substrate according to a second embodiment. [Figure 9A] 9A to 9C are diagrams showing a manufacturing process of the array substrate shown in FIG. [Figure 9B] FIG. 9B is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 9A; [Figure 9C] FIG. 9C is a diagram showing a manufacturing process of the array substrate subsequent to FIG. 9B. [Figure 9D] FIG. 9C is a diagram showing a manufacturing process of the array substrate; [Figure 9E] FIG. 9C is a diagram showing a manufacturing process of the array substrate, subsequent to FIG. 9D. [Figure 10] FIG. 13 is an enlarged cross-sectional view of a first TFT of an array substrate according to another embodiment; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] <Embodiment 1> A liquid crystal panel 11 (an example of a display panel) according to embodiment 1 will be described with reference to Fig. 1 to Fig. 6F. Note that the drawings show X-axis, Y-axis, and Z-axis, and each axis direction is drawn to be a common direction in each drawing.

[0017] As shown in Fig. 1, the liquid crystal panel 11 is divided into a display area (active area) AA capable of displaying an image and arranged at the center, and a non-display area (non-active area) NAA arranged on the outer periphery of the display area AA and forming a frame-like shape (picture frame-like shape) in a plan view. In Fig. 1, the dashed line represents the outer shape of the display area AA, and the area outside the dashed line is the non-display area NAA. The planar shape of the liquid crystal panel 11 is not limited, but in this embodiment, it is an elongated rectangle as a whole, with the short side direction coinciding with the X-axis direction, the long side direction coinciding with the Y-axis direction in each drawing, and the plate thickness direction coinciding with the Z-axis direction.

[0018] As shown in FIG. 2, the liquid crystal panel 11 is formed by bonding a pair of substrates 20, 21 together. Between the pair of substrates 20, 21, at least a liquid crystal layer 22 and a seal portion 23 for sealing the liquid crystal layer 22 are provided. The liquid crystal layer 22 contains liquid crystal molecules, which are a substance whose optical properties change when an electric field is applied. The seal portion 23 has a rectangular frame shape as a whole in a plan view, and surrounds the liquid crystal layer 22 in the non-display area NAA. The seal portion 23 maintains a gap (cell gap) equivalent to the thickness of the liquid crystal layer 22. A polarizing plate 24 is attached to each of the outer surfaces of the pair of substrates 20, 21.

[0019] Of the pair of substrates 20, 21, the one disposed on the front side (display surface side) is the counter substrate (CF substrate) 20, and the one disposed on the back side is the array substrate (active matrix substrate, TFT substrate) 21. Both the counter substrate 20 and the array substrate 21 are formed by laminating various films on the inner surface side (liquid crystal layer 22 side) of a glass substrate that is almost transparent and has excellent light transmission properties.

[0020] A backlight device that irradiates light onto the liquid crystal panel 11 is provided on the rear side (array substrate 21 side) of the liquid crystal panel 11. The liquid crystal panel 11 according to this embodiment is used, for example, in a head mounted display, and has extremely high definition. The pixel density of the liquid crystal panel 11 is, for example, in the range of about 800 ppi to 1800 ppi.

[0021] The array substrate 21 is larger than the counter substrate 20, and a portion of it protrudes beyond the counter substrate 20. A flexible substrate 13 is mounted on the protruding portion 21A of the array substrate 21. The flexible substrate 13 is configured by forming a number of wiring patterns on an insulating and flexible base material. One end of the flexible substrate 13 is connected to the array substrate 21, and the other end is connected to an external control substrate (signal supply source). Various signals supplied from the control substrate are transmitted to the liquid crystal panel 11 via the flexible substrate 13.

[0022] As shown in FIG. 3, a plurality of gate wirings (scanning wirings) 25 and source wirings (image wirings) 26 are arranged in a grid pattern in the display area AA of the array substrate 21. The gate wirings 25 extend generally along the X-axis direction across the display area AA. A plurality of gate wirings 25 are arranged in parallel at intervals in the Y-axis direction. A scanning signal output from a first circuit section 14A described later is supplied to the plurality of gate wirings 25 in order from the upper side of FIG. 3. The source wirings 26 extend generally along the Y-axis direction across the display area AA and intersect with the gate wirings 25. A plurality of source wirings 26 are arranged at intervals in the X-axis direction. An image signal output from a second circuit section 14B described later is distributed to the source wirings 26.

[0023] A first TFT 27 and a pixel electrode 28 are provided near the intersection of the gate line 25 and the source line 26. The first TFTs 27 and the pixel electrodes 28 are regularly arranged in groups along the X-axis direction and the Y-axis direction. The first TFT 27 is connected to the gate line 25, the source line 26, and the pixel electrode 28. When the first TFT 27 is driven based on a scanning signal supplied to the gate line 25, it charges the pixel electrode 28 to a potential based on an image signal supplied to the source line 26.

[0024] 1, a circuit section (peripheral circuit section) 14 is provided in the non-display area NAA of the array substrate 21. The circuit section 14 includes a first circuit section 14A and a second circuit section 14B. A pair of first circuit sections 14A are arranged to sandwich the display area AA from both sides in the X-axis direction, but they may be provided on only one side.

[0025] The first circuit section 14A is provided in a strip-shaped range extending along the Y-axis direction. The first circuit section 14A is for supplying scanning signals to the gate wiring 25, and is monolithically provided on the array substrate 21. The first circuit section 14A is a GDM (Gate Driver Monolithic) circuit. The first circuit section 14A includes a shift register circuit that outputs scanning signals at a predetermined timing, a buffer circuit that amplifies the scanning signals, and the like.

[0026] The second circuit section 14B is disposed at a position sandwiched between the display area AA and the flexible substrate 13 in the Y-axis direction. The second circuit section 14B is provided in a strip-shaped range extending along the X-axis direction. The second circuit section 14B is for supplying image signals (data signals) to the source wirings 26, and is provided monolithically on the array substrate 21. The second circuit section 14B includes a demultiplexer circuit (source signal division circuit) and the like. The second circuit section 14B has a switch function for dividing an image signal (source signal) supplied by the source driver 14C and distributing it to each source wiring 26. The first circuit section 14A and the second circuit section 14B constituting the circuit section 14 include various circuit elements, among which at least the second TFT 15 is included.

[0027] Next, the cross-sectional configuration of the array substrate 21 will be described in detail. FIG. 4 shows the cross-sectional configuration of the display area AA (first TFT 27) and the cross-sectional configuration of the circuit section 14 (second TFT 15) in the non-display area NAA. As shown in the right diagram of FIG. 4, the display area AA of the array substrate 21 is provided with the first TFT 27. The first TFT 27 has a first gate electrode 27E, a second gate electrode 27A, a first source electrode 27B, a first drain electrode 27C, and a first semiconductor film 27D. The first semiconductor film 27D is located above the second gate electrode 27A and below the first source electrode 27B, the first drain electrode 27C, and the first gate electrode 27E. Therefore, the first semiconductor film 27D is sandwiched between the two gate electrodes 27A and 27E from above and below, and the first TFT 27 has a double-gate structure. The double gate structure allows a channel region to be stably generated in the first semiconductor film 27D.

[0028] As shown in the left diagram of Fig. 4, the second TFT 15 is provided in the non-display area NAA of the array substrate 21. The second TFT 15 has a third gate electrode 15A, a second source electrode 15B, a second drain electrode 15C, and a second semiconductor film 15D. The second semiconductor film 15D is located at the bottommost layer with respect to the electrodes 15A to 15C. Therefore, the second TFT 15 has a top-gate structure.

[0029] The array substrate 21 includes the above-described two types of TFTs 15 and 27, and is formed by laminating various films on a glass substrate 21GS (an example of an insulating substrate). The glass substrate 21GS contains, for example, non-alkali glass as a main material. On the array substrate 21, in order from the lower layer side (the glass substrate 21GS side), a first light-shielding portion 40 and a second light-shielding portion 16 made of a light-shielding film, a base coat film 29, a second semiconductor film 15D, a gate insulating film 30, a third gate electrode 15A and a second gate electrode 27A made of a first metal film, a first insulating film 31, a first semiconductor film 27D, an auxiliary film 32 made of a first transparent conductive film, a second insulating film 33, a first gate electrode 27E made of a second metal film, a third insulating film 34, a first source electrode 27B made of a third metal film, a first drain electrode 27C, a second source electrode 15B, and a second drain electrode 15C, a planarization film 37, a pixel electrode 28 made of a second transparent conductive film, a fourth insulating film 38, and a common electrode 39 made of a third transparent conductive film are laminated and formed. Also, an alignment film is applied to cover these various laminated films on the uppermost layer (the layer closest to the liquid crystal layer 22) of the array substrate 21.

[0030] The light-shielding film, the first metal film, the second metal film, and the third metal film are a single-layer film made of one type of metal material, or a laminated film or alloy made of different types of metal materials, and have conductivity and light-shielding properties.

[0031] The first transparent conductive film, the second transparent conductive film, and the third transparent conductive film are made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide).

[0032] The base coat film 29, the gate insulating film 30, the first insulating film 31, the second insulating film 33, the third insulating film 34, and the fourth insulating film 38 are made of an inorganic material (inorganic resin material), and are made of, for example, a single layer film or a laminated film of SiO (silicon oxide, silicon oxide) or SiN (silicon nitride). The thicknesses of the gate insulating film 30 and the second insulating film 33 are, for example, in the range of about 80 nm to 120 nm. The second insulating film 33 plays a role as a gate insulating film of the first gate electrode 27E made of the second metal film. The second insulating film 33 has a planar size that overlaps with the first gate electrode 27E. The thickness of the first insulating film 31 is larger than that of the gate insulating film 30, and is, for example, about 300 nm. The thickness of the third insulating film 34 is, for example, in the range of about 500 nm to 700 nm.

[0033] The planarization film 37 is made of an organic material (organic resin material), for example, PMMA (acrylic resin). The planarization film 37 usually has a thickness larger than other insulating films made of inorganic materials.

[0034] The first semiconductor film 27D is made of an oxide semiconductor material. Compared to polysilicon semiconductor materials, oxide semiconductor materials have a characteristic of having a higher resistance value when no voltage is applied (off state). In addition, oxide semiconductor materials have a higher electron mobility than amorphous silicon semiconductor materials.

[0035] As the oxide semiconductor material, for example, an oxide semiconductor material containing at least one metal element selected from the group consisting of In, Ga, and Zn can be used. The oxide semiconductor material may be amorphous or crystalline, and may be, for example, an In-Ga-Zn-O-based semiconductor (for example, indium gallium zinc oxide). In addition, for example, an In-Sn-Zn-O-based semiconductor (for example, In 2 O 3 -SnO 2-ZnO; InSnZnO), In-W-Zn-O based semiconductors, In-W-Sn-Zn-O based semiconductors, In-Al-Zn-O based semiconductors, In-Al-Sn-Zn-O based semiconductors, Zn-O based semiconductors, In-Zn-O based semiconductors, Zn-Ti-O based semiconductors, Cd-Ge-O based semiconductors, Cd-Pb-O based semiconductors, CdO (cadmium oxide), Mg-Zn-O based semiconductors, In-Ga-Sn-O based semiconductors, In-Ga-O based semiconductors, Zr-In-Zn-O based semiconductors, Hf-In-Zn-O based semiconductors, Al-Ga-Zn-O based semiconductors, Ga-Zn-O based semiconductors, and In-Ga-Zn-Sn-O based semiconductors.

[0036] The second gate electrode 27A is made of a first metal film. The second gate electrode 27A is arranged to overlap the first semiconductor film 27D on the lower layer side with a first insulating film 31 interposed therebetween. The second gate electrode 27A is arranged to overlap a central portion of the first semiconductor film 27D.

[0037] The first gate electrode 27E is made of a second metal film. The first gate electrode 27E is disposed on the upper layer side of the first semiconductor film 27D via the second insulating film 33. The first gate electrode 27E is disposed so as to overlap with the central portion of the first semiconductor film 27D. The first gate electrode 27E has a smaller planar size than the second gate electrode 27A, and is disposed so as to overlap with the central portion of the second gate electrode 27A.

[0038] The first gate electrode 27E and the second gate electrode 27A are connected to each other. At least one of the gate electrodes 27A and 27E is connected to the gate wiring 25 (see FIG. 3). Therefore, a scanning signal supplied to the gate wiring 25 is supplied to the gate electrodes 27A and 27E, and the gate electrodes 27A and 27E are at the same potential. When the scanning signal is supplied to the gate electrodes 27A and 27E, a channel region is generated in the first semiconductor film 27D.

[0039] The first source electrode 27B and the first drain electrode 27C are made of a third metal film. The first source electrode 27B overlaps one end portion of the first semiconductor film 27D, and the first drain electrode 27C overlaps the other end portion of the first semiconductor film 27D. The first source electrode 27B is connected to the source wiring 26 (see FIG. 3).

[0040] The upper portions of the first source electrode 27B and the first drain electrode 27C are disposed on the upper layer side of the first semiconductor film 27D via a third insulating film 34. A first contact hole 36 is formed in the third insulating film 34. The first contact hole 36 is disposed at a position where each of the first source electrode 27B and the first drain electrode 27C overlaps with the first semiconductor film 27D but does not overlap with the first gate electrode 27E. The first source electrode 27B and the first drain electrode 27C are connected to the auxiliary film 32 through the first contact hole 36 (filled in the first contact hole 36), and are connected to the first semiconductor film 27D via the auxiliary film 32.

[0041] The auxiliary film 32 is made of a first transparent conductive film. As shown in FIG. 5, the auxiliary film 32 is provided between the lower surface 27B1 of the first source electrode 27B and the first semiconductor film 27D, and between the lower surface 27C1 of the first drain electrode 27C and the first semiconductor film 27D. Therefore, the auxiliary film 32 is arranged at a position where it overlaps with the lower surface 27B1 of the first source electrode 27B and the lower surface 27C1 of the first drain electrode 27C, but does not overlap with the first gate electrode 27E and the second insulating film 33. The auxiliary film 32 according to this embodiment serves as a stop film for preventing the first semiconductor film 27D below the first contact hole 36 from being etched (overetching) when the first contact hole 36 is formed by etching.

[0042] The auxiliary film 32 according to this embodiment has a protective portion 32A and an extension portion 32B. The protective portion 32A overlaps with the lower surface 27B1 of the first source electrode 27B and the lower surface 27C1 of the first drain electrode 27C, and is interposed between the lower surfaces 27B1, 27C1 and the first semiconductor film 27D to protect the first semiconductor film 27D. The extension portion 32B is a portion that extends from the protective portion 32A to the opposite side to the first gate electrode 27E. The extension portion 32B serves as a margin for dealing with variations in planar patterns during manufacturing and positional deviations between planar patterns of each portion. As described later, by providing the extension portion 32B, it becomes easier to deal with positional deviations with the first semiconductor film 27D, for example, when forming the first contact hole 36.

[0043] The pixel electrode 28 is made of a second transparent conductive film. An upper portion of the pixel electrode 28 is disposed so as to overlap the first drain electrode 27C. A contact hole 35 is provided in the planarization film 37 interposed between the pixel electrode 28 and the first drain electrode 27C, and the pixel electrode 28 is connected to the first drain electrode 27C through the contact hole 35.

[0044] The common electrode 39 is made of a third transparent conductive film. The common electrode 39 is disposed on the upper layer side of all the pixel electrodes 28 via a fourth insulating film 38. A plurality of slits 39A are formed in the portions of the common electrode 39 that overlap the plurality of pixel electrodes 28. A common potential signal that is a common potential (reference potential) is supplied to the common electrode 39. When the pixel electrodes 28 are charged to a potential based on an image signal transmitted to the source wiring 26 in response to the driving of the first TFT 27, a potential difference is generated between the pixel electrodes 28 and the common electrode 39. Then, a fringe electric field (oblique electric field) including a component along the plate surface of the array substrate 21 and a component in the normal direction to the plate surface of the array substrate 21 is generated between the opening edge of the slit 39A in the common electrode 39 and the pixel electrodes 28. The alignment state of the liquid crystal molecules contained in the liquid crystal layer 22 can be controlled by this fringe electric field. That is, the liquid crystal panel 11 according to this embodiment operates in a FFS (Fringe Field Switching) mode.

[0045] In addition, the display area AA is provided with a first light-shielding portion 40 at a position overlapping at least the entire area of ​​the first gate electrode 27E. The first light-shielding portion 40 is made of a light-shielding film located at the lowest layer among the films provided on the array substrate 21. The first light-shielding portion 40 is arranged overlapping most of the second gate electrode 27A. The first light-shielding portion 40 is arranged overlapping the lower layer side of each channel region of the first semiconductor film 27D that is generated when a voltage is applied to the first gate electrode 27E and the second gate electrode 27A. This allows the first light-shielding portion 40 to block light irradiated from the lower layer side onto each channel region of the first semiconductor film 27D from the backlight device. As a result, it is possible to suppress fluctuations in the characteristics of the first TFT 27 that may occur when each channel region of the first semiconductor film 27D is irradiated with light.

[0046] Next, the cross-sectional structure of the second TFT 15 of the circuit section 14 will be described with reference to FIG. 4. As described above, the second TFT 15 has the third gate electrode 15A, the second source electrode 15B, the second drain electrode 15C, and the second semiconductor film 15D. The second semiconductor film 15D is located at the lowermost layer side with respect to the electrodes 15A to 15C. The second semiconductor film 15D is made of a polysilicon semiconductor material having a crystalline quality produced by a known method such as laser crystallization. The polysilicon semiconductor material has a higher electron mobility than the oxide semiconductor material.

[0047] The third gate electrode 15A is made of a part of the first metal film that is different from the second gate electrode 27A. Therefore, since the third gate electrode 15A of the second TFT 15 and the second gate electrode 27A of the first TFT 27 are both made of the first metal film, the number of layers of the metal film can be reduced compared to the case where these electrodes are made of different metal films for each of the TFTs 15 and 27. The third gate electrode 15A is disposed on the upper layer side of the second semiconductor film 15D via the gate insulating film 30. The first gate electrode 15A is disposed so as to overlap the central portion of the second semiconductor film 15D.

[0048] The second source electrode 15B and the second drain electrode 15C are made of a portion of the third metal film that is separate from the first source electrode 27B and the first drain electrode 27. Therefore, the second source electrode 15B and the second drain electrode 15C of the second TFT 15 and the first source electrode 27B and the first drain electrode 27C of the first TFT 27 are all made of the third metal film, so that the number of layers of the metal film can be reduced compared to a case in which these metals are made of separate metal films for each of the TFTs 15 and 27. The second source electrode 15B overlaps one end portion of the second semiconductor film 15D, and the second drain electrode 15C overlaps the other end portion of the second semiconductor film 15D.

[0049] A part of the second source electrode 15B and the second drain electrode 15C is disposed on the upper layer side of the second semiconductor film 15D via the gate insulating film 30, the first insulating film 31, and the third insulating film 34. A second contact hole 18 is formed in the gate insulating film 30, the first insulating film 31, and the third insulating film 34. The second contact hole 18 is disposed at a position where the second source electrode 15B and the second drain electrode 15C overlap with the second semiconductor film 15D, respectively, but do not overlap with the third gate electrode 15A. The second source electrode 15B and the second drain electrode 15C are connected to the second semiconductor film 15D through the second contact hole 18 (by filling the second contact hole 18).

[0050] The circuit section 14 is also provided with a second light-shielding section 16 at a position overlapping at least the third gate electrode 15A. The second light-shielding section 16 is a portion of the light-shielding film that is separate from the first light-shielding section 40. The second light-shielding section 16 is arranged to overlap the lower layer side of the channel region of the second semiconductor film 15D that is generated when a voltage is applied to the third gate electrode 15A. This allows the second light-shielding section 16 to block light that is irradiated from the backlight device onto the channel region of the second semiconductor film 15D from the lower layer side. As a result, it is possible to suppress fluctuations in the characteristics of the second TFT 15 that may occur when the channel region of the second semiconductor film 15D is irradiated with light.

[0051] Next, a method for manufacturing the array substrate 21 will be described. The manufacturing process after the formation of the first insulating film 31 and before the formation of the planarizing film 37 will be described in detail below with reference to FIGS. 6A to 6F, taking as an example the lamination process of the cross-sectional portion shown in FIG. 4.

[0052] A first semiconductor film 27D is formed by patterning on the first insulating film 31 (FIG. 6A), and a transparent conductive film L1 made of a transparent conductive material is formed on the first semiconductor film 27D (FIG. 6B). The formed transparent conductive film L1 is patterned to form an auxiliary film 32 (FIG. 6C). Next, a second insulating film 33 and a first gate electrode 27E are formed by patterning on the first semiconductor film 27D, and then a third insulating film 34 is formed (FIG. 6D).

[0053] Here, "patterning" means processing of a film based on a general photolithography method. Specifically, it means forming a photoresist film on a film to be processed, exposing the photoresist film to light using an exposure device through a photomask having a predetermined pattern, developing the photoresist film, and etching the film to be processed through the developed photoresist film.

[0054] Next, the first contact hole 36 and the second contact hole 18 are formed in the same process (FIG. 6E). The first contact hole 36 is formed by etching and patterning the third insulating film 34, with the auxiliary film 32 serving as a stop film for the etching. The second contact hole 18 is formed by successively etching and patterning the three layers, the third insulating film 34, the first insulating film 31, and the gate insulating film 30, from the upper layer side, with the second semiconductor film 15D serving as a stop film for the etching.

[0055] After the first contact hole 36 and the second contact hole 18 are formed, the first source electrode 27B, the first drain electrode 27C, the second source electrode 15B, and the second drain electrode 15C are patterned (FIG. 6F). As a result, the first contact hole 36 is filled with the first source electrode 27B and the first drain electrode 27C, and the second contact hole 18 is filled with the second source electrode 15B and the second drain electrode 15C. The lower surface 27B1 of the first source electrode 27B and the lower surface 27C1 of the first drain electrode 27C are in contact with and connected to the upper surface of the protective portion 32A of the auxiliary film 32. As a result, the first source electrode 27B and the first drain electrode 27C are connected to the first semiconductor film 27D via the auxiliary film 32. On the other hand, the lower surface 15B1 of the second source electrode 15B and the lower surface 15C1 of the second drain electrode 15C are in contact with the upper surface of the second semiconductor film 15D and are directly connected to the second semiconductor film 15D.

[0056] Incidentally, in the contact hole forming process described above (FIG. 6E), the first contact hole 36 and the second contact hole 18 are formed in the same process, but the length (depth) of the two contact holes is different. Therefore, the shorter first contact hole 36 is over-etched, and the layer below it is easily corroded by the corrosive agent. More specifically, if the auxiliary film 32 is not provided, the first semiconductor film 27D may be corroded and the film thickness may be excessively reduced, as shown in the manufacturing process according to Comparative Example 1 in FIGS. 7A and 7B. In addition, depending on the etching time, the positional deviation of the photomask, etc., there is a concern that the first contact hole 936 may penetrate the lower first semiconductor film 27D.

[0057] In this embodiment, as shown in Fig. 5, an auxiliary film 32 is provided on the first semiconductor film 27D, and the first semiconductor film 27D is protected by a protective portion 32A of the auxiliary film 32. This makes it possible to prevent the first semiconductor film 27D from being excessively thinned in thickness or penetrated by the first semiconductor film 27D due to over-etching of the first contact hole 36. As a result, the first contact hole 36 and the second contact hole 18 can be appropriately formed in the same process, and compared to the case where these are provided in separate processes, the number of times that the insulating films (the third insulating film 34, the first insulating film 31, and the gate insulating film 30) are patterned (etched) can be reduced, thereby shortening the manufacturing process.

[0058] Furthermore, the auxiliary film 32 is made of the first transparent conductive film and does not have a light-shielding property. Therefore, even if the planar size of the auxiliary film 32 is formed large in consideration of manufacturing variations, etc., it is possible to prevent the aperture ratio from decreasing due to the auxiliary film 32. Therefore, the auxiliary film 32 can protect the first semiconductor film 27D of the first TFT 27 while preventing the aperture ratio from decreasing.

[0059] In addition, the extension 32B of the auxiliary film 32 makes it easier to accommodate misalignment with the first semiconductor film 27D when the first contact hole 36 is formed. If the auxiliary film 32 is not provided, as shown in the manufacturing process according to Comparative Example 1 in FIGS. 7A and 7B, when the first contact hole 936 is formed with misalignment, it may penetrate the first insulating film 31, the gate insulating film 30, and the base coat film 29 below the first semiconductor film 27D. For this reason, in order to protect the glass substrate 21GS from overetching of the first contact hole 936, the planar size of the first light-shielding portion 940 must be formed larger than the first semiconductor film 27D. As a result, the aperture ratio is actually reduced by the first light-shielding portion 940 having a large planar size.

[0060] In contrast, in this embodiment, even if the first contact hole 936 is misaligned with the first semiconductor film 27D (see the dashed line in FIG. 6E), the extension 32B of the auxiliary film 32 can suppress overetching of the first contact hole 936. Therefore, it is not necessary to form the planar size of the first light-shielding portion 40 to be larger than the first semiconductor film 27D, and it is easier to suppress a decrease in the aperture ratio. The planar size of the first light-shielding portion 40 may be a size (for example, the same size as the second gate electrode 27A) that can block light irradiated from the lower layer side to the channel region of the first semiconductor film 27D.

[0061] <Embodiment 2> The first TFT 127 of the array substrate 121 according to the second embodiment will be described with reference to Fig. 8 to Fig. 9E. The first TFT 127 differs from the first embodiment in that an auxiliary film 132 is provided under the first semiconductor film 127D and is made of the same material as the first semiconductor film 127D. In the second embodiment, the same reference characters are used for the same configurations, actions, and effects as those in the first embodiment, and duplicated descriptions will be omitted.

[0062] The auxiliary film 132 is provided in the lower layer of the first semiconductor film 127D at portions overlapping with the lower surface 27B1 of the first source electrode 27B and the lower surface 27C1 of the first drain electrode 27C. Since the auxiliary film 132 is made of the same material as the first semiconductor film 127D, the portions of the first semiconductor film 127D according to this embodiment that overlap with the auxiliary film 132 are thickened.

[0063] In this way, even if the film thickness of the first semiconductor film 127D is reduced due to overetching of the first contact hole 36, the auxiliary film 132 can compensate for the reduced thickness.

[0064] Next, a manufacturing method of the array substrate 121 will be described. A semiconductor film L11 made of a semiconductor material is formed on the first insulating film 31 (FIG. 9A). The material of the semiconductor film L11 is the same as that of the first semiconductor film 127D. The formed semiconductor film L11 is patterned to form an auxiliary film 132 (FIG. 9B). A semiconductor film L12 made of a semiconductor material is formed on the auxiliary film 132 (FIG. 9C). The formed semiconductor film L12 is patterned to form the first semiconductor film 127D (FIG. 9D). Next, the second insulating film 33 and the first gate electrode 27E are patterned on the first semiconductor film 127D, and then the third insulating film 34 is formed, and the first contact hole 36 and the second contact hole 18 are formed in the same process (FIG. 9E).

[0065] The first contact hole 36 is formed by etching and patterning the third insulating film 34, and the first semiconductor film 127D serves as a stop film for the etching. At this time, even if the film thickness of the first semiconductor film 127D is reduced due to overetching of the first contact hole 36 as shown in Fig. 9E, the reduction can be compensated for by the auxiliary film 132. By forming the auxiliary film 132 from the same material as the first semiconductor film 127D in this way, it is possible to suppress a situation in which the characteristics of the first TFT 127 are changed due to the provision of the auxiliary film 132.

[0066] Incidentally, when the auxiliary film 132 is made of the same material as the first semiconductor film 127D, if the auxiliary film 132 is provided above the first semiconductor film 127D as in the first embodiment, when the auxiliary film 132 is etched and patterned, the portion of the first semiconductor film 127D that does not overlap with the auxiliary film 132 is also etched. In this regard, in the present embodiment, the auxiliary film 132 is provided below the first semiconductor film 127D, and this situation can be avoided.

[0067] <Other embodiments> The technology described in this specification is not limited to the embodiments described above with reference to the drawings, and for example, the following embodiments are also included within the technical scope of the present invention.

[0068] (1) As shown in Fig. 10, the auxiliary film 232 according to the first embodiment only needs to have at least the protective portion 32A, and may not have the extending portion 32B. In this case, it is preferable that the planar size of the first light-shielding portion 240 is large. In this way, it is easy to prevent the characteristics of the first TFT 27 from being changed due to the provision of the auxiliary film 232.

[0069] (2) The material of the auxiliary films 32 and 232 according to the first embodiment and the above (1) is not limited to a transparent conductive material, and may be a semiconductor material different from that of the first semiconductor film 27D.

[0070] (3) The layer configuration and layout pattern of the array substrates 21 and 121 are not limited to those shown in the drawings. For example, the array substrates 21 and 121 may include wiring for implementing a touch panel function.

[0071] (4) The driving method of the liquid crystal panel 11 is not limited to the FFS mode, and may be other methods such as the IPS (In Plane Switching) mode. Furthermore, the common electrode 39 may be provided on the counter substrate 20 depending on the driving method.

[0072] (5) This technology can also be applied to other types of display panels, such as organic electroluminescence (EL) panels. [Explanation of symbols]

[0073] 11...liquid crystal panel (display panel), 22...liquid crystal layer, 21, 121...array substrate, 20...counter substrate, 21GS...glass substrate (insulating substrate), 15...second TFT (thin film transistor), 15A...third gate electrode, 15B...second source electrode, 15C...second drain electrode, 15D...second semiconductor film, 27, 127...first TFT, 27A...second gate electrode, 27B...second source electrode, 27B1...lower surface, 27C...second drain electrode, 27C1...lower surface, 27D, 127D...first semiconductor film, 27E...first gate electrode, 30...gate insulating film, 31...first insulating film, 32, 132, 232...auxiliary film, 33...second insulating film, 34...third insulating film, 40...first light-shielding portion

Claims

1. A first insulating film disposed on an upper layer side of an insulating substrate; a first semiconductor film disposed on an upper layer of the first insulating film; A second insulating film disposed on the first semiconductor film; a first gate electrode disposed on the second insulating film and overlapping the first semiconductor film; a third insulating film disposed on an upper layer of the first gate electrode; a first source electrode and a first drain electrode made of a metal film disposed on the third insulating film and connected to the first semiconductor film through a first contact hole penetrating the third insulating film; an auxiliary film made of a non-metallic material, the auxiliary film being arranged in an upper or lower layer of the first semiconductor film at a position overlapping at least the lower surfaces of the first source electrode and the first drain electrode;

2. The array substrate according to claim 1 , wherein the auxiliary film is disposed above the first semiconductor film and is made of a transparent conductive material.

3. 2. The array substrate according to claim 1, wherein the auxiliary film is disposed below the first semiconductor film and is made of the same material as the first semiconductor film.

4. a first light-shielding portion provided on a lower layer side of the first insulating film; 4 . The array substrate according to claim 1 , wherein the first light-shielding portion overlaps the first gate electrode but does not overlap the lower surfaces of the first source electrode and the first drain electrode.

5. 4. The array substrate according to claim 1, wherein the first TFT is a TFT of a double-gate structure further having a second gate electrode disposed under the first insulating film.

6. A second semiconductor film; a gate insulating film disposed on an upper layer of the second semiconductor film; a third gate electrode disposed on the gate insulating film and made of the same material as the second gate electrode; the first insulating film disposed on an upper layer of the third gate electrode; the third insulating film disposed on an upper layer of the first insulating film; a second TFT having a second source electrode and a second drain electrode connected to the second semiconductor film through a second contact hole penetrating the third insulating film, the first insulating film, and the gate insulating film from an upper layer of the third insulating film; the first semiconductor film of the first TFT is made of an oxide semiconductor material; 6. The array substrate according to claim 5, wherein the second semiconductor film of the second TFT is made of a polysilicon semiconductor material.

7. An array substrate according to any one of claims 1 to 3; an opposing substrate disposed opposite to the array substrate with an internal space therebetween; a liquid crystal layer sealed in the internal space.

Images