Flip chip structure and circuit board thereof

Abstract

To provide a flip chip structure.SOLUTION: A flip chip structure 100 includes a circuit board 110 and a chip 120. The circuit board 110 includes a plurality of first inner leads 112 and a plurality of second inner leads 113, each of the first inner leads 112 has a first bonding portion 112b. An included angle exists between the second bonding portion 113b and the first connecting segment 113a1 of the second inner lead 113, and an included angle exists between the center line of the first bonding portion 112b and the center line of the second bonding portion 113b. The chip 120 includes a plurality of first bumps 122 and a plurality of second bumps 123, and an included angle exists between the center line of the first bump 122 and the center line of the second bump 123. Each of the first bumps 122 is bonded to the first bonding portion 112b, and each of the second bumps 123 is bonded to the second bonding portion 113b and the first connecting segment 113a1. Thus, a situation that to bonding shift occurs between the inner leads and the bumps is avoided or a shift degree of bonding is lessened.SELECTED DRAWING: Figure 9

Description

[Technical field]

[0001] The present invention relates to a flip chip structure and its circuit board, and is directed to preventing or suppressing bonding shift that occurs when bonding bumps of a chip to inner leads of a circuit board. [Background technology]

[0002] 10 and 11, in a conventional circuit board 11, a circuit layer 11b is formed on a substrate 11a, and a protective layer (not shown) covers the circuit layer 11b, and the protective layer exposes a chip mounting area 11c of the substrate 11a, a plurality of inner leads 11b1 of the circuit layer 11b, and a plurality of outer leads (not shown). Each inner lead 11b1 is mounted on the chip mounting area 11c, and a plurality of bumps 12a of a chip 12 are bonded to each inner lead 11b1, thereby forming a flip chip structure 10. Summary of the Invention [Problem to be solved by the invention]

[0003] However, in the conventional technology described above, due to a mismatch in the coefficient of thermal expansion (CTE) between the substrate 11a, the circuit layer 11b, and the protective layer, when bonding each bump 12a to each inner lead 11b1, a phenomenon occurs in which the circuit substrate 11 thermally expands or contracts due to the process temperature, causing a bonding displacement in each bump 12a and each inner lead 11b1 in the chip mounting area 11c. If the bonding displacement is too large, each bump 12a cannot be bonded to each inner lead 11b1, or the bonding area becomes insufficient.

[0004] Therefore, the present inventors believed that the above-mentioned drawbacks could be improved, and as a result of extensive research, they came to propose the present invention, which effectively improves the above-mentioned problems through rational design.

[0005] The present invention has been made in view of the above circumstances, and aims to provide a flip chip structure and a circuit board thereof, in which a first bonding portion of a first inner lead and a second bonding portion of a second inner lead are disposed in a chip mounting area of ​​a circuit board along different directions, and a first bump and a second bump of a chip are bonded to the first bonding portion and the second bonding portion along the mounting directions of the first bonding portion and the second bonding portion, respectively, thereby increasing resistance to changes in thermal expansion or contraction of the circuit board, preventing a situation in which a bonding shift occurs between the inner lead and the bump, or suppressing the degree of the bonding shift. [Means for solving the problem]

[0006] In order to achieve the above object, a flip chip structure according to one aspect of the present invention includes a circuit board and a chip. The circuit board has a plurality of first inner leads and a plurality of second inner leads, and each of the first inner leads and the second inner leads is disposed in a chip mounting area. Each of the first inner leads has a first lead portion and a first joint portion, and each of the second inner leads has a second lead portion and a second joint portion. The first connection portion of the second lead portion is connected to the second joint portion, and a first included angle is formed between the second joint portion and the first connection portion, and each of the first joint portions and the second joint portions are arranged to intersect with the chip mounting area along a first direction. Along a second direction intersecting with the first direction, a first gap is formed between the first joint portion and the second joint portion, and the first joint portion is closer to an edge of the chip mounting area than the second joint portion. A second included angle is formed between a center line of the first joint portion and a center line of the second joint portion. The chip has a plurality of first bumps and a plurality of second bumps, each of the first bumps and each of the second bumps arranged intersecting the active surface along a first direction, each of the first bumps being closer to an edge of the active surface than each of the second bumps along a second direction, a third included angle being defined between a centerline of each of the first bumps and a centerline of each of the second bumps, each of the first bumps being bonded to a first bonding portion of a respective one of the first inner leads, and each of the second bumps being bonded to a second bonding portion and a first connecting portion of a respective one of the second inner leads.

[0007] A circuit board according to another embodiment of the present invention includes a plurality of first inner leads and a plurality of second inner leads. Each of the first inner leads has a first lead portion and a first joint portion, and each of the second inner leads has a second lead portion and a second joint portion. The first joint portion of the second lead portion is connected to the second joint portion, and a first included angle is formed between the second joint portion and the first joint portion, and the second joint portion and the first joint portion are used to join the bump. The first and second joint portions are arranged to intersect with the chip installation area along a first direction. Along a second direction intersecting the first direction, a first gap is formed between the first and second joint portions, and the first joint portion is closer to the edge of the chip installation area than the second joint portion. A second included angle is formed between the center line of the first joint portion and the center line of the second joint portion.

[0008] The first and second bonding portions are arranged along different directions, and the first and second bumps of the chip are bonded to the first and second bonding portions along the installation directions of the first and second bonding portions, respectively, thereby increasing resistance to changes in thermal expansion or contraction of the circuit board, preventing or suppressing the degree of displacement of the bond between the inner lead and the bump, and solving problems such as the bump being unable to be bonded to the inner lead or the bond area being insufficient.

[0009] At least the following points will become apparent from the following specification and drawings. [Brief description of the drawings]

[0010] [Figure 1] 1 is a plan view showing a flip chip structure according to an embodiment of the present invention; [Diagram 2] 1 is a plan view showing a portion of a circuit board having a flip chip structure according to an embodiment of the present invention; [Diagram 3] 1 is a plan view showing a portion of a circuit board having a flip chip structure according to an embodiment of the present invention; [Figure 4A] 1 is a plan view showing a portion of a circuit board having a flip chip structure according to an embodiment of the present invention; [Figure 4B] 1 is a plan view showing a portion of a circuit board having a flip chip structure according to an embodiment of the present invention; [Figure 5A] FIG. 4 is a plan view showing a shape of a second bonding portion according to an embodiment of the present invention. [Figure 5B] FIG. 4 is a plan view showing a shape of a second bonding portion according to an embodiment of the present invention. [Figure 5C] FIG. 4 is a plan view showing a shape of a second bonding portion according to an embodiment of the present invention. [Figure 5D] FIG. 4 is a plan view showing a shape of a second bonding portion according to an embodiment of the present invention. [Figure 6] FIG. 2 is a bottom view showing a chip having a flip chip structure according to an embodiment of the present invention. [Figure 7] 1 is a plan view showing a portion of a chip having a flip chip structure according to an embodiment of the present invention; [Figure 8] 1 is a plan view showing a portion of a flip chip structure according to an embodiment of the present invention; [Figure 9] 1 is a plan view showing a portion of a flip chip structure according to an embodiment of the present invention; [Figure 10] FIG. 1 is a cross-sectional view showing a conventional flip chip structure. [Figure 11] FIG. 1 is a plan view showing a conventional flip chip structure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Below, embodiments of the flip chip structure and its circuit board of the present invention will be described with reference to the drawings. However, the present invention is not limited to these embodiments, and the components, materials, etc. described below can be modified in various ways within the spirit and scope of the present invention.

[0012] First, an example of a specific embodiment of a flip chip structure 100 of the present invention will be described with reference to FIGS.

[0013] The flip chip structure 100 according to the present invention includes a circuit board 110 and a chip 120. In this embodiment, the circuit board 110 includes a substrate (not shown), a circuit layer 110a, and a solder mask layer (not shown). The substrate may be a flexible material such as polyimide (PI) or polyethylene terephthalate (PET). The solder mask layer covers the circuit layer 110a and exposes a chip mounting area 111 of the circuit board 110. The chip 120 is flip chip bonded to the chip mounting area 111 by an active surface 121.

[0014] 2 and 3, the circuit layer 110a has a plurality of first inner leads 112 and a plurality of second inner leads 113, and each of the first inner leads 112 and the second inner leads 113 is installed in a chip installation area 111. Each of the first inner leads 112 has a first lead portion 112a and a first bonding portion 112b.

[0015] 2 and 3, each of the second inner leads 113 has a second lead portion 113a and a second joint portion 113b, the second lead portion 113a has a first connection portion 113a1 and a first body 113a3, the first connection portion 113a1 is connected to the second joint portion 113b, and a first included angle A is formed between the first connection portion 113a1 and the second joint portion 113b. The first length H1 of the first body 113a3 is shorter than the second length H2 of the first connection portion 113a1. In this embodiment, the second joint portion 113b is disposed in the chip mounting area 111 along the first direction X, and the first joint portion 112b is disposed in the chip mounting area 111 along the second direction Y, and the first direction X intersects with the second direction Y. In other words, the first joint portion 112b and the second joint portion 113b are disposed in the chip mounting area 111 along different directions.

[0016] 2 to 4B, the first and second bonding portions 112b and 113b are arranged to intersect with each other in the chip mounting area 111 along the first direction X. Along the second direction Y, there is a first gap S1 between the first and second bonding portions 112b and 113b, and the first bonding portion 112b is closer to the edge 111a of the chip mounting area 111 than the second bonding portion 113b. There is a second included angle B between the center line L1 of the first bonding portion 112b and the center line L2 of the second bonding portion 113b. In this embodiment, the center line L1 of the first bonding portion 112b is parallel to the second direction Y, and the center line L2 of the second bonding portion 113b is parallel to the first direction X.

[0017] 3, the second lead portion 113a further includes a second connection portion 113a2, which is located between the first connection portion 113a1 and the first body 113a3. A third length H3 of the second connection portion 113a2 gradually decreases from the first connection portion 113a1 toward the first body 113a3.

[0018] 3 to 4B, the circuit layer 110a further includes a plurality of third inner leads 114, each of which is disposed in the chip mounting area 111. Each of the third inner leads 114 includes a third lead portion 114a and a third joint portion 114b, and the third lead portion 114a includes a third connection portion 114a1 and a second body 114a2. The third connection portion 114a1 is connected to the third joint portion 114b, and a fourth included angle D is formed between the third connection portion 114a1 and the third joint portion 114b.

[0019] 3 to 4B, the first bonding portion 112b, the second bonding portion 113b, and the third bonding portion 114b are arranged so as to intersect with each other in the chip installation area 111 along the first direction X. Along the second direction Y, there is a second gap S2 between the first bonding portion 112b and the third bonding portion 114b, and the second gap S2 is narrower than the first gap S1. The first bonding portion 112b is closer to the edge 111a of the chip installation area 111 than the third bonding portion 114b, and the third bonding portion 114b is closer to the edge 111a of the chip installation area 111 than the second bonding portion 113b. There is a fifth included angle E between the center line L1 of the first bonding portion 112b and the center line L5 of the third bonding portion 114b. In this embodiment, the center line L5 of the third bonding portion 114b is parallel to the second direction Y.

[0020] As shown in Figures 5A to 5D, the second joint 113b has an inverted L-shape, a T-shape, a Y-shape, or a cross shape, and similarly, the third joint 114b also has an inverted L-shape, a T-shape, a Y-shape, or a cross shape.

[0021] 6 and 7, the chip 120 has a plurality of first bumps 122 and a plurality of second bumps 123, and in this embodiment, the chip 120 further has a plurality of third bumps 124. The first bumps 122, the second bumps 123, and the third bumps 124 are arranged to intersect with each other on the active surface 121 along the first direction X. Along the second direction Y, the first bump 122 is closer to the edge 121a of the active surface 121 than the second bump 123 and the third bump 124, and the third bump 124 is closer to the edge 121a of the active surface 121 than the second bump 123. A third included angle C is formed between the center line L3 of the first bump 122 and the center line L4 of the second bump 123, and the third included angle C is substantially equal to the second included angle B. In this embodiment, the center line L3 of the first bump 122 is parallel to the second direction Y, and the center line L4 of the second bump 123 is parallel to the first direction X.

[0022] 7, along the direction of the center line L4 of the second bump 123, the first bump 122 has a fourth length H4, and the second bump 123 has a fifth length H5, which is longer than the fourth length H4. A sixth included angle F is formed between the center line L3 of the first bump 122 and the center line L6 of the third bump 124, and in this embodiment, the center line L6 of the third bump 124 is parallel to the first direction X. Along the direction of the center line L6 of the third bump 124, the third bump 124 has a sixth length H6, which is longer than the fourth length H4 of the first bump 122. In this embodiment, the sixth length H6 of the third bump 124 is shorter than the fifth length H5 of the second bump 123. The directions of the first bump 122, the second bump 123, and the third bump 124 are the same as those of the first bonding portion 112b, the second bonding portion 113b, and the third bonding portion 114b, respectively.

[0023] 7, along the direction of the center line L3 of the first bump 122, the first bump 122 has a first width W1, the second bump 123 has a second width W2, and the third bump 124 has a third width W3, and the second width W2 and the third width W3 are narrower than the first width W1. The fourth length H4 of the first bump 122 is shorter than the first width W1, the fifth length H5 of the second bump 123 is longer than the second width W2, and the sixth length H6 of the third bump 124 is longer than the third width W3. In addition, the fifth length H5 is equal to or shorter than the first width W1. Preferably, the fifth length H5 and the sixth length H6 are shorter than the first width W1, thereby reducing the amount of metal material used for the second bump 123 and the third bump 124.

[0024] 8 and 9, the first bump 122 is bonded to the first bonding portion 112b, the second bump 123 is bonded to the second bonding portion 113b and the first connecting portion 113a1, and the third bump 124 is bonded to the third bonding portion 114b and the third connecting portion 114a1. The first bonding portion 112b, the second bonding portion 113b, and the third bonding portion 114b are installed in the chip installation area 111 along different directions, and the installation directions of the first bump 122, the second bump 123, and the third bump 124 are the same as the first bonding portion 112b, the second bonding portion 113b, and the third bonding portion 114b, respectively. This increases resistance to changes in thermal expansion or thermal contraction of the circuit board 110 in the first direction X and the second direction Y, and prevents a situation in which a bonding shift occurs between the inner lead and the bump, or suppresses the degree of the bonding shift.

[0025] 3, 7 and 9, the second width W2 of the second bump 123 is narrower than the first width W1 of the first bump 122, and the fifth length H5 of the second bump 123 is longer than the fourth length H4 of the first bump 122 but not longer than the first width W1 of the first bump 122. This reduces the amount of metal material used to manufacture the second bump 123. In addition, since the second length H2 of the first connection portion 113a1 is longer than the first length H1 of the first body 113a3, when the second bump 123 is bonded to the second bonding portion 113b and the first connection portion 113a1, the bonding area between the second bump 123 and the second inner lead 113 is increased, preventing the second bump 123 from being detached from the second inner lead 113 and increasing the resistance to changes in thermal expansion or contraction of the circuit board 110.

[0026] Although the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is clear to those skilled in the art that various modifications and improvements can be made to the above embodiments. It is clear from the claims that such modifications and improvements can also be included in the technical scope of the present invention. [Explanation of symbols]

[0027] 10. Flip Chip Construction 11 Circuit Board 11a Substrate 11b circuit layer 11b1 Inner lead 11c Chip Setting Area 12 Chips 12a Bump 100 Flip chip construction 110 Circuit Board 110a circuit layer 111 Chip installation area 111a edge 112 1st Inner Lead 112a First lead part 112b 1st joint 113 2nd Inner Lead 113a Second lead part 113a1 First connection part 113a2 Second connection part 113a3 1st body 113b 2nd joint 114 3rd Inner Lead 114a Third lead part 114a1 Third connection part 114a2 2nd body 114b 3rd joint 120 Chips 121 Active Surface 122 First Bump 123 2nd Bump 124 3rd Bump A 1st inclusion angle B Second containment angle C 3rd angle D 4th inclusion angle E 5th angle F 6th inclusion angle L1 center line L2 center line L3 center line L4 center line L5 center line L6 center line H1 First length H2 Second length H3 3rd length H4 4th length H5 5th length H6 6th length S1 First gap S2 Second gap W1 1st width W2 Second width W3 3rd width X 1st direction Y Second direction

Claims

1. a circuit board having a plurality of first inner leads and a plurality of second inner leads, each of the first inner leads and each of the second inner leads being installed in a chip installation area, each of the first inner leads having a first lead portion and a first joint portion, each of the second inner leads having a second lead portion and a second joint portion, a first connection portion of the second lead portion being connected to the second joint portion, a first included angle being formed between the second joint portion and the first connection portion, each of the first joint portions and each of the second joint portions being arranged to intersect with the chip installation area along a first direction, a first gap being formed between the first joint portion and the second joint portion along a second direction intersecting with the first direction, the first joint portion being closer to an edge of the chip installation area than the second joint portion, and a second included angle being formed between a center line of the first joint portion and a center line of the second joint portion; a chip having a plurality of first bumps and a plurality of second bumps, each of the first bumps and each of the second bumps arranged to intersect an active surface along the first direction, each of the first bumps being closer to an edge of the active surface than each of the second bumps along the second direction, a third included angle being formed between a center line of each of the first bumps and a center line of each of the second bumps, each of the first bumps being bonded to the first bonding portion of each of the first inner leads, and each of the second bumps being bonded to the second bonding portion and the first connection portion of each of the second inner leads.

2. 2. The flip chip structure of claim 1, wherein the second lead portion further comprises a first body, the first length of the first body being shorter than the second length of the first connection portion.

3. 3. The flip chip structure of claim 2, wherein the second lead portion further includes a second connection portion, the second connection portion being located between the first connection portion and the first body, and a third length of the second connection portion gradually shortens in a direction from the first connection portion to the first body.

4. 2. The flip chip structure of claim 1, wherein along a direction of the center line of each of the first bumps, a first width of each of the first bumps is wider than a second width of each of the second bumps, along a direction of the center line of each of the second bumps, a fourth length of each of the first bumps is shorter than a fifth length of each of the second bumps, the first width of each of the first bumps is longer than the fourth length of each of the first bumps, the second width of each of the second bumps is shorter than the fifth length of each of the second bumps, and the fifth length of each of the second bumps is less than or equal to the first width of each of the first bumps.

5. 2. The flip chip structure of claim 1, wherein the first bonding portion is disposed in the chip mounting area along the second direction, the center line of the first bonding portion being parallel to the second direction, and the second bonding portion is disposed in the chip mounting area along the first direction, the center line of the second bonding portion being parallel to the first direction.

6. The circuit board further includes a plurality of third inner leads, each of the third inner leads being disposed in the chip mounting area, each of the third inner leads having a third lead portion and a third joint portion, a third connection portion of the third lead portion being connected to the third joint portion, a fourth included angle being formed between the third joint portion and the third connection portion, each of the first joint portions, each of the second joint portions, and each of the third joint portions being arranged to intersect with the chip mounting area along the first direction, a second gap being formed between the first joint portion and the third joint portion along the second direction, the second gap being shorter than the first gap, and the first joint portion being closer to the chip mounting area than the third joint portion.

5. The flip chip structure of claim 4, wherein the chip further comprises a plurality of third bumps, each of the first bumps, each of the second bumps, and each of the third bumps are arranged to intersect the active surface along the first direction, each of the first bumps being closer to the edge of the active surface than each of the third bumps, a sixth included angle is formed between the center line of each of the first bumps and the center line of each of the third bumps, and each of the third bumps is bonded to the third bonding portion and the third connection portion of each of the third inner leads.

7. 7. The flip chip structure of claim 6, wherein along the direction of the centerline of each of the first bumps, the first width of each of the first bumps is wider than the third width of each of the third bumps, and along the direction of the centerline of each of the third bumps, the sixth length of each of the third bumps is longer than the fourth length of each of the first bumps.

8. 8. The flip chip structure of claim 7, wherein the first bonding portion is disposed in the chip mounting area along the second direction, the center line of the first bonding portion and the center line of each of the first bumps are parallel to the second direction, the second bonding portion and the third bonding portion are disposed in the chip mounting area along the first direction, and the center line of the second bonding portion, the center line of the third bonding portion, the center line of each of the second bumps, and the center line of each of the third bumps are parallel to the first direction.

9. 2. The flip chip structure of claim 1, wherein the second joint has an inverted L-shape, a T-shape, a Y-shape, or a cross-shape.

10. a plurality of first inner leads each having a first lead portion and a first bonding portion; a first connection portion of the second lead portion is connected to the second connection portion, a first included angle is formed between the second connection portion and the first connection portion, the second connection portion and the first connection portion are used to join bumps, each of the first and second connection portions is arranged to intersect a chip installation area along a first direction, a first gap is formed between the first and second connection portions along a second direction intersecting the first direction, the first connection portion is closer to an edge of the chip installation area than the second connection portion, and a second included angle is formed between a center line of the first connection portion and a center line of the second connection portion.

11. 11. The circuit board according to claim 10, wherein the second lead portion further comprises a first body, the first length of the first body being shorter than the second length of the first connection portion.

12. 12. The circuit board according to claim 11, wherein the second lead portion further includes a second connection portion, the second connection portion being located between the first connection portion and the first body, and a third length of the second connection portion gradually shortens in a direction from the first connection portion to the first body.

13. 11. The circuit board of claim 10, wherein the first bonding portion is disposed in the chip mounting area along the second direction, the center line of the first bonding portion being parallel to the second direction, and the second bonding portion is disposed in the chip mounting area along the first direction, the center line of the second bonding portion being parallel to the first direction.

14. 11. The circuit board according to claim 10, further comprising a plurality of third inner leads, each of the third inner leads being installed in the chip installation area, each of the third inner leads having a third lead portion and a third joint portion, a third connection portion of the third lead portion being connected to the third joint portion, a fourth included angle being formed between the third joint portion and the third connection portion, each of the first joint portion, the second joint portion and the third joint portion being arranged to intersect with the chip installation area along the first direction, a second gap being formed between the first joint portion and the third joint portion along the second direction, the second gap being shorter than the first gap, the first joint portion being closer to the edge of the chip installation area than the third joint portion, and a fifth included angle being formed between the center line of the first joint portion and the center line of the third joint portion.

15. 15. The circuit board of claim 14, wherein the first bonding portion is disposed in the chip mounting area along the second direction, the center line of the first bonding portion being parallel to the second direction, the second bonding portion and the third bonding portion are disposed in the chip mounting area along the first direction, and the center line of the second bonding portion and the center line of the third bonding portion are parallel to the first direction.

16. The circuit board according to claim 10 , wherein the second joint portion has an inverted L-shape, a T-shape, a Y-shape, or a cross shape.

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